15254 %ymm registers not restored after signal handler
15367 x86 getfpregs() summons corrupting %xmm ghosts
15333 want x86 /proc xregs support (libc_db, libproc, mdb, etc.)
15336 want libc functions for extended ucontext_t
15334 want ps_lwphandle-specific reg routines
15328 FPU_CW_INIT mistreats reserved bit
15335 i86pc fpu_subr.c isn't really platform-specific
15332 setcontext(2) isn't actually noreturn
15331 need <sys/stdalign.h>
Change-Id: I7060aa86042dfb989f77fc3323c065ea2eafa9ad
Conflicts:
    usr/src/uts/common/fs/proc/prcontrol.c
    usr/src/uts/intel/os/archdep.c
    usr/src/uts/intel/sys/ucontext.h
    usr/src/uts/intel/syscall/getcontext.c

@@ -6093,25 +6093,68 @@
         if (vabits)
                 *vabits = cpi->cpi_vabits;
 }
 
 size_t
-cpuid_get_xsave_size()
+cpuid_get_xsave_size(void)
 {
         return (MAX(cpuid_info0.cpi_xsave.xsav_max_size,
             sizeof (struct xsave_state)));
 }
 
 /*
+ * Export information about known offsets to the kernel. We only care about
+ * things we have actually enabled support for in %xcr0.
+ */
+void
+cpuid_get_xsave_info(uint64_t bit, size_t *sizep, size_t *offp)
+{
+        size_t size, off;
+
+        VERIFY3U(bit & xsave_bv_all, !=, 0);
+
+        if (sizep == NULL)
+                sizep = &size;
+        if (offp == NULL)
+                offp = &off;
+
+        switch (bit) {
+        case XFEATURE_LEGACY_FP:
+        case XFEATURE_SSE:
+                *sizep = sizeof (struct fxsave_state);
+                *offp = 0;
+                break;
+        case XFEATURE_AVX:
+                *sizep = cpuid_info0.cpi_xsave.ymm_size;
+                *offp = cpuid_info0.cpi_xsave.ymm_offset;
+                break;
+        case XFEATURE_AVX512_OPMASK:
+                *sizep = cpuid_info0.cpi_xsave.opmask_size;
+                *offp = cpuid_info0.cpi_xsave.opmask_offset;
+                break;
+        case XFEATURE_AVX512_ZMM:
+                *sizep = cpuid_info0.cpi_xsave.zmmlo_size;
+                *offp = cpuid_info0.cpi_xsave.zmmlo_offset;
+                break;
+        case XFEATURE_AVX512_HI_ZMM:
+                *sizep = cpuid_info0.cpi_xsave.zmmhi_size;
+                *offp = cpuid_info0.cpi_xsave.zmmhi_offset;
+                break;
+        default:
+                panic("asked for unsupported xsave feature: 0x%lx", bit);
+        }
+}
+
+/*
  * Return true if the CPUs on this system require 'pointer clearing' for the
  * floating point error pointer exception handling. In the past, this has been
  * true for all AMD K7 & K8 CPUs, although newer AMD CPUs have been changed to
  * behave the same as Intel. This is checked via the CPUID_AMD_EBX_ERR_PTR_ZERO
  * feature bit and is reflected in the cpi_fp_amd_save member.
  */
 boolean_t
-cpuid_need_fp_excp_handling()
+cpuid_need_fp_excp_handling(void)
 {
         return (cpuid_info0.cpi_vendor == X86_VENDOR_AMD &&
             cpuid_info0.cpi_fp_amd_save != 0);
 }