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--- old/usr/src/uts/intel/os/archdep.c
+++ new/usr/src/uts/intel/os/archdep.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21 /*
22 22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 25 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
26 26 /* All Rights Reserved */
27 27 /*
28 28 * Copyright (c) 2018, Joyent, Inc.
29 29 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
30 - * Copyright 2022 Oxide Computer Company
30 + * Copyright 2023 Oxide Computer Company
31 31 */
32 32
33 33 #include <sys/param.h>
34 34 #include <sys/types.h>
35 35 #include <sys/vmparam.h>
36 36 #include <sys/systm.h>
37 37 #include <sys/signal.h>
38 38 #include <sys/stack.h>
39 39 #include <sys/regset.h>
40 40 #include <sys/privregs.h>
41 41 #include <sys/frame.h>
42 42 #include <sys/proc.h>
43 43 #include <sys/psw.h>
44 44 #include <sys/siginfo.h>
45 45 #include <sys/cpuvar.h>
46 46 #include <sys/asm_linkage.h>
47 47 #include <sys/kmem.h>
48 48 #include <sys/errno.h>
49 49 #include <sys/bootconf.h>
50 50 #include <sys/archsystm.h>
51 51 #include <sys/debug.h>
52 52 #include <sys/elf.h>
53 53 #include <sys/spl.h>
54 54 #include <sys/time.h>
55 55 #include <sys/atomic.h>
56 56 #include <sys/sysmacros.h>
57 57 #include <sys/cmn_err.h>
58 58 #include <sys/modctl.h>
59 59 #include <sys/kobj.h>
60 60 #include <sys/panic.h>
61 61 #include <sys/reboot.h>
62 62 #include <sys/time.h>
63 63 #include <sys/fp.h>
64 64 #include <sys/x86_archext.h>
65 65 #include <sys/auxv.h>
66 66 #include <sys/auxv_386.h>
67 67 #include <sys/dtrace.h>
68 68 #include <sys/brand.h>
69 69 #include <sys/machbrand.h>
70 70 #include <sys/cmn_err.h>
71 71
72 72 /*
73 73 * Map an fnsave-formatted save area into an fxsave-formatted save area.
74 74 *
75 75 * Most fields are the same width, content and semantics. However
76 76 * the tag word is compressed.
77 77 */
78 78 static void
79 79 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx)
80 80 {
81 81 uint_t i, tagbits;
82 82
83 83 fx->fx_fcw = fn->f_fcw;
84 84 fx->fx_fsw = fn->f_fsw;
85 85
86 86 /*
87 87 * copy element by element (because of holes)
88 88 */
89 89 for (i = 0; i < 8; i++)
90 90 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0],
91 91 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
92 92
93 93 /*
94 94 * synthesize compressed tag bits
95 95 */
96 96 fx->fx_fctw = 0;
97 97 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2)
98 98 if ((tagbits & 3) != 3)
99 99 fx->fx_fctw |= (1 << i);
100 100
101 101 fx->fx_fop = fn->f_fop;
102 102
103 103 fx->fx_rip = (uint64_t)fn->f_eip;
104 104 fx->fx_rdp = (uint64_t)fn->f_dp;
105 105 }
106 106
107 107 /*
108 108 * Map from an fxsave-format save area to an fnsave-format save area.
109 109 */
110 110 static void
111 111 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn)
112 112 {
113 113 uint_t i, top, tagbits;
114 114
115 115 fn->f_fcw = fx->fx_fcw;
116 116 fn->__f_ign0 = 0;
117 117 fn->f_fsw = fx->fx_fsw;
118 118 fn->__f_ign1 = 0;
119 119
120 120 top = (fx->fx_fsw & FPS_TOP) >> 11;
121 121
122 122 /*
123 123 * copy element by element (because of holes)
124 124 */
125 125 for (i = 0; i < 8; i++)
126 126 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0],
127 127 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
128 128
129 129 /*
130 130 * synthesize uncompressed tag bits
131 131 */
132 132 fn->f_ftw = 0;
133 133 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) {
134 134 uint_t ibit, expo;
135 135 const uint16_t *fpp;
136 136 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 };
137 137
138 138 if ((tagbits & 1) == 0) {
139 139 fn->f_ftw |= 3 << (i << 1); /* empty */
140 140 continue;
141 141 }
142 142
143 143 /*
144 144 * (tags refer to *physical* registers)
145 145 */
146 146 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0];
147 147 ibit = fpp[3] >> 15;
148 148 expo = fpp[4] & 0x7fff;
149 149
150 150 if (ibit && expo != 0 && expo != 0x7fff)
151 151 continue; /* valid fp number */
152 152
153 153 if (bcmp(fpp, &zero, sizeof (zero)))
154 154 fn->f_ftw |= 2 << (i << 1); /* NaN */
155 155 else
156 156 fn->f_ftw |= 1 << (i << 1); /* fp zero */
157 157 }
158 158
159 159 fn->f_fop = fx->fx_fop;
160 160
161 161 fn->__f_ign2 = 0;
162 162 fn->f_eip = (uint32_t)fx->fx_rip;
163 163 fn->f_cs = U32CS_SEL;
164 164 fn->f_dp = (uint32_t)fx->fx_rdp;
165 165 fn->f_ds = UDS_SEL;
166 166 fn->__f_ign3 = 0;
167 167 }
168 168
169 169 /*
170 170 * Map from an fpregset_t into an fxsave-format save area
171 171 */
172 172 static void
173 173 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx)
174 174 {
175 175 bcopy(fp, fx, sizeof (*fx));
176 176 /*
177 177 * avoid useless #gp exceptions - mask reserved bits
178 178 */
179 179 fx->fx_mxcsr &= sse_mxcsr_mask;
180 180 }
181 181
182 182 /*
183 183 * Map from an fxsave-format save area into a fpregset_t
184 184 */
185 185 static void
186 186 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp)
187 187 {
188 188 bcopy(fx, fp, sizeof (*fx));
189 189 }
190 190
191 191 #if defined(_SYSCALL32_IMPL)
192 192 static void
193 193 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx)
194 194 {
195 195 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
196 196
197 197 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
198 198 /*
199 199 * avoid useless #gp exceptions - mask reserved bits
200 200 */
201 201 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr;
202 202 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
203 203 }
204 204
205 205 static void
206 206 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp)
207 207 {
208 208 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
209 209
210 210 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
211 211 fc->mxcsr = fx->fx_mxcsr;
212 212 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
213 213 }
214 214
215 215 static void
216 216 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst)
217 217 {
218 218 fxsave_to_fpregset32((struct fxsave_state *)src, dst);
219 219 dst->fp_reg_set.fpchip_state.status =
220 220 src->fp_reg_set.fpchip_state.status;
221 221 dst->fp_reg_set.fpchip_state.xstatus =
222 222 src->fp_reg_set.fpchip_state.xstatus;
223 223 }
224 224
225 225 static void
226 226 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst)
227 227 {
228 228 fpregset32_to_fxsave(src, (struct fxsave_state *)dst);
229 229 dst->fp_reg_set.fpchip_state.status =
230 230 src->fp_reg_set.fpchip_state.status;
231 231 dst->fp_reg_set.fpchip_state.xstatus =
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232 232 src->fp_reg_set.fpchip_state.xstatus;
233 233 }
234 234 #endif
235 235
236 236 /*
237 237 * Set floating-point registers from a native fpregset_t.
238 238 */
239 239 void
240 240 setfpregs(klwp_t *lwp, fpregset_t *fp)
241 241 {
242 - struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
243 -
244 - if (fpu->fpu_flags & FPU_EN) {
245 - if (!(fpu->fpu_flags & FPU_VALID)) {
246 - /*
247 - * FPU context is still active, release the
248 - * ownership.
249 - */
250 - fp_free(fpu);
251 - }
252 - }
253 - /*
254 - * Else: if we are trying to change the FPU state of a thread which
255 - * hasn't yet initialized floating point, store the state in
256 - * the pcb and indicate that the state is valid. When the
257 - * thread enables floating point, it will use this state instead
258 - * of the default state.
259 - */
260 -
261 - switch (fp_save_mech) {
262 - case FP_FXSAVE:
263 - fpregset_to_fxsave(fp, fpu->fpu_regs.kfpu_u.kfpu_fx);
264 - fpu->fpu_regs.kfpu_xstatus =
265 - fp->fp_reg_set.fpchip_state.xstatus;
266 - break;
267 -
268 - case FP_XSAVE:
269 - fpregset_to_fxsave(fp,
270 - &fpu->fpu_regs.kfpu_u.kfpu_xs->xs_fxsave);
271 - fpu->fpu_regs.kfpu_xstatus =
272 - fp->fp_reg_set.fpchip_state.xstatus;
273 - fpu->fpu_regs.kfpu_u.kfpu_xs->xs_header.xsh_xstate_bv |=
274 - (XFEATURE_LEGACY_FP | XFEATURE_SSE);
275 - break;
276 - default:
277 - panic("Invalid fp_save_mech");
278 - /*NOTREACHED*/
279 - }
280 -
281 - fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status;
282 - fpu->fpu_flags |= FPU_VALID;
283 - PCB_SET_UPDATE_FPU(&lwp->lwp_pcb);
242 + fpu_set_fpregset(lwp, fp);
284 243 }
285 244
286 245 /*
287 246 * Get floating-point registers into a native fpregset_t.
288 247 */
289 248 void
290 249 getfpregs(klwp_t *lwp, fpregset_t *fp)
291 250 {
292 - struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
293 -
294 - kpreempt_disable();
295 - if (fpu->fpu_flags & FPU_EN) {
296 - /*
297 - * If we have FPU hw and the thread's pcb doesn't have
298 - * a valid FPU state then get the state from the hw.
299 - */
300 - if (fpu_exists && ttolwp(curthread) == lwp &&
301 - !(fpu->fpu_flags & FPU_VALID))
302 - fp_save(fpu); /* get the current FPU state */
303 - }
304 -
305 - /*
306 - * There are 3 possible cases we have to be aware of here:
307 - *
308 - * 1. FPU is enabled. FPU state is stored in the current LWP.
309 - *
310 - * 2. FPU is not enabled, and there have been no intervening /proc
311 - * modifications. Return initial FPU state.
312 - *
313 - * 3. FPU is not enabled, but a /proc consumer has modified FPU state.
314 - * FPU state is stored in the current LWP.
315 - */
316 - if ((fpu->fpu_flags & FPU_EN) || (fpu->fpu_flags & FPU_VALID)) {
317 - /*
318 - * Cases 1 and 3.
319 - */
320 - switch (fp_save_mech) {
321 - case FP_FXSAVE:
322 - fxsave_to_fpregset(fpu->fpu_regs.kfpu_u.kfpu_fx, fp);
323 - fp->fp_reg_set.fpchip_state.xstatus =
324 - fpu->fpu_regs.kfpu_xstatus;
325 - break;
326 - case FP_XSAVE:
327 - fxsave_to_fpregset(
328 - &fpu->fpu_regs.kfpu_u.kfpu_xs->xs_fxsave, fp);
329 - fp->fp_reg_set.fpchip_state.xstatus =
330 - fpu->fpu_regs.kfpu_xstatus;
331 - break;
332 - default:
333 - panic("Invalid fp_save_mech");
334 - /*NOTREACHED*/
335 - }
336 - fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
337 - } else {
338 - /*
339 - * Case 2.
340 - */
341 - switch (fp_save_mech) {
342 - case FP_FXSAVE:
343 - case FP_XSAVE:
344 - /*
345 - * For now, we don't have any AVX specific field in ABI.
346 - * If we add any in the future, we need to initial them
347 - * as well.
348 - */
349 - fxsave_to_fpregset(&sse_initial, fp);
350 - fp->fp_reg_set.fpchip_state.xstatus =
351 - fpu->fpu_regs.kfpu_xstatus;
352 - break;
353 - default:
354 - panic("Invalid fp_save_mech");
355 - /*NOTREACHED*/
356 - }
357 - fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
358 - }
359 - kpreempt_enable();
251 + bzero(fp, sizeof (*fp));
252 + fpu_get_fpregset(lwp, fp);
360 253 }
361 254
362 255 #if defined(_SYSCALL32_IMPL)
363 256
364 257 /*
365 258 * Set floating-point registers from an fpregset32_t.
366 259 */
367 260 void
368 261 setfpregs32(klwp_t *lwp, fpregset32_t *fp)
369 262 {
370 263 fpregset_t fpregs;
371 264
372 265 fpregset_32ton(fp, &fpregs);
373 266 setfpregs(lwp, &fpregs);
374 267 }
375 268
376 269 /*
377 270 * Get floating-point registers into an fpregset32_t.
378 271 */
379 272 void
380 273 getfpregs32(klwp_t *lwp, fpregset32_t *fp)
381 274 {
382 275 fpregset_t fpregs;
383 276
384 277 getfpregs(lwp, &fpregs);
385 278 fpregset_nto32(&fpregs, fp);
386 279 }
387 280
388 281 #endif /* _SYSCALL32_IMPL */
389 282
390 283 /*
391 284 * Return the general registers
392 285 */
393 286 void
394 287 getgregs(klwp_t *lwp, gregset_t grp)
395 288 {
396 289 struct regs *rp = lwptoregs(lwp);
397 290 struct pcb *pcb = &lwp->lwp_pcb;
398 291 int thisthread = lwptot(lwp) == curthread;
399 292
400 293 grp[REG_RDI] = rp->r_rdi;
401 294 grp[REG_RSI] = rp->r_rsi;
402 295 grp[REG_RDX] = rp->r_rdx;
403 296 grp[REG_RCX] = rp->r_rcx;
404 297 grp[REG_R8] = rp->r_r8;
405 298 grp[REG_R9] = rp->r_r9;
406 299 grp[REG_RAX] = rp->r_rax;
407 300 grp[REG_RBX] = rp->r_rbx;
408 301 grp[REG_RBP] = rp->r_rbp;
409 302 grp[REG_R10] = rp->r_r10;
410 303 grp[REG_R11] = rp->r_r11;
411 304 grp[REG_R12] = rp->r_r12;
412 305 grp[REG_R13] = rp->r_r13;
413 306 grp[REG_R14] = rp->r_r14;
414 307 grp[REG_R15] = rp->r_r15;
415 308 grp[REG_FSBASE] = pcb->pcb_fsbase;
416 309 grp[REG_GSBASE] = pcb->pcb_gsbase;
417 310 if (thisthread)
418 311 kpreempt_disable();
419 312 if (PCB_NEED_UPDATE_SEGS(pcb)) {
420 313 grp[REG_DS] = pcb->pcb_ds;
421 314 grp[REG_ES] = pcb->pcb_es;
422 315 grp[REG_FS] = pcb->pcb_fs;
423 316 grp[REG_GS] = pcb->pcb_gs;
424 317 } else {
425 318 grp[REG_DS] = rp->r_ds;
426 319 grp[REG_ES] = rp->r_es;
427 320 grp[REG_FS] = rp->r_fs;
428 321 grp[REG_GS] = rp->r_gs;
429 322 }
430 323 if (thisthread)
431 324 kpreempt_enable();
432 325 grp[REG_TRAPNO] = rp->r_trapno;
433 326 grp[REG_ERR] = rp->r_err;
434 327 grp[REG_RIP] = rp->r_rip;
435 328 grp[REG_CS] = rp->r_cs;
436 329 grp[REG_SS] = rp->r_ss;
437 330 grp[REG_RFL] = rp->r_rfl;
438 331 grp[REG_RSP] = rp->r_rsp;
439 332 }
440 333
441 334 #if defined(_SYSCALL32_IMPL)
442 335
443 336 void
444 337 getgregs32(klwp_t *lwp, gregset32_t grp)
445 338 {
446 339 struct regs *rp = lwptoregs(lwp);
447 340 struct pcb *pcb = &lwp->lwp_pcb;
448 341 int thisthread = lwptot(lwp) == curthread;
449 342
450 343 if (thisthread)
451 344 kpreempt_disable();
452 345 if (PCB_NEED_UPDATE_SEGS(pcb)) {
453 346 grp[GS] = (uint16_t)pcb->pcb_gs;
454 347 grp[FS] = (uint16_t)pcb->pcb_fs;
455 348 grp[DS] = (uint16_t)pcb->pcb_ds;
456 349 grp[ES] = (uint16_t)pcb->pcb_es;
457 350 } else {
458 351 grp[GS] = (uint16_t)rp->r_gs;
459 352 grp[FS] = (uint16_t)rp->r_fs;
460 353 grp[DS] = (uint16_t)rp->r_ds;
461 354 grp[ES] = (uint16_t)rp->r_es;
462 355 }
463 356 if (thisthread)
464 357 kpreempt_enable();
465 358 grp[EDI] = (greg32_t)rp->r_rdi;
466 359 grp[ESI] = (greg32_t)rp->r_rsi;
467 360 grp[EBP] = (greg32_t)rp->r_rbp;
468 361 grp[ESP] = 0;
469 362 grp[EBX] = (greg32_t)rp->r_rbx;
470 363 grp[EDX] = (greg32_t)rp->r_rdx;
471 364 grp[ECX] = (greg32_t)rp->r_rcx;
472 365 grp[EAX] = (greg32_t)rp->r_rax;
473 366 grp[TRAPNO] = (greg32_t)rp->r_trapno;
474 367 grp[ERR] = (greg32_t)rp->r_err;
475 368 grp[EIP] = (greg32_t)rp->r_rip;
476 369 grp[CS] = (uint16_t)rp->r_cs;
477 370 grp[EFL] = (greg32_t)rp->r_rfl;
478 371 grp[UESP] = (greg32_t)rp->r_rsp;
479 372 grp[SS] = (uint16_t)rp->r_ss;
480 373 }
481 374
482 375 void
483 376 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst)
484 377 {
485 378 mcontext_t *dmc = &dst->uc_mcontext;
486 379 const mcontext32_t *smc = &src->uc_mcontext;
487 380
488 381 bzero(dst, sizeof (*dst));
489 382 dst->uc_flags = src->uc_flags;
490 383 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link;
491 384
492 385 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask));
493 386
494 387 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp;
495 388 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size;
496 389 dst->uc_stack.ss_flags = src->uc_stack.ss_flags;
497 390
498 391 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS];
499 392 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS];
500 393 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES];
501 394 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS];
502 395 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI];
503 396 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI];
504 397 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP];
505 398 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX];
506 399 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX];
507 400 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX];
508 401 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX];
509 402 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO];
510 403 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR];
511 404 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP];
512 405 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS];
513 406 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL];
514 407 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP];
515 408 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS];
516 409
517 410 /*
518 411 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set
519 412 * otherwise there is no guarantee that anything in fpregs is valid.
520 413 */
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521 414 if (src->uc_flags & UC_FPU)
522 415 fpregset_32ton(&src->uc_mcontext.fpregs,
523 416 &dst->uc_mcontext.fpregs);
524 417
525 418 /*
526 419 * Copy the brand-private data:
527 420 */
528 421 dst->uc_brand_data[0] = (void *)(uintptr_t)src->uc_brand_data[0];
529 422 dst->uc_brand_data[1] = (void *)(uintptr_t)src->uc_brand_data[1];
530 423 dst->uc_brand_data[2] = (void *)(uintptr_t)src->uc_brand_data[2];
424 +
425 + if (src->uc_flags & UC_XSAVE) {
426 + dst->uc_xsave = (long)(uint32_t)src->uc_xsave;
427 + } else {
428 + dst->uc_xsave = 0;
429 + }
531 430 }
532 431
533 432 #endif /* _SYSCALL32_IMPL */
534 433
535 434 /*
536 435 * Return the user-level PC.
537 436 * If in a system call, return the address of the syscall trap.
538 437 */
539 438 greg_t
540 -getuserpc()
439 +getuserpc(void)
541 440 {
542 441 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc;
543 442 uint32_t insn;
544 443
545 444 if (curthread->t_sysnum == 0)
546 445 return (upc);
547 446
548 447 /*
549 448 * We might've gotten here from sysenter (0xf 0x34),
550 449 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0).
551 450 *
552 451 * Go peek at the binary to figure it out..
553 452 */
554 453 if (fuword32((void *)(upc - 2), &insn) != -1 &&
555 454 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f)
556 455 return (upc - 2);
557 456 return (upc - 7);
558 457 }
559 458
560 459 /*
561 460 * Protect segment registers from non-user privilege levels and GDT selectors
562 461 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment
563 462 * selector is non-null and not USER_CS/USER_DS, we make sure that the
564 463 * TI bit is set to point into the LDT and that the RPL is set to 3.
565 464 *
566 465 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we
567 466 * also explicitly zero the top 16 bits since they may be coming from the
568 467 * user's address space via setcontext(2) or /proc.
569 468 *
570 469 * Note about null selector. When running on the hypervisor if we allow a
571 470 * process to set its %cs to null selector with RPL of 0 the hypervisor will
572 471 * crash the domain. If running on bare metal we would get a #gp fault and
573 472 * be able to kill the process and continue on. Therefore we make sure to
574 473 * force RPL to SEL_UPL even for null selector when setting %cs.
575 474 */
576 475
577 476 #if defined(IS_CS) || defined(IS_NOT_CS)
578 477 #error "IS_CS and IS_NOT_CS already defined"
579 478 #endif
580 479
581 480 #define IS_CS 1
582 481 #define IS_NOT_CS 0
583 482
584 483 /*ARGSUSED*/
585 484 greg_t
586 485 fix_segreg(greg_t sr, int iscs, model_t datamodel)
587 486 {
588 487 kthread_t *t = curthread;
589 488
590 489 switch (sr &= 0xffff) {
591 490
592 491 case 0:
593 492 if (iscs == IS_CS)
594 493 return (0 | SEL_UPL);
595 494 else
596 495 return (0);
597 496
598 497 /*
599 498 * If lwp attempts to switch data model then force their
600 499 * code selector to be null selector.
601 500 */
602 501 case U32CS_SEL:
603 502 if (datamodel == DATAMODEL_NATIVE)
604 503 return (0 | SEL_UPL);
605 504 else
606 505 return (sr);
607 506
608 507 case UCS_SEL:
609 508 if (datamodel == DATAMODEL_ILP32)
610 509 return (0 | SEL_UPL);
611 510 /*FALLTHROUGH*/
612 511 case UDS_SEL:
613 512 case LWPFS_SEL:
614 513 case LWPGS_SEL:
615 514 case SEL_UPL:
616 515 return (sr);
617 516 default:
618 517 break;
619 518 }
620 519
621 520 /*
622 521 * Allow this process's brand to do any necessary segment register
623 522 * manipulation.
624 523 */
625 524 if (PROC_IS_BRANDED(t->t_procp) && BRMOP(t->t_procp)->b_fixsegreg) {
626 525 greg_t bsr = BRMOP(t->t_procp)->b_fixsegreg(sr, datamodel);
627 526
628 527 if (bsr == 0 && iscs == IS_CS)
629 528 return (0 | SEL_UPL);
630 529 else
631 530 return (bsr);
632 531 }
633 532
634 533 /*
635 534 * Force it into the LDT in ring 3 for 32-bit processes, which by
636 535 * default do not have an LDT, so that any attempt to use an invalid
637 536 * selector will reference the (non-existant) LDT, and cause a #gp
638 537 * fault for the process.
639 538 *
640 539 * 64-bit processes get the null gdt selector since they
641 540 * are not allowed to have a private LDT.
642 541 */
643 542 if (datamodel == DATAMODEL_ILP32) {
644 543 return (sr | SEL_TI_LDT | SEL_UPL);
645 544 } else {
646 545 if (iscs == IS_CS)
647 546 return (0 | SEL_UPL);
648 547 else
649 548 return (0);
650 549 }
651 550
652 551 }
653 552
654 553 /*
655 554 * Set general registers.
656 555 */
657 556 void
658 557 setgregs(klwp_t *lwp, gregset_t grp)
659 558 {
660 559 struct regs *rp = lwptoregs(lwp);
661 560 model_t datamodel = lwp_getdatamodel(lwp);
662 561
663 562 struct pcb *pcb = &lwp->lwp_pcb;
664 563 int thisthread = lwptot(lwp) == curthread;
665 564
666 565 if (datamodel == DATAMODEL_NATIVE) {
667 566 if (thisthread)
668 567 (void) save_syscall_args(); /* copy the args */
669 568
670 569 rp->r_rdi = grp[REG_RDI];
671 570 rp->r_rsi = grp[REG_RSI];
672 571 rp->r_rdx = grp[REG_RDX];
673 572 rp->r_rcx = grp[REG_RCX];
674 573 rp->r_r8 = grp[REG_R8];
675 574 rp->r_r9 = grp[REG_R9];
676 575 rp->r_rax = grp[REG_RAX];
677 576 rp->r_rbx = grp[REG_RBX];
678 577 rp->r_rbp = grp[REG_RBP];
679 578 rp->r_r10 = grp[REG_R10];
680 579 rp->r_r11 = grp[REG_R11];
681 580 rp->r_r12 = grp[REG_R12];
682 581 rp->r_r13 = grp[REG_R13];
683 582 rp->r_r14 = grp[REG_R14];
684 583 rp->r_r15 = grp[REG_R15];
685 584 rp->r_trapno = grp[REG_TRAPNO];
686 585 rp->r_err = grp[REG_ERR];
687 586 rp->r_rip = grp[REG_RIP];
688 587 /*
689 588 * Setting %cs or %ss to anything else is quietly but
690 589 * quite definitely forbidden!
691 590 */
692 591 rp->r_cs = UCS_SEL;
693 592 rp->r_ss = UDS_SEL;
694 593 rp->r_rsp = grp[REG_RSP];
695 594
696 595 if (thisthread)
697 596 kpreempt_disable();
698 597
699 598 pcb->pcb_ds = UDS_SEL;
700 599 pcb->pcb_es = UDS_SEL;
701 600
702 601 /*
703 602 * 64-bit processes -are- allowed to set their fsbase/gsbase
704 603 * values directly, but only if they're using the segment
705 604 * selectors that allow that semantic.
706 605 *
707 606 * (32-bit processes must use lwp_set_private().)
708 607 */
709 608 pcb->pcb_fsbase = grp[REG_FSBASE];
710 609 pcb->pcb_gsbase = grp[REG_GSBASE];
711 610 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
712 611 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
713 612
714 613 /*
715 614 * Ensure that we go out via update_sregs
716 615 */
717 616 PCB_SET_UPDATE_SEGS(pcb);
718 617 lwptot(lwp)->t_post_sys = 1;
719 618 if (thisthread)
720 619 kpreempt_enable();
721 620 #if defined(_SYSCALL32_IMPL)
722 621 } else {
723 622 rp->r_rdi = (uint32_t)grp[REG_RDI];
724 623 rp->r_rsi = (uint32_t)grp[REG_RSI];
725 624 rp->r_rdx = (uint32_t)grp[REG_RDX];
726 625 rp->r_rcx = (uint32_t)grp[REG_RCX];
727 626 rp->r_rax = (uint32_t)grp[REG_RAX];
728 627 rp->r_rbx = (uint32_t)grp[REG_RBX];
729 628 rp->r_rbp = (uint32_t)grp[REG_RBP];
730 629 rp->r_trapno = (uint32_t)grp[REG_TRAPNO];
731 630 rp->r_err = (uint32_t)grp[REG_ERR];
732 631 rp->r_rip = (uint32_t)grp[REG_RIP];
733 632
734 633 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel);
735 634 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
736 635
737 636 rp->r_rsp = (uint32_t)grp[REG_RSP];
738 637
739 638 if (thisthread)
740 639 kpreempt_disable();
741 640
742 641 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
743 642 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel);
744 643
745 644 /*
746 645 * (See fsbase/gsbase commentary above)
747 646 */
748 647 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
749 648 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
750 649
751 650 /*
752 651 * Ensure that we go out via update_sregs
753 652 */
754 653 PCB_SET_UPDATE_SEGS(pcb);
755 654 lwptot(lwp)->t_post_sys = 1;
756 655 if (thisthread)
757 656 kpreempt_enable();
758 657 #endif
759 658 }
760 659
761 660 /*
762 661 * Only certain bits of the flags register can be modified.
763 662 */
764 663 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) |
765 664 (grp[REG_RFL] & PSL_USERMASK);
766 665 }
767 666
768 667 /*
769 668 * Determine whether eip is likely to have an interrupt frame
770 669 * on the stack. We do this by comparing the address to the
771 670 * range of addresses spanned by several well-known routines.
772 671 */
773 672 extern void _interrupt();
774 673 extern void _allsyscalls();
775 674 extern void _cmntrap();
776 675 extern void fakesoftint();
777 676
778 677 extern size_t _interrupt_size;
779 678 extern size_t _allsyscalls_size;
780 679 extern size_t _cmntrap_size;
781 680 extern size_t _fakesoftint_size;
782 681
783 682 /*
784 683 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking.
785 684 * Returns MIN(current stack depth, pcstack_limit).
786 685 */
787 686 int
788 687 getpcstack(pc_t *pcstack, int pcstack_limit)
789 688 {
790 689 struct frame *fp = (struct frame *)getfp();
791 690 struct frame *nextfp, *minfp, *stacktop;
792 691 int depth = 0;
793 692 int on_intr;
794 693 uintptr_t pc;
795 694
796 695 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
797 696 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
798 697 else
799 698 stacktop = (struct frame *)curthread->t_stk;
800 699 minfp = fp;
801 700
802 701 pc = ((struct regs *)fp)->r_pc;
803 702
804 703 while (depth < pcstack_limit) {
805 704 nextfp = (struct frame *)fp->fr_savfp;
806 705 pc = fp->fr_savpc;
807 706 if (nextfp <= minfp || nextfp >= stacktop) {
808 707 if (on_intr) {
809 708 /*
810 709 * Hop from interrupt stack to thread stack.
811 710 */
812 711 stacktop = (struct frame *)curthread->t_stk;
813 712 minfp = (struct frame *)curthread->t_stkbase;
814 713 on_intr = 0;
815 714 continue;
816 715 }
817 716 break;
818 717 }
819 718 pcstack[depth++] = (pc_t)pc;
820 719 fp = nextfp;
821 720 minfp = fp;
822 721 }
823 722 return (depth);
824 723 }
825 724
826 725 /*
827 726 * The following ELF header fields are defined as processor-specific
828 727 * in the V8 ABI:
829 728 *
830 729 * e_ident[EI_DATA] encoding of the processor-specific
831 730 * data in the object file
832 731 * e_machine processor identification
833 732 * e_flags processor-specific flags associated
834 733 * with the file
835 734 */
836 735
837 736 /*
838 737 * The value of at_flags reflects a platform's cpu module support.
839 738 * at_flags is used to check for allowing a binary to execute and
840 739 * is passed as the value of the AT_FLAGS auxiliary vector.
841 740 */
842 741 int at_flags = 0;
843 742
844 743 /*
845 744 * Check the processor-specific fields of an ELF header.
846 745 *
847 746 * returns 1 if the fields are valid, 0 otherwise
848 747 */
849 748 /*ARGSUSED2*/
850 749 int
851 750 elfheadcheck(
852 751 unsigned char e_data,
853 752 Elf32_Half e_machine,
854 753 Elf32_Word e_flags)
855 754 {
856 755 if (e_data != ELFDATA2LSB)
857 756 return (0);
858 757 if (e_machine == EM_AMD64)
859 758 return (1);
860 759 return (e_machine == EM_386);
861 760 }
862 761
863 762 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */
864 763 uint_t auxv_hwcap_include_2 = 0; /* second word */
865 764 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */
866 765 uint_t auxv_hwcap_exclude_2 = 0; /* second word */
867 766 #if defined(_SYSCALL32_IMPL)
868 767 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */
869 768 uint_t auxv_hwcap32_include_2 = 0; /* ditto for 32-bit apps */
870 769 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */
871 770 uint_t auxv_hwcap32_exclude_2 = 0; /* ditto for 32-bit apps */
872 771 #endif
873 772
874 773 /*
875 774 * Gather information about the processor and place it into auxv_hwcap
876 775 * so that it can be exported to the linker via the aux vector.
877 776 *
878 777 * We use this seemingly complicated mechanism so that we can ensure
879 778 * that /etc/system can be used to override what the system can or
880 779 * cannot discover for itself. Due to a lack of use, this has not
881 780 * been extended to the 3rd word.
882 781 */
883 782 void
884 783 bind_hwcap(void)
885 784 {
886 785 uint_t cpu_hwcap_flags[3];
887 786 cpuid_execpass(NULL, CPUID_PASS_RESOLVE, cpu_hwcap_flags);
888 787
889 788 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags[0]) &
890 789 ~auxv_hwcap_exclude;
891 790 auxv_hwcap_2 = (auxv_hwcap_include_2 | cpu_hwcap_flags[1]) &
892 791 ~auxv_hwcap_exclude_2;
893 792 auxv_hwcap_3 = cpu_hwcap_flags[2];
894 793
895 794 /*
896 795 * On AMD processors, sysenter just doesn't work at all
897 796 * when the kernel is in long mode. On IA-32e processors
898 797 * it does, but there's no real point in all the alternate
899 798 * mechanism when syscall works on both.
900 799 *
901 800 * Besides, the kernel's sysenter handler is expecting a
902 801 * 32-bit lwp ...
903 802 */
904 803 auxv_hwcap &= ~AV_386_SEP;
905 804
906 805 if (auxv_hwcap_include || auxv_hwcap_exclude || auxv_hwcap_include_2 ||
907 806 auxv_hwcap_exclude_2) {
908 807 /*
909 808 * The below assignment is regrettably required to get lint
910 809 * to accept the validity of our format string. The format
911 810 * string is in fact valid, but whatever intelligence in lint
912 811 * understands the cmn_err()-specific %b appears to have an
913 812 * off-by-one error: it (mistakenly) complains about bit
914 813 * number 32 (even though this is explicitly permitted).
915 814 * Normally, one would will away such warnings with a "LINTED"
916 815 * directive, but for reasons unclear and unknown, lint
917 816 * refuses to be assuaged in this case. Fortunately, lint
918 817 * doesn't pretend to have solved the Halting Problem --
919 818 * and as soon as the format string is programmatic, it
920 819 * knows enough to shut up.
921 820 */
922 821 char *fmt = "?user ABI extensions: %b\n";
923 822 cmn_err(CE_CONT, fmt, auxv_hwcap, FMT_AV_386);
924 823 fmt = "?user ABI extensions (word 2): %b\n";
925 824 cmn_err(CE_CONT, fmt, auxv_hwcap_2, FMT_AV_386_2);
926 825 fmt = "?user ABI extensions (word 2): %b\n";
927 826 cmn_err(CE_CONT, fmt, auxv_hwcap_3, FMT_AV_386_3);
928 827 }
929 828
930 829 #if defined(_SYSCALL32_IMPL)
931 830 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags[0]) &
932 831 ~auxv_hwcap32_exclude;
933 832 auxv_hwcap32_2 = (auxv_hwcap32_include_2 | cpu_hwcap_flags[1]) &
934 833 ~auxv_hwcap32_exclude_2;
935 834 auxv_hwcap32_3 = auxv_hwcap_3;
936 835
937 836 /*
938 837 * If this is an amd64 architecture machine from Intel, then
939 838 * syscall -doesn't- work in compatibility mode, only sysenter does.
940 839 *
941 840 * Sigh.
942 841 */
943 842 if (!cpuid_syscall32_insn(NULL))
944 843 auxv_hwcap32 &= ~AV_386_AMD_SYSC;
945 844
946 845 /*
947 846 * 32-bit processes can -always- use the lahf/sahf instructions
948 847 */
949 848 auxv_hwcap32 |= AV_386_AHF;
950 849
951 850 /*
952 851 * 32-bit processes can -never- use fsgsbase instructions.
953 852 */
954 853 auxv_hwcap32_2 &= ~AV_386_2_FSGSBASE;
955 854
956 855 if (auxv_hwcap32_include || auxv_hwcap32_exclude ||
957 856 auxv_hwcap32_include_2 || auxv_hwcap32_exclude_2) {
958 857 /*
959 858 * See the block comment in the cmn_err() of auxv_hwcap, above.
960 859 */
961 860 char *fmt = "?32-bit user ABI extensions: %b\n";
962 861 cmn_err(CE_CONT, fmt, auxv_hwcap32, FMT_AV_386);
963 862 fmt = "?32-bit user ABI extensions (word 2): %b\n";
964 863 cmn_err(CE_CONT, fmt, auxv_hwcap32_2, FMT_AV_386_2);
965 864 fmt = "?32-bit user ABI extensions (word 3): %b\n";
966 865 cmn_err(CE_CONT, fmt, auxv_hwcap32_3, FMT_AV_386_3);
967 866 }
968 867 #endif
969 868 }
970 869
971 870 /*
972 871 * sync_icache() - this is called
973 872 * in proc/fs/prusrio.c. x86 has an unified cache and therefore
974 873 * this is a nop.
975 874 */
976 875 /* ARGSUSED */
977 876 void
978 877 sync_icache(caddr_t addr, uint_t len)
979 878 {
980 879 /* Do nothing for now */
981 880 }
982 881
983 882 /*ARGSUSED*/
984 883 void
985 884 sync_data_memory(caddr_t va, size_t len)
986 885 {
987 886 /* Not implemented for this platform */
988 887 }
989 888
990 889 int
991 890 __ipltospl(int ipl)
992 891 {
993 892 return (ipltospl(ipl));
994 893 }
995 894
996 895 /*
997 896 * The panic code invokes panic_saveregs() to record the contents of a
998 897 * regs structure into the specified panic_data structure for debuggers.
999 898 */
1000 899 void
1001 900 panic_saveregs(panic_data_t *pdp, struct regs *rp)
1002 901 {
1003 902 panic_nv_t *pnv = PANICNVGET(pdp);
1004 903
1005 904 struct cregs creg;
1006 905
1007 906 getcregs(&creg);
1008 907
1009 908 PANICNVADD(pnv, "rdi", rp->r_rdi);
1010 909 PANICNVADD(pnv, "rsi", rp->r_rsi);
1011 910 PANICNVADD(pnv, "rdx", rp->r_rdx);
1012 911 PANICNVADD(pnv, "rcx", rp->r_rcx);
1013 912 PANICNVADD(pnv, "r8", rp->r_r8);
1014 913 PANICNVADD(pnv, "r9", rp->r_r9);
1015 914 PANICNVADD(pnv, "rax", rp->r_rax);
1016 915 PANICNVADD(pnv, "rbx", rp->r_rbx);
1017 916 PANICNVADD(pnv, "rbp", rp->r_rbp);
1018 917 PANICNVADD(pnv, "r10", rp->r_r10);
1019 918 PANICNVADD(pnv, "r11", rp->r_r11);
1020 919 PANICNVADD(pnv, "r12", rp->r_r12);
1021 920 PANICNVADD(pnv, "r13", rp->r_r13);
1022 921 PANICNVADD(pnv, "r14", rp->r_r14);
1023 922 PANICNVADD(pnv, "r15", rp->r_r15);
1024 923 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE));
1025 924 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE));
1026 925 PANICNVADD(pnv, "ds", rp->r_ds);
1027 926 PANICNVADD(pnv, "es", rp->r_es);
1028 927 PANICNVADD(pnv, "fs", rp->r_fs);
1029 928 PANICNVADD(pnv, "gs", rp->r_gs);
1030 929 PANICNVADD(pnv, "trapno", rp->r_trapno);
1031 930 PANICNVADD(pnv, "err", rp->r_err);
1032 931 PANICNVADD(pnv, "rip", rp->r_rip);
1033 932 PANICNVADD(pnv, "cs", rp->r_cs);
1034 933 PANICNVADD(pnv, "rflags", rp->r_rfl);
1035 934 PANICNVADD(pnv, "rsp", rp->r_rsp);
1036 935 PANICNVADD(pnv, "ss", rp->r_ss);
1037 936 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3]));
1038 937 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0]));
1039 938 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3]));
1040 939 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0]));
1041 940
1042 941 PANICNVADD(pnv, "ldt", creg.cr_ldt);
1043 942 PANICNVADD(pnv, "task", creg.cr_task);
1044 943 PANICNVADD(pnv, "cr0", creg.cr_cr0);
1045 944 PANICNVADD(pnv, "cr2", creg.cr_cr2);
1046 945 PANICNVADD(pnv, "cr3", creg.cr_cr3);
1047 946 if (creg.cr_cr4)
1048 947 PANICNVADD(pnv, "cr4", creg.cr_cr4);
1049 948
1050 949 PANICNVSET(pdp, pnv);
1051 950 }
1052 951
1053 952 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */
1054 953
1055 954
1056 955 /*
1057 956 * Print a stack backtrace using the specified frame pointer. We delay two
1058 957 * seconds before continuing, unless this is the panic traceback.
1059 958 * If we are in the process of panicking, we also attempt to write the
1060 959 * stack backtrace to a staticly assigned buffer, to allow the panic
1061 960 * code to find it and write it in to uncompressed pages within the
1062 961 * system crash dump.
1063 962 * Note that the frame for the starting stack pointer value is omitted because
1064 963 * the corresponding %eip is not known.
1065 964 */
1066 965
1067 966 extern char *dump_stack_scratch;
1068 967
1069 968
1070 969 void
1071 970 traceback(caddr_t fpreg)
1072 971 {
1073 972 struct frame *fp = (struct frame *)fpreg;
1074 973 struct frame *nextfp;
1075 974 uintptr_t pc, nextpc;
1076 975 ulong_t off;
1077 976 char args[TR_ARG_MAX * 2 + 16], *sym;
1078 977 uint_t offset = 0;
1079 978 uint_t next_offset = 0;
1080 979 char stack_buffer[1024];
1081 980
1082 981 if (!panicstr)
1083 982 printf("traceback: %%fp = %p\n", (void *)fp);
1084 983
1085 984 if (panicstr && !dump_stack_scratch) {
1086 985 printf("Warning - stack not written to the dump buffer\n");
1087 986 }
1088 987
1089 988 fp = (struct frame *)plat_traceback(fpreg);
1090 989 if ((uintptr_t)fp < KERNELBASE)
1091 990 goto out;
1092 991
1093 992 pc = fp->fr_savpc;
1094 993 fp = (struct frame *)fp->fr_savfp;
1095 994
1096 995 while ((uintptr_t)fp >= KERNELBASE) {
1097 996 /*
1098 997 * XX64 Until port is complete tolerate 8-byte aligned
1099 998 * frame pointers but flag with a warning so they can
1100 999 * be fixed.
1101 1000 */
1102 1001 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) {
1103 1002 if (((uintptr_t)fp & (8 - 1)) == 0) {
1104 1003 printf(" >> warning! 8-byte"
1105 1004 " aligned %%fp = %p\n", (void *)fp);
1106 1005 } else {
1107 1006 printf(
1108 1007 " >> mis-aligned %%fp = %p\n", (void *)fp);
1109 1008 break;
1110 1009 }
1111 1010 }
1112 1011
1113 1012 args[0] = '\0';
1114 1013 nextpc = (uintptr_t)fp->fr_savpc;
1115 1014 nextfp = (struct frame *)fp->fr_savfp;
1116 1015 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
1117 1016 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
1118 1017 mod_containing_pc((caddr_t)pc), sym, off, args);
1119 1018 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1120 1019 "%s:%s+%lx (%s) | ",
1121 1020 mod_containing_pc((caddr_t)pc), sym, off, args);
1122 1021 } else {
1123 1022 printf("%016lx %lx (%s)\n",
1124 1023 (uintptr_t)fp, pc, args);
1125 1024 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1126 1025 "%lx (%s) | ", pc, args);
1127 1026 }
1128 1027
1129 1028 if (panicstr && dump_stack_scratch) {
1130 1029 next_offset = offset + strlen(stack_buffer);
1131 1030 if (next_offset < STACK_BUF_SIZE) {
1132 1031 bcopy(stack_buffer, dump_stack_scratch + offset,
1133 1032 strlen(stack_buffer));
1134 1033 offset = next_offset;
1135 1034 } else {
1136 1035 /*
1137 1036 * In attempting to save the panic stack
1138 1037 * to the dumpbuf we have overflowed that area.
1139 1038 * Print a warning and continue to printf the
1140 1039 * stack to the msgbuf
1141 1040 */
1142 1041 printf("Warning: stack in the dump buffer"
1143 1042 " may be incomplete\n");
1144 1043 offset = next_offset;
1145 1044 }
1146 1045 }
1147 1046
1148 1047 pc = nextpc;
1149 1048 fp = nextfp;
1150 1049 }
1151 1050 out:
1152 1051 if (!panicstr) {
1153 1052 printf("end of traceback\n");
1154 1053 DELAY(2 * MICROSEC);
1155 1054 } else if (dump_stack_scratch) {
1156 1055 dump_stack_scratch[offset] = '\0';
1157 1056 }
1158 1057 }
1159 1058
1160 1059
1161 1060 /*
1162 1061 * Generate a stack backtrace from a saved register set.
1163 1062 */
1164 1063 void
1165 1064 traceregs(struct regs *rp)
1166 1065 {
1167 1066 traceback((caddr_t)rp->r_fp);
1168 1067 }
1169 1068
1170 1069 void
1171 1070 exec_set_sp(size_t stksize)
1172 1071 {
1173 1072 klwp_t *lwp = ttolwp(curthread);
1174 1073
1175 1074 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize;
1176 1075 }
1177 1076
1178 1077 hrtime_t
1179 1078 gethrtime_waitfree(void)
1180 1079 {
1181 1080 return (dtrace_gethrtime());
1182 1081 }
1183 1082
1184 1083 hrtime_t
1185 1084 gethrtime(void)
1186 1085 {
1187 1086 return (gethrtimef());
1188 1087 }
1189 1088
1190 1089 hrtime_t
1191 1090 gethrtime_unscaled(void)
1192 1091 {
1193 1092 return (gethrtimeunscaledf());
1194 1093 }
1195 1094
1196 1095 void
1197 1096 scalehrtime(hrtime_t *hrt)
1198 1097 {
1199 1098 scalehrtimef(hrt);
1200 1099 }
1201 1100
1202 1101 uint64_t
1203 1102 unscalehrtime(hrtime_t nsecs)
1204 1103 {
1205 1104 return (unscalehrtimef(nsecs));
1206 1105 }
1207 1106
1208 1107 void
1209 1108 gethrestime(timespec_t *tp)
1210 1109 {
1211 1110 gethrestimef(tp);
1212 1111 }
1213 1112
1214 1113 /*
1215 1114 * Part of the implementation of hres_tick(); this routine is
1216 1115 * easier in C than assembler .. called with the hres_lock held.
1217 1116 *
1218 1117 * XX64 Many of these timekeeping variables need to be extern'ed in a header
1219 1118 */
1220 1119
1221 1120 #include <sys/time.h>
1222 1121 #include <sys/machlock.h>
1223 1122
1224 1123 extern int one_sec;
1225 1124 extern int max_hres_adj;
1226 1125
1227 1126 void
1228 1127 __adj_hrestime(void)
1229 1128 {
1230 1129 long long adj;
1231 1130
1232 1131 if (hrestime_adj == 0)
1233 1132 adj = 0;
1234 1133 else if (hrestime_adj > 0) {
1235 1134 if (hrestime_adj < max_hres_adj)
1236 1135 adj = hrestime_adj;
1237 1136 else
1238 1137 adj = max_hres_adj;
1239 1138 } else {
1240 1139 if (hrestime_adj < -max_hres_adj)
1241 1140 adj = -max_hres_adj;
1242 1141 else
1243 1142 adj = hrestime_adj;
1244 1143 }
1245 1144
1246 1145 timedelta -= adj;
1247 1146 hrestime_adj = timedelta;
1248 1147 hrestime.tv_nsec += adj;
1249 1148
1250 1149 while (hrestime.tv_nsec >= NANOSEC) {
1251 1150 one_sec++;
1252 1151 hrestime.tv_sec++;
1253 1152 hrestime.tv_nsec -= NANOSEC;
1254 1153 }
1255 1154 }
1256 1155
1257 1156 /*
1258 1157 * Wrapper functions to maintain backwards compability
1259 1158 */
1260 1159 int
1261 1160 xcopyin(const void *uaddr, void *kaddr, size_t count)
1262 1161 {
1263 1162 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED));
1264 1163 }
1265 1164
1266 1165 int
1267 1166 xcopyout(const void *kaddr, void *uaddr, size_t count)
1268 1167 {
1269 1168 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED));
1270 1169 }
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