1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
26 /* All Rights Reserved */
27 /*
28 * Copyright (c) 2018, Joyent, Inc.
29 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
30 * Copyright 2022 Oxide Computer Company
31 */
32
33 #include <sys/param.h>
34 #include <sys/types.h>
35 #include <sys/vmparam.h>
36 #include <sys/systm.h>
37 #include <sys/signal.h>
38 #include <sys/stack.h>
39 #include <sys/regset.h>
40 #include <sys/privregs.h>
41 #include <sys/frame.h>
42 #include <sys/proc.h>
43 #include <sys/psw.h>
44 #include <sys/siginfo.h>
45 #include <sys/cpuvar.h>
46 #include <sys/asm_linkage.h>
47 #include <sys/kmem.h>
48 #include <sys/errno.h>
49 #include <sys/bootconf.h>
50 #include <sys/archsystm.h>
51 #include <sys/debug.h>
52 #include <sys/elf.h>
53 #include <sys/spl.h>
54 #include <sys/time.h>
55 #include <sys/atomic.h>
56 #include <sys/sysmacros.h>
57 #include <sys/cmn_err.h>
58 #include <sys/modctl.h>
59 #include <sys/kobj.h>
60 #include <sys/panic.h>
61 #include <sys/reboot.h>
62 #include <sys/time.h>
63 #include <sys/fp.h>
64 #include <sys/x86_archext.h>
65 #include <sys/auxv.h>
66 #include <sys/auxv_386.h>
67 #include <sys/dtrace.h>
68 #include <sys/brand.h>
69 #include <sys/machbrand.h>
70 #include <sys/cmn_err.h>
71
72 /*
73 * Map an fnsave-formatted save area into an fxsave-formatted save area.
74 *
75 * Most fields are the same width, content and semantics. However
76 * the tag word is compressed.
77 */
78 static void
79 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx)
80 {
81 uint_t i, tagbits;
82
83 fx->fx_fcw = fn->f_fcw;
84 fx->fx_fsw = fn->f_fsw;
85
86 /*
87 * copy element by element (because of holes)
88 */
89 for (i = 0; i < 8; i++)
90 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0],
91 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
92
93 /*
94 * synthesize compressed tag bits
95 */
96 fx->fx_fctw = 0;
97 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2)
98 if ((tagbits & 3) != 3)
99 fx->fx_fctw |= (1 << i);
100
101 fx->fx_fop = fn->f_fop;
102
103 fx->fx_rip = (uint64_t)fn->f_eip;
104 fx->fx_rdp = (uint64_t)fn->f_dp;
105 }
106
107 /*
108 * Map from an fxsave-format save area to an fnsave-format save area.
109 */
110 static void
111 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn)
112 {
113 uint_t i, top, tagbits;
114
115 fn->f_fcw = fx->fx_fcw;
116 fn->__f_ign0 = 0;
117 fn->f_fsw = fx->fx_fsw;
118 fn->__f_ign1 = 0;
119
120 top = (fx->fx_fsw & FPS_TOP) >> 11;
121
122 /*
123 * copy element by element (because of holes)
124 */
125 for (i = 0; i < 8; i++)
126 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0],
127 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
128
129 /*
130 * synthesize uncompressed tag bits
131 */
132 fn->f_ftw = 0;
133 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) {
134 uint_t ibit, expo;
135 const uint16_t *fpp;
136 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 };
137
138 if ((tagbits & 1) == 0) {
139 fn->f_ftw |= 3 << (i << 1); /* empty */
140 continue;
141 }
142
143 /*
144 * (tags refer to *physical* registers)
145 */
146 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0];
147 ibit = fpp[3] >> 15;
148 expo = fpp[4] & 0x7fff;
149
150 if (ibit && expo != 0 && expo != 0x7fff)
151 continue; /* valid fp number */
152
153 if (bcmp(fpp, &zero, sizeof (zero)))
154 fn->f_ftw |= 2 << (i << 1); /* NaN */
155 else
156 fn->f_ftw |= 1 << (i << 1); /* fp zero */
157 }
158
159 fn->f_fop = fx->fx_fop;
160
161 fn->__f_ign2 = 0;
162 fn->f_eip = (uint32_t)fx->fx_rip;
163 fn->f_cs = U32CS_SEL;
164 fn->f_dp = (uint32_t)fx->fx_rdp;
165 fn->f_ds = UDS_SEL;
166 fn->__f_ign3 = 0;
167 }
168
169 /*
170 * Map from an fpregset_t into an fxsave-format save area
171 */
172 static void
173 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx)
174 {
175 bcopy(fp, fx, sizeof (*fx));
176 /*
177 * avoid useless #gp exceptions - mask reserved bits
178 */
179 fx->fx_mxcsr &= sse_mxcsr_mask;
180 }
181
182 /*
183 * Map from an fxsave-format save area into a fpregset_t
184 */
185 static void
186 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp)
187 {
188 bcopy(fx, fp, sizeof (*fx));
189 }
190
191 #if defined(_SYSCALL32_IMPL)
192 static void
193 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx)
194 {
195 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
196
197 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
198 /*
199 * avoid useless #gp exceptions - mask reserved bits
200 */
201 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr;
202 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
203 }
204
205 static void
206 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp)
207 {
208 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
209
210 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
211 fc->mxcsr = fx->fx_mxcsr;
212 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
213 }
214
215 static void
216 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst)
217 {
218 fxsave_to_fpregset32((struct fxsave_state *)src, dst);
219 dst->fp_reg_set.fpchip_state.status =
220 src->fp_reg_set.fpchip_state.status;
221 dst->fp_reg_set.fpchip_state.xstatus =
222 src->fp_reg_set.fpchip_state.xstatus;
223 }
224
225 static void
226 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst)
227 {
228 fpregset32_to_fxsave(src, (struct fxsave_state *)dst);
229 dst->fp_reg_set.fpchip_state.status =
230 src->fp_reg_set.fpchip_state.status;
231 dst->fp_reg_set.fpchip_state.xstatus =
232 src->fp_reg_set.fpchip_state.xstatus;
233 }
234 #endif
235
236 /*
237 * Set floating-point registers from a native fpregset_t.
238 */
239 void
240 setfpregs(klwp_t *lwp, fpregset_t *fp)
241 {
242 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
243
244 if (fpu->fpu_flags & FPU_EN) {
245 if (!(fpu->fpu_flags & FPU_VALID)) {
246 /*
247 * FPU context is still active, release the
248 * ownership.
249 */
250 fp_free(fpu);
251 }
252 }
253 /*
254 * Else: if we are trying to change the FPU state of a thread which
255 * hasn't yet initialized floating point, store the state in
256 * the pcb and indicate that the state is valid. When the
257 * thread enables floating point, it will use this state instead
258 * of the default state.
259 */
260
261 switch (fp_save_mech) {
262 case FP_FXSAVE:
263 fpregset_to_fxsave(fp, fpu->fpu_regs.kfpu_u.kfpu_fx);
264 fpu->fpu_regs.kfpu_xstatus =
265 fp->fp_reg_set.fpchip_state.xstatus;
266 break;
267
268 case FP_XSAVE:
269 fpregset_to_fxsave(fp,
270 &fpu->fpu_regs.kfpu_u.kfpu_xs->xs_fxsave);
271 fpu->fpu_regs.kfpu_xstatus =
272 fp->fp_reg_set.fpchip_state.xstatus;
273 fpu->fpu_regs.kfpu_u.kfpu_xs->xs_header.xsh_xstate_bv |=
274 (XFEATURE_LEGACY_FP | XFEATURE_SSE);
275 break;
276 default:
277 panic("Invalid fp_save_mech");
278 /*NOTREACHED*/
279 }
280
281 fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status;
282 fpu->fpu_flags |= FPU_VALID;
283 PCB_SET_UPDATE_FPU(&lwp->lwp_pcb);
284 }
285
286 /*
287 * Get floating-point registers into a native fpregset_t.
288 */
289 void
290 getfpregs(klwp_t *lwp, fpregset_t *fp)
291 {
292 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
293
294 kpreempt_disable();
295 if (fpu->fpu_flags & FPU_EN) {
296 /*
297 * If we have FPU hw and the thread's pcb doesn't have
298 * a valid FPU state then get the state from the hw.
299 */
300 if (fpu_exists && ttolwp(curthread) == lwp &&
301 !(fpu->fpu_flags & FPU_VALID))
302 fp_save(fpu); /* get the current FPU state */
303 }
304
305 /*
306 * There are 3 possible cases we have to be aware of here:
307 *
308 * 1. FPU is enabled. FPU state is stored in the current LWP.
309 *
310 * 2. FPU is not enabled, and there have been no intervening /proc
311 * modifications. Return initial FPU state.
312 *
313 * 3. FPU is not enabled, but a /proc consumer has modified FPU state.
314 * FPU state is stored in the current LWP.
315 */
316 if ((fpu->fpu_flags & FPU_EN) || (fpu->fpu_flags & FPU_VALID)) {
317 /*
318 * Cases 1 and 3.
319 */
320 switch (fp_save_mech) {
321 case FP_FXSAVE:
322 fxsave_to_fpregset(fpu->fpu_regs.kfpu_u.kfpu_fx, fp);
323 fp->fp_reg_set.fpchip_state.xstatus =
324 fpu->fpu_regs.kfpu_xstatus;
325 break;
326 case FP_XSAVE:
327 fxsave_to_fpregset(
328 &fpu->fpu_regs.kfpu_u.kfpu_xs->xs_fxsave, fp);
329 fp->fp_reg_set.fpchip_state.xstatus =
330 fpu->fpu_regs.kfpu_xstatus;
331 break;
332 default:
333 panic("Invalid fp_save_mech");
334 /*NOTREACHED*/
335 }
336 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
337 } else {
338 /*
339 * Case 2.
340 */
341 switch (fp_save_mech) {
342 case FP_FXSAVE:
343 case FP_XSAVE:
344 /*
345 * For now, we don't have any AVX specific field in ABI.
346 * If we add any in the future, we need to initial them
347 * as well.
348 */
349 fxsave_to_fpregset(&sse_initial, fp);
350 fp->fp_reg_set.fpchip_state.xstatus =
351 fpu->fpu_regs.kfpu_xstatus;
352 break;
353 default:
354 panic("Invalid fp_save_mech");
355 /*NOTREACHED*/
356 }
357 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
358 }
359 kpreempt_enable();
360 }
361
362 #if defined(_SYSCALL32_IMPL)
363
364 /*
365 * Set floating-point registers from an fpregset32_t.
366 */
367 void
368 setfpregs32(klwp_t *lwp, fpregset32_t *fp)
369 {
370 fpregset_t fpregs;
371
372 fpregset_32ton(fp, &fpregs);
373 setfpregs(lwp, &fpregs);
374 }
375
376 /*
377 * Get floating-point registers into an fpregset32_t.
378 */
379 void
380 getfpregs32(klwp_t *lwp, fpregset32_t *fp)
381 {
382 fpregset_t fpregs;
383
384 getfpregs(lwp, &fpregs);
385 fpregset_nto32(&fpregs, fp);
386 }
387
388 #endif /* _SYSCALL32_IMPL */
389
390 /*
391 * Return the general registers
392 */
393 void
394 getgregs(klwp_t *lwp, gregset_t grp)
395 {
396 struct regs *rp = lwptoregs(lwp);
397 struct pcb *pcb = &lwp->lwp_pcb;
398 int thisthread = lwptot(lwp) == curthread;
399
400 grp[REG_RDI] = rp->r_rdi;
401 grp[REG_RSI] = rp->r_rsi;
402 grp[REG_RDX] = rp->r_rdx;
403 grp[REG_RCX] = rp->r_rcx;
404 grp[REG_R8] = rp->r_r8;
405 grp[REG_R9] = rp->r_r9;
406 grp[REG_RAX] = rp->r_rax;
407 grp[REG_RBX] = rp->r_rbx;
408 grp[REG_RBP] = rp->r_rbp;
409 grp[REG_R10] = rp->r_r10;
410 grp[REG_R11] = rp->r_r11;
411 grp[REG_R12] = rp->r_r12;
412 grp[REG_R13] = rp->r_r13;
413 grp[REG_R14] = rp->r_r14;
414 grp[REG_R15] = rp->r_r15;
415 grp[REG_FSBASE] = pcb->pcb_fsbase;
416 grp[REG_GSBASE] = pcb->pcb_gsbase;
417 if (thisthread)
418 kpreempt_disable();
419 if (PCB_NEED_UPDATE_SEGS(pcb)) {
420 grp[REG_DS] = pcb->pcb_ds;
421 grp[REG_ES] = pcb->pcb_es;
422 grp[REG_FS] = pcb->pcb_fs;
423 grp[REG_GS] = pcb->pcb_gs;
424 } else {
425 grp[REG_DS] = rp->r_ds;
426 grp[REG_ES] = rp->r_es;
427 grp[REG_FS] = rp->r_fs;
428 grp[REG_GS] = rp->r_gs;
429 }
430 if (thisthread)
431 kpreempt_enable();
432 grp[REG_TRAPNO] = rp->r_trapno;
433 grp[REG_ERR] = rp->r_err;
434 grp[REG_RIP] = rp->r_rip;
435 grp[REG_CS] = rp->r_cs;
436 grp[REG_SS] = rp->r_ss;
437 grp[REG_RFL] = rp->r_rfl;
438 grp[REG_RSP] = rp->r_rsp;
439 }
440
441 #if defined(_SYSCALL32_IMPL)
442
443 void
444 getgregs32(klwp_t *lwp, gregset32_t grp)
445 {
446 struct regs *rp = lwptoregs(lwp);
447 struct pcb *pcb = &lwp->lwp_pcb;
448 int thisthread = lwptot(lwp) == curthread;
449
450 if (thisthread)
451 kpreempt_disable();
452 if (PCB_NEED_UPDATE_SEGS(pcb)) {
453 grp[GS] = (uint16_t)pcb->pcb_gs;
454 grp[FS] = (uint16_t)pcb->pcb_fs;
455 grp[DS] = (uint16_t)pcb->pcb_ds;
456 grp[ES] = (uint16_t)pcb->pcb_es;
457 } else {
458 grp[GS] = (uint16_t)rp->r_gs;
459 grp[FS] = (uint16_t)rp->r_fs;
460 grp[DS] = (uint16_t)rp->r_ds;
461 grp[ES] = (uint16_t)rp->r_es;
462 }
463 if (thisthread)
464 kpreempt_enable();
465 grp[EDI] = (greg32_t)rp->r_rdi;
466 grp[ESI] = (greg32_t)rp->r_rsi;
467 grp[EBP] = (greg32_t)rp->r_rbp;
468 grp[ESP] = 0;
469 grp[EBX] = (greg32_t)rp->r_rbx;
470 grp[EDX] = (greg32_t)rp->r_rdx;
471 grp[ECX] = (greg32_t)rp->r_rcx;
472 grp[EAX] = (greg32_t)rp->r_rax;
473 grp[TRAPNO] = (greg32_t)rp->r_trapno;
474 grp[ERR] = (greg32_t)rp->r_err;
475 grp[EIP] = (greg32_t)rp->r_rip;
476 grp[CS] = (uint16_t)rp->r_cs;
477 grp[EFL] = (greg32_t)rp->r_rfl;
478 grp[UESP] = (greg32_t)rp->r_rsp;
479 grp[SS] = (uint16_t)rp->r_ss;
480 }
481
482 void
483 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst)
484 {
485 mcontext_t *dmc = &dst->uc_mcontext;
486 const mcontext32_t *smc = &src->uc_mcontext;
487
488 bzero(dst, sizeof (*dst));
489 dst->uc_flags = src->uc_flags;
490 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link;
491
492 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask));
493
494 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp;
495 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size;
496 dst->uc_stack.ss_flags = src->uc_stack.ss_flags;
497
498 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS];
499 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS];
500 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES];
501 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS];
502 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI];
503 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI];
504 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP];
505 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX];
506 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX];
507 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX];
508 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX];
509 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO];
510 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR];
511 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP];
512 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS];
513 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL];
514 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP];
515 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS];
516
517 /*
518 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set
519 * otherwise there is no guarantee that anything in fpregs is valid.
520 */
521 if (src->uc_flags & UC_FPU)
522 fpregset_32ton(&src->uc_mcontext.fpregs,
523 &dst->uc_mcontext.fpregs);
524
525 /*
526 * Copy the brand-private data:
527 */
528 dst->uc_brand_data[0] = (void *)(uintptr_t)src->uc_brand_data[0];
529 dst->uc_brand_data[1] = (void *)(uintptr_t)src->uc_brand_data[1];
530 dst->uc_brand_data[2] = (void *)(uintptr_t)src->uc_brand_data[2];
531 }
532
533 #endif /* _SYSCALL32_IMPL */
534
535 /*
536 * Return the user-level PC.
537 * If in a system call, return the address of the syscall trap.
538 */
539 greg_t
540 getuserpc()
541 {
542 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc;
543 uint32_t insn;
544
545 if (curthread->t_sysnum == 0)
546 return (upc);
547
548 /*
549 * We might've gotten here from sysenter (0xf 0x34),
550 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0).
551 *
552 * Go peek at the binary to figure it out..
553 */
554 if (fuword32((void *)(upc - 2), &insn) != -1 &&
555 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f)
556 return (upc - 2);
557 return (upc - 7);
558 }
559
560 /*
561 * Protect segment registers from non-user privilege levels and GDT selectors
562 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment
563 * selector is non-null and not USER_CS/USER_DS, we make sure that the
564 * TI bit is set to point into the LDT and that the RPL is set to 3.
565 *
566 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we
567 * also explicitly zero the top 16 bits since they may be coming from the
568 * user's address space via setcontext(2) or /proc.
569 *
570 * Note about null selector. When running on the hypervisor if we allow a
571 * process to set its %cs to null selector with RPL of 0 the hypervisor will
572 * crash the domain. If running on bare metal we would get a #gp fault and
573 * be able to kill the process and continue on. Therefore we make sure to
574 * force RPL to SEL_UPL even for null selector when setting %cs.
575 */
576
577 #if defined(IS_CS) || defined(IS_NOT_CS)
578 #error "IS_CS and IS_NOT_CS already defined"
579 #endif
580
581 #define IS_CS 1
582 #define IS_NOT_CS 0
583
584 /*ARGSUSED*/
585 greg_t
586 fix_segreg(greg_t sr, int iscs, model_t datamodel)
587 {
588 kthread_t *t = curthread;
589
590 switch (sr &= 0xffff) {
591
592 case 0:
593 if (iscs == IS_CS)
594 return (0 | SEL_UPL);
595 else
596 return (0);
597
598 /*
599 * If lwp attempts to switch data model then force their
600 * code selector to be null selector.
601 */
602 case U32CS_SEL:
603 if (datamodel == DATAMODEL_NATIVE)
604 return (0 | SEL_UPL);
605 else
606 return (sr);
607
608 case UCS_SEL:
609 if (datamodel == DATAMODEL_ILP32)
610 return (0 | SEL_UPL);
611 /*FALLTHROUGH*/
612 case UDS_SEL:
613 case LWPFS_SEL:
614 case LWPGS_SEL:
615 case SEL_UPL:
616 return (sr);
617 default:
618 break;
619 }
620
621 /*
622 * Allow this process's brand to do any necessary segment register
623 * manipulation.
624 */
625 if (PROC_IS_BRANDED(t->t_procp) && BRMOP(t->t_procp)->b_fixsegreg) {
626 greg_t bsr = BRMOP(t->t_procp)->b_fixsegreg(sr, datamodel);
627
628 if (bsr == 0 && iscs == IS_CS)
629 return (0 | SEL_UPL);
630 else
631 return (bsr);
632 }
633
634 /*
635 * Force it into the LDT in ring 3 for 32-bit processes, which by
636 * default do not have an LDT, so that any attempt to use an invalid
637 * selector will reference the (non-existant) LDT, and cause a #gp
638 * fault for the process.
639 *
640 * 64-bit processes get the null gdt selector since they
641 * are not allowed to have a private LDT.
642 */
643 if (datamodel == DATAMODEL_ILP32) {
644 return (sr | SEL_TI_LDT | SEL_UPL);
645 } else {
646 if (iscs == IS_CS)
647 return (0 | SEL_UPL);
648 else
649 return (0);
650 }
651
652 }
653
654 /*
655 * Set general registers.
656 */
657 void
658 setgregs(klwp_t *lwp, gregset_t grp)
659 {
660 struct regs *rp = lwptoregs(lwp);
661 model_t datamodel = lwp_getdatamodel(lwp);
662
663 struct pcb *pcb = &lwp->lwp_pcb;
664 int thisthread = lwptot(lwp) == curthread;
665
666 if (datamodel == DATAMODEL_NATIVE) {
667 if (thisthread)
668 (void) save_syscall_args(); /* copy the args */
669
670 rp->r_rdi = grp[REG_RDI];
671 rp->r_rsi = grp[REG_RSI];
672 rp->r_rdx = grp[REG_RDX];
673 rp->r_rcx = grp[REG_RCX];
674 rp->r_r8 = grp[REG_R8];
675 rp->r_r9 = grp[REG_R9];
676 rp->r_rax = grp[REG_RAX];
677 rp->r_rbx = grp[REG_RBX];
678 rp->r_rbp = grp[REG_RBP];
679 rp->r_r10 = grp[REG_R10];
680 rp->r_r11 = grp[REG_R11];
681 rp->r_r12 = grp[REG_R12];
682 rp->r_r13 = grp[REG_R13];
683 rp->r_r14 = grp[REG_R14];
684 rp->r_r15 = grp[REG_R15];
685 rp->r_trapno = grp[REG_TRAPNO];
686 rp->r_err = grp[REG_ERR];
687 rp->r_rip = grp[REG_RIP];
688 /*
689 * Setting %cs or %ss to anything else is quietly but
690 * quite definitely forbidden!
691 */
692 rp->r_cs = UCS_SEL;
693 rp->r_ss = UDS_SEL;
694 rp->r_rsp = grp[REG_RSP];
695
696 if (thisthread)
697 kpreempt_disable();
698
699 pcb->pcb_ds = UDS_SEL;
700 pcb->pcb_es = UDS_SEL;
701
702 /*
703 * 64-bit processes -are- allowed to set their fsbase/gsbase
704 * values directly, but only if they're using the segment
705 * selectors that allow that semantic.
706 *
707 * (32-bit processes must use lwp_set_private().)
708 */
709 pcb->pcb_fsbase = grp[REG_FSBASE];
710 pcb->pcb_gsbase = grp[REG_GSBASE];
711 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
712 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
713
714 /*
715 * Ensure that we go out via update_sregs
716 */
717 PCB_SET_UPDATE_SEGS(pcb);
718 lwptot(lwp)->t_post_sys = 1;
719 if (thisthread)
720 kpreempt_enable();
721 #if defined(_SYSCALL32_IMPL)
722 } else {
723 rp->r_rdi = (uint32_t)grp[REG_RDI];
724 rp->r_rsi = (uint32_t)grp[REG_RSI];
725 rp->r_rdx = (uint32_t)grp[REG_RDX];
726 rp->r_rcx = (uint32_t)grp[REG_RCX];
727 rp->r_rax = (uint32_t)grp[REG_RAX];
728 rp->r_rbx = (uint32_t)grp[REG_RBX];
729 rp->r_rbp = (uint32_t)grp[REG_RBP];
730 rp->r_trapno = (uint32_t)grp[REG_TRAPNO];
731 rp->r_err = (uint32_t)grp[REG_ERR];
732 rp->r_rip = (uint32_t)grp[REG_RIP];
733
734 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel);
735 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
736
737 rp->r_rsp = (uint32_t)grp[REG_RSP];
738
739 if (thisthread)
740 kpreempt_disable();
741
742 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
743 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel);
744
745 /*
746 * (See fsbase/gsbase commentary above)
747 */
748 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
749 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
750
751 /*
752 * Ensure that we go out via update_sregs
753 */
754 PCB_SET_UPDATE_SEGS(pcb);
755 lwptot(lwp)->t_post_sys = 1;
756 if (thisthread)
757 kpreempt_enable();
758 #endif
759 }
760
761 /*
762 * Only certain bits of the flags register can be modified.
763 */
764 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) |
765 (grp[REG_RFL] & PSL_USERMASK);
766 }
767
768 /*
769 * Determine whether eip is likely to have an interrupt frame
770 * on the stack. We do this by comparing the address to the
771 * range of addresses spanned by several well-known routines.
772 */
773 extern void _interrupt();
774 extern void _allsyscalls();
775 extern void _cmntrap();
776 extern void fakesoftint();
777
778 extern size_t _interrupt_size;
779 extern size_t _allsyscalls_size;
780 extern size_t _cmntrap_size;
781 extern size_t _fakesoftint_size;
782
783 /*
784 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking.
785 * Returns MIN(current stack depth, pcstack_limit).
786 */
787 int
788 getpcstack(pc_t *pcstack, int pcstack_limit)
789 {
790 struct frame *fp = (struct frame *)getfp();
791 struct frame *nextfp, *minfp, *stacktop;
792 int depth = 0;
793 int on_intr;
794 uintptr_t pc;
795
796 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
797 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
798 else
799 stacktop = (struct frame *)curthread->t_stk;
800 minfp = fp;
801
802 pc = ((struct regs *)fp)->r_pc;
803
804 while (depth < pcstack_limit) {
805 nextfp = (struct frame *)fp->fr_savfp;
806 pc = fp->fr_savpc;
807 if (nextfp <= minfp || nextfp >= stacktop) {
808 if (on_intr) {
809 /*
810 * Hop from interrupt stack to thread stack.
811 */
812 stacktop = (struct frame *)curthread->t_stk;
813 minfp = (struct frame *)curthread->t_stkbase;
814 on_intr = 0;
815 continue;
816 }
817 break;
818 }
819 pcstack[depth++] = (pc_t)pc;
820 fp = nextfp;
821 minfp = fp;
822 }
823 return (depth);
824 }
825
826 /*
827 * The following ELF header fields are defined as processor-specific
828 * in the V8 ABI:
829 *
830 * e_ident[EI_DATA] encoding of the processor-specific
831 * data in the object file
832 * e_machine processor identification
833 * e_flags processor-specific flags associated
834 * with the file
835 */
836
837 /*
838 * The value of at_flags reflects a platform's cpu module support.
839 * at_flags is used to check for allowing a binary to execute and
840 * is passed as the value of the AT_FLAGS auxiliary vector.
841 */
842 int at_flags = 0;
843
844 /*
845 * Check the processor-specific fields of an ELF header.
846 *
847 * returns 1 if the fields are valid, 0 otherwise
848 */
849 /*ARGSUSED2*/
850 int
851 elfheadcheck(
852 unsigned char e_data,
853 Elf32_Half e_machine,
854 Elf32_Word e_flags)
855 {
856 if (e_data != ELFDATA2LSB)
857 return (0);
858 if (e_machine == EM_AMD64)
859 return (1);
860 return (e_machine == EM_386);
861 }
862
863 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */
864 uint_t auxv_hwcap_include_2 = 0; /* second word */
865 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */
866 uint_t auxv_hwcap_exclude_2 = 0; /* second word */
867 #if defined(_SYSCALL32_IMPL)
868 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */
869 uint_t auxv_hwcap32_include_2 = 0; /* ditto for 32-bit apps */
870 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */
871 uint_t auxv_hwcap32_exclude_2 = 0; /* ditto for 32-bit apps */
872 #endif
873
874 /*
875 * Gather information about the processor and place it into auxv_hwcap
876 * so that it can be exported to the linker via the aux vector.
877 *
878 * We use this seemingly complicated mechanism so that we can ensure
879 * that /etc/system can be used to override what the system can or
880 * cannot discover for itself. Due to a lack of use, this has not
881 * been extended to the 3rd word.
882 */
883 void
884 bind_hwcap(void)
885 {
886 uint_t cpu_hwcap_flags[3];
887 cpuid_execpass(NULL, CPUID_PASS_RESOLVE, cpu_hwcap_flags);
888
889 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags[0]) &
890 ~auxv_hwcap_exclude;
891 auxv_hwcap_2 = (auxv_hwcap_include_2 | cpu_hwcap_flags[1]) &
892 ~auxv_hwcap_exclude_2;
893 auxv_hwcap_3 = cpu_hwcap_flags[2];
894
895 /*
896 * On AMD processors, sysenter just doesn't work at all
897 * when the kernel is in long mode. On IA-32e processors
898 * it does, but there's no real point in all the alternate
899 * mechanism when syscall works on both.
900 *
901 * Besides, the kernel's sysenter handler is expecting a
902 * 32-bit lwp ...
903 */
904 auxv_hwcap &= ~AV_386_SEP;
905
906 if (auxv_hwcap_include || auxv_hwcap_exclude || auxv_hwcap_include_2 ||
907 auxv_hwcap_exclude_2) {
908 /*
909 * The below assignment is regrettably required to get lint
910 * to accept the validity of our format string. The format
911 * string is in fact valid, but whatever intelligence in lint
912 * understands the cmn_err()-specific %b appears to have an
913 * off-by-one error: it (mistakenly) complains about bit
914 * number 32 (even though this is explicitly permitted).
915 * Normally, one would will away such warnings with a "LINTED"
916 * directive, but for reasons unclear and unknown, lint
917 * refuses to be assuaged in this case. Fortunately, lint
918 * doesn't pretend to have solved the Halting Problem --
919 * and as soon as the format string is programmatic, it
920 * knows enough to shut up.
921 */
922 char *fmt = "?user ABI extensions: %b\n";
923 cmn_err(CE_CONT, fmt, auxv_hwcap, FMT_AV_386);
924 fmt = "?user ABI extensions (word 2): %b\n";
925 cmn_err(CE_CONT, fmt, auxv_hwcap_2, FMT_AV_386_2);
926 fmt = "?user ABI extensions (word 2): %b\n";
927 cmn_err(CE_CONT, fmt, auxv_hwcap_3, FMT_AV_386_3);
928 }
929
930 #if defined(_SYSCALL32_IMPL)
931 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags[0]) &
932 ~auxv_hwcap32_exclude;
933 auxv_hwcap32_2 = (auxv_hwcap32_include_2 | cpu_hwcap_flags[1]) &
934 ~auxv_hwcap32_exclude_2;
935 auxv_hwcap32_3 = auxv_hwcap_3;
936
937 /*
938 * If this is an amd64 architecture machine from Intel, then
939 * syscall -doesn't- work in compatibility mode, only sysenter does.
940 *
941 * Sigh.
942 */
943 if (!cpuid_syscall32_insn(NULL))
944 auxv_hwcap32 &= ~AV_386_AMD_SYSC;
945
946 /*
947 * 32-bit processes can -always- use the lahf/sahf instructions
948 */
949 auxv_hwcap32 |= AV_386_AHF;
950
951 /*
952 * 32-bit processes can -never- use fsgsbase instructions.
953 */
954 auxv_hwcap32_2 &= ~AV_386_2_FSGSBASE;
955
956 if (auxv_hwcap32_include || auxv_hwcap32_exclude ||
957 auxv_hwcap32_include_2 || auxv_hwcap32_exclude_2) {
958 /*
959 * See the block comment in the cmn_err() of auxv_hwcap, above.
960 */
961 char *fmt = "?32-bit user ABI extensions: %b\n";
962 cmn_err(CE_CONT, fmt, auxv_hwcap32, FMT_AV_386);
963 fmt = "?32-bit user ABI extensions (word 2): %b\n";
964 cmn_err(CE_CONT, fmt, auxv_hwcap32_2, FMT_AV_386_2);
965 fmt = "?32-bit user ABI extensions (word 3): %b\n";
966 cmn_err(CE_CONT, fmt, auxv_hwcap32_3, FMT_AV_386_3);
967 }
968 #endif
969 }
970
971 /*
972 * sync_icache() - this is called
973 * in proc/fs/prusrio.c. x86 has an unified cache and therefore
974 * this is a nop.
975 */
976 /* ARGSUSED */
977 void
978 sync_icache(caddr_t addr, uint_t len)
979 {
980 /* Do nothing for now */
981 }
982
983 /*ARGSUSED*/
984 void
985 sync_data_memory(caddr_t va, size_t len)
986 {
987 /* Not implemented for this platform */
988 }
989
990 int
991 __ipltospl(int ipl)
992 {
993 return (ipltospl(ipl));
994 }
995
996 /*
997 * The panic code invokes panic_saveregs() to record the contents of a
998 * regs structure into the specified panic_data structure for debuggers.
999 */
1000 void
1001 panic_saveregs(panic_data_t *pdp, struct regs *rp)
1002 {
1003 panic_nv_t *pnv = PANICNVGET(pdp);
1004
1005 struct cregs creg;
1006
1007 getcregs(&creg);
1008
1009 PANICNVADD(pnv, "rdi", rp->r_rdi);
1010 PANICNVADD(pnv, "rsi", rp->r_rsi);
1011 PANICNVADD(pnv, "rdx", rp->r_rdx);
1012 PANICNVADD(pnv, "rcx", rp->r_rcx);
1013 PANICNVADD(pnv, "r8", rp->r_r8);
1014 PANICNVADD(pnv, "r9", rp->r_r9);
1015 PANICNVADD(pnv, "rax", rp->r_rax);
1016 PANICNVADD(pnv, "rbx", rp->r_rbx);
1017 PANICNVADD(pnv, "rbp", rp->r_rbp);
1018 PANICNVADD(pnv, "r10", rp->r_r10);
1019 PANICNVADD(pnv, "r11", rp->r_r11);
1020 PANICNVADD(pnv, "r12", rp->r_r12);
1021 PANICNVADD(pnv, "r13", rp->r_r13);
1022 PANICNVADD(pnv, "r14", rp->r_r14);
1023 PANICNVADD(pnv, "r15", rp->r_r15);
1024 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE));
1025 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE));
1026 PANICNVADD(pnv, "ds", rp->r_ds);
1027 PANICNVADD(pnv, "es", rp->r_es);
1028 PANICNVADD(pnv, "fs", rp->r_fs);
1029 PANICNVADD(pnv, "gs", rp->r_gs);
1030 PANICNVADD(pnv, "trapno", rp->r_trapno);
1031 PANICNVADD(pnv, "err", rp->r_err);
1032 PANICNVADD(pnv, "rip", rp->r_rip);
1033 PANICNVADD(pnv, "cs", rp->r_cs);
1034 PANICNVADD(pnv, "rflags", rp->r_rfl);
1035 PANICNVADD(pnv, "rsp", rp->r_rsp);
1036 PANICNVADD(pnv, "ss", rp->r_ss);
1037 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3]));
1038 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0]));
1039 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3]));
1040 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0]));
1041
1042 PANICNVADD(pnv, "ldt", creg.cr_ldt);
1043 PANICNVADD(pnv, "task", creg.cr_task);
1044 PANICNVADD(pnv, "cr0", creg.cr_cr0);
1045 PANICNVADD(pnv, "cr2", creg.cr_cr2);
1046 PANICNVADD(pnv, "cr3", creg.cr_cr3);
1047 if (creg.cr_cr4)
1048 PANICNVADD(pnv, "cr4", creg.cr_cr4);
1049
1050 PANICNVSET(pdp, pnv);
1051 }
1052
1053 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */
1054
1055
1056 /*
1057 * Print a stack backtrace using the specified frame pointer. We delay two
1058 * seconds before continuing, unless this is the panic traceback.
1059 * If we are in the process of panicking, we also attempt to write the
1060 * stack backtrace to a staticly assigned buffer, to allow the panic
1061 * code to find it and write it in to uncompressed pages within the
1062 * system crash dump.
1063 * Note that the frame for the starting stack pointer value is omitted because
1064 * the corresponding %eip is not known.
1065 */
1066
1067 extern char *dump_stack_scratch;
1068
1069
1070 void
1071 traceback(caddr_t fpreg)
1072 {
1073 struct frame *fp = (struct frame *)fpreg;
1074 struct frame *nextfp;
1075 uintptr_t pc, nextpc;
1076 ulong_t off;
1077 char args[TR_ARG_MAX * 2 + 16], *sym;
1078 uint_t offset = 0;
1079 uint_t next_offset = 0;
1080 char stack_buffer[1024];
1081
1082 if (!panicstr)
1083 printf("traceback: %%fp = %p\n", (void *)fp);
1084
1085 if (panicstr && !dump_stack_scratch) {
1086 printf("Warning - stack not written to the dump buffer\n");
1087 }
1088
1089 fp = (struct frame *)plat_traceback(fpreg);
1090 if ((uintptr_t)fp < KERNELBASE)
1091 goto out;
1092
1093 pc = fp->fr_savpc;
1094 fp = (struct frame *)fp->fr_savfp;
1095
1096 while ((uintptr_t)fp >= KERNELBASE) {
1097 /*
1098 * XX64 Until port is complete tolerate 8-byte aligned
1099 * frame pointers but flag with a warning so they can
1100 * be fixed.
1101 */
1102 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) {
1103 if (((uintptr_t)fp & (8 - 1)) == 0) {
1104 printf(" >> warning! 8-byte"
1105 " aligned %%fp = %p\n", (void *)fp);
1106 } else {
1107 printf(
1108 " >> mis-aligned %%fp = %p\n", (void *)fp);
1109 break;
1110 }
1111 }
1112
1113 args[0] = '\0';
1114 nextpc = (uintptr_t)fp->fr_savpc;
1115 nextfp = (struct frame *)fp->fr_savfp;
1116 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
1117 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
1118 mod_containing_pc((caddr_t)pc), sym, off, args);
1119 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1120 "%s:%s+%lx (%s) | ",
1121 mod_containing_pc((caddr_t)pc), sym, off, args);
1122 } else {
1123 printf("%016lx %lx (%s)\n",
1124 (uintptr_t)fp, pc, args);
1125 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1126 "%lx (%s) | ", pc, args);
1127 }
1128
1129 if (panicstr && dump_stack_scratch) {
1130 next_offset = offset + strlen(stack_buffer);
1131 if (next_offset < STACK_BUF_SIZE) {
1132 bcopy(stack_buffer, dump_stack_scratch + offset,
1133 strlen(stack_buffer));
1134 offset = next_offset;
1135 } else {
1136 /*
1137 * In attempting to save the panic stack
1138 * to the dumpbuf we have overflowed that area.
1139 * Print a warning and continue to printf the
1140 * stack to the msgbuf
1141 */
1142 printf("Warning: stack in the dump buffer"
1143 " may be incomplete\n");
1144 offset = next_offset;
1145 }
1146 }
1147
1148 pc = nextpc;
1149 fp = nextfp;
1150 }
1151 out:
1152 if (!panicstr) {
1153 printf("end of traceback\n");
1154 DELAY(2 * MICROSEC);
1155 } else if (dump_stack_scratch) {
1156 dump_stack_scratch[offset] = '\0';
1157 }
1158 }
1159
1160
1161 /*
1162 * Generate a stack backtrace from a saved register set.
1163 */
1164 void
1165 traceregs(struct regs *rp)
1166 {
1167 traceback((caddr_t)rp->r_fp);
1168 }
1169
1170 void
1171 exec_set_sp(size_t stksize)
1172 {
1173 klwp_t *lwp = ttolwp(curthread);
1174
1175 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize;
1176 }
1177
1178 hrtime_t
1179 gethrtime_waitfree(void)
1180 {
1181 return (dtrace_gethrtime());
1182 }
1183
1184 hrtime_t
1185 gethrtime(void)
1186 {
1187 return (gethrtimef());
1188 }
1189
1190 hrtime_t
1191 gethrtime_unscaled(void)
1192 {
1193 return (gethrtimeunscaledf());
1194 }
1195
1196 void
1197 scalehrtime(hrtime_t *hrt)
1198 {
1199 scalehrtimef(hrt);
1200 }
1201
1202 uint64_t
1203 unscalehrtime(hrtime_t nsecs)
1204 {
1205 return (unscalehrtimef(nsecs));
1206 }
1207
1208 void
1209 gethrestime(timespec_t *tp)
1210 {
1211 gethrestimef(tp);
1212 }
1213
1214 /*
1215 * Part of the implementation of hres_tick(); this routine is
1216 * easier in C than assembler .. called with the hres_lock held.
1217 *
1218 * XX64 Many of these timekeeping variables need to be extern'ed in a header
1219 */
1220
1221 #include <sys/time.h>
1222 #include <sys/machlock.h>
1223
1224 extern int one_sec;
1225 extern int max_hres_adj;
1226
1227 void
1228 __adj_hrestime(void)
1229 {
1230 long long adj;
1231
1232 if (hrestime_adj == 0)
1233 adj = 0;
1234 else if (hrestime_adj > 0) {
1235 if (hrestime_adj < max_hres_adj)
1236 adj = hrestime_adj;
1237 else
1238 adj = max_hres_adj;
1239 } else {
1240 if (hrestime_adj < -max_hres_adj)
1241 adj = -max_hres_adj;
1242 else
1243 adj = hrestime_adj;
1244 }
1245
1246 timedelta -= adj;
1247 hrestime_adj = timedelta;
1248 hrestime.tv_nsec += adj;
1249
1250 while (hrestime.tv_nsec >= NANOSEC) {
1251 one_sec++;
1252 hrestime.tv_sec++;
1253 hrestime.tv_nsec -= NANOSEC;
1254 }
1255 }
1256
1257 /*
1258 * Wrapper functions to maintain backwards compability
1259 */
1260 int
1261 xcopyin(const void *uaddr, void *kaddr, size_t count)
1262 {
1263 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED));
1264 }
1265
1266 int
1267 xcopyout(const void *kaddr, void *uaddr, size_t count)
1268 {
1269 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED));
1270 }