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15254 %ymm registers not restored after signal handler
15367 x86 getfpregs() summons corrupting %xmm ghosts
15333 want x86 /proc xregs support (libc_db, libproc, mdb, etc.)
15336 want libc functions for extended ucontext_t
15334 want ps_lwphandle-specific reg routines
15328 FPU_CW_INIT mistreats reserved bit
15335 i86pc fpu_subr.c isn't really platform-specific
15332 setcontext(2) isn't actually noreturn
15331 need <sys/stdalign.h>
Change-Id: I7060aa86042dfb989f77fc3323c065ea2eafa9ad
Conflicts:
    usr/src/uts/common/fs/proc/prcontrol.c
    usr/src/uts/intel/os/archdep.c
    usr/src/uts/intel/sys/ucontext.h
    usr/src/uts/intel/syscall/getcontext.c

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          --- old/usr/src/man/man5/proc.5
          +++ new/usr/src/man/man5/proc.5
   1    1  .\" Copyright 1989 AT&T
   2    2  .\" Copyright (c) 2006, Sun Microsystems, Inc. All Rights Reserved.
   3    3  .\" Copyright 2019, Joyent, Inc.
   4    4  .\" Copyright 2020 OmniOS Community Edition (OmniOSce) Association.
        5 +.\" Copyright 2023 Oxide computer Company
   5    6  .\"
   6    7  .\" The contents of this file are subject to the terms of the
   7    8  .\" Common Development and Distribution License (the "License").
   8    9  .\" You may not use this file except in compliance with the License.
   9   10  .\"
  10   11  .\" You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  11   12  .\" or http://www.opensolaris.org/os/licensing.
  12   13  .\" See the License for the specific language governing permissions
  13   14  .\" and limitations under the License.
  14   15  .\"
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1889 1890  creation time of the agent lwp.
1890 1891  .Ss templates
1891 1892  A directory which contains references to the active templates for the lwp,
1892 1893  named by the contract type.
1893 1894  Changes made to an active template descriptor do
1894 1895  not affect the original template which was activated, though they do affect the
1895 1896  active template.
1896 1897  It is not possible to activate an active template descriptor.
1897 1898  See
1898 1899  .Xr contract 5 .
     1900 +.Sh ARCHITECTURE-SPECIFIC STRUCTURES
     1901 +.Ss x86
     1902 +The x86
     1903 +.Vt prxregset_t
     1904 +structure is opaque and is made up of several different components due
     1905 +to the fact that different x86 processors enumerate different
     1906 +architectural extensions.
     1907 +.Pp
     1908 +The structure begins with a header, the
     1909 +.Vt prxregset_hdr_t ,
     1910 +which is followed by a number of different information sections which
     1911 +describe different possible extended registers.
     1912 +Each of those is covered by a
     1913 +.Vt prxregset_info_t ,
     1914 +and then finally there are different data payloads that represent each
     1915 +extended register.
     1916 +.Pp
     1917 +The number of different informational entries varies from system to
     1918 +system based on the set of architectural features that the system
     1919 +supports and the corresponding OS enablement for them.
     1920 +This structure is built around the idea of the x86
     1921 +.Sy xsave
     1922 +structure.
     1923 +That is, there is a central header which describes a bit-vector of what
     1924 +extended features are present and have valid state.
     1925 +.Pp
     1926 +Each x86 xregs file begins with the
     1927 +.Vt prxregset_hdr_t
     1928 +which looks like:
     1929 +.Bd -literal -offset 2
     1930 +typedef struct prxregset_hdr {
     1931 +        uint32_t        pr_type;
     1932 +        uint32_t        pr_size;
     1933 +        uint32_t        pr_flags;
     1934 +        uint32_t        pr_pad[4];
     1935 +        uint32_t        pr_ninfo;
     1936 +        prxregset_info_t pr_info[];
     1937 +} prxregset_hdr_t;
     1938 +.Ed
     1939 +.Pp
     1940 +The
     1941 +.Fa pr_type
     1942 +member is always set to
     1943 +.Dv PR_TYPE_XSAVE .
     1944 +This is used to indicate the type of file that is present.
     1945 +There may be different file types in the future on x86 so this value
     1946 +should always be checked.
     1947 +If it is not
     1948 +.Dv PR_TYPE_XSAVE
     1949 +then the rest of the structure may look different.
     1950 +The
     1951 +.Fa pr_size
     1952 +member indicates the size in bytes of the overall structure.
     1953 +The
     1954 +.Fa pr_flags
     1955 +and
     1956 +.Fa pr_pad
     1957 +values are currently reserved for future use.
     1958 +They will be set to zero right now when read and must be set to zero when
     1959 +writing the data.
     1960 +The
     1961 +.Fa pr_ninfo
     1962 +member indicates the number of informational items are present in
     1963 +.Fa pr_info.
     1964 +There will be one informational item for each register set that exists.
     1965 +.Pp
     1966 +The
     1967 +.Fa pr_info
     1968 +member points to an array of informational members.
     1969 +These immediately follow the structure, though the
     1970 +.Fa pr_info
     1971 +member may not be available directly if not in an environment compatible with
     1972 +some C99 features.
     1973 +Each
     1974 +.Vt prxregset_info_t
     1975 +structure looks like:
     1976 +.Bd -literal -offset 2
     1977 +typedef struct prxregset_info {
     1978 +        uint32_t pri_type;
     1979 +        uint32_t pri_flags;
     1980 +        uint32_t pri_size;
     1981 +        uint32_t pri_offset;
     1982 +} prxregset_info_t;
     1983 +.Ed
     1984 +.Pp
     1985 +The
     1986 +.Fa pri_type
     1987 +member is used to indicate the type of data and its format that this represents.
     1988 +Types are listed below.
     1989 +The
     1990 +.Fa pri_flags
     1991 +member is used to indicate future extensions or information about these items.
     1992 +Right now, these are all zero.
     1993 +The
     1994 +.Fa pri_size
     1995 +member indicates the size in bytes of the type's data.
     1996 +The
     1997 +.Fa pri_offset
     1998 +member indicates the offset to the start of the data section from the beginning
     1999 +of the xregs file.
     2000 +That is an offset of 0 would be the first byte of the
     2001 +.Vt prxregset_hdr_t .
     2002 +.Pp
     2003 +The following types of structures and their corresponding data structures are
     2004 +currently defined:
     2005 +.Bl -tag -width Ds
     2006 +.It Dv PRX_INFO_XCR - Vt prxregset_xcr_t
     2007 +This structure provides read-only access to understanding the CPU's settings for
     2008 +this thread.
     2009 +In particular, it lets you see what is set in the x86 %xcr0 register which is
     2010 +the extended feature control register and controls what extended features the
     2011 +CPU actually uses.
     2012 +It also contains the x86 extended feature disable MSR which controls features
     2013 +that are ignored.
     2014 +The
     2015 +.Vt prxregset_xcr_t
     2016 +looks like:
     2017 +.Bd -literal -offset -indent
     2018 +typedef struct prxregset_xcr {
     2019 +        uint64_t        prx_xcr_xcr0;
     2020 +        uint64_t        prx_xcr_xfd;
     2021 +        uint64_t        prx_xcr_pad[2];
     2022 +} prxregset_xcr_t;
     2023 +.Ed
     2024 +.Pp
     2025 +When setting the xregs, this entry can be left out.
     2026 +If it is included, it must match the existing entries, otherwise an error will
     2027 +be generated.
     2028 +.It Dv PRX_INFO_XSAVE - Vt prxregset_xsave_t
     2029 +This structure represents the same as the actual Intel xsave structure, which
     2030 +has both the traditional XMM state that comes from the fxsave instruction and
     2031 +then also contains the xsave header itself.
     2032 +The structure varies between 32-bit and 64-bit applications.
     2033 +The structure itself looks like:
     2034 +.Bd -literal
     2035 +typedef struct prxregset_xsave {
     2036 +        uint16_t        prx_fx_fcw;
     2037 +        uint16_t        prx_fx_fsw;
     2038 +        uint16_t        prx_fx_fctw;    /* compressed tag word */
     2039 +        uint16_t        prx_fx_fop;
     2040 +#if defined(__amd64)
     2041 +        uint64_t        prx_fx_rip;
     2042 +        uint64_t        prx_fx_rdp;
     2043 +#else
     2044 +        uint32_t        prx_fx_eip;
     2045 +        uint16_t        prx_fx_cs;
     2046 +        uint16_t        __prx_fx_ign0;
     2047 +        uint32_t        prx_fx_dp;
     2048 +        uint16_t        prx_fx_ds;
     2049 +        uint16_t        __prx_fx_ign1;
     2050 +#endif
     2051 +        uint32_t        prx_fx_mxcsr;
     2052 +        uint32_t        prx_fx_mxcsr_mask;
     2053 +        union {
     2054 +                uint16_t prx_fpr_16[5]; /* 80-bits of x87 state */
     2055 +                u_longlong_t prx_fpr_mmx;       /* 64-bit mmx register */
     2056 +                uint32_t _prx__fpr_pad[4];      /* (pad out to 128-bits) */
     2057 +        } fx_st[8];
     2058 +#if defined(__amd64)
     2059 +        upad128_t       prx_fx_xmm[16]; /* 128-bit registers */
     2060 +        upad128_t       __prx_fx_ign2[6];
     2061 +#else
     2062 +        upad128_t       prx_fx_xmm[8];  /* 128-bit registers */
     2063 +        upad128_t       __prx_fx_ign2[14];
     2064 +#endif
     2065 +        uint64_t        prx_xsh_xstate_bv;
     2066 +        uint64_t        prx_xsh_xcomp_bv;
     2067 +        uint64_t        prx_xsh_reserved[6];
     2068 +} prxregset_xsave_t;
     2069 +.Ed
     2070 +.Pp
     2071 +In the classical fxsave portion of the structure, most of the members follow the
     2072 +same meaning and match their presence in the fpregs file and their use as
     2073 +discussed in the Intel and AMD software developer manuals.
     2074 +The one exception is that when setting the
     2075 +.Fa prx_fx_mxcsr
     2076 +member reserved bits that are set will be masked off and ignored.
     2077 +.Pp
     2078 +The most notable fields to consider here right now are the last few members
     2079 +which are part of the xsave header itself.
     2080 +In particular, the
     2081 +.Fa prx_xsh_xstate_bv
     2082 +component is used to track the actual features whose content are valid.
     2083 +When reading the registers, if a given entry is not valid, the register state
     2084 +will write out the informational entry in its default state.
     2085 +When setting the extended registers, this notes which features will be loaded
     2086 +from their default state
     2087 +.Pq as defined by Intel and AMD's manuals
     2088 +and which will be loaded from the informational entries.
     2089 +If a bit is set in the
     2090 +.Fa prx_xsh_xstate_bv
     2091 +entry, then it must be present as its own informational entry otherwise a write
     2092 +will fail.
     2093 +If an informational entry is present in a write, but not set in the
     2094 +.Fa prx_xsh_xstate_bv
     2095 +then its contents will be ignored.
     2096 +.Pp
     2097 +The xregs format currently does not support any compressed items being specified
     2098 +nor does it specify any, so the
     2099 +.Fa prx_xsh_xcomp_bv
     2100 +member will be always set to zero and it and the reserved members
     2101 +.Fa prx_xsh_reserved
     2102 +must all be left as zero.
     2103 +.It Dv PRX_INFO_YMM - Vt prxregset_ymm_t
     2104 +This structure contains the upper 128-bits of the first 16 %ymm registers
     2105 +.Pq 8 for 32-bit applications .
     2106 +To construct a full vector register, it must be combined with the
     2107 +.Fa prx_fx_xmm
     2108 +member of the
     2109 +.Dv PRX_INFO_XSAVE
     2110 +data.
     2111 +In 32-bit applications, the reserved registers must be written as zero.
     2112 +The structure itself looks like:
     2113 +.Bd -literal -offset 2
     2114 +typedef struct prxregset_ymm {
     2115 +#if defined(__amd64)
     2116 +        upad128_t       prx_ymm[16];
     2117 +#else
     2118 +        upad128_t       prx_ymm[8];
     2119 +        upad128_t       prx_rsvd[8];
     2120 +#endif
     2121 +} prxregset_ymm_t;
     2122 +.Ed
     2123 +.It Dv PRX_INFO_OPMASK - Vt prxregset_opmask_t
     2124 +This structure represents one portion of Intel's AVX-512 state: the 8 64-bit
     2125 +mask registers, %k0 through %k7.
     2126 +The structure looks like:
     2127 +.Bd -literal -offset 2
     2128 +typedef struct prxregset_opmask {
     2129 +        uint64_t        prx_opmask[8];
     2130 +} prxregset_opmask_t;
     2131 +.Ed
     2132 +.It Dv PRX_INFO_ZMM - Vt prxregset_zmm_t
     2133 +This structure represents one portion of Intel's AVX-512 state: the upper
     2134 +256 bits of the 512-bit %zmm0 through %zmm15 registers.
     2135 +Bits 0-127 are found in the
     2136 +.Fa prx_fx_xmm
     2137 +member of the
     2138 +.Dv PRX_INFO_XSAVE
     2139 +data and bits 128-255 are found in the
     2140 +.Fa prx_ymm
     2141 +member of the
     2142 +.Dv PRX_INFO_YMM .
     2143 +32-bit applications only have access to %zmm0 through %zmm7.
     2144 +This structure looks like:
     2145 +.Bd -literal -offset 2
     2146 +typedef struct prxregset_zmm {
     2147 +#if defined(__amd64)
     2148 +        upad256_t       prx_zmm[16];
     2149 +#else
     2150 +        upad256_t       prx_zmm[8];
     2151 +        upad256_t       prx_rsvd[8];
     2152 +#endif
     2153 +} prxregset_zmm_t;
     2154 +.Ed
     2155 +.It Dv PRX_INFO_HI_ZMM - Vt prxregset_hi_zmm_t
     2156 +This structure represents the third portion of Intel's AVX-512 state: the
     2157 +additional 16 512-bit registers that are available to 64-bit applications, but
     2158 +not 32-bit applications.
     2159 +This represents %zmm16 through %zmm31.
     2160 +This structure looks like:
     2161 +.Bd -literal -offset indent
     2162 +typedef struct prxregset_hi_zmm {
     2163 +#if defined(__amd64)
     2164 +        upad512_t       prx_hi_zmm[16];
     2165 +#else
     2166 +        upad512_t       prx_rsvd[16];
     2167 +#endif
     2168 +} prxregset_hi_zmm_t;
     2169 +.Pp
     2170 +Unlike the other lower %zmm registers of %zmm0 through %zmm15, this contains the
     2171 +entire 512-bit register in one spot and there is no need to look at other
     2172 +information items to reconstitute the entire vector.
     2173 +.Ed
     2174 +.Pp
     2175 +When setting the extended registers, at least the
     2176 +.Dv PRX_INFO_XSAVE
     2177 +component must be present.
     2178 +None of the component offsets may overlap with the
     2179 +.Vt prxregset_hdr_t
     2180 +or any of the
     2181 +.Vt prxregset_info_t
     2182 +structures.
     2183 +In the written data file, it is expected that the various structures start with
     2184 +their naturally expected alignment, which is most often 16 bytes
     2185 +.Po
     2186 +that is the value that the C
     2187 +.Fn alignof
     2188 +keyword will return
     2189 +.Pc .
     2190 +The structures that we use are all multiples of 16 bytes to make this easier.
     2191 +The kernel will write out structures with a greater alignment such that the
     2192 +portions of registers are aligned and safely usable with instructions that move
     2193 +aligned integers such as vmovdqu64.
     2194 +.El
1899 2195  .Sh CONTROL MESSAGES
1900 2196  Process state changes are effected through messages written to a process's
1901 2197  .Sy ctl
1902 2198  file or to an individual lwp's
1903 2199  .Sy lwpctl
1904 2200  file.
1905 2201  All control messages consist of a
1906 2202  .Sy long
1907 2203  that names the specific operation followed by
1908 2204  additional data containing the operand, if any.
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1931 2227  .Sy PCDSTOP
1932 2228  directs all lwps to stop without waiting for them to stop, and
1933 2229  .Sy PCWSTOP
1934 2230  simply waits for all lwps to stop.
1935 2231  When applied to an lwp control file,
1936 2232  .Sy PCSTOP
1937 2233  directs the specific lwp to stop and waits until it has stopped,
1938 2234  .Sy PCDSTOP
1939 2235  directs the specific lwp to stop without waiting for it to stop, and
1940 2236  .Sy PCWSTOP
1941      - simply waits for the specific lwp to stop.
     2237 +simply waits for the specific lwp to stop.
1942 2238  When applied to an lwp control file,
1943 2239  .Sy PCSTOP
1944 2240  and
1945 2241  .Sy PCWSTOP
1946 2242  complete when the lwp stops on an event of interest, immediately
1947 2243  if already so stopped; when applied to the process control file, they complete
1948 2244  when every lwp has stopped either on an event of interest or on a
1949 2245  .Sy PR_SUSPENDED
1950 2246  stop.
1951 2247  .Pp
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1966 2262  .Dq event of interest
1967 2263  is either a
1968 2264  .Sy PR_REQUESTED
1969 2265  stop or a stop that has been specified in the process's tracing flags (set by
1970 2266  .Sy PCSTRACE ,
1971 2267  .Sy PCSFAULT ,
1972 2268  .Sy PCSENTRY ,
1973 2269  and
1974 2270  .Sy PCSEXIT ) .
1975 2271  .Sy PR_JOBCONTROL
1976      - and
     2272 +and
1977 2273  .Sy PR_SUSPENDED
1978 2274  stops are specifically not events of interest.
1979 2275  (An lwp may stop twice due to a stop signal, first showing
1980 2276  .Sy PR_SIGNALLED
1981 2277  if the signal is traced and again showing
1982 2278  .Sy PR_JOBCONTROL
1983 2279  if the lwp is set running without clearing the signal.)
1984 2280  If
1985 2281  .Sy PCSTOP
1986 2282  or
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2580 2876  fails with
2581 2877  .Er EBUSY
2582 2878  if the lwp is not stopped on an event of interest.
2583 2879  .Ss PCSXREG
2584 2880  Set the extra state registers for the specific or representative lwp according
2585 2881  to the architecture-dependent operand
2586 2882  .Vt prxregset_t
2587 2883  structure.
2588 2884  An error
2589 2885  .Pq Er EINVAL
2590      -is returned if the system does not support extra state registers.
     2886 +is returned if the system does not support extra state registers or the register
     2887 +state is invalid.
2591 2888  .Sy PCSXREG
2592 2889  fails with
2593 2890  .Er EBUSY
2594 2891  if the lwp is not stopped on an event of interest.
2595 2892  .Ss PCSASRS
2596 2893  Set the ancillary state registers for the specific or representative lwp
2597 2894  according to the SPARC V9 platform-dependent operand
2598 2895  .Vt asrset_t
2599 2896  structure.
2600 2897  An error
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