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--- old/usr/src/uts/common/io/i40e/i40e_main.c
+++ new/usr/src/uts/common/io/i40e/i40e_main.c
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
|
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7 lines elided |
↑ open up ↑ |
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
14 14 * Copyright 2019 Joyent, Inc.
15 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved.
16 16 * Copyright 2020 RackTop Systems, Inc.
17 17 * Copyright 2020 Ryan Zezeski
18 + * Copyright 2021 Oxide Computer Company
18 19 */
19 20
20 21 /*
21 22 * i40e - Intel 10/40 Gb Ethernet driver
22 23 *
23 24 * The i40e driver is the main software device driver for the Intel 40 Gb family
24 25 * of devices. Note that these devices come in many flavors with both 40 GbE
25 26 * ports and 10 GbE ports. This device is the successor to the 82599 family of
26 27 * devices (ixgbe).
27 28 *
28 29 * Unlike previous generations of Intel 1 GbE and 10 GbE devices, the 40 GbE
29 30 * devices defined in the XL710 controller (previously known as Fortville) are a
30 31 * rather different beast and have a small switch embedded inside of them. In
31 32 * addition, the way that most of the programming is done has been overhauled.
32 33 * As opposed to just using PCIe memory mapped registers, it also has an
33 34 * administrative queue which is used to communicate with firmware running on
34 35 * the chip.
35 36 *
36 37 * Each physical function in the hardware shows up as a device that this driver
37 38 * will bind to. The hardware splits many resources evenly across all of the
38 39 * physical functions present on the device, while other resources are instead
39 40 * shared across the entire card and its up to the device driver to
40 41 * intelligently partition them.
41 42 *
42 43 * ------------
43 44 * Organization
44 45 * ------------
45 46 *
46 47 * This driver is made up of several files which have their own theory
47 48 * statements spread across them. We'll touch on the high level purpose of each
48 49 * file here, and then we'll get into more discussion on how the device is
49 50 * generally modelled with respect to the interfaces in illumos.
50 51 *
51 52 * i40e_gld.c: This file contains all of the bindings to MAC and the networking
52 53 * stack.
53 54 *
54 55 * i40e_intr.c: This file contains all of the interrupt service routines and
55 56 * contains logic to enable and disable interrupts on the hardware.
56 57 * It also contains the logic to map hardware resources such as the
57 58 * rings to and from interrupts and controls their ability to fire.
58 59 *
59 60 * There is a big theory statement on interrupts present there.
60 61 *
61 62 * i40e_main.c: The file that you're currently in. It interfaces with the
62 63 * traditional OS DDI interfaces and is in charge of configuring
63 64 * the device.
64 65 *
65 66 * i40e_osdep.[ch]: These files contain interfaces and definitions needed to
66 67 * work with Intel's common code for the device.
67 68 *
68 69 * i40e_stats.c: This file contains the general work and logic around our
69 70 * kstats. A theory statement on their organization and use of the
70 71 * hardware exists there.
71 72 *
72 73 * i40e_sw.h: This header file contains all of the primary structure definitions
73 74 * and constants that are used across the entire driver.
74 75 *
75 76 * i40e_transceiver.c: This file contains all of the logic for sending and
76 77 * receiving data. It contains all of the ring and DMA
77 78 * allocation logic, as well as, the actual interfaces to
78 79 * send and receive data.
79 80 *
80 81 * A big theory statement on ring management, descriptors,
81 82 * and how it ties into the OS is present there.
82 83 *
83 84 * --------------
84 85 * General Design
85 86 * --------------
86 87 *
87 88 * Before we go too far into the general way we've laid out data structures and
88 89 * the like, it's worth taking some time to explain how the hardware is
89 90 * organized. This organization informs a lot of how we do things at this time
90 91 * in the driver.
91 92 *
92 93 * Each physical device consists of a number of one or more ports, which are
93 94 * considered physical functions in the PCI sense and thus each get enumerated
94 95 * by the system, resulting in an instance being created and attached to. While
95 96 * there are many resources that are unique to each physical function eg.
96 97 * instance of the device, there are many that are shared across all of them.
97 98 * Several resources have an amount reserved for each Virtual Station Interface
98 99 * (VSI) and then a static pool of resources, available for all functions on the
99 100 * card.
100 101 *
101 102 * The most important resource in hardware are its transmit and receive queue
102 103 * pairs (i40e_trqpair_t). These should be thought of as rings in GLDv3
103 104 * parlance. There are a set number of these on each device; however, they are
104 105 * statically partitioned among all of the different physical functions.
105 106 *
106 107 * 'Fortville' (the code name for this device family) is basically a switch. To
107 108 * map MAC addresses and other things to queues, we end up having to create
108 109 * Virtual Station Interfaces (VSIs) and establish forwarding rules that direct
109 110 * traffic to a queue. A VSI owns a collection of queues and has a series of
110 111 * forwarding rules that point to it. One way to think of this is to treat it
111 112 * like MAC does a VNIC. When MAC refers to a group, a collection of rings and
112 113 * classification resources, that is a VSI in i40e.
113 114 *
114 115 * The sets of VSIs is shared across the entire device, though there may be some
115 116 * amount that are reserved to each PF. Because the GLDv3 does not let us change
116 117 * the number of groups dynamically, we instead statically divide this amount
117 118 * evenly between all the functions that exist. In addition, we have the same
118 119 * problem with the mac address forwarding rules. There are a static number that
119 120 * exist shared across all the functions.
120 121 *
121 122 * To handle both of these resources, what we end up doing is going through and
122 123 * determining which functions belong to the same device. Nominally one might do
123 124 * this by having a nexus driver; however, a prime requirement for a nexus
124 125 * driver is identifying the various children and activating them. While it is
125 126 * possible to get this information from NVRAM, we would end up duplicating a
126 127 * lot of the PCI enumeration logic. Really, at the end of the day, the device
127 128 * doesn't give us the traditional identification properties we want from a
128 129 * nexus driver.
129 130 *
130 131 * Instead, we rely on some properties that are guaranteed to be unique. While
131 132 * it might be tempting to leverage the PBA or serial number of the device from
132 133 * NVRAM, there is nothing that says that two devices can't be mis-programmed to
133 134 * have the same values in NVRAM. Instead, we uniquely identify a group of
134 135 * functions based on their parent in the /devices tree, their PCI bus and PCI
135 136 * function identifiers. Using either on their own may not be sufficient.
136 137 *
137 138 * For each unique PCI device that we encounter, we'll create a i40e_device_t.
138 139 * From there, because we don't have a good way to tell the GLDv3 about sharing
139 140 * resources between everything, we'll end up just dividing the resources
140 141 * evenly between all of the functions. Longer term, if we don't have to declare
141 142 * to the GLDv3 that these resources are shared, then we'll maintain a pool and
142 143 * have each PF allocate from the pool in the device, thus if only two of four
143 144 * ports are being used, for example, then all of the resources can still be
144 145 * used.
145 146 *
146 147 * -------------------------------------------
147 148 * Transmit and Receive Queue Pair Allocations
148 149 * -------------------------------------------
149 150 *
150 151 * NVRAM ends up assigning each PF its own share of the transmit and receive LAN
151 152 * queue pairs, we have no way of modifying it, only observing it. From there,
152 153 * it's up to us to map these queues to VSIs and VFs. Since we don't support any
153 154 * VFs at this time, we only focus on assignments to VSIs.
154 155 *
155 156 * At the moment, we used a static mapping of transmit/receive queue pairs to a
156 157 * given VSI (eg. rings to a group). Though in the fullness of time, we want to
157 158 * make this something which is fully dynamic and take advantage of documented,
158 159 * but not yet available functionality for adding filters based on VXLAN and
159 160 * other encapsulation technologies.
160 161 *
161 162 * -------------------------------------
162 163 * Broadcast, Multicast, and Promiscuous
163 164 * -------------------------------------
164 165 *
165 166 * As part of the GLDv3, we need to make sure that we can handle receiving
166 167 * broadcast and multicast traffic. As well as enabling promiscuous mode when
167 168 * requested. GLDv3 requires that all broadcast and multicast traffic be
168 169 * retrieved by the default group, eg. the first one. This is the same thing as
169 170 * the default VSI.
170 171 *
171 172 * To receieve broadcast traffic, we enable it through the admin queue, rather
172 173 * than use one of our filters for it. For multicast traffic, we reserve a
173 174 * certain number of the hash filters and assign them to a given PF. When we
174 175 * exceed those, we then switch to using promiscuous mode for multicast traffic.
175 176 *
176 177 * More specifically, once we exceed the number of filters (indicated because
177 178 * the i40e_t`i40e_resources.ifr_nmcastfilt ==
178 179 * i40e_t`i40e_resources.ifr_nmcastfilt_used), we then instead need to toggle
179 180 * promiscuous mode. If promiscuous mode is toggled then we keep track of the
180 181 * number of MACs added to it by incrementing i40e_t`i40e_mcast_promisc_count.
181 182 * That will stay enabled until that count reaches zero indicating that we have
182 183 * only added multicast addresses that we have a corresponding entry for.
183 184 *
184 185 * Because MAC itself wants to toggle promiscuous mode, which includes both
185 186 * unicast and multicast traffic, we go through and keep track of that
186 187 * ourselves. That is maintained through the use of the i40e_t`i40e_promisc_on
187 188 * member.
188 189 *
189 190 * --------------
190 191 * VSI Management
191 192 * --------------
192 193 *
193 194 * The PFs share 384 VSIs. The firmware creates one VSI per PF by default.
194 195 * During chip start we retrieve the SEID of this VSI and assign it as the
195 196 * default VSI for our VEB (one VEB per PF). We then add additional VSIs to
196 197 * the VEB up to the determined number of rx groups: i40e_t`i40e_num_rx_groups.
197 198 * We currently cap this number to I40E_GROUP_MAX to a) make sure all PFs can
198 199 * allocate the same number of VSIs, and b) to keep the interrupt multiplexing
199 200 * under control. In the future, when we improve the interrupt allocation, we
200 201 * may want to revisit this cap to make better use of the available VSIs. The
201 202 * VSI allocation and configuration can be found in i40e_chip_start().
202 203 *
203 204 * ----------------
204 205 * Structure Layout
205 206 * ----------------
206 207 *
207 208 * The following images relates the core data structures together. The primary
208 209 * structure in the system is the i40e_t. It itself contains multiple rings,
209 210 * i40e_trqpair_t's which contain the various transmit and receive data. The
210 211 * receive data is stored outside of the i40e_trqpair_t and instead in the
211 212 * i40e_rx_data_t. The i40e_t has a corresponding i40e_device_t which keeps
212 213 * track of per-physical device state. Finally, for every active descriptor,
213 214 * there is a corresponding control block, which is where the
214 215 * i40e_rx_control_block_t and the i40e_tx_control_block_t come from.
215 216 *
216 217 * +-----------------------+ +-----------------------+
217 218 * | Global i40e_t list | | Global Device list |
218 219 * | | +--| |
219 220 * | i40e_glist | | | i40e_dlist |
220 221 * +-----------------------+ | +-----------------------+
221 222 * | v
222 223 * | +------------------------+ +-----------------------+
223 224 * | | Device-wide Structure |----->| Device-wide Structure |--> ...
224 225 * | | i40e_device_t | | i40e_device_t |
225 226 * | | | +-----------------------+
226 227 * | | dev_info_t * ------+--> Parent in devices tree.
227 228 * | | uint_t ------+--> PCI bus number
228 229 * | | uint_t ------+--> PCI device number
229 230 * | | uint_t ------+--> Number of functions
230 231 * | | i40e_switch_rsrcs_t ---+--> Captured total switch resources
231 232 * | | list_t ------+-------------+
232 233 * | +------------------------+ |
233 234 * | ^ |
234 235 * | +--------+ |
235 236 * | | v
236 237 * | +---------------------------+ | +-------------------+
237 238 * +->| GLDv3 Device, per PF |-----|-->| GLDv3 Device (PF) |--> ...
238 239 * | i40e_t | | | i40e_t |
239 240 * | **Primary Structure** | | +-------------------+
240 241 * | | |
241 242 * | i40e_device_t * --+-----+
242 243 * | i40e_state_t --+---> Device State
243 244 * | i40e_hw_t --+---> Intel common code structure
244 245 * | mac_handle_t --+---> GLDv3 handle to MAC
245 246 * | ddi_periodic_t --+---> Link activity timer
246 247 * | i40e_vsi_t * --+---> Array of VSIs
247 248 * | i40e_func_rsrc_t --+---> Available hardware resources
248 249 * | i40e_switch_rsrc_t * --+---> Switch resource snapshot
249 250 * | i40e_sdu --+---> Current MTU
250 251 * | i40e_frame_max --+---> Current HW frame size
251 252 * | i40e_uaddr_t * --+---> Array of assigned unicast MACs
252 253 * | i40e_maddr_t * --+---> Array of assigned multicast MACs
253 254 * | i40e_mcast_promisccount --+---> Active multicast state
254 255 * | i40e_promisc_on --+---> Current promiscuous mode state
255 256 * | uint_t --+---> Number of transmit/receive pairs
256 257 * | i40e_rx_group_t * --+---> Array of Rx groups
257 258 * | kstat_t * --+---> PF kstats
258 259 * | i40e_pf_stats_t --+---> PF kstat backing data
259 260 * | i40e_trqpair_t * --+---------+
260 261 * +---------------------------+ |
261 262 * |
262 263 * v
263 264 * +-------------------------------+ +-----------------------------+
264 265 * | Transmit/Receive Queue Pair |-------| Transmit/Receive Queue Pair |->...
265 266 * | i40e_trqpair_t | | i40e_trqpair_t |
266 267 * + Ring Data Structure | +-----------------------------+
267 268 * | |
268 269 * | mac_ring_handle_t +--> MAC RX ring handle
269 270 * | mac_ring_handle_t +--> MAC TX ring handle
270 271 * | i40e_rxq_stat_t --+--> RX Queue stats
271 272 * | i40e_txq_stat_t --+--> TX Queue stats
272 273 * | uint32_t (tx ring size) +--> TX Ring Size
273 274 * | uint32_t (tx free list size) +--> TX Free List Size
274 275 * | i40e_dma_buffer_t --------+--> TX Descriptor ring DMA
275 276 * | i40e_tx_desc_t * --------+--> TX descriptor ring
276 277 * | volatile unt32_t * +--> TX Write back head
277 278 * | uint32_t -------+--> TX ring head
278 279 * | uint32_t -------+--> TX ring tail
279 280 * | uint32_t -------+--> Num TX desc free
280 281 * | i40e_tx_control_block_t * --+--> TX control block array ---+
281 282 * | i40e_tx_control_block_t ** --+--> TCB work list ----+
282 283 * | i40e_tx_control_block_t ** --+--> TCB free list ---+
283 284 * | uint32_t -------+--> Free TCB count |
284 285 * | i40e_rx_data_t * -------+--+ v
285 286 * +-------------------------------+ | +---------------------------+
286 287 * | | Per-TX Frame Metadata |
287 288 * | | i40e_tx_control_block_t |
288 289 * +--------------------+ | |
289 290 * | mblk to transmit <--+--- mblk_t * |
290 291 * | type of transmit <--+--- i40e_tx_type_t |
291 292 * | TX DMA handle <--+--- ddi_dma_handle_t |
292 293 * v TX DMA buffer <--+--- i40e_dma_buffer_t |
293 294 * +------------------------------+ +---------------------------+
294 295 * | Core Receive Data |
295 296 * | i40e_rx_data_t |
296 297 * | |
297 298 * | i40e_dma_buffer_t --+--> RX descriptor DMA Data
298 299 * | i40e_rx_desc_t --+--> RX descriptor ring
299 300 * | uint32_t --+--> Next free desc.
300 301 * | i40e_rx_control_block_t * --+--> RX Control Block Array ---+
301 302 * | i40e_rx_control_block_t ** --+--> RCB work list ---+
302 303 * | i40e_rx_control_block_t ** --+--> RCB free list ---+
303 304 * +------------------------------+ |
304 305 * ^ |
305 306 * | +---------------------------+ |
306 307 * | | Per-RX Frame Metadata |<---------------+
307 308 * | | i40e_rx_control_block_t |
308 309 * | | |
309 310 * | | mblk_t * ----+--> Received mblk_t data
310 311 * | | uint32_t ----+--> Reference count
311 312 * | | i40e_dma_buffer_t ----+--> Receive data DMA info
312 313 * | | frtn_t ----+--> mblk free function info
313 314 * +-----+-- i40e_rx_data_t * |
314 315 * +---------------------------+
315 316 *
316 317 * -------------
317 318 * Lock Ordering
318 319 * -------------
319 320 *
320 321 * In order to ensure that we don't deadlock, the following represents the
321 322 * lock order being used. When grabbing locks, follow the following order. Lower
322 323 * numbers are more important. Thus, the i40e_glock which is number 0, must be
323 324 * taken before any other locks in the driver. On the other hand, the
324 325 * i40e_t`i40e_stat_lock, has the highest number because it's the least
325 326 * important lock. Note, that just because one lock is higher than another does
326 327 * not mean that all intermediary locks are required.
327 328 *
328 329 * 0) i40e_glock
329 330 * 1) i40e_t`i40e_general_lock
330 331 *
331 332 * 2) i40e_trqpair_t`itrq_rx_lock
332 333 * 3) i40e_trqpair_t`itrq_tx_lock
333 334 * 4) i40e_trqpair_t`itrq_intr_lock
334 335 * 5) i40e_t`i40e_rx_pending_lock
335 336 * 6) i40e_trqpair_t`itrq_tcb_lock
336 337 *
337 338 * 7) i40e_t`i40e_stat_lock
338 339 *
339 340 * Rules and expectations:
340 341 *
341 342 * 1) A thread holding locks belong to one PF should not hold locks belonging to
342 343 * a second. If for some reason this becomes necessary, locks should be grabbed
343 344 * based on the list order in the i40e_device_t, which implies that the
344 345 * i40e_glock is held.
345 346 *
346 347 * 2) When grabbing locks between multiple transmit and receive queues, the
347 348 * locks for the lowest number transmit/receive queue should be grabbed first.
348 349 *
349 350 * 3) When grabbing both the transmit and receive lock for a given queue, always
350 351 * grab i40e_trqpair_t`itrq_rx_lock before the i40e_trqpair_t`itrq_tx_lock.
351 352 *
352 353 * 4) The following pairs of locks are not expected to be held at the same time:
353 354 *
354 355 * o i40e_t`i40e_rx_pending_lock and i40e_trqpair_t`itrq_tcb_lock
355 356 * o i40e_trqpair_t`itrq_intr_lock is not expected to be held with any
356 357 * other lock except i40e_t`i40e_general_lock in mc_start(9E) and
357 358 * mc_stop(9e).
358 359 *
359 360 * -----------
360 361 * Future Work
361 362 * -----------
362 363 *
363 364 * At the moment the i40e_t driver is rather bare bones, allowing us to start
364 365 * getting data flowing and folks using it while we develop additional features.
365 366 * While bugs have been filed to cover this future work, the following gives an
366 367 * overview of expected work:
367 368 *
368 369 * o DMA binding and breaking up the locking in ring recycling.
369 370 * o Enhanced detection of device errors
370 371 * o Participation in IRM
371 372 * o FMA device reset
372 373 * o Stall detection, temperature error detection, etc.
373 374 * o More dynamic resource pools
374 375 */
375 376
376 377 #include "i40e_sw.h"
377 378
378 379 static char i40e_ident[] = "Intel 10/40Gb Ethernet v1.0.3";
379 380
380 381 /*
381 382 * The i40e_glock primarily protects the lists below and the i40e_device_t
382 383 * structures.
383 384 */
384 385 static kmutex_t i40e_glock;
385 386 static list_t i40e_glist;
386 387 static list_t i40e_dlist;
387 388
388 389 /*
389 390 * Access attributes for register mapping.
390 391 */
391 392 static ddi_device_acc_attr_t i40e_regs_acc_attr = {
392 393 DDI_DEVICE_ATTR_V1,
393 394 DDI_STRUCTURE_LE_ACC,
394 395 DDI_STRICTORDER_ACC,
395 396 DDI_FLAGERR_ACC
396 397 };
397 398
398 399 /*
399 400 * Logging function for this driver.
400 401 */
401 402 static void
402 403 i40e_dev_err(i40e_t *i40e, int level, boolean_t console, const char *fmt,
403 404 va_list ap)
404 405 {
405 406 char buf[1024];
406 407
407 408 (void) vsnprintf(buf, sizeof (buf), fmt, ap);
408 409
409 410 if (i40e == NULL) {
410 411 cmn_err(level, (console) ? "%s: %s" : "!%s: %s",
411 412 I40E_MODULE_NAME, buf);
412 413 } else {
413 414 dev_err(i40e->i40e_dip, level, (console) ? "%s" : "!%s",
414 415 buf);
415 416 }
416 417 }
417 418
418 419 /*
419 420 * Because there's the stupid trailing-comma problem with the C preprocessor
420 421 * and variable arguments, I need to instantiate these. Pardon the redundant
421 422 * code.
422 423 */
423 424 /*PRINTFLIKE2*/
424 425 void
425 426 i40e_error(i40e_t *i40e, const char *fmt, ...)
426 427 {
427 428 va_list ap;
428 429
429 430 va_start(ap, fmt);
430 431 i40e_dev_err(i40e, CE_WARN, B_FALSE, fmt, ap);
431 432 va_end(ap);
432 433 }
433 434
434 435 /*PRINTFLIKE2*/
435 436 void
436 437 i40e_log(i40e_t *i40e, const char *fmt, ...)
437 438 {
438 439 va_list ap;
439 440
440 441 va_start(ap, fmt);
441 442 i40e_dev_err(i40e, CE_NOTE, B_FALSE, fmt, ap);
442 443 va_end(ap);
443 444 }
444 445
445 446 /*PRINTFLIKE2*/
446 447 void
447 448 i40e_notice(i40e_t *i40e, const char *fmt, ...)
448 449 {
449 450 va_list ap;
450 451
451 452 va_start(ap, fmt);
452 453 i40e_dev_err(i40e, CE_NOTE, B_TRUE, fmt, ap);
453 454 va_end(ap);
454 455 }
455 456
456 457 /*
457 458 * Various parts of the driver need to know if the controller is from the X722
458 459 * family, which has a few additional capabilities and different programming
459 460 * means. We don't consider virtual functions as part of this as they are quite
460 461 * different and will require substantially more work.
461 462 */
462 463 static boolean_t
463 464 i40e_is_x722(i40e_t *i40e)
464 465 {
465 466 return (i40e->i40e_hw_space.mac.type == I40E_MAC_X722);
466 467 }
467 468
468 469 static void
469 470 i40e_device_rele(i40e_t *i40e)
470 471 {
471 472 i40e_device_t *idp = i40e->i40e_device;
472 473
473 474 if (idp == NULL)
474 475 return;
475 476
476 477 mutex_enter(&i40e_glock);
477 478 VERIFY(idp->id_nreg > 0);
478 479 list_remove(&idp->id_i40e_list, i40e);
479 480 idp->id_nreg--;
480 481 if (idp->id_nreg == 0) {
481 482 list_remove(&i40e_dlist, idp);
482 483 list_destroy(&idp->id_i40e_list);
483 484 kmem_free(idp->id_rsrcs, sizeof (i40e_switch_rsrc_t) *
484 485 idp->id_rsrcs_alloc);
485 486 kmem_free(idp, sizeof (i40e_device_t));
486 487 }
487 488 i40e->i40e_device = NULL;
488 489 mutex_exit(&i40e_glock);
489 490 }
490 491
491 492 static i40e_device_t *
492 493 i40e_device_find(i40e_t *i40e, dev_info_t *parent, uint_t bus, uint_t device)
493 494 {
494 495 i40e_device_t *idp;
495 496 mutex_enter(&i40e_glock);
496 497 for (idp = list_head(&i40e_dlist); idp != NULL;
497 498 idp = list_next(&i40e_dlist, idp)) {
498 499 if (idp->id_parent == parent && idp->id_pci_bus == bus &&
499 500 idp->id_pci_device == device) {
500 501 break;
501 502 }
502 503 }
503 504
504 505 if (idp != NULL) {
505 506 VERIFY(idp->id_nreg < idp->id_nfuncs);
506 507 idp->id_nreg++;
507 508 } else {
508 509 i40e_hw_t *hw = &i40e->i40e_hw_space;
509 510 ASSERT(hw->num_ports > 0);
510 511 ASSERT(hw->num_partitions > 0);
511 512
512 513 /*
513 514 * The Intel common code doesn't exactly keep the number of PCI
514 515 * functions. But it calculates it during discovery of
515 516 * partitions and ports. So what we do is undo the calculation
516 517 * that it does originally, as functions are evenly spread
517 518 * across ports in the rare case of partitions.
518 519 */
519 520 idp = kmem_alloc(sizeof (i40e_device_t), KM_SLEEP);
520 521 idp->id_parent = parent;
521 522 idp->id_pci_bus = bus;
522 523 idp->id_pci_device = device;
523 524 idp->id_nfuncs = hw->num_ports * hw->num_partitions;
524 525 idp->id_nreg = 1;
525 526 idp->id_rsrcs_alloc = i40e->i40e_switch_rsrc_alloc;
526 527 idp->id_rsrcs_act = i40e->i40e_switch_rsrc_actual;
527 528 idp->id_rsrcs = kmem_alloc(sizeof (i40e_switch_rsrc_t) *
528 529 idp->id_rsrcs_alloc, KM_SLEEP);
529 530 bcopy(i40e->i40e_switch_rsrcs, idp->id_rsrcs,
530 531 sizeof (i40e_switch_rsrc_t) * idp->id_rsrcs_alloc);
531 532 list_create(&idp->id_i40e_list, sizeof (i40e_t),
532 533 offsetof(i40e_t, i40e_dlink));
533 534
534 535 list_insert_tail(&i40e_dlist, idp);
535 536 }
536 537
537 538 list_insert_tail(&idp->id_i40e_list, i40e);
538 539 mutex_exit(&i40e_glock);
539 540
540 541 return (idp);
541 542 }
542 543
543 544 static void
544 545 i40e_link_state_set(i40e_t *i40e, link_state_t state)
545 546 {
546 547 if (i40e->i40e_link_state == state)
547 548 return;
548 549
549 550 i40e->i40e_link_state = state;
550 551 mac_link_update(i40e->i40e_mac_hdl, i40e->i40e_link_state);
551 552 }
552 553
553 554 /*
554 555 * This is a basic link check routine. Mostly we're using this just to see
555 556 * if we can get any accurate information about the state of the link being
556 557 * up or down, as well as updating the link state, speed, etc. information.
557 558 */
558 559 void
559 560 i40e_link_check(i40e_t *i40e)
560 561 {
561 562 i40e_hw_t *hw = &i40e->i40e_hw_space;
562 563 boolean_t ls;
563 564 int ret;
564 565
565 566 ASSERT(MUTEX_HELD(&i40e->i40e_general_lock));
566 567
567 568 hw->phy.get_link_info = B_TRUE;
568 569 if ((ret = i40e_get_link_status(hw, &ls)) != I40E_SUCCESS) {
569 570 i40e->i40e_s_link_status_errs++;
570 571 i40e->i40e_s_link_status_lasterr = ret;
571 572 return;
572 573 }
573 574
574 575 /*
575 576 * Firmware abstracts all of the mac and phy information for us, so we
576 577 * can use i40e_get_link_status to determine the current state.
577 578 */
578 579 if (ls == B_TRUE) {
579 580 enum i40e_aq_link_speed speed;
580 581
581 582 speed = i40e_get_link_speed(hw);
582 583
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555 lines elided |
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583 584 /*
584 585 * Translate from an i40e value to a value in Mbits/s.
585 586 */
586 587 switch (speed) {
587 588 case I40E_LINK_SPEED_100MB:
588 589 i40e->i40e_link_speed = 100;
589 590 break;
590 591 case I40E_LINK_SPEED_1GB:
591 592 i40e->i40e_link_speed = 1000;
592 593 break;
594 + case I40E_LINK_SPEED_2_5GB:
595 + i40e->i40e_link_speed = 2500;
596 + break;
597 + case I40E_LINK_SPEED_5GB:
598 + i40e->i40e_link_speed = 5000;
599 + break;
593 600 case I40E_LINK_SPEED_10GB:
594 601 i40e->i40e_link_speed = 10000;
595 602 break;
596 603 case I40E_LINK_SPEED_20GB:
597 604 i40e->i40e_link_speed = 20000;
598 605 break;
599 606 case I40E_LINK_SPEED_40GB:
600 607 i40e->i40e_link_speed = 40000;
601 608 break;
602 609 case I40E_LINK_SPEED_25GB:
603 610 i40e->i40e_link_speed = 25000;
604 611 break;
605 612 default:
606 613 i40e->i40e_link_speed = 0;
607 614 break;
608 615 }
609 616
610 617 /*
611 618 * At this time, hardware does not support half-duplex
612 619 * operation, hence why we don't ask the hardware about our
613 620 * current speed.
614 621 */
615 622 i40e->i40e_link_duplex = LINK_DUPLEX_FULL;
616 623 i40e_link_state_set(i40e, LINK_STATE_UP);
617 624 } else {
618 625 i40e->i40e_link_speed = 0;
619 626 i40e->i40e_link_duplex = 0;
620 627 i40e_link_state_set(i40e, LINK_STATE_DOWN);
621 628 }
622 629 }
623 630
624 631 static void
625 632 i40e_rem_intrs(i40e_t *i40e)
626 633 {
627 634 int i, rc;
628 635
629 636 for (i = 0; i < i40e->i40e_intr_count; i++) {
630 637 rc = ddi_intr_free(i40e->i40e_intr_handles[i]);
631 638 if (rc != DDI_SUCCESS) {
632 639 i40e_log(i40e, "failed to free interrupt %d: %d",
633 640 i, rc);
634 641 }
635 642 }
636 643
637 644 kmem_free(i40e->i40e_intr_handles, i40e->i40e_intr_size);
638 645 i40e->i40e_intr_handles = NULL;
639 646 }
640 647
641 648 static void
642 649 i40e_rem_intr_handlers(i40e_t *i40e)
643 650 {
644 651 int i, rc;
645 652
646 653 for (i = 0; i < i40e->i40e_intr_count; i++) {
647 654 rc = ddi_intr_remove_handler(i40e->i40e_intr_handles[i]);
648 655 if (rc != DDI_SUCCESS) {
649 656 i40e_log(i40e, "failed to remove interrupt %d: %d",
650 657 i, rc);
651 658 }
652 659 }
653 660 }
654 661
655 662 /*
656 663 * illumos Fault Management Architecture (FMA) support.
657 664 */
658 665
659 666 int
660 667 i40e_check_acc_handle(ddi_acc_handle_t handle)
661 668 {
662 669 ddi_fm_error_t de;
663 670
664 671 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
665 672 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
666 673 return (de.fme_status);
667 674 }
668 675
669 676 int
670 677 i40e_check_dma_handle(ddi_dma_handle_t handle)
671 678 {
672 679 ddi_fm_error_t de;
673 680
674 681 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
675 682 return (de.fme_status);
676 683 }
677 684
678 685 /*
679 686 * Fault service error handling callback function.
680 687 */
681 688 /* ARGSUSED */
682 689 static int
683 690 i40e_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
684 691 {
685 692 pci_ereport_post(dip, err, NULL);
686 693 return (err->fme_status);
687 694 }
688 695
689 696 static void
690 697 i40e_fm_init(i40e_t *i40e)
691 698 {
692 699 ddi_iblock_cookie_t iblk;
693 700
694 701 i40e->i40e_fm_capabilities = ddi_prop_get_int(DDI_DEV_T_ANY,
695 702 i40e->i40e_dip, DDI_PROP_DONTPASS, "fm_capable",
696 703 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
697 704 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
698 705
699 706 if (i40e->i40e_fm_capabilities < 0) {
700 707 i40e->i40e_fm_capabilities = 0;
701 708 } else if (i40e->i40e_fm_capabilities > 0xf) {
702 709 i40e->i40e_fm_capabilities = DDI_FM_EREPORT_CAPABLE |
703 710 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE |
704 711 DDI_FM_ERRCB_CAPABLE;
705 712 }
706 713
707 714 /*
708 715 * Only register with IO Fault Services if we have some capability
709 716 */
710 717 if (i40e->i40e_fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
711 718 i40e_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
712 719 } else {
713 720 i40e_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
714 721 }
715 722
716 723 if (i40e->i40e_fm_capabilities) {
717 724 ddi_fm_init(i40e->i40e_dip, &i40e->i40e_fm_capabilities, &iblk);
718 725
719 726 if (DDI_FM_EREPORT_CAP(i40e->i40e_fm_capabilities) ||
720 727 DDI_FM_ERRCB_CAP(i40e->i40e_fm_capabilities)) {
721 728 pci_ereport_setup(i40e->i40e_dip);
722 729 }
723 730
724 731 if (DDI_FM_ERRCB_CAP(i40e->i40e_fm_capabilities)) {
725 732 ddi_fm_handler_register(i40e->i40e_dip,
726 733 i40e_fm_error_cb, (void*)i40e);
727 734 }
728 735 }
729 736
730 737 if (i40e->i40e_fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
731 738 i40e_init_dma_attrs(i40e, B_TRUE);
732 739 } else {
733 740 i40e_init_dma_attrs(i40e, B_FALSE);
734 741 }
735 742 }
736 743
737 744 static void
738 745 i40e_fm_fini(i40e_t *i40e)
739 746 {
740 747 if (i40e->i40e_fm_capabilities) {
741 748
742 749 if (DDI_FM_EREPORT_CAP(i40e->i40e_fm_capabilities) ||
743 750 DDI_FM_ERRCB_CAP(i40e->i40e_fm_capabilities))
744 751 pci_ereport_teardown(i40e->i40e_dip);
745 752
746 753 if (DDI_FM_ERRCB_CAP(i40e->i40e_fm_capabilities))
747 754 ddi_fm_handler_unregister(i40e->i40e_dip);
748 755
749 756 ddi_fm_fini(i40e->i40e_dip);
750 757 }
751 758 }
752 759
753 760 void
754 761 i40e_fm_ereport(i40e_t *i40e, char *detail)
755 762 {
756 763 uint64_t ena;
757 764 char buf[FM_MAX_CLASS];
758 765
759 766 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
760 767 ena = fm_ena_generate(0, FM_ENA_FMT1);
761 768 if (DDI_FM_EREPORT_CAP(i40e->i40e_fm_capabilities)) {
762 769 ddi_fm_ereport_post(i40e->i40e_dip, buf, ena, DDI_NOSLEEP,
763 770 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
764 771 }
765 772 }
766 773
767 774 /*
768 775 * Here we're trying to set the SEID of the default VSI. In general,
769 776 * when we come through and look at this shortly after attach, we
770 777 * expect there to only be a single element present, which is the
771 778 * default VSI. Importantly, each PF seems to not see any other
772 779 * devices, in part because of the simple switch mode that we're
773 780 * using. If for some reason, we see more artifacts, we'll need to
774 781 * revisit what we're doing here.
775 782 */
776 783 static boolean_t
777 784 i40e_set_def_vsi_seid(i40e_t *i40e)
778 785 {
779 786 i40e_hw_t *hw = &i40e->i40e_hw_space;
780 787 struct i40e_aqc_get_switch_config_resp *sw_config;
781 788 uint8_t aq_buf[I40E_AQ_LARGE_BUF];
782 789 uint16_t next = 0;
783 790 int rc;
784 791
785 792 /* LINTED: E_BAD_PTR_CAST_ALIGN */
786 793 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
787 794 rc = i40e_aq_get_switch_config(hw, sw_config, sizeof (aq_buf), &next,
788 795 NULL);
789 796 if (rc != I40E_SUCCESS) {
790 797 i40e_error(i40e, "i40e_aq_get_switch_config() failed %d: %d",
791 798 rc, hw->aq.asq_last_status);
792 799 return (B_FALSE);
793 800 }
794 801
795 802 if (LE_16(sw_config->header.num_reported) != 1) {
796 803 i40e_error(i40e, "encountered multiple (%d) switching units "
797 804 "during attach, not proceeding",
798 805 LE_16(sw_config->header.num_reported));
799 806 return (B_FALSE);
800 807 }
801 808
802 809 I40E_DEF_VSI_SEID(i40e) = sw_config->element[0].seid;
803 810 return (B_TRUE);
804 811 }
805 812
806 813 /*
807 814 * Get the SEID of the uplink MAC.
808 815 */
809 816 static int
810 817 i40e_get_mac_seid(i40e_t *i40e)
811 818 {
812 819 i40e_hw_t *hw = &i40e->i40e_hw_space;
813 820 struct i40e_aqc_get_switch_config_resp *sw_config;
814 821 uint8_t aq_buf[I40E_AQ_LARGE_BUF];
815 822 uint16_t next = 0;
816 823 int rc;
817 824
818 825 /* LINTED: E_BAD_PTR_CAST_ALIGN */
819 826 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
820 827 rc = i40e_aq_get_switch_config(hw, sw_config, sizeof (aq_buf), &next,
821 828 NULL);
822 829 if (rc != I40E_SUCCESS) {
823 830 i40e_error(i40e, "i40e_aq_get_switch_config() failed %d: %d",
824 831 rc, hw->aq.asq_last_status);
825 832 return (-1);
826 833 }
827 834
828 835 return (LE_16(sw_config->element[0].uplink_seid));
829 836 }
830 837
831 838 /*
832 839 * We need to fill the i40e_hw_t structure with the capabilities of this PF. We
833 840 * must also provide the memory for it; however, we don't need to keep it around
834 841 * to the call to the common code. It takes it and parses it into an internal
835 842 * structure.
836 843 */
837 844 static boolean_t
838 845 i40e_get_hw_capabilities(i40e_t *i40e, i40e_hw_t *hw)
839 846 {
840 847 struct i40e_aqc_list_capabilities_element_resp *buf;
841 848 int rc;
842 849 size_t len;
843 850 uint16_t needed;
844 851 int nelems = I40E_HW_CAP_DEFAULT;
845 852
846 853 len = nelems * sizeof (*buf);
847 854
848 855 for (;;) {
849 856 ASSERT(len > 0);
850 857 buf = kmem_alloc(len, KM_SLEEP);
851 858 rc = i40e_aq_discover_capabilities(hw, buf, len,
852 859 &needed, i40e_aqc_opc_list_func_capabilities, NULL);
853 860 kmem_free(buf, len);
854 861
855 862 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOMEM &&
856 863 nelems == I40E_HW_CAP_DEFAULT) {
857 864 if (nelems == needed) {
858 865 i40e_error(i40e, "Capability discovery failed "
859 866 "due to byzantine common code");
860 867 return (B_FALSE);
861 868 }
862 869 len = needed;
863 870 continue;
864 871 } else if (rc != I40E_SUCCESS ||
865 872 hw->aq.asq_last_status != I40E_AQ_RC_OK) {
866 873 i40e_error(i40e, "Capability discovery failed: %d", rc);
867 874 return (B_FALSE);
868 875 }
869 876
870 877 break;
871 878 }
872 879
873 880 return (B_TRUE);
874 881 }
875 882
876 883 /*
877 884 * Obtain the switch's capabilities as seen by this PF and keep it around for
878 885 * our later use.
879 886 */
880 887 static boolean_t
881 888 i40e_get_switch_resources(i40e_t *i40e)
882 889 {
883 890 i40e_hw_t *hw = &i40e->i40e_hw_space;
884 891 uint8_t cnt = 2;
885 892 uint8_t act;
886 893 size_t size;
887 894 i40e_switch_rsrc_t *buf;
888 895
889 896 for (;;) {
890 897 enum i40e_status_code ret;
891 898 size = cnt * sizeof (i40e_switch_rsrc_t);
892 899 ASSERT(size > 0);
893 900 if (size > UINT16_MAX)
894 901 return (B_FALSE);
895 902 buf = kmem_alloc(size, KM_SLEEP);
896 903
897 904 ret = i40e_aq_get_switch_resource_alloc(hw, &act, buf,
898 905 cnt, NULL);
899 906 if (ret == I40E_ERR_ADMIN_QUEUE_ERROR &&
900 907 hw->aq.asq_last_status == I40E_AQ_RC_EINVAL) {
901 908 kmem_free(buf, size);
902 909 cnt += I40E_SWITCH_CAP_DEFAULT;
903 910 continue;
904 911 } else if (ret != I40E_SUCCESS) {
905 912 kmem_free(buf, size);
906 913 i40e_error(i40e,
907 914 "failed to retrieve switch statistics: %d", ret);
908 915 return (B_FALSE);
909 916 }
910 917
911 918 break;
912 919 }
913 920
914 921 i40e->i40e_switch_rsrc_alloc = cnt;
915 922 i40e->i40e_switch_rsrc_actual = act;
916 923 i40e->i40e_switch_rsrcs = buf;
917 924
918 925 return (B_TRUE);
919 926 }
920 927
921 928 static void
922 929 i40e_cleanup_resources(i40e_t *i40e)
923 930 {
924 931 if (i40e->i40e_uaddrs != NULL) {
925 932 kmem_free(i40e->i40e_uaddrs, sizeof (i40e_uaddr_t) *
926 933 i40e->i40e_resources.ifr_nmacfilt);
927 934 i40e->i40e_uaddrs = NULL;
928 935 }
929 936
930 937 if (i40e->i40e_maddrs != NULL) {
931 938 kmem_free(i40e->i40e_maddrs, sizeof (i40e_maddr_t) *
932 939 i40e->i40e_resources.ifr_nmcastfilt);
933 940 i40e->i40e_maddrs = NULL;
934 941 }
935 942
936 943 if (i40e->i40e_switch_rsrcs != NULL) {
937 944 size_t sz = sizeof (i40e_switch_rsrc_t) *
938 945 i40e->i40e_switch_rsrc_alloc;
939 946 ASSERT(sz > 0);
940 947 kmem_free(i40e->i40e_switch_rsrcs, sz);
941 948 i40e->i40e_switch_rsrcs = NULL;
942 949 }
943 950
944 951 if (i40e->i40e_device != NULL)
945 952 i40e_device_rele(i40e);
946 953 }
947 954
948 955 static boolean_t
949 956 i40e_get_available_resources(i40e_t *i40e)
950 957 {
951 958 dev_info_t *parent;
952 959 uint16_t bus, device, func;
953 960 uint_t nregs;
954 961 int *regs, i;
955 962 i40e_device_t *idp;
956 963 i40e_hw_t *hw = &i40e->i40e_hw_space;
957 964
958 965 parent = ddi_get_parent(i40e->i40e_dip);
959 966
960 967 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, i40e->i40e_dip, 0, "reg",
961 968 ®s, &nregs) != DDI_PROP_SUCCESS) {
962 969 return (B_FALSE);
963 970 }
964 971
965 972 if (nregs < 1) {
966 973 ddi_prop_free(regs);
967 974 return (B_FALSE);
968 975 }
969 976
970 977 bus = PCI_REG_BUS_G(regs[0]);
971 978 device = PCI_REG_DEV_G(regs[0]);
972 979 func = PCI_REG_FUNC_G(regs[0]);
973 980 ddi_prop_free(regs);
974 981
975 982 i40e->i40e_hw_space.bus.func = func;
976 983 i40e->i40e_hw_space.bus.device = device;
977 984
978 985 if (i40e_get_switch_resources(i40e) == B_FALSE) {
979 986 return (B_FALSE);
980 987 }
981 988
982 989 /*
983 990 * To calculate the total amount of a resource we have available, we
984 991 * need to add how many our i40e_t thinks it has guaranteed, if any, and
985 992 * then we need to go through and divide the number of available on the
986 993 * device, which was snapshotted before anyone should have allocated
987 994 * anything, and use that to derive how many are available from the
988 995 * pool. Longer term, we may want to turn this into something that's
989 996 * more of a pool-like resource that everything can share (though that
990 997 * may require some more assistance from MAC).
991 998 *
992 999 * Though for transmit and receive queue pairs, we just have to ask
993 1000 * firmware instead.
994 1001 */
995 1002 idp = i40e_device_find(i40e, parent, bus, device);
996 1003 i40e->i40e_device = idp;
997 1004 i40e->i40e_resources.ifr_nvsis = 0;
998 1005 i40e->i40e_resources.ifr_nvsis_used = 0;
999 1006 i40e->i40e_resources.ifr_nmacfilt = 0;
1000 1007 i40e->i40e_resources.ifr_nmacfilt_used = 0;
1001 1008 i40e->i40e_resources.ifr_nmcastfilt = 0;
1002 1009 i40e->i40e_resources.ifr_nmcastfilt_used = 0;
1003 1010
1004 1011 for (i = 0; i < i40e->i40e_switch_rsrc_actual; i++) {
1005 1012 i40e_switch_rsrc_t *srp = &i40e->i40e_switch_rsrcs[i];
1006 1013
1007 1014 switch (srp->resource_type) {
1008 1015 case I40E_AQ_RESOURCE_TYPE_VSI:
1009 1016 i40e->i40e_resources.ifr_nvsis +=
1010 1017 LE_16(srp->guaranteed);
1011 1018 i40e->i40e_resources.ifr_nvsis_used = LE_16(srp->used);
1012 1019 break;
1013 1020 case I40E_AQ_RESOURCE_TYPE_MACADDR:
1014 1021 i40e->i40e_resources.ifr_nmacfilt +=
1015 1022 LE_16(srp->guaranteed);
1016 1023 i40e->i40e_resources.ifr_nmacfilt_used =
1017 1024 LE_16(srp->used);
1018 1025 break;
1019 1026 case I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH:
1020 1027 i40e->i40e_resources.ifr_nmcastfilt +=
1021 1028 LE_16(srp->guaranteed);
1022 1029 i40e->i40e_resources.ifr_nmcastfilt_used =
1023 1030 LE_16(srp->used);
1024 1031 break;
1025 1032 default:
1026 1033 break;
1027 1034 }
1028 1035 }
1029 1036
1030 1037 for (i = 0; i < idp->id_rsrcs_act; i++) {
1031 1038 i40e_switch_rsrc_t *srp = &i40e->i40e_switch_rsrcs[i];
1032 1039 switch (srp->resource_type) {
1033 1040 case I40E_AQ_RESOURCE_TYPE_VSI:
1034 1041 i40e->i40e_resources.ifr_nvsis +=
1035 1042 LE_16(srp->total_unalloced) / idp->id_nfuncs;
1036 1043 break;
1037 1044 case I40E_AQ_RESOURCE_TYPE_MACADDR:
1038 1045 i40e->i40e_resources.ifr_nmacfilt +=
1039 1046 LE_16(srp->total_unalloced) / idp->id_nfuncs;
1040 1047 break;
1041 1048 case I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH:
1042 1049 i40e->i40e_resources.ifr_nmcastfilt +=
1043 1050 LE_16(srp->total_unalloced) / idp->id_nfuncs;
1044 1051 default:
1045 1052 break;
1046 1053 }
1047 1054 }
1048 1055
1049 1056 i40e->i40e_resources.ifr_nrx_queue = hw->func_caps.num_rx_qp;
1050 1057 i40e->i40e_resources.ifr_ntx_queue = hw->func_caps.num_tx_qp;
1051 1058
1052 1059 i40e->i40e_uaddrs = kmem_zalloc(sizeof (i40e_uaddr_t) *
1053 1060 i40e->i40e_resources.ifr_nmacfilt, KM_SLEEP);
1054 1061 i40e->i40e_maddrs = kmem_zalloc(sizeof (i40e_maddr_t) *
1055 1062 i40e->i40e_resources.ifr_nmcastfilt, KM_SLEEP);
1056 1063
1057 1064 /*
1058 1065 * Initialize these as multicast addresses to indicate it's invalid for
1059 1066 * sanity purposes. Think of it like 0xdeadbeef.
1060 1067 */
1061 1068 for (i = 0; i < i40e->i40e_resources.ifr_nmacfilt; i++)
1062 1069 i40e->i40e_uaddrs[i].iua_mac[0] = 0x01;
1063 1070
1064 1071 return (B_TRUE);
1065 1072 }
1066 1073
1067 1074 static boolean_t
1068 1075 i40e_enable_interrupts(i40e_t *i40e)
1069 1076 {
1070 1077 int i, rc;
1071 1078
1072 1079 if (i40e->i40e_intr_cap & DDI_INTR_FLAG_BLOCK) {
1073 1080 rc = ddi_intr_block_enable(i40e->i40e_intr_handles,
1074 1081 i40e->i40e_intr_count);
1075 1082 if (rc != DDI_SUCCESS) {
1076 1083 i40e_error(i40e, "Interrupt block-enable failed: %d",
1077 1084 rc);
1078 1085 return (B_FALSE);
1079 1086 }
1080 1087 } else {
1081 1088 for (i = 0; i < i40e->i40e_intr_count; i++) {
1082 1089 rc = ddi_intr_enable(i40e->i40e_intr_handles[i]);
1083 1090 if (rc != DDI_SUCCESS) {
1084 1091 i40e_error(i40e,
1085 1092 "Failed to enable interrupt %d: %d", i, rc);
1086 1093 while (--i >= 0) {
1087 1094 (void) ddi_intr_disable(
1088 1095 i40e->i40e_intr_handles[i]);
1089 1096 }
1090 1097 return (B_FALSE);
1091 1098 }
1092 1099 }
1093 1100 }
1094 1101
1095 1102 return (B_TRUE);
1096 1103 }
1097 1104
1098 1105 static boolean_t
1099 1106 i40e_disable_interrupts(i40e_t *i40e)
1100 1107 {
1101 1108 int i, rc;
1102 1109
1103 1110 if (i40e->i40e_intr_cap & DDI_INTR_FLAG_BLOCK) {
1104 1111 rc = ddi_intr_block_disable(i40e->i40e_intr_handles,
1105 1112 i40e->i40e_intr_count);
1106 1113 if (rc != DDI_SUCCESS) {
1107 1114 i40e_error(i40e,
1108 1115 "Interrupt block-disabled failed: %d", rc);
1109 1116 return (B_FALSE);
1110 1117 }
1111 1118 } else {
1112 1119 for (i = 0; i < i40e->i40e_intr_count; i++) {
1113 1120 rc = ddi_intr_disable(i40e->i40e_intr_handles[i]);
1114 1121 if (rc != DDI_SUCCESS) {
1115 1122 i40e_error(i40e,
1116 1123 "Failed to disable interrupt %d: %d",
1117 1124 i, rc);
1118 1125 return (B_FALSE);
1119 1126 }
1120 1127 }
1121 1128 }
1122 1129
1123 1130 return (B_TRUE);
1124 1131 }
1125 1132
1126 1133 /*
1127 1134 * Free receive & transmit rings.
1128 1135 */
1129 1136 static void
1130 1137 i40e_free_trqpairs(i40e_t *i40e)
1131 1138 {
1132 1139 i40e_trqpair_t *itrq;
1133 1140
1134 1141 if (i40e->i40e_rx_groups != NULL) {
1135 1142 kmem_free(i40e->i40e_rx_groups,
1136 1143 sizeof (i40e_rx_group_t) * i40e->i40e_num_rx_groups);
1137 1144 i40e->i40e_rx_groups = NULL;
1138 1145 }
1139 1146
1140 1147 if (i40e->i40e_trqpairs != NULL) {
1141 1148 for (uint_t i = 0; i < i40e->i40e_num_trqpairs; i++) {
1142 1149 itrq = &i40e->i40e_trqpairs[i];
1143 1150 mutex_destroy(&itrq->itrq_intr_lock);
1144 1151 mutex_destroy(&itrq->itrq_rx_lock);
1145 1152 mutex_destroy(&itrq->itrq_tx_lock);
1146 1153 mutex_destroy(&itrq->itrq_tcb_lock);
1147 1154 cv_destroy(&itrq->itrq_intr_cv);
1148 1155 cv_destroy(&itrq->itrq_tx_cv);
1149 1156
1150 1157 i40e_stats_trqpair_fini(itrq);
1151 1158 }
1152 1159
1153 1160 kmem_free(i40e->i40e_trqpairs,
1154 1161 sizeof (i40e_trqpair_t) * i40e->i40e_num_trqpairs);
1155 1162 i40e->i40e_trqpairs = NULL;
1156 1163 }
1157 1164
1158 1165 cv_destroy(&i40e->i40e_rx_pending_cv);
1159 1166 mutex_destroy(&i40e->i40e_rx_pending_lock);
1160 1167 mutex_destroy(&i40e->i40e_general_lock);
1161 1168 }
1162 1169
1163 1170 /*
1164 1171 * Allocate transmit and receive rings, as well as other data structures that we
1165 1172 * need.
1166 1173 */
1167 1174 static boolean_t
1168 1175 i40e_alloc_trqpairs(i40e_t *i40e)
1169 1176 {
1170 1177 void *mutexpri = DDI_INTR_PRI(i40e->i40e_intr_pri);
1171 1178
1172 1179 /*
1173 1180 * Now that we have the priority for the interrupts, initialize
1174 1181 * all relevant locks.
1175 1182 */
1176 1183 mutex_init(&i40e->i40e_general_lock, NULL, MUTEX_DRIVER, mutexpri);
1177 1184 mutex_init(&i40e->i40e_rx_pending_lock, NULL, MUTEX_DRIVER, mutexpri);
1178 1185 cv_init(&i40e->i40e_rx_pending_cv, NULL, CV_DRIVER, NULL);
1179 1186
1180 1187 i40e->i40e_trqpairs = kmem_zalloc(sizeof (i40e_trqpair_t) *
1181 1188 i40e->i40e_num_trqpairs, KM_SLEEP);
1182 1189 for (uint_t i = 0; i < i40e->i40e_num_trqpairs; i++) {
1183 1190 i40e_trqpair_t *itrq = &i40e->i40e_trqpairs[i];
1184 1191
1185 1192 itrq->itrq_i40e = i40e;
1186 1193 mutex_init(&itrq->itrq_intr_lock, NULL, MUTEX_DRIVER, mutexpri);
1187 1194 mutex_init(&itrq->itrq_rx_lock, NULL, MUTEX_DRIVER, mutexpri);
1188 1195 mutex_init(&itrq->itrq_tx_lock, NULL, MUTEX_DRIVER, mutexpri);
1189 1196 mutex_init(&itrq->itrq_tcb_lock, NULL, MUTEX_DRIVER, mutexpri);
1190 1197 cv_init(&itrq->itrq_intr_cv, NULL, CV_DRIVER, NULL);
1191 1198 cv_init(&itrq->itrq_tx_cv, NULL, CV_DRIVER, NULL);
1192 1199 itrq->itrq_index = i;
1193 1200 itrq->itrq_intr_quiesce = B_TRUE;
1194 1201 itrq->itrq_tx_quiesce = B_TRUE;
1195 1202 }
1196 1203
1197 1204 for (uint_t i = 0; i < i40e->i40e_num_trqpairs; i++) {
1198 1205 /*
1199 1206 * Keeping this in a separate iteration makes the
1200 1207 * clean up path safe.
1201 1208 */
1202 1209 if (!i40e_stats_trqpair_init(&i40e->i40e_trqpairs[i])) {
1203 1210 i40e_free_trqpairs(i40e);
1204 1211 return (B_FALSE);
1205 1212 }
1206 1213 }
1207 1214
1208 1215 i40e->i40e_rx_groups = kmem_zalloc(sizeof (i40e_rx_group_t) *
1209 1216 i40e->i40e_num_rx_groups, KM_SLEEP);
1210 1217
1211 1218 for (uint_t i = 0; i < i40e->i40e_num_rx_groups; i++) {
1212 1219 i40e_rx_group_t *rxg = &i40e->i40e_rx_groups[i];
1213 1220
1214 1221 rxg->irg_index = i;
1215 1222 rxg->irg_i40e = i40e;
1216 1223 }
1217 1224
1218 1225 return (B_TRUE);
1219 1226 }
1220 1227
1221 1228
1222 1229
1223 1230 /*
1224 1231 * Unless a .conf file already overrode i40e_t structure values, they will
1225 1232 * be 0, and need to be set in conjunction with the now-available HW report.
1226 1233 */
1227 1234 /* ARGSUSED */
1228 1235 static void
1229 1236 i40e_hw_to_instance(i40e_t *i40e, i40e_hw_t *hw)
1230 1237 {
1231 1238 if (i40e->i40e_num_trqpairs_per_vsi == 0) {
1232 1239 if (i40e_is_x722(i40e)) {
1233 1240 i40e->i40e_num_trqpairs_per_vsi =
1234 1241 I40E_722_MAX_TC_QUEUES;
1235 1242 } else {
1236 1243 i40e->i40e_num_trqpairs_per_vsi =
1237 1244 I40E_710_MAX_TC_QUEUES;
1238 1245 }
1239 1246 }
1240 1247
1241 1248 if (i40e->i40e_num_rx_groups == 0) {
1242 1249 i40e->i40e_num_rx_groups = I40E_DEF_NUM_RX_GROUPS;
1243 1250 }
1244 1251 }
1245 1252
1246 1253 /*
1247 1254 * Free any resources required by, or setup by, the Intel common code.
1248 1255 */
1249 1256 static void
1250 1257 i40e_common_code_fini(i40e_t *i40e)
1251 1258 {
1252 1259 i40e_hw_t *hw = &i40e->i40e_hw_space;
1253 1260 int rc;
1254 1261
1255 1262 rc = i40e_shutdown_lan_hmc(hw);
1256 1263 if (rc != I40E_SUCCESS)
1257 1264 i40e_error(i40e, "failed to shutdown LAN hmc: %d", rc);
1258 1265
1259 1266 rc = i40e_shutdown_adminq(hw);
1260 1267 if (rc != I40E_SUCCESS)
1261 1268 i40e_error(i40e, "failed to shutdown admin queue: %d", rc);
1262 1269 }
1263 1270
1264 1271 /*
1265 1272 * Initialize and call Intel common-code routines, includes some setup
1266 1273 * the common code expects from the driver. Also prints on failure, so
1267 1274 * the caller doesn't have to.
1268 1275 */
1269 1276 static boolean_t
1270 1277 i40e_common_code_init(i40e_t *i40e, i40e_hw_t *hw)
1271 1278 {
1272 1279 int rc;
1273 1280
1274 1281 i40e_clear_hw(hw);
1275 1282 rc = i40e_pf_reset(hw);
1276 1283 if (rc != 0) {
1277 1284 i40e_error(i40e, "failed to reset hardware: %d", rc);
1278 1285 i40e_fm_ereport(i40e, DDI_FM_DEVICE_NO_RESPONSE);
1279 1286 return (B_FALSE);
1280 1287 }
1281 1288
1282 1289 rc = i40e_init_shared_code(hw);
1283 1290 if (rc != 0) {
1284 1291 i40e_error(i40e, "failed to initialize i40e core: %d", rc);
1285 1292 return (B_FALSE);
1286 1293 }
1287 1294
1288 1295 hw->aq.num_arq_entries = I40E_DEF_ADMINQ_SIZE;
1289 1296 hw->aq.num_asq_entries = I40E_DEF_ADMINQ_SIZE;
1290 1297 hw->aq.arq_buf_size = I40E_ADMINQ_BUFSZ;
1291 1298 hw->aq.asq_buf_size = I40E_ADMINQ_BUFSZ;
1292 1299
1293 1300 rc = i40e_init_adminq(hw);
1294 1301 if (rc != 0) {
1295 1302 i40e_error(i40e, "failed to initialize firmware admin queue: "
1296 1303 "%d, potential firmware version mismatch", rc);
1297 1304 i40e_fm_ereport(i40e, DDI_FM_DEVICE_INVAL_STATE);
1298 1305 return (B_FALSE);
1299 1306 }
1300 1307
1301 1308 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1302 1309 hw->aq.api_min_ver > I40E_FW_MINOR_VERSION(hw)) {
1303 1310 i40e_log(i40e, "The driver for the device detected a newer "
1304 1311 "version of the NVM image (%d.%d) than expected (%d.%d).\n"
1305 1312 "Please install the most recent version of the network "
1306 1313 "driver.\n", hw->aq.api_maj_ver, hw->aq.api_min_ver,
1307 1314 I40E_FW_API_VERSION_MAJOR, I40E_FW_MINOR_VERSION(hw));
1308 1315 } else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
1309 1316 hw->aq.api_min_ver < (I40E_FW_MINOR_VERSION(hw) - 1)) {
1310 1317 i40e_log(i40e, "The driver for the device detected an older"
1311 1318 " version of the NVM image (%d.%d) than expected (%d.%d)."
1312 1319 "\nPlease update the NVM image.\n",
1313 1320 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1314 1321 I40E_FW_API_VERSION_MAJOR, I40E_FW_MINOR_VERSION(hw) - 1);
1315 1322 }
1316 1323
1317 1324 i40e_clear_pxe_mode(hw);
1318 1325
1319 1326 /*
1320 1327 * We need to call this so that the common code can discover
1321 1328 * capabilities of the hardware, which it uses throughout the rest.
1322 1329 */
1323 1330 if (!i40e_get_hw_capabilities(i40e, hw)) {
1324 1331 i40e_error(i40e, "failed to obtain hardware capabilities");
1325 1332 return (B_FALSE);
1326 1333 }
1327 1334
1328 1335 if (i40e_get_available_resources(i40e) == B_FALSE) {
1329 1336 i40e_error(i40e, "failed to obtain hardware resources");
1330 1337 return (B_FALSE);
1331 1338 }
1332 1339
1333 1340 i40e_hw_to_instance(i40e, hw);
1334 1341
1335 1342 rc = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1336 1343 hw->func_caps.num_rx_qp, 0, 0);
1337 1344 if (rc != 0) {
1338 1345 i40e_error(i40e, "failed to initialize hardware memory cache: "
1339 1346 "%d", rc);
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1340 1347 return (B_FALSE);
1341 1348 }
1342 1349
1343 1350 rc = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1344 1351 if (rc != 0) {
1345 1352 i40e_error(i40e, "failed to configure hardware memory cache: "
1346 1353 "%d", rc);
1347 1354 return (B_FALSE);
1348 1355 }
1349 1356
1350 - (void) i40e_aq_stop_lldp(hw, TRUE, NULL);
1357 + (void) i40e_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1351 1358
1352 1359 rc = i40e_get_mac_addr(hw, hw->mac.addr);
1353 1360 if (rc != I40E_SUCCESS) {
1354 1361 i40e_error(i40e, "failed to retrieve hardware mac address: %d",
1355 1362 rc);
1356 1363 return (B_FALSE);
1357 1364 }
1358 1365
1359 1366 rc = i40e_validate_mac_addr(hw->mac.addr);
1360 1367 if (rc != 0) {
1361 1368 i40e_error(i40e, "failed to validate internal mac address: "
1362 1369 "%d", rc);
1363 1370 return (B_FALSE);
1364 1371 }
1365 1372 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
1366 1373 if ((rc = i40e_get_port_mac_addr(hw, hw->mac.port_addr)) !=
1367 1374 I40E_SUCCESS) {
1368 1375 i40e_error(i40e, "failed to retrieve port mac address: %d",
1369 1376 rc);
1370 1377 return (B_FALSE);
1371 1378 }
1372 1379
1373 1380 /*
1374 1381 * We need to obtain the Default Virtual Station SEID (VSI)
1375 1382 * before we can perform other operations on the device.
1376 1383 */
1377 1384 if (!i40e_set_def_vsi_seid(i40e)) {
1378 1385 i40e_error(i40e, "failed to obtain Default VSI SEID");
1379 1386 return (B_FALSE);
1380 1387 }
1381 1388
1382 1389 return (B_TRUE);
1383 1390 }
1384 1391
1385 1392 static void
1386 1393 i40e_unconfigure(dev_info_t *devinfo, i40e_t *i40e)
1387 1394 {
1388 1395 int rc;
1389 1396
1390 1397 if (i40e->i40e_attach_progress & I40E_ATTACH_ENABLE_INTR)
1391 1398 (void) i40e_disable_interrupts(i40e);
1392 1399
1393 1400 if ((i40e->i40e_attach_progress & I40E_ATTACH_LINK_TIMER) &&
1394 1401 i40e->i40e_periodic_id != 0) {
1395 1402 ddi_periodic_delete(i40e->i40e_periodic_id);
1396 1403 i40e->i40e_periodic_id = 0;
1397 1404 }
1398 1405
1399 1406 if (i40e->i40e_attach_progress & I40E_ATTACH_UFM_INIT)
1400 1407 ddi_ufm_fini(i40e->i40e_ufmh);
1401 1408
1402 1409 if (i40e->i40e_attach_progress & I40E_ATTACH_MAC) {
1403 1410 rc = mac_unregister(i40e->i40e_mac_hdl);
1404 1411 if (rc != 0) {
1405 1412 i40e_error(i40e, "failed to unregister from mac: %d",
1406 1413 rc);
1407 1414 }
1408 1415 }
1409 1416
1410 1417 if (i40e->i40e_attach_progress & I40E_ATTACH_STATS) {
1411 1418 i40e_stats_fini(i40e);
1412 1419 }
1413 1420
1414 1421 if (i40e->i40e_attach_progress & I40E_ATTACH_ADD_INTR)
1415 1422 i40e_rem_intr_handlers(i40e);
1416 1423
1417 1424 if (i40e->i40e_attach_progress & I40E_ATTACH_ALLOC_RINGSLOCKS)
1418 1425 i40e_free_trqpairs(i40e);
1419 1426
1420 1427 if (i40e->i40e_attach_progress & I40E_ATTACH_ALLOC_INTR)
1421 1428 i40e_rem_intrs(i40e);
1422 1429
1423 1430 if (i40e->i40e_attach_progress & I40E_ATTACH_COMMON_CODE)
1424 1431 i40e_common_code_fini(i40e);
1425 1432
1426 1433 i40e_cleanup_resources(i40e);
1427 1434
1428 1435 if (i40e->i40e_attach_progress & I40E_ATTACH_PROPS)
1429 1436 (void) ddi_prop_remove_all(devinfo);
1430 1437
1431 1438 if (i40e->i40e_attach_progress & I40E_ATTACH_REGS_MAP &&
1432 1439 i40e->i40e_osdep_space.ios_reg_handle != NULL) {
1433 1440 ddi_regs_map_free(&i40e->i40e_osdep_space.ios_reg_handle);
1434 1441 i40e->i40e_osdep_space.ios_reg_handle = NULL;
1435 1442 }
1436 1443
1437 1444 if ((i40e->i40e_attach_progress & I40E_ATTACH_PCI_CONFIG) &&
1438 1445 i40e->i40e_osdep_space.ios_cfg_handle != NULL) {
1439 1446 pci_config_teardown(&i40e->i40e_osdep_space.ios_cfg_handle);
1440 1447 i40e->i40e_osdep_space.ios_cfg_handle = NULL;
1441 1448 }
1442 1449
1443 1450 if (i40e->i40e_attach_progress & I40E_ATTACH_FM_INIT)
1444 1451 i40e_fm_fini(i40e);
1445 1452
1446 1453 kmem_free(i40e->i40e_aqbuf, I40E_ADMINQ_BUFSZ);
1447 1454 kmem_free(i40e, sizeof (i40e_t));
1448 1455
1449 1456 ddi_set_driver_private(devinfo, NULL);
1450 1457 }
1451 1458
1452 1459 static boolean_t
1453 1460 i40e_final_init(i40e_t *i40e)
1454 1461 {
1455 1462 i40e_hw_t *hw = &i40e->i40e_hw_space;
1456 1463 struct i40e_osdep *osdep = OS_DEP(hw);
1457 1464 uint8_t pbanum[I40E_PBANUM_STRLEN];
1458 1465 enum i40e_status_code irc;
1459 1466 char buf[I40E_DDI_PROP_LEN];
1460 1467
1461 1468 pbanum[0] = '\0';
1462 1469 irc = i40e_read_pba_string(hw, pbanum, sizeof (pbanum));
1463 1470 if (irc != I40E_SUCCESS) {
1464 1471 i40e_log(i40e, "failed to read PBA string: %d", irc);
1465 1472 } else {
1466 1473 (void) ddi_prop_update_string(DDI_DEV_T_NONE, i40e->i40e_dip,
1467 1474 "printed-board-assembly", (char *)pbanum);
1468 1475 }
1469 1476
1470 1477 #ifdef DEBUG
1471 1478 ASSERT(snprintf(NULL, 0, "%d.%d", hw->aq.fw_maj_ver,
1472 1479 hw->aq.fw_min_ver) < sizeof (buf));
1473 1480 ASSERT(snprintf(NULL, 0, "%x", hw->aq.fw_build) < sizeof (buf));
1474 1481 ASSERT(snprintf(NULL, 0, "%d.%d", hw->aq.api_maj_ver,
1475 1482 hw->aq.api_min_ver) < sizeof (buf));
1476 1483 #endif
1477 1484
1478 1485 (void) snprintf(buf, sizeof (buf), "%d.%d", hw->aq.fw_maj_ver,
1479 1486 hw->aq.fw_min_ver);
1480 1487 (void) ddi_prop_update_string(DDI_DEV_T_NONE, i40e->i40e_dip,
1481 1488 "firmware-version", buf);
1482 1489 (void) snprintf(buf, sizeof (buf), "%x", hw->aq.fw_build);
1483 1490 (void) ddi_prop_update_string(DDI_DEV_T_NONE, i40e->i40e_dip,
1484 1491 "firmware-build", buf);
1485 1492 (void) snprintf(buf, sizeof (buf), "%d.%d", hw->aq.api_maj_ver,
1486 1493 hw->aq.api_min_ver);
1487 1494 (void) ddi_prop_update_string(DDI_DEV_T_NONE, i40e->i40e_dip,
1488 1495 "api-version", buf);
1489 1496
1490 1497 if (!i40e_set_hw_bus_info(hw))
1491 1498 return (B_FALSE);
1492 1499
1493 1500 if (i40e_check_acc_handle(osdep->ios_reg_handle) != DDI_FM_OK) {
1494 1501 ddi_fm_service_impact(i40e->i40e_dip, DDI_SERVICE_LOST);
1495 1502 return (B_FALSE);
1496 1503 }
1497 1504
1498 1505 return (B_TRUE);
1499 1506 }
1500 1507
1501 1508 static void
1502 1509 i40e_identify_hardware(i40e_t *i40e)
1503 1510 {
1504 1511 i40e_hw_t *hw = &i40e->i40e_hw_space;
1505 1512 struct i40e_osdep *osdep = &i40e->i40e_osdep_space;
1506 1513
1507 1514 hw->vendor_id = pci_config_get16(osdep->ios_cfg_handle, PCI_CONF_VENID);
1508 1515 hw->device_id = pci_config_get16(osdep->ios_cfg_handle, PCI_CONF_DEVID);
1509 1516 hw->revision_id = pci_config_get8(osdep->ios_cfg_handle,
1510 1517 PCI_CONF_REVID);
1511 1518 hw->subsystem_device_id =
1512 1519 pci_config_get16(osdep->ios_cfg_handle, PCI_CONF_SUBSYSID);
1513 1520 hw->subsystem_vendor_id =
1514 1521 pci_config_get16(osdep->ios_cfg_handle, PCI_CONF_SUBVENID);
1515 1522
1516 1523 /*
1517 1524 * Note that we set the hardware's bus information later on, in
1518 1525 * i40e_get_available_resources(). The common code doesn't seem to
1519 1526 * require that it be set in any ways, it seems to be mostly for
1520 1527 * book-keeping.
1521 1528 */
1522 1529 }
1523 1530
1524 1531 static boolean_t
1525 1532 i40e_regs_map(i40e_t *i40e)
1526 1533 {
1527 1534 dev_info_t *devinfo = i40e->i40e_dip;
1528 1535 i40e_hw_t *hw = &i40e->i40e_hw_space;
1529 1536 struct i40e_osdep *osdep = &i40e->i40e_osdep_space;
1530 1537 off_t memsize;
1531 1538 int ret;
1532 1539
1533 1540 if (ddi_dev_regsize(devinfo, I40E_ADAPTER_REGSET, &memsize) !=
1534 1541 DDI_SUCCESS) {
1535 1542 i40e_error(i40e, "Used invalid register set to map PCIe regs");
1536 1543 return (B_FALSE);
1537 1544 }
1538 1545
1539 1546 if ((ret = ddi_regs_map_setup(devinfo, I40E_ADAPTER_REGSET,
1540 1547 (caddr_t *)&hw->hw_addr, 0, memsize, &i40e_regs_acc_attr,
1541 1548 &osdep->ios_reg_handle)) != DDI_SUCCESS) {
1542 1549 i40e_error(i40e, "failed to map device registers: %d", ret);
1543 1550 return (B_FALSE);
1544 1551 }
1545 1552
1546 1553 osdep->ios_reg_size = memsize;
1547 1554 return (B_TRUE);
1548 1555 }
1549 1556
1550 1557 /*
1551 1558 * Update parameters required when a new MTU has been configured. Calculate the
1552 1559 * maximum frame size, as well as, size our DMA buffers which we size in
1553 1560 * increments of 1K.
1554 1561 */
1555 1562 void
1556 1563 i40e_update_mtu(i40e_t *i40e)
1557 1564 {
1558 1565 uint32_t rx, tx;
1559 1566
1560 1567 i40e->i40e_frame_max = i40e->i40e_sdu +
1561 1568 sizeof (struct ether_vlan_header) + ETHERFCSL;
1562 1569
1563 1570 rx = i40e->i40e_frame_max + I40E_BUF_IPHDR_ALIGNMENT;
1564 1571 i40e->i40e_rx_buf_size = ((rx >> 10) +
1565 1572 ((rx & (((uint32_t)1 << 10) -1)) > 0 ? 1 : 0)) << 10;
1566 1573
1567 1574 tx = i40e->i40e_frame_max;
1568 1575 i40e->i40e_tx_buf_size = ((tx >> 10) +
1569 1576 ((tx & (((uint32_t)1 << 10) -1)) > 0 ? 1 : 0)) << 10;
1570 1577 }
1571 1578
1572 1579 static int
1573 1580 i40e_get_prop(i40e_t *i40e, char *prop, int min, int max, int def)
1574 1581 {
1575 1582 int val;
1576 1583
1577 1584 val = ddi_prop_get_int(DDI_DEV_T_ANY, i40e->i40e_dip, DDI_PROP_DONTPASS,
1578 1585 prop, def);
1579 1586 if (val > max)
1580 1587 val = max;
1581 1588 if (val < min)
1582 1589 val = min;
1583 1590 return (val);
1584 1591 }
1585 1592
1586 1593 static void
1587 1594 i40e_init_properties(i40e_t *i40e)
1588 1595 {
1589 1596 i40e->i40e_sdu = i40e_get_prop(i40e, "default_mtu",
1590 1597 I40E_MIN_MTU, I40E_MAX_MTU, I40E_DEF_MTU);
1591 1598
1592 1599 i40e->i40e_intr_force = i40e_get_prop(i40e, "intr_force",
1593 1600 I40E_INTR_NONE, I40E_INTR_LEGACY, I40E_INTR_NONE);
1594 1601
1595 1602 i40e->i40e_mr_enable = i40e_get_prop(i40e, "mr_enable",
1596 1603 B_FALSE, B_TRUE, B_TRUE);
1597 1604
1598 1605 i40e->i40e_tx_ring_size = i40e_get_prop(i40e, "tx_ring_size",
1599 1606 I40E_MIN_TX_RING_SIZE, I40E_MAX_TX_RING_SIZE,
1600 1607 I40E_DEF_TX_RING_SIZE);
1601 1608 if ((i40e->i40e_tx_ring_size % I40E_DESC_ALIGN) != 0) {
1602 1609 i40e->i40e_tx_ring_size = P2ROUNDUP(i40e->i40e_tx_ring_size,
1603 1610 I40E_DESC_ALIGN);
1604 1611 }
1605 1612
1606 1613 i40e->i40e_tx_block_thresh = i40e_get_prop(i40e, "tx_resched_threshold",
1607 1614 I40E_MIN_TX_BLOCK_THRESH,
1608 1615 i40e->i40e_tx_ring_size - I40E_TX_MAX_COOKIE,
1609 1616 I40E_DEF_TX_BLOCK_THRESH);
1610 1617
1611 1618 i40e->i40e_num_rx_groups = i40e_get_prop(i40e, "rx_num_groups",
1612 1619 I40E_MIN_NUM_RX_GROUPS, I40E_MAX_NUM_RX_GROUPS,
1613 1620 I40E_DEF_NUM_RX_GROUPS);
1614 1621
1615 1622 i40e->i40e_rx_ring_size = i40e_get_prop(i40e, "rx_ring_size",
1616 1623 I40E_MIN_RX_RING_SIZE, I40E_MAX_RX_RING_SIZE,
1617 1624 I40E_DEF_RX_RING_SIZE);
1618 1625 if ((i40e->i40e_rx_ring_size % I40E_DESC_ALIGN) != 0) {
1619 1626 i40e->i40e_rx_ring_size = P2ROUNDUP(i40e->i40e_rx_ring_size,
1620 1627 I40E_DESC_ALIGN);
1621 1628 }
1622 1629
1623 1630 i40e->i40e_rx_limit_per_intr = i40e_get_prop(i40e, "rx_limit_per_intr",
1624 1631 I40E_MIN_RX_LIMIT_PER_INTR, I40E_MAX_RX_LIMIT_PER_INTR,
1625 1632 I40E_DEF_RX_LIMIT_PER_INTR);
1626 1633
1627 1634 i40e->i40e_tx_hcksum_enable = i40e_get_prop(i40e, "tx_hcksum_enable",
1628 1635 B_FALSE, B_TRUE, B_TRUE);
1629 1636
1630 1637 i40e->i40e_tx_lso_enable = i40e_get_prop(i40e, "tx_lso_enable",
1631 1638 B_FALSE, B_TRUE, B_TRUE);
1632 1639
1633 1640 i40e->i40e_rx_hcksum_enable = i40e_get_prop(i40e, "rx_hcksum_enable",
1634 1641 B_FALSE, B_TRUE, B_TRUE);
1635 1642
1636 1643 i40e->i40e_rx_dma_min = i40e_get_prop(i40e, "rx_dma_threshold",
1637 1644 I40E_MIN_RX_DMA_THRESH, I40E_MAX_RX_DMA_THRESH,
1638 1645 I40E_DEF_RX_DMA_THRESH);
1639 1646
1640 1647 i40e->i40e_tx_dma_min = i40e_get_prop(i40e, "tx_dma_threshold",
1641 1648 I40E_MIN_TX_DMA_THRESH, I40E_MAX_TX_DMA_THRESH,
1642 1649 I40E_DEF_TX_DMA_THRESH);
1643 1650
1644 1651 i40e->i40e_tx_itr = i40e_get_prop(i40e, "tx_intr_throttle",
1645 1652 I40E_MIN_ITR, I40E_MAX_ITR, I40E_DEF_TX_ITR);
1646 1653
1647 1654 i40e->i40e_rx_itr = i40e_get_prop(i40e, "rx_intr_throttle",
1648 1655 I40E_MIN_ITR, I40E_MAX_ITR, I40E_DEF_RX_ITR);
1649 1656
1650 1657 i40e->i40e_other_itr = i40e_get_prop(i40e, "other_intr_throttle",
1651 1658 I40E_MIN_ITR, I40E_MAX_ITR, I40E_DEF_OTHER_ITR);
1652 1659
1653 1660 if (!i40e->i40e_mr_enable) {
1654 1661 i40e->i40e_num_trqpairs = I40E_TRQPAIR_NOMSIX;
1655 1662 i40e->i40e_num_rx_groups = I40E_GROUP_NOMSIX;
1656 1663 }
1657 1664
1658 1665 i40e_update_mtu(i40e);
1659 1666 }
1660 1667
1661 1668 /*
1662 1669 * There are a few constraints on interrupts that we're currently imposing, some
1663 1670 * of which are restrictions from hardware. For a fuller treatment, see
1664 1671 * i40e_intr.c.
1665 1672 *
1666 1673 * Currently, to use MSI-X we require two interrupts be available though in
1667 1674 * theory we should participate in IRM and happily use more interrupts.
1668 1675 *
1669 1676 * Hardware only supports a single MSI being programmed and therefore if we
1670 1677 * don't have MSI-X interrupts available at this time, then we ratchet down the
1671 1678 * number of rings and groups available. Obviously, we only bother with a single
1672 1679 * fixed interrupt.
1673 1680 */
1674 1681 static boolean_t
1675 1682 i40e_alloc_intr_handles(i40e_t *i40e, dev_info_t *devinfo, int intr_type)
1676 1683 {
1677 1684 i40e_hw_t *hw = &i40e->i40e_hw_space;
1678 1685 ddi_acc_handle_t rh = i40e->i40e_osdep_space.ios_reg_handle;
1679 1686 int request, count, actual, rc, min;
1680 1687 uint32_t reg;
1681 1688
1682 1689 switch (intr_type) {
1683 1690 case DDI_INTR_TYPE_FIXED:
1684 1691 case DDI_INTR_TYPE_MSI:
1685 1692 request = 1;
1686 1693 min = 1;
1687 1694 break;
1688 1695 case DDI_INTR_TYPE_MSIX:
1689 1696 min = 2;
1690 1697 if (!i40e->i40e_mr_enable) {
1691 1698 request = 2;
1692 1699 break;
1693 1700 }
1694 1701 reg = I40E_READ_REG(hw, I40E_GLPCI_CNF2);
1695 1702 /*
1696 1703 * Should this read fail, we will drop back to using
1697 1704 * MSI or fixed interrupts.
1698 1705 */
1699 1706 if (i40e_check_acc_handle(rh) != DDI_FM_OK) {
1700 1707 ddi_fm_service_impact(i40e->i40e_dip,
1701 1708 DDI_SERVICE_DEGRADED);
1702 1709 return (B_FALSE);
1703 1710 }
1704 1711 request = (reg & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1705 1712 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1706 1713 request++; /* the register value is n - 1 */
1707 1714 break;
1708 1715 default:
1709 1716 panic("bad interrupt type passed to i40e_alloc_intr_handles: "
1710 1717 "%d", intr_type);
1711 1718 }
1712 1719
1713 1720 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
1714 1721 if (rc != DDI_SUCCESS || count < min) {
1715 1722 i40e_log(i40e, "Get interrupt number failed, "
1716 1723 "returned %d, count %d", rc, count);
1717 1724 return (B_FALSE);
1718 1725 }
1719 1726
1720 1727 rc = ddi_intr_get_navail(devinfo, intr_type, &count);
1721 1728 if (rc != DDI_SUCCESS || count < min) {
1722 1729 i40e_log(i40e, "Get AVAILABLE interrupt number failed, "
1723 1730 "returned %d, count %d", rc, count);
1724 1731 return (B_FALSE);
1725 1732 }
1726 1733
1727 1734 actual = 0;
1728 1735 i40e->i40e_intr_count = 0;
1729 1736 i40e->i40e_intr_count_max = 0;
1730 1737 i40e->i40e_intr_count_min = 0;
1731 1738
1732 1739 i40e->i40e_intr_size = request * sizeof (ddi_intr_handle_t);
1733 1740 ASSERT(i40e->i40e_intr_size != 0);
1734 1741 i40e->i40e_intr_handles = kmem_alloc(i40e->i40e_intr_size, KM_SLEEP);
1735 1742
1736 1743 rc = ddi_intr_alloc(devinfo, i40e->i40e_intr_handles, intr_type, 0,
1737 1744 min(request, count), &actual, DDI_INTR_ALLOC_NORMAL);
1738 1745 if (rc != DDI_SUCCESS) {
1739 1746 i40e_log(i40e, "Interrupt allocation failed with %d.", rc);
1740 1747 goto alloc_handle_fail;
1741 1748 }
1742 1749
1743 1750 i40e->i40e_intr_count = actual;
1744 1751 i40e->i40e_intr_count_max = request;
1745 1752 i40e->i40e_intr_count_min = min;
1746 1753
1747 1754 if (actual < min) {
1748 1755 i40e_log(i40e, "actual (%d) is less than minimum (%d).",
1749 1756 actual, min);
1750 1757 goto alloc_handle_fail;
1751 1758 }
1752 1759
1753 1760 /*
1754 1761 * Record the priority and capabilities for our first vector. Once
1755 1762 * we have it, that's our priority until detach time. Even if we
1756 1763 * eventually participate in IRM, our priority shouldn't change.
1757 1764 */
1758 1765 rc = ddi_intr_get_pri(i40e->i40e_intr_handles[0], &i40e->i40e_intr_pri);
1759 1766 if (rc != DDI_SUCCESS) {
1760 1767 i40e_log(i40e,
1761 1768 "Getting interrupt priority failed with %d.", rc);
1762 1769 goto alloc_handle_fail;
1763 1770 }
1764 1771
1765 1772 rc = ddi_intr_get_cap(i40e->i40e_intr_handles[0], &i40e->i40e_intr_cap);
1766 1773 if (rc != DDI_SUCCESS) {
1767 1774 i40e_log(i40e,
1768 1775 "Getting interrupt capabilities failed with %d.", rc);
1769 1776 goto alloc_handle_fail;
1770 1777 }
1771 1778
1772 1779 i40e->i40e_intr_type = intr_type;
1773 1780 return (B_TRUE);
1774 1781
1775 1782 alloc_handle_fail:
1776 1783
1777 1784 i40e_rem_intrs(i40e);
1778 1785 return (B_FALSE);
1779 1786 }
1780 1787
1781 1788 static boolean_t
1782 1789 i40e_alloc_intrs(i40e_t *i40e, dev_info_t *devinfo)
1783 1790 {
1784 1791 i40e_hw_t *hw = &i40e->i40e_hw_space;
1785 1792 int intr_types, rc;
1786 1793 uint_t max_trqpairs;
1787 1794
1788 1795 if (i40e_is_x722(i40e)) {
1789 1796 max_trqpairs = I40E_722_MAX_TC_QUEUES;
1790 1797 } else {
1791 1798 max_trqpairs = I40E_710_MAX_TC_QUEUES;
1792 1799 }
1793 1800
1794 1801 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
1795 1802 if (rc != DDI_SUCCESS) {
1796 1803 i40e_error(i40e, "failed to get supported interrupt types: %d",
1797 1804 rc);
1798 1805 return (B_FALSE);
1799 1806 }
1800 1807
1801 1808 i40e->i40e_intr_type = 0;
1802 1809
1803 1810 /*
1804 1811 * We need to determine the number of queue pairs per traffic
1805 1812 * class. We only have one traffic class (TC0), so we'll base
1806 1813 * this off the number of interrupts provided. Furthermore,
1807 1814 * since we only use one traffic class, the number of queues
1808 1815 * per traffic class and per VSI are the same.
1809 1816 */
1810 1817 if ((intr_types & DDI_INTR_TYPE_MSIX) &&
1811 1818 (i40e->i40e_intr_force <= I40E_INTR_MSIX) &&
1812 1819 (i40e_alloc_intr_handles(i40e, devinfo, DDI_INTR_TYPE_MSIX))) {
1813 1820 uint32_t n, qp_cap, num_trqpairs;
1814 1821
1815 1822 /*
1816 1823 * While we want the number of queue pairs to match
1817 1824 * the number of interrupts, we must keep stay in
1818 1825 * bounds of the maximum number of queues per traffic
1819 1826 * class. We subtract one from i40e_intr_count to
1820 1827 * account for interrupt zero; which is currently
1821 1828 * restricted to admin queue commands and other
1822 1829 * interrupt causes.
1823 1830 */
1824 1831 n = MIN(i40e->i40e_intr_count - 1, max_trqpairs);
1825 1832 ASSERT3U(n, >, 0);
1826 1833
1827 1834 /*
1828 1835 * Round up to the nearest power of two to ensure that
1829 1836 * the QBASE aligns with the TC size which must be
1830 1837 * programmed as a power of two. See the queue mapping
1831 1838 * description in section 7.4.9.5.5.1.
1832 1839 *
1833 1840 * If i40e_intr_count - 1 is not a power of two then
1834 1841 * some queue pairs on the same VSI will have to share
1835 1842 * an interrupt.
1836 1843 *
1837 1844 * We may want to revisit this logic in a future where
1838 1845 * we have more interrupts and more VSIs. Otherwise,
1839 1846 * each VSI will use as many interrupts as possible.
1840 1847 * Using more QPs per VSI means better RSS for each
1841 1848 * group, but at the same time may require more
1842 1849 * sharing of interrupts across VSIs. This may be a
1843 1850 * good candidate for a .conf tunable.
1844 1851 */
1845 1852 n = 0x1 << ddi_fls(n);
1846 1853 i40e->i40e_num_trqpairs_per_vsi = n;
1847 1854
1848 1855 /*
1849 1856 * Make sure the number of tx/rx qpairs does not exceed
1850 1857 * the device's capabilities.
1851 1858 */
1852 1859 ASSERT3U(i40e->i40e_num_rx_groups, >, 0);
1853 1860 qp_cap = MIN(hw->func_caps.num_rx_qp, hw->func_caps.num_tx_qp);
1854 1861 num_trqpairs = i40e->i40e_num_trqpairs_per_vsi *
1855 1862 i40e->i40e_num_rx_groups;
1856 1863 if (num_trqpairs > qp_cap) {
1857 1864 i40e->i40e_num_rx_groups = MAX(1, qp_cap /
1858 1865 i40e->i40e_num_trqpairs_per_vsi);
1859 1866 num_trqpairs = i40e->i40e_num_trqpairs_per_vsi *
1860 1867 i40e->i40e_num_rx_groups;
1861 1868 i40e_log(i40e, "Rx groups restricted to %u",
1862 1869 i40e->i40e_num_rx_groups);
1863 1870 }
1864 1871 ASSERT3U(num_trqpairs, >, 0);
1865 1872 i40e->i40e_num_trqpairs = num_trqpairs;
1866 1873 return (B_TRUE);
1867 1874 }
1868 1875
1869 1876 /*
1870 1877 * We only use multiple transmit/receive pairs when MSI-X interrupts are
1871 1878 * available due to the fact that the device basically only supports a
1872 1879 * single MSI interrupt.
1873 1880 */
1874 1881 i40e->i40e_num_trqpairs = I40E_TRQPAIR_NOMSIX;
1875 1882 i40e->i40e_num_trqpairs_per_vsi = i40e->i40e_num_trqpairs;
1876 1883 i40e->i40e_num_rx_groups = I40E_GROUP_NOMSIX;
1877 1884
1878 1885 if ((intr_types & DDI_INTR_TYPE_MSI) &&
1879 1886 (i40e->i40e_intr_force <= I40E_INTR_MSI)) {
1880 1887 if (i40e_alloc_intr_handles(i40e, devinfo, DDI_INTR_TYPE_MSI))
1881 1888 return (B_TRUE);
1882 1889 }
1883 1890
1884 1891 if (intr_types & DDI_INTR_TYPE_FIXED) {
1885 1892 if (i40e_alloc_intr_handles(i40e, devinfo, DDI_INTR_TYPE_FIXED))
1886 1893 return (B_TRUE);
1887 1894 }
1888 1895
1889 1896 return (B_FALSE);
1890 1897 }
1891 1898
1892 1899 /*
1893 1900 * Map different interrupts to MSI-X vectors.
1894 1901 */
1895 1902 static boolean_t
1896 1903 i40e_map_intrs_to_vectors(i40e_t *i40e)
1897 1904 {
1898 1905 if (i40e->i40e_intr_type != DDI_INTR_TYPE_MSIX) {
1899 1906 return (B_TRUE);
1900 1907 }
1901 1908
1902 1909 /*
1903 1910 * Each queue pair is mapped to a single interrupt, so
1904 1911 * transmit and receive interrupts for a given queue share the
1905 1912 * same vector. Vector zero is reserved for the admin queue.
1906 1913 */
1907 1914 for (uint_t i = 0; i < i40e->i40e_num_trqpairs; i++) {
1908 1915 uint_t vector = i % (i40e->i40e_intr_count - 1);
1909 1916
1910 1917 i40e->i40e_trqpairs[i].itrq_rx_intrvec = vector + 1;
1911 1918 i40e->i40e_trqpairs[i].itrq_tx_intrvec = vector + 1;
1912 1919 }
1913 1920
1914 1921 return (B_TRUE);
1915 1922 }
1916 1923
1917 1924 static boolean_t
1918 1925 i40e_add_intr_handlers(i40e_t *i40e)
1919 1926 {
1920 1927 int rc, vector;
1921 1928
1922 1929 switch (i40e->i40e_intr_type) {
1923 1930 case DDI_INTR_TYPE_MSIX:
1924 1931 for (vector = 0; vector < i40e->i40e_intr_count; vector++) {
1925 1932 rc = ddi_intr_add_handler(
1926 1933 i40e->i40e_intr_handles[vector],
1927 1934 (ddi_intr_handler_t *)i40e_intr_msix, i40e,
1928 1935 (void *)(uintptr_t)vector);
1929 1936 if (rc != DDI_SUCCESS) {
1930 1937 i40e_log(i40e, "Add interrupt handler (MSI-X) "
1931 1938 "failed: return %d, vector %d", rc, vector);
1932 1939 for (vector--; vector >= 0; vector--) {
1933 1940 (void) ddi_intr_remove_handler(
1934 1941 i40e->i40e_intr_handles[vector]);
1935 1942 }
1936 1943 return (B_FALSE);
1937 1944 }
1938 1945 }
1939 1946 break;
1940 1947 case DDI_INTR_TYPE_MSI:
1941 1948 rc = ddi_intr_add_handler(i40e->i40e_intr_handles[0],
1942 1949 (ddi_intr_handler_t *)i40e_intr_msi, i40e, NULL);
1943 1950 if (rc != DDI_SUCCESS) {
1944 1951 i40e_log(i40e, "Add interrupt handler (MSI) failed: "
1945 1952 "return %d", rc);
1946 1953 return (B_FALSE);
1947 1954 }
1948 1955 break;
1949 1956 case DDI_INTR_TYPE_FIXED:
1950 1957 rc = ddi_intr_add_handler(i40e->i40e_intr_handles[0],
1951 1958 (ddi_intr_handler_t *)i40e_intr_legacy, i40e, NULL);
1952 1959 if (rc != DDI_SUCCESS) {
1953 1960 i40e_log(i40e, "Add interrupt handler (legacy) failed:"
1954 1961 " return %d", rc);
1955 1962 return (B_FALSE);
1956 1963 }
1957 1964 break;
1958 1965 default:
1959 1966 /* Cast to pacify lint */
1960 1967 panic("i40e_intr_type %p contains an unknown type: %d",
1961 1968 (void *)i40e, i40e->i40e_intr_type);
1962 1969 }
1963 1970
1964 1971 return (B_TRUE);
1965 1972 }
1966 1973
1967 1974 /*
1968 1975 * Perform periodic checks. Longer term, we should be thinking about additional
1969 1976 * things here:
1970 1977 *
1971 1978 * o Stall Detection
1972 1979 * o Temperature sensor detection
1973 1980 * o Device resetting
1974 1981 * o Statistics updating to avoid wraparound
1975 1982 */
1976 1983 static void
1977 1984 i40e_timer(void *arg)
1978 1985 {
1979 1986 i40e_t *i40e = arg;
1980 1987
1981 1988 mutex_enter(&i40e->i40e_general_lock);
1982 1989 i40e_link_check(i40e);
1983 1990 mutex_exit(&i40e->i40e_general_lock);
1984 1991 }
1985 1992
1986 1993 /*
1987 1994 * Get the hardware state, and scribble away anything that needs scribbling.
1988 1995 */
1989 1996 static void
1990 1997 i40e_get_hw_state(i40e_t *i40e, i40e_hw_t *hw)
1991 1998 {
1992 1999 int rc;
1993 2000
1994 2001 ASSERT(MUTEX_HELD(&i40e->i40e_general_lock));
1995 2002
1996 2003 (void) i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1997 2004 i40e_link_check(i40e);
1998 2005
1999 2006 /*
2000 2007 * Try and determine our PHY. Note that we may have to retry to and
2001 2008 * delay to detect fiber correctly.
2002 2009 */
2003 2010 rc = i40e_aq_get_phy_capabilities(hw, B_FALSE, B_TRUE, &i40e->i40e_phy,
2004 2011 NULL);
2005 2012 if (rc == I40E_ERR_UNKNOWN_PHY) {
2006 2013 i40e_msec_delay(200);
2007 2014 rc = i40e_aq_get_phy_capabilities(hw, B_FALSE, B_TRUE,
2008 2015 &i40e->i40e_phy, NULL);
2009 2016 }
2010 2017
2011 2018 if (rc != I40E_SUCCESS) {
2012 2019 if (rc == I40E_ERR_UNKNOWN_PHY) {
2013 2020 i40e_error(i40e, "encountered unknown PHY type, "
2014 2021 "not attaching.");
2015 2022 } else {
2016 2023 i40e_error(i40e, "error getting physical capabilities: "
2017 2024 "%d, %d", rc, hw->aq.asq_last_status);
2018 2025 }
2019 2026 }
2020 2027
2021 2028 rc = i40e_update_link_info(hw);
2022 2029 if (rc != I40E_SUCCESS) {
2023 2030 i40e_error(i40e, "failed to update link information: %d", rc);
2024 2031 }
2025 2032
2026 2033 /*
2027 2034 * In general, we don't want to mask off (as in stop from being a cause)
2028 2035 * any of the interrupts that the phy might be able to generate.
2029 2036 */
2030 2037 rc = i40e_aq_set_phy_int_mask(hw, 0, NULL);
2031 2038 if (rc != I40E_SUCCESS) {
2032 2039 i40e_error(i40e, "failed to update phy link mask: %d", rc);
2033 2040 }
2034 2041 }
2035 2042
2036 2043 /*
2037 2044 * Go through and re-initialize any existing filters that we may have set up for
2038 2045 * this device. Note that we would only expect them to exist if hardware had
2039 2046 * already been initialized and we had just reset it. While we're not
2040 2047 * implementing this yet, we're keeping this around for when we add reset
2041 2048 * capabilities, so this isn't forgotten.
2042 2049 */
2043 2050 /* ARGSUSED */
2044 2051 static void
2045 2052 i40e_init_macaddrs(i40e_t *i40e, i40e_hw_t *hw)
2046 2053 {
2047 2054 }
2048 2055
2049 2056 /*
2050 2057 * Set the properties which have common values across all the VSIs.
2051 2058 * Consult the "Add VSI" command section (7.4.9.5.5.1) for a
2052 2059 * complete description of these properties.
2053 2060 */
2054 2061 static void
2055 2062 i40e_set_shared_vsi_props(i40e_t *i40e,
2056 2063 struct i40e_aqc_vsi_properties_data *info, uint_t vsi_idx)
2057 2064 {
2058 2065 uint_t tc_queues;
2059 2066 uint16_t vsi_qp_base;
2060 2067
2061 2068 /*
2062 2069 * It's important that we use bitwise-OR here; callers to this
2063 2070 * function might enable other sections before calling this
2064 2071 * function.
2065 2072 */
2066 2073 info->valid_sections |= LE_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID |
2067 2074 I40E_AQ_VSI_PROP_VLAN_VALID);
2068 2075
2069 2076 /*
2070 2077 * Calculate the starting QP index for this VSI. This base is
2071 2078 * relative to the PF queue space; so a value of 0 for PF#1
2072 2079 * represents the absolute index PFLAN_QALLOC_FIRSTQ for PF#1.
2073 2080 */
2074 2081 vsi_qp_base = vsi_idx * i40e->i40e_num_trqpairs_per_vsi;
2075 2082 info->mapping_flags = LE_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2076 2083 info->queue_mapping[0] =
2077 2084 LE_16((vsi_qp_base << I40E_AQ_VSI_QUEUE_SHIFT) &
2078 2085 I40E_AQ_VSI_QUEUE_MASK);
2079 2086
2080 2087 /*
2081 2088 * tc_queues determines the size of the traffic class, where
2082 2089 * the size is 2^^tc_queues to a maximum of 64 for the X710
2083 2090 * and 128 for the X722.
2084 2091 *
2085 2092 * Some examples:
2086 2093 * i40e_num_trqpairs_per_vsi == 1 => tc_queues = 0, 2^^0 = 1.
2087 2094 * i40e_num_trqpairs_per_vsi == 7 => tc_queues = 3, 2^^3 = 8.
2088 2095 * i40e_num_trqpairs_per_vsi == 8 => tc_queues = 3, 2^^3 = 8.
2089 2096 * i40e_num_trqpairs_per_vsi == 9 => tc_queues = 4, 2^^4 = 16.
2090 2097 * i40e_num_trqpairs_per_vsi == 17 => tc_queues = 5, 2^^5 = 32.
2091 2098 * i40e_num_trqpairs_per_vsi == 64 => tc_queues = 6, 2^^6 = 64.
2092 2099 */
2093 2100 tc_queues = ddi_fls(i40e->i40e_num_trqpairs_per_vsi - 1);
2094 2101
2095 2102 /*
2096 2103 * The TC queue mapping is in relation to the VSI queue space.
2097 2104 * Since we are only using one traffic class (TC0) we always
2098 2105 * start at queue offset 0.
2099 2106 */
2100 2107 info->tc_mapping[0] =
2101 2108 LE_16(((0 << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) &
2102 2109 I40E_AQ_VSI_TC_QUE_OFFSET_MASK) |
2103 2110 ((tc_queues << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) &
2104 2111 I40E_AQ_VSI_TC_QUE_NUMBER_MASK));
2105 2112
2106 2113 /*
2107 2114 * I40E_AQ_VSI_PVLAN_MODE_ALL ("VLAN driver insertion mode")
2108 2115 *
2109 2116 * Allow tagged and untagged packets to be sent to this
2110 2117 * VSI from the host.
2111 2118 *
2112 2119 * I40E_AQ_VSI_PVLAN_EMOD_NOTHING ("VLAN and UP expose mode")
2113 2120 *
2114 2121 * Leave the tag on the frame and place no VLAN
2115 2122 * information in the descriptor. We want this mode
2116 2123 * because our MAC layer will take care of the VLAN tag,
2117 2124 * if there is one.
2118 2125 */
2119 2126 info->port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2120 2127 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2121 2128 }
2122 2129
2123 2130 /*
2124 2131 * Delete the VSI at this index, if one exists. We assume there is no
2125 2132 * action we can take if this command fails but to log the failure.
2126 2133 */
2127 2134 static void
2128 2135 i40e_delete_vsi(i40e_t *i40e, uint_t idx)
2129 2136 {
2130 2137 i40e_hw_t *hw = &i40e->i40e_hw_space;
2131 2138 uint16_t seid = i40e->i40e_vsis[idx].iv_seid;
2132 2139
2133 2140 if (seid != 0) {
2134 2141 int rc;
2135 2142
2136 2143 rc = i40e_aq_delete_element(hw, seid, NULL);
2137 2144
2138 2145 if (rc != I40E_SUCCESS) {
2139 2146 i40e_error(i40e, "Failed to delete VSI %d: %d",
2140 2147 rc, hw->aq.asq_last_status);
2141 2148 }
2142 2149
2143 2150 i40e->i40e_vsis[idx].iv_seid = 0;
2144 2151 }
2145 2152 }
2146 2153
2147 2154 /*
2148 2155 * Add a new VSI.
2149 2156 */
2150 2157 static boolean_t
2151 2158 i40e_add_vsi(i40e_t *i40e, i40e_hw_t *hw, uint_t idx)
2152 2159 {
2153 2160 struct i40e_vsi_context ctx;
2154 2161 i40e_rx_group_t *rxg;
2155 2162 int rc;
2156 2163
2157 2164 /*
2158 2165 * The default VSI is created by the controller. This function
2159 2166 * creates new, non-defualt VSIs only.
2160 2167 */
2161 2168 ASSERT3U(idx, !=, 0);
2162 2169
2163 2170 bzero(&ctx, sizeof (struct i40e_vsi_context));
2164 2171 ctx.uplink_seid = i40e->i40e_veb_seid;
2165 2172 ctx.pf_num = hw->pf_id;
2166 2173 ctx.flags = I40E_AQ_VSI_TYPE_PF;
2167 2174 ctx.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
2168 2175 i40e_set_shared_vsi_props(i40e, &ctx.info, idx);
2169 2176
2170 2177 rc = i40e_aq_add_vsi(hw, &ctx, NULL);
2171 2178 if (rc != I40E_SUCCESS) {
2172 2179 i40e_error(i40e, "i40e_aq_add_vsi() failed %d: %d", rc,
2173 2180 hw->aq.asq_last_status);
2174 2181 return (B_FALSE);
2175 2182 }
2176 2183
2177 2184 rxg = &i40e->i40e_rx_groups[idx];
2178 2185 rxg->irg_vsi_seid = ctx.seid;
2179 2186 i40e->i40e_vsis[idx].iv_number = ctx.vsi_number;
2180 2187 i40e->i40e_vsis[idx].iv_seid = ctx.seid;
2181 2188 i40e->i40e_vsis[idx].iv_stats_id = LE_16(ctx.info.stat_counter_idx);
2182 2189
2183 2190 if (i40e_stat_vsi_init(i40e, idx) == B_FALSE)
2184 2191 return (B_FALSE);
2185 2192
2186 2193 return (B_TRUE);
2187 2194 }
2188 2195
2189 2196 /*
2190 2197 * Configure the hardware for the Default Virtual Station Interface (VSI).
2191 2198 */
2192 2199 static boolean_t
2193 2200 i40e_config_def_vsi(i40e_t *i40e, i40e_hw_t *hw)
2194 2201 {
2195 2202 struct i40e_vsi_context ctx;
2196 2203 i40e_rx_group_t *def_rxg;
2197 2204 int err;
2198 2205 struct i40e_aqc_remove_macvlan_element_data filt;
2199 2206
2200 2207 bzero(&ctx, sizeof (struct i40e_vsi_context));
2201 2208 ctx.seid = I40E_DEF_VSI_SEID(i40e);
2202 2209 ctx.pf_num = hw->pf_id;
2203 2210 err = i40e_aq_get_vsi_params(hw, &ctx, NULL);
2204 2211 if (err != I40E_SUCCESS) {
2205 2212 i40e_error(i40e, "get VSI params failed with %d", err);
2206 2213 return (B_FALSE);
2207 2214 }
2208 2215
2209 2216 ctx.info.valid_sections = 0;
2210 2217 i40e->i40e_vsis[0].iv_number = ctx.vsi_number;
2211 2218 i40e->i40e_vsis[0].iv_stats_id = LE_16(ctx.info.stat_counter_idx);
2212 2219 if (i40e_stat_vsi_init(i40e, 0) == B_FALSE)
2213 2220 return (B_FALSE);
2214 2221
2215 2222 i40e_set_shared_vsi_props(i40e, &ctx.info, I40E_DEF_VSI_IDX);
2216 2223
2217 2224 err = i40e_aq_update_vsi_params(hw, &ctx, NULL);
2218 2225 if (err != I40E_SUCCESS) {
2219 2226 i40e_error(i40e, "Update VSI params failed with %d", err);
2220 2227 return (B_FALSE);
2221 2228 }
2222 2229
2223 2230 def_rxg = &i40e->i40e_rx_groups[0];
2224 2231 def_rxg->irg_vsi_seid = I40E_DEF_VSI_SEID(i40e);
2225 2232
2226 2233 /*
2227 2234 * We have seen three different behaviors in regards to the
2228 2235 * Default VSI and its implicit L2 MAC+VLAN filter.
2229 2236 *
2230 2237 * 1. It has an implicit filter for the factory MAC address
2231 2238 * and this filter counts against 'ifr_nmacfilt_used'.
2232 2239 *
2233 2240 * 2. It has an implicit filter for the factory MAC address
2234 2241 * and this filter DOES NOT count against 'ifr_nmacfilt_used'.
2235 2242 *
2236 2243 * 3. It DOES NOT have an implicit filter.
2237 2244 *
2238 2245 * All three of these cases are accounted for below. If we
2239 2246 * fail to remove the L2 filter (ENOENT) then we assume there
2240 2247 * wasn't one. Otherwise, if we successfully remove the
2241 2248 * filter, we make sure to update the 'ifr_nmacfilt_used'
2242 2249 * count accordingly.
2243 2250 *
2244 2251 * We remove this filter to prevent duplicate delivery of
2245 2252 * packets destined for the primary MAC address as DLS will
2246 2253 * create the same filter on a non-default VSI for the primary
2247 2254 * MAC client.
2248 2255 *
2249 2256 * If you change the following code please test it across as
2250 2257 * many X700 series controllers and firmware revisions as you
2251 2258 * can.
2252 2259 */
2253 2260 bzero(&filt, sizeof (filt));
2254 2261 bcopy(hw->mac.port_addr, filt.mac_addr, ETHERADDRL);
2255 2262 filt.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
2256 2263 filt.vlan_tag = 0;
2257 2264
2258 2265 ASSERT3U(i40e->i40e_resources.ifr_nmacfilt_used, <=, 1);
2259 2266 i40e_log(i40e, "Num L2 filters: %u",
2260 2267 i40e->i40e_resources.ifr_nmacfilt_used);
2261 2268
2262 2269 err = i40e_aq_remove_macvlan(hw, I40E_DEF_VSI_SEID(i40e), &filt, 1,
2263 2270 NULL);
2264 2271 if (err == I40E_SUCCESS) {
2265 2272 i40e_log(i40e,
2266 2273 "Removed L2 filter from Default VSI with SEID %u",
2267 2274 I40E_DEF_VSI_SEID(i40e));
2268 2275 } else if (hw->aq.asq_last_status == ENOENT) {
2269 2276 i40e_log(i40e,
2270 2277 "No L2 filter for Default VSI with SEID %u",
2271 2278 I40E_DEF_VSI_SEID(i40e));
2272 2279 } else {
2273 2280 i40e_error(i40e, "Failed to remove L2 filter from"
2274 2281 " Default VSI with SEID %u: %d (%d)",
2275 2282 I40E_DEF_VSI_SEID(i40e), err, hw->aq.asq_last_status);
2276 2283
2277 2284 return (B_FALSE);
2278 2285 }
2279 2286
2280 2287 /*
2281 2288 * As mentioned above, the controller created an implicit L2
2282 2289 * filter for the primary MAC. We want to remove both the
2283 2290 * filter and decrement the filter count. However, not all
2284 2291 * controllers count this implicit filter against the total
2285 2292 * MAC filter count. So here we are making sure it is either
2286 2293 * one or zero. If it is one, then we know it is for the
2287 2294 * implicit filter and we should decrement since we just
2288 2295 * removed the filter above. If it is zero then we know the
2289 2296 * controller that does not count the implicit filter, and it
2290 2297 * was enough to just remove it; we leave the count alone.
2291 2298 * But if it is neither, then we have never seen a controller
2292 2299 * like this before and we should fail to attach.
2293 2300 *
2294 2301 * It is unfortunate that this code must exist but the
2295 2302 * behavior of this implicit L2 filter and its corresponding
2296 2303 * count were dicovered through empirical testing. The
2297 2304 * programming manuals hint at this filter but do not
2298 2305 * explicitly call out the exact behavior.
2299 2306 */
2300 2307 if (i40e->i40e_resources.ifr_nmacfilt_used == 1) {
2301 2308 i40e->i40e_resources.ifr_nmacfilt_used--;
2302 2309 } else {
2303 2310 if (i40e->i40e_resources.ifr_nmacfilt_used != 0) {
2304 2311 i40e_error(i40e, "Unexpected L2 filter count: %u"
2305 2312 " (expected 0)",
2306 2313 i40e->i40e_resources.ifr_nmacfilt_used);
2307 2314 return (B_FALSE);
2308 2315 }
2309 2316 }
2310 2317
2311 2318 return (B_TRUE);
2312 2319 }
2313 2320
2314 2321 static boolean_t
2315 2322 i40e_config_rss_key_x722(i40e_t *i40e, i40e_hw_t *hw)
2316 2323 {
2317 2324 for (uint_t i = 0; i < i40e->i40e_num_rx_groups; i++) {
2318 2325 uint32_t seed[I40E_PFQF_HKEY_MAX_INDEX + 1];
2319 2326 struct i40e_aqc_get_set_rss_key_data key;
2320 2327 const char *u8seed;
2321 2328 enum i40e_status_code status;
2322 2329 uint16_t vsi_number = i40e->i40e_vsis[i].iv_number;
2323 2330
2324 2331 (void) random_get_pseudo_bytes((uint8_t *)seed, sizeof (seed));
2325 2332 u8seed = (char *)seed;
2326 2333
2327 2334 CTASSERT(sizeof (key) >= (sizeof (key.standard_rss_key) +
2328 2335 sizeof (key.extended_hash_key)));
2329 2336
2330 2337 bcopy(u8seed, key.standard_rss_key,
2331 2338 sizeof (key.standard_rss_key));
2332 2339 bcopy(&u8seed[sizeof (key.standard_rss_key)],
2333 2340 key.extended_hash_key, sizeof (key.extended_hash_key));
2334 2341
2335 2342 ASSERT3U(vsi_number, !=, 0);
2336 2343 status = i40e_aq_set_rss_key(hw, vsi_number, &key);
2337 2344
2338 2345 if (status != I40E_SUCCESS) {
2339 2346 i40e_error(i40e, "failed to set RSS key for VSI %u: %d",
2340 2347 vsi_number, status);
2341 2348 return (B_FALSE);
2342 2349 }
2343 2350 }
2344 2351
2345 2352 return (B_TRUE);
2346 2353 }
2347 2354
2348 2355 /*
2349 2356 * Configure the RSS key. For the X710 controller family, this is set on a
2350 2357 * per-PF basis via registers. For the X722, this is done on a per-VSI basis
2351 2358 * through the admin queue.
2352 2359 */
2353 2360 static boolean_t
2354 2361 i40e_config_rss_key(i40e_t *i40e, i40e_hw_t *hw)
2355 2362 {
2356 2363 if (i40e_is_x722(i40e)) {
2357 2364 if (!i40e_config_rss_key_x722(i40e, hw))
2358 2365 return (B_FALSE);
2359 2366 } else {
2360 2367 uint32_t seed[I40E_PFQF_HKEY_MAX_INDEX + 1];
2361 2368
2362 2369 (void) random_get_pseudo_bytes((uint8_t *)seed, sizeof (seed));
2363 2370 for (uint_t i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
2364 2371 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), seed[i]);
2365 2372 }
2366 2373
2367 2374 return (B_TRUE);
2368 2375 }
2369 2376
2370 2377 /*
2371 2378 * Populate the LUT. The size of each entry in the LUT depends on the controller
2372 2379 * family, with the X722 using a known 7-bit width. On the X710 controller, this
2373 2380 * is programmed through its control registers where as on the X722 this is
2374 2381 * configured through the admin queue. Also of note, the X722 allows the LUT to
2375 2382 * be set on a per-PF or VSI basis. At this time we use the PF setting. If we
2376 2383 * decide to use the per-VSI LUT in the future, then we will need to modify the
2377 2384 * i40e_add_vsi() function to set the RSS LUT bits in the queueing section.
2378 2385 *
2379 2386 * We populate the LUT in a round robin fashion with the rx queue indices from 0
2380 2387 * to i40e_num_trqpairs_per_vsi - 1.
2381 2388 */
2382 2389 static boolean_t
2383 2390 i40e_config_rss_hlut(i40e_t *i40e, i40e_hw_t *hw)
2384 2391 {
2385 2392 uint32_t *hlut;
2386 2393 uint8_t lut_mask;
2387 2394 uint_t i;
2388 2395 boolean_t ret = B_FALSE;
2389 2396
2390 2397 /*
2391 2398 * We always configure the PF with a table size of 512 bytes in
2392 2399 * i40e_chip_start().
2393 2400 */
2394 2401 hlut = kmem_alloc(I40E_HLUT_TABLE_SIZE, KM_NOSLEEP);
2395 2402 if (hlut == NULL) {
2396 2403 i40e_error(i40e, "i40e_config_rss() buffer allocation failed");
2397 2404 return (B_FALSE);
2398 2405 }
2399 2406
2400 2407 /*
2401 2408 * The width of the X722 is apparently defined to be 7 bits, regardless
2402 2409 * of the capability.
2403 2410 */
2404 2411 if (i40e_is_x722(i40e)) {
2405 2412 lut_mask = (1 << 7) - 1;
2406 2413 } else {
2407 2414 lut_mask = (1 << hw->func_caps.rss_table_entry_width) - 1;
2408 2415 }
2409 2416
2410 2417 for (i = 0; i < I40E_HLUT_TABLE_SIZE; i++) {
2411 2418 ((uint8_t *)hlut)[i] =
2412 2419 (i % i40e->i40e_num_trqpairs_per_vsi) & lut_mask;
2413 2420 }
2414 2421
2415 2422 if (i40e_is_x722(i40e)) {
2416 2423 enum i40e_status_code status;
2417 2424
2418 2425 status = i40e_aq_set_rss_lut(hw, 0, B_TRUE, (uint8_t *)hlut,
2419 2426 I40E_HLUT_TABLE_SIZE);
2420 2427
2421 2428 if (status != I40E_SUCCESS) {
2422 2429 i40e_error(i40e, "failed to set RSS LUT %d: %d",
2423 2430 status, hw->aq.asq_last_status);
2424 2431 goto out;
2425 2432 }
2426 2433 } else {
2427 2434 for (i = 0; i < I40E_HLUT_TABLE_SIZE >> 2; i++) {
2428 2435 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), hlut[i]);
2429 2436 }
2430 2437 }
2431 2438 ret = B_TRUE;
2432 2439 out:
2433 2440 kmem_free(hlut, I40E_HLUT_TABLE_SIZE);
2434 2441 return (ret);
2435 2442 }
2436 2443
2437 2444 /*
2438 2445 * Set up RSS.
2439 2446 * 1. Seed the hash key.
2440 2447 * 2. Enable PCTYPEs for the hash filter.
2441 2448 * 3. Populate the LUT.
2442 2449 */
2443 2450 static boolean_t
2444 2451 i40e_config_rss(i40e_t *i40e, i40e_hw_t *hw)
2445 2452 {
2446 2453 uint64_t hena;
2447 2454
2448 2455 /*
2449 2456 * 1. Seed the hash key
2450 2457 */
2451 2458 if (!i40e_config_rss_key(i40e, hw))
2452 2459 return (B_FALSE);
2453 2460
2454 2461 /*
2455 2462 * 2. Configure PCTYPES
2456 2463 */
2457 2464 hena = (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |
2458 2465 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
2459 2466 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) |
2460 2467 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
2461 2468 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) |
2462 2469 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
2463 2470 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
2464 2471 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) |
2465 2472 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
2466 2473 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) |
2467 2474 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
2468 2475
2469 2476 /*
2470 2477 * Add additional types supported by the X722 controller.
2471 2478 */
2472 2479 if (i40e_is_x722(i40e)) {
2473 2480 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
2474 2481 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |
2475 2482 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) |
2476 2483 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
2477 2484 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |
2478 2485 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
2479 2486 }
2480 2487
2481 2488 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
2482 2489 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
2483 2490
2484 2491 /*
2485 2492 * 3. Populate LUT
2486 2493 */
2487 2494 return (i40e_config_rss_hlut(i40e, hw));
2488 2495 }
2489 2496
2490 2497 /*
2491 2498 * Wrapper to kick the chipset on.
2492 2499 */
2493 2500 static boolean_t
2494 2501 i40e_chip_start(i40e_t *i40e)
2495 2502 {
2496 2503 i40e_hw_t *hw = &i40e->i40e_hw_space;
2497 2504 struct i40e_filter_control_settings filter;
2498 2505 int rc;
2499 2506 uint8_t err;
2500 2507
2501 2508 if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) ||
2502 2509 (hw->aq.fw_maj_ver < 4)) {
2503 2510 i40e_msec_delay(75);
2504 2511 if (i40e_aq_set_link_restart_an(hw, TRUE, NULL) !=
2505 2512 I40E_SUCCESS) {
2506 2513 i40e_error(i40e, "failed to restart link: admin queue "
2507 2514 "error: %d", hw->aq.asq_last_status);
2508 2515 return (B_FALSE);
2509 2516 }
2510 2517 }
2511 2518
2512 2519 /* Determine hardware state */
2513 2520 i40e_get_hw_state(i40e, hw);
2514 2521
2515 2522 /* For now, we always disable Ethernet Flow Control. */
2516 2523 hw->fc.requested_mode = I40E_FC_NONE;
2517 2524 rc = i40e_set_fc(hw, &err, B_TRUE);
2518 2525 if (rc != I40E_SUCCESS) {
2519 2526 i40e_error(i40e, "Setting flow control failed, returned %d"
2520 2527 " with error: 0x%x", rc, err);
2521 2528 return (B_FALSE);
2522 2529 }
2523 2530
2524 2531 /* Initialize mac addresses. */
2525 2532 i40e_init_macaddrs(i40e, hw);
2526 2533
2527 2534 /*
2528 2535 * Set up the filter control. If the hash lut size is changed from
2529 2536 * I40E_HASH_LUT_SIZE_512 then I40E_HLUT_TABLE_SIZE and
2530 2537 * i40e_config_rss_hlut() will need to be updated.
2531 2538 */
2532 2539 bzero(&filter, sizeof (filter));
2533 2540 filter.enable_ethtype = TRUE;
2534 2541 filter.enable_macvlan = TRUE;
2535 2542 filter.hash_lut_size = I40E_HASH_LUT_SIZE_512;
2536 2543
2537 2544 rc = i40e_set_filter_control(hw, &filter);
2538 2545 if (rc != I40E_SUCCESS) {
2539 2546 i40e_error(i40e, "i40e_set_filter_control() returned %d", rc);
2540 2547 return (B_FALSE);
2541 2548 }
2542 2549
2543 2550 i40e_intr_chip_init(i40e);
2544 2551
2545 2552 rc = i40e_get_mac_seid(i40e);
2546 2553 if (rc == -1) {
2547 2554 i40e_error(i40e, "failed to obtain MAC Uplink SEID");
2548 2555 return (B_FALSE);
2549 2556 }
2550 2557 i40e->i40e_mac_seid = (uint16_t)rc;
2551 2558
2552 2559 /*
2553 2560 * Create a VEB in order to support multiple VSIs. Each VSI
2554 2561 * functions as a MAC group. This call sets the PF's MAC as
2555 2562 * the uplink port and the PF's default VSI as the default
2556 2563 * downlink port.
2557 2564 */
2558 2565 rc = i40e_aq_add_veb(hw, i40e->i40e_mac_seid, I40E_DEF_VSI_SEID(i40e),
2559 2566 0x1, B_TRUE, &i40e->i40e_veb_seid, B_FALSE, NULL);
2560 2567 if (rc != I40E_SUCCESS) {
2561 2568 i40e_error(i40e, "i40e_aq_add_veb() failed %d: %d", rc,
2562 2569 hw->aq.asq_last_status);
2563 2570 return (B_FALSE);
2564 2571 }
2565 2572
2566 2573 if (!i40e_config_def_vsi(i40e, hw))
2567 2574 return (B_FALSE);
2568 2575
2569 2576 for (uint_t i = 1; i < i40e->i40e_num_rx_groups; i++) {
2570 2577 if (!i40e_add_vsi(i40e, hw, i))
2571 2578 return (B_FALSE);
2572 2579 }
2573 2580
2574 2581 if (!i40e_config_rss(i40e, hw))
2575 2582 return (B_FALSE);
2576 2583
2577 2584 i40e_flush(hw);
2578 2585
2579 2586 return (B_TRUE);
2580 2587 }
2581 2588
2582 2589 /*
2583 2590 * Take care of tearing down the rx ring. See 8.3.3.1.2 for more information.
2584 2591 */
2585 2592 static void
2586 2593 i40e_shutdown_rx_ring(i40e_trqpair_t *itrq)
2587 2594 {
2588 2595 i40e_t *i40e = itrq->itrq_i40e;
2589 2596 i40e_hw_t *hw = &i40e->i40e_hw_space;
2590 2597 uint32_t reg;
2591 2598
2592 2599 /*
2593 2600 * Step 1. 8.3.3.1.2 suggests the interrupt is removed from the
2594 2601 * hardware interrupt linked list (see i40e_intr.c) but for
2595 2602 * simplicity we keep this list immutable until the device
2596 2603 * (distinct from an individual ring) is stopped.
2597 2604 */
2598 2605
2599 2606 /*
2600 2607 * Step 2. Request the queue by clearing QENA_REQ. It may not be
2601 2608 * set due to unwinding from failures and a partially enabled
2602 2609 * ring set.
2603 2610 */
2604 2611 reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
2605 2612 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK))
2606 2613 return;
2607 2614 VERIFY((reg & I40E_QRX_ENA_QENA_REQ_MASK) ==
2608 2615 I40E_QRX_ENA_QENA_REQ_MASK);
2609 2616 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
2610 2617 I40E_WRITE_REG(hw, I40E_QRX_ENA(itrq->itrq_index), reg);
2611 2618
2612 2619 /*
2613 2620 * Step 3. Wait for the disable to take, by having QENA_STAT in the FPM
2614 2621 * be cleared. Note that we could still receive data in the queue during
2615 2622 * this time. We don't actually wait for this now and instead defer this
2616 2623 * to i40e_shutdown_ring_wait(), after we've interleaved disabling the
2617 2624 * TX queue as well.
2618 2625 */
2619 2626 }
2620 2627
2621 2628 static void
2622 2629 i40e_shutdown_tx_ring(i40e_trqpair_t *itrq)
2623 2630 {
2624 2631 i40e_t *i40e = itrq->itrq_i40e;
2625 2632 i40e_hw_t *hw = &i40e->i40e_hw_space;
2626 2633 uint32_t reg;
2627 2634
2628 2635 /*
2629 2636 * Step 2. Set the SET_QDIS flag for the queue.
2630 2637 */
2631 2638 i40e_pre_tx_queue_cfg(hw, itrq->itrq_index, B_FALSE);
2632 2639
2633 2640 /*
2634 2641 * Step 3. Wait at least 400 usec.
2635 2642 */
2636 2643 drv_usecwait(500);
2637 2644
2638 2645 /*
2639 2646 * Step 4. Clear the QENA_REQ flag which tells hardware to
2640 2647 * quiesce. If QENA_REQ is not already set then that means that
2641 2648 * we likely already tried to disable this queue.
2642 2649 */
2643 2650 reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
2644 2651 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) != 0) {
2645 2652 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2646 2653 I40E_WRITE_REG(hw, I40E_QTX_ENA(itrq->itrq_index), reg);
2647 2654 }
2648 2655
2649 2656 /*
2650 2657 * Step 5. Wait for the drain to finish. This will be done by the
2651 2658 * hardware removing the QENA_STAT flag from the queue. Rather than
2652 2659 * waiting here, we interleave it with the receive shutdown in
2653 2660 * i40e_shutdown_ring_wait().
2654 2661 */
2655 2662 }
2656 2663
2657 2664 /*
2658 2665 * Wait for a ring to be shut down. e.g. Steps 2 and 5 from the above
2659 2666 * functions.
2660 2667 */
2661 2668 static boolean_t
2662 2669 i40e_shutdown_ring_wait(i40e_trqpair_t *itrq)
2663 2670 {
2664 2671 i40e_t *i40e = itrq->itrq_i40e;
2665 2672 i40e_hw_t *hw = &i40e->i40e_hw_space;
2666 2673 uint32_t reg;
2667 2674 int try;
2668 2675
2669 2676 for (try = 0; try < I40E_RING_WAIT_NTRIES; try++) {
2670 2677 reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
2671 2678 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0)
2672 2679 break;
2673 2680 i40e_msec_delay(I40E_RING_WAIT_PAUSE);
2674 2681 }
2675 2682
2676 2683 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) != 0) {
2677 2684 i40e_error(i40e, "timed out disabling rx queue %d",
2678 2685 itrq->itrq_index);
2679 2686 return (B_FALSE);
2680 2687 }
2681 2688
2682 2689 for (try = 0; try < I40E_RING_WAIT_NTRIES; try++) {
2683 2690 reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
2684 2691 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0)
2685 2692 break;
2686 2693 i40e_msec_delay(I40E_RING_WAIT_PAUSE);
2687 2694 }
2688 2695
2689 2696 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) != 0) {
2690 2697 i40e_error(i40e, "timed out disabling tx queue %d",
2691 2698 itrq->itrq_index);
2692 2699 return (B_FALSE);
2693 2700 }
2694 2701
2695 2702 return (B_TRUE);
2696 2703 }
2697 2704
2698 2705
2699 2706 /*
2700 2707 * Shutdown an individual ring and release any memory.
2701 2708 */
2702 2709 boolean_t
2703 2710 i40e_shutdown_ring(i40e_trqpair_t *itrq)
2704 2711 {
2705 2712 boolean_t rv = B_TRUE;
2706 2713
2707 2714 /*
2708 2715 * Tell transmit path to quiesce, and wait until done.
2709 2716 */
2710 2717 if (i40e_ring_tx_quiesce(itrq)) {
2711 2718 /* Already quiesced. */
2712 2719 return (B_TRUE);
2713 2720 }
2714 2721
2715 2722 i40e_shutdown_rx_ring(itrq);
2716 2723 i40e_shutdown_tx_ring(itrq);
2717 2724 if (!i40e_shutdown_ring_wait(itrq))
2718 2725 rv = B_FALSE;
2719 2726
2720 2727 /*
2721 2728 * After the ring has stopped, we need to wait 50ms before
2722 2729 * programming it again. Rather than wait here, we'll record
2723 2730 * the time the ring was stopped. When the ring is started, we'll
2724 2731 * check if enough time has expired and then wait if necessary.
2725 2732 */
2726 2733 itrq->irtq_time_stopped = gethrtime();
2727 2734
2728 2735 /*
2729 2736 * The rings have been stopped in the hardware, now wait for
2730 2737 * a possibly active interrupt thread.
2731 2738 */
2732 2739 i40e_intr_quiesce(itrq);
2733 2740
2734 2741 mutex_enter(&itrq->itrq_tx_lock);
2735 2742 i40e_tx_cleanup_ring(itrq);
2736 2743 mutex_exit(&itrq->itrq_tx_lock);
2737 2744
2738 2745 i40e_free_ring_mem(itrq, B_FALSE);
2739 2746
2740 2747 return (rv);
2741 2748 }
2742 2749
2743 2750 /*
2744 2751 * Shutdown all the rings.
2745 2752 * Called from i40e_stop(), and hopefully the mac layer has already
2746 2753 * called ring stop for each ring, which would make this almost a no-op.
2747 2754 */
2748 2755 static boolean_t
2749 2756 i40e_shutdown_rings(i40e_t *i40e)
2750 2757 {
2751 2758 boolean_t rv = B_TRUE;
2752 2759 int i;
2753 2760
2754 2761 for (i = 0; i < i40e->i40e_num_trqpairs; i++) {
2755 2762 if (!i40e_shutdown_ring(&i40e->i40e_trqpairs[i]))
2756 2763 rv = B_FALSE;
2757 2764 }
2758 2765
2759 2766 return (rv);
2760 2767 }
2761 2768
2762 2769 static void
2763 2770 i40e_setup_rx_descs(i40e_trqpair_t *itrq)
2764 2771 {
2765 2772 int i;
2766 2773 i40e_rx_data_t *rxd = itrq->itrq_rxdata;
2767 2774
2768 2775 for (i = 0; i < rxd->rxd_ring_size; i++) {
2769 2776 i40e_rx_control_block_t *rcb;
2770 2777 i40e_rx_desc_t *rdesc;
2771 2778
2772 2779 rcb = rxd->rxd_work_list[i];
2773 2780 rdesc = &rxd->rxd_desc_ring[i];
2774 2781
2775 2782 rdesc->read.pkt_addr =
2776 2783 CPU_TO_LE64((uintptr_t)rcb->rcb_dma.dmab_dma_address);
2777 2784 rdesc->read.hdr_addr = 0;
2778 2785 }
2779 2786 }
2780 2787
2781 2788 static boolean_t
2782 2789 i40e_setup_rx_hmc(i40e_trqpair_t *itrq)
2783 2790 {
2784 2791 i40e_rx_data_t *rxd = itrq->itrq_rxdata;
2785 2792 i40e_t *i40e = itrq->itrq_i40e;
2786 2793 i40e_hw_t *hw = &i40e->i40e_hw_space;
2787 2794
2788 2795 struct i40e_hmc_obj_rxq rctx;
2789 2796 int err;
2790 2797
2791 2798 bzero(&rctx, sizeof (struct i40e_hmc_obj_rxq));
2792 2799 rctx.base = rxd->rxd_desc_area.dmab_dma_address /
2793 2800 I40E_HMC_RX_CTX_UNIT;
2794 2801 rctx.qlen = rxd->rxd_ring_size;
2795 2802 VERIFY(i40e->i40e_rx_buf_size >= I40E_HMC_RX_DBUFF_MIN);
2796 2803 VERIFY(i40e->i40e_rx_buf_size <= I40E_HMC_RX_DBUFF_MAX);
2797 2804 rctx.dbuff = i40e->i40e_rx_buf_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
2798 2805 rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT;
2799 2806 rctx.dtype = I40E_HMC_RX_DTYPE_NOSPLIT;
2800 2807 rctx.dsize = I40E_HMC_RX_DSIZE_32BYTE;
2801 2808 rctx.crcstrip = I40E_HMC_RX_CRCSTRIP_ENABLE;
2802 2809 rctx.fc_ena = I40E_HMC_RX_FC_DISABLE;
2803 2810 rctx.l2tsel = I40E_HMC_RX_L2TAGORDER;
2804 2811 rctx.hsplit_0 = I40E_HMC_RX_HDRSPLIT_DISABLE;
2805 2812 rctx.hsplit_1 = I40E_HMC_RX_HDRSPLIT_DISABLE;
2806 2813 rctx.showiv = I40E_HMC_RX_INVLAN_DONTSTRIP;
2807 2814 rctx.rxmax = i40e->i40e_frame_max;
2808 2815 rctx.tphrdesc_ena = I40E_HMC_RX_TPH_DISABLE;
2809 2816 rctx.tphwdesc_ena = I40E_HMC_RX_TPH_DISABLE;
2810 2817 rctx.tphdata_ena = I40E_HMC_RX_TPH_DISABLE;
2811 2818 rctx.tphhead_ena = I40E_HMC_RX_TPH_DISABLE;
2812 2819 rctx.lrxqthresh = I40E_HMC_RX_LOWRXQ_NOINTR;
2813 2820
2814 2821 /*
2815 2822 * This must be set to 0x1, see Table 8-12 in section 8.3.3.2.2.
2816 2823 */
2817 2824 rctx.prefena = I40E_HMC_RX_PREFENA;
2818 2825
2819 2826 err = i40e_clear_lan_rx_queue_context(hw, itrq->itrq_index);
2820 2827 if (err != I40E_SUCCESS) {
2821 2828 i40e_error(i40e, "failed to clear rx queue %d context: %d",
2822 2829 itrq->itrq_index, err);
2823 2830 return (B_FALSE);
2824 2831 }
2825 2832
2826 2833 err = i40e_set_lan_rx_queue_context(hw, itrq->itrq_index, &rctx);
2827 2834 if (err != I40E_SUCCESS) {
2828 2835 i40e_error(i40e, "failed to set rx queue %d context: %d",
2829 2836 itrq->itrq_index, err);
2830 2837 return (B_FALSE);
2831 2838 }
2832 2839
2833 2840 return (B_TRUE);
2834 2841 }
2835 2842
2836 2843 /*
2837 2844 * Take care of setting up the descriptor ring and actually programming the
2838 2845 * device. See 8.3.3.1.1 for the full list of steps we need to do to enable the
2839 2846 * rx rings.
2840 2847 */
2841 2848 static boolean_t
2842 2849 i40e_setup_rx_ring(i40e_trqpair_t *itrq)
2843 2850 {
2844 2851 i40e_t *i40e = itrq->itrq_i40e;
2845 2852 i40e_hw_t *hw = &i40e->i40e_hw_space;
2846 2853 i40e_rx_data_t *rxd = itrq->itrq_rxdata;
2847 2854 uint32_t reg;
2848 2855 int i;
2849 2856
2850 2857 /*
2851 2858 * Step 1. Program all receive ring descriptors.
2852 2859 */
2853 2860 i40e_setup_rx_descs(itrq);
2854 2861
2855 2862 /*
2856 2863 * Step 2. Program the queue's FPM/HMC context.
2857 2864 */
2858 2865 if (!i40e_setup_rx_hmc(itrq))
2859 2866 return (B_FALSE);
2860 2867
2861 2868 /*
2862 2869 * Step 3. Clear the queue's tail pointer and set it to the end
2863 2870 * of the space.
2864 2871 */
2865 2872 I40E_WRITE_REG(hw, I40E_QRX_TAIL(itrq->itrq_index), 0);
2866 2873 I40E_WRITE_REG(hw, I40E_QRX_TAIL(itrq->itrq_index),
2867 2874 rxd->rxd_ring_size - 1);
2868 2875
2869 2876 /*
2870 2877 * Step 4. Enable the queue via the QENA_REQ.
2871 2878 */
2872 2879 reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
2873 2880 VERIFY0(reg & (I40E_QRX_ENA_QENA_REQ_MASK |
2874 2881 I40E_QRX_ENA_QENA_STAT_MASK));
2875 2882 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
2876 2883 I40E_WRITE_REG(hw, I40E_QRX_ENA(itrq->itrq_index), reg);
2877 2884
2878 2885 /*
2879 2886 * Step 5. Verify that QENA_STAT has been set. It's promised
2880 2887 * that this should occur within about 10 us, but like other
2881 2888 * systems, we give the card a bit more time.
2882 2889 */
2883 2890 for (i = 0; i < I40E_RING_WAIT_NTRIES; i++) {
2884 2891 reg = I40E_READ_REG(hw, I40E_QRX_ENA(itrq->itrq_index));
2885 2892
2886 2893 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
2887 2894 break;
2888 2895 i40e_msec_delay(I40E_RING_WAIT_PAUSE);
2889 2896 }
2890 2897
2891 2898 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) {
2892 2899 i40e_error(i40e, "failed to enable rx queue %d, timed "
2893 2900 "out.", itrq->itrq_index);
2894 2901 return (B_FALSE);
2895 2902 }
2896 2903
2897 2904 return (B_TRUE);
2898 2905 }
2899 2906
2900 2907 static boolean_t
2901 2908 i40e_setup_tx_hmc(i40e_trqpair_t *itrq)
2902 2909 {
2903 2910 i40e_t *i40e = itrq->itrq_i40e;
2904 2911 i40e_hw_t *hw = &i40e->i40e_hw_space;
2905 2912
2906 2913 struct i40e_hmc_obj_txq tctx;
2907 2914 struct i40e_vsi_context context;
2908 2915 int err;
2909 2916
2910 2917 bzero(&tctx, sizeof (struct i40e_hmc_obj_txq));
2911 2918 tctx.new_context = I40E_HMC_TX_NEW_CONTEXT;
2912 2919 tctx.base = itrq->itrq_desc_area.dmab_dma_address /
2913 2920 I40E_HMC_TX_CTX_UNIT;
2914 2921 tctx.fc_ena = I40E_HMC_TX_FC_DISABLE;
2915 2922 tctx.timesync_ena = I40E_HMC_TX_TS_DISABLE;
2916 2923 tctx.fd_ena = I40E_HMC_TX_FD_DISABLE;
2917 2924 tctx.alt_vlan_ena = I40E_HMC_TX_ALT_VLAN_DISABLE;
2918 2925 tctx.head_wb_ena = I40E_HMC_TX_WB_ENABLE;
2919 2926 tctx.qlen = itrq->itrq_tx_ring_size;
2920 2927 tctx.tphrdesc_ena = I40E_HMC_TX_TPH_DISABLE;
2921 2928 tctx.tphrpacket_ena = I40E_HMC_TX_TPH_DISABLE;
2922 2929 tctx.tphwdesc_ena = I40E_HMC_TX_TPH_DISABLE;
2923 2930 tctx.head_wb_addr = itrq->itrq_desc_area.dmab_dma_address +
2924 2931 sizeof (i40e_tx_desc_t) * itrq->itrq_tx_ring_size;
2925 2932
2926 2933 /*
2927 2934 * This field isn't actually documented, like crc, but it suggests that
2928 2935 * it should be zeroed. We leave both of these here because of that for
2929 2936 * now. We should check with Intel on why these are here even.
2930 2937 */
2931 2938 tctx.crc = 0;
2932 2939 tctx.rdylist_act = 0;
2933 2940
2934 2941 /*
2935 2942 * We're supposed to assign the rdylist field with the value of the
2936 2943 * traffic class index for the first device. We query the VSI parameters
2937 2944 * again to get what the handle is. Note that every queue is always
2938 2945 * assigned to traffic class zero, because we don't actually use them.
2939 2946 */
2940 2947 bzero(&context, sizeof (struct i40e_vsi_context));
2941 2948 context.seid = I40E_DEF_VSI_SEID(i40e);
2942 2949 context.pf_num = hw->pf_id;
2943 2950 err = i40e_aq_get_vsi_params(hw, &context, NULL);
2944 2951 if (err != I40E_SUCCESS) {
2945 2952 i40e_error(i40e, "get VSI params failed with %d", err);
2946 2953 return (B_FALSE);
2947 2954 }
2948 2955 tctx.rdylist = LE_16(context.info.qs_handle[0]);
2949 2956
2950 2957 err = i40e_clear_lan_tx_queue_context(hw, itrq->itrq_index);
2951 2958 if (err != I40E_SUCCESS) {
2952 2959 i40e_error(i40e, "failed to clear tx queue %d context: %d",
2953 2960 itrq->itrq_index, err);
2954 2961 return (B_FALSE);
2955 2962 }
2956 2963
2957 2964 err = i40e_set_lan_tx_queue_context(hw, itrq->itrq_index, &tctx);
2958 2965 if (err != I40E_SUCCESS) {
2959 2966 i40e_error(i40e, "failed to set tx queue %d context: %d",
2960 2967 itrq->itrq_index, err);
2961 2968 return (B_FALSE);
2962 2969 }
2963 2970
2964 2971 return (B_TRUE);
2965 2972 }
2966 2973
2967 2974 /*
2968 2975 * Take care of setting up the descriptor ring and actually programming the
2969 2976 * device. See 8.4.3.1.1 for what we need to do here.
2970 2977 */
2971 2978 static boolean_t
2972 2979 i40e_setup_tx_ring(i40e_trqpair_t *itrq)
2973 2980 {
2974 2981 i40e_t *i40e = itrq->itrq_i40e;
2975 2982 i40e_hw_t *hw = &i40e->i40e_hw_space;
2976 2983 uint32_t reg;
2977 2984 int i;
2978 2985
2979 2986 /*
2980 2987 * Step 1. Clear the queue disable flag and verify that the
2981 2988 * index is set correctly.
2982 2989 */
2983 2990 i40e_pre_tx_queue_cfg(hw, itrq->itrq_index, B_TRUE);
2984 2991
2985 2992 /*
2986 2993 * Step 2. Prepare the queue's FPM/HMC context.
2987 2994 */
2988 2995 if (!i40e_setup_tx_hmc(itrq))
2989 2996 return (B_FALSE);
2990 2997
2991 2998 /*
2992 2999 * Step 3. Verify that it's clear that this PF owns this queue.
2993 3000 */
2994 3001 reg = I40E_QTX_CTL_PF_QUEUE;
2995 3002 reg |= (hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2996 3003 I40E_QTX_CTL_PF_INDX_MASK;
2997 3004 I40E_WRITE_REG(hw, I40E_QTX_CTL(itrq->itrq_index), reg);
2998 3005 i40e_flush(hw);
2999 3006
3000 3007 /*
3001 3008 * Step 4. Set the QENA_REQ flag.
3002 3009 */
3003 3010 reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
3004 3011 VERIFY0(reg & (I40E_QTX_ENA_QENA_REQ_MASK |
3005 3012 I40E_QTX_ENA_QENA_STAT_MASK));
3006 3013 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3007 3014 I40E_WRITE_REG(hw, I40E_QTX_ENA(itrq->itrq_index), reg);
3008 3015
3009 3016 /*
3010 3017 * Step 5. Verify that QENA_STAT has been set. It's promised
3011 3018 * that this should occur within about 10 us, but like BSD,
3012 3019 * we'll try for up to 100 ms for this queue.
3013 3020 */
3014 3021 for (i = 0; i < I40E_RING_WAIT_NTRIES; i++) {
3015 3022 reg = I40E_READ_REG(hw, I40E_QTX_ENA(itrq->itrq_index));
3016 3023
3017 3024 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3018 3025 break;
3019 3026 i40e_msec_delay(I40E_RING_WAIT_PAUSE);
3020 3027 }
3021 3028
3022 3029 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) {
3023 3030 i40e_error(i40e, "failed to enable tx queue %d, timed "
3024 3031 "out", itrq->itrq_index);
3025 3032 return (B_FALSE);
3026 3033 }
3027 3034
3028 3035 return (B_TRUE);
3029 3036 }
3030 3037
3031 3038 int
3032 3039 i40e_setup_ring(i40e_trqpair_t *itrq)
3033 3040 {
3034 3041 i40e_t *i40e = itrq->itrq_i40e;
3035 3042 hrtime_t now, gap;
3036 3043
3037 3044 if (!i40e_alloc_ring_mem(itrq)) {
3038 3045 i40e_error(i40e, "Failed to allocate ring memory");
3039 3046 return (ENOMEM);
3040 3047 }
3041 3048
3042 3049 /*
3043 3050 * 8.3.3.1.1 Receive Queue Enable Flow states software should
3044 3051 * wait at least 50ms between ring disable and enable. See how
3045 3052 * long we need to wait, and wait only if required.
3046 3053 */
3047 3054 now = gethrtime();
3048 3055 gap = NSEC2MSEC(now - itrq->irtq_time_stopped);
3049 3056 if (gap < I40E_RING_ENABLE_GAP && gap != 0)
3050 3057 delay(drv_usectohz(gap * 1000));
3051 3058
3052 3059 mutex_enter(&itrq->itrq_intr_lock);
3053 3060 if (!i40e_setup_rx_ring(itrq))
3054 3061 goto failed;
3055 3062
3056 3063 if (!i40e_setup_tx_ring(itrq))
3057 3064 goto failed;
3058 3065
3059 3066 if (i40e_check_acc_handle(i40e->i40e_osdep_space.ios_reg_handle) !=
3060 3067 DDI_FM_OK)
3061 3068 goto failed;
3062 3069
3063 3070 itrq->itrq_intr_quiesce = B_FALSE;
3064 3071 mutex_exit(&itrq->itrq_intr_lock);
3065 3072
3066 3073 mutex_enter(&itrq->itrq_tx_lock);
3067 3074 itrq->itrq_tx_quiesce = B_FALSE;
3068 3075 mutex_exit(&itrq->itrq_tx_lock);
3069 3076
3070 3077 return (0);
3071 3078
3072 3079 failed:
3073 3080 mutex_exit(&itrq->itrq_intr_lock);
3074 3081 i40e_free_ring_mem(itrq, B_TRUE);
3075 3082 ddi_fm_service_impact(i40e->i40e_dip, DDI_SERVICE_LOST);
3076 3083
3077 3084 return (EIO);
3078 3085 }
3079 3086
3080 3087 void
3081 3088 i40e_stop(i40e_t *i40e)
3082 3089 {
3083 3090 uint_t i;
3084 3091 i40e_hw_t *hw = &i40e->i40e_hw_space;
3085 3092
3086 3093 ASSERT(MUTEX_HELD(&i40e->i40e_general_lock));
3087 3094
3088 3095 /*
3089 3096 * Shutdown and drain the tx and rx pipeline. We do this using the
3090 3097 * following steps.
3091 3098 *
3092 3099 * 1) Shutdown interrupts to all the queues (trying to keep the admin
3093 3100 * queue alive).
3094 3101 *
3095 3102 * 2) Remove all of the interrupt tx and rx causes by setting the
3096 3103 * interrupt linked lists to zero.
3097 3104 *
3098 3105 * 2) Shutdown the tx and rx rings. Because i40e_shutdown_rings() should
3099 3106 * wait for all the queues to be disabled, once we reach that point
3100 3107 * it should be safe to free associated data.
3101 3108 *
3102 3109 * 4) Wait 50ms after all that is done. This ensures that the rings are
3103 3110 * ready for programming again and we don't have to think about this
3104 3111 * in other parts of the driver.
3105 3112 *
3106 3113 * 5) Disable remaining chip interrupts, (admin queue, etc.)
3107 3114 *
3108 3115 * 6) Verify that FM is happy with all the register accesses we
3109 3116 * performed.
3110 3117 */
3111 3118 i40e_intr_io_disable_all(i40e);
3112 3119 i40e_intr_io_clear_cause(i40e);
3113 3120
3114 3121 if (!i40e_shutdown_rings(i40e))
3115 3122 ddi_fm_service_impact(i40e->i40e_dip, DDI_SERVICE_LOST);
3116 3123
3117 3124 /*
3118 3125 * We don't delete the default VSI because it replaces the VEB
3119 3126 * after VEB deletion (see the "Delete Element" section).
3120 3127 * Furthermore, since the default VSI is provided by the
3121 3128 * firmware, we never attempt to delete it.
3122 3129 */
3123 3130 for (i = 1; i < i40e->i40e_num_rx_groups; i++) {
3124 3131 i40e_delete_vsi(i40e, i);
3125 3132 }
3126 3133
3127 3134 if (i40e->i40e_veb_seid != 0) {
3128 3135 int rc = i40e_aq_delete_element(hw, i40e->i40e_veb_seid, NULL);
3129 3136
3130 3137 if (rc != I40E_SUCCESS) {
3131 3138 i40e_error(i40e, "Failed to delete VEB %d: %d", rc,
3132 3139 hw->aq.asq_last_status);
3133 3140 }
3134 3141
3135 3142 i40e->i40e_veb_seid = 0;
3136 3143 }
3137 3144
3138 3145 i40e_intr_chip_fini(i40e);
3139 3146
3140 3147 if (i40e_check_acc_handle(i40e->i40e_osdep_space.ios_cfg_handle) !=
3141 3148 DDI_FM_OK) {
3142 3149 ddi_fm_service_impact(i40e->i40e_dip, DDI_SERVICE_LOST);
3143 3150 }
3144 3151
3145 3152 for (i = 0; i < i40e->i40e_num_rx_groups; i++) {
3146 3153 i40e_stat_vsi_fini(i40e, i);
3147 3154 }
3148 3155
3149 3156 i40e->i40e_link_speed = 0;
3150 3157 i40e->i40e_link_duplex = 0;
3151 3158 i40e_link_state_set(i40e, LINK_STATE_UNKNOWN);
3152 3159 }
3153 3160
3154 3161 boolean_t
3155 3162 i40e_start(i40e_t *i40e)
3156 3163 {
3157 3164 i40e_hw_t *hw = &i40e->i40e_hw_space;
3158 3165 boolean_t rc = B_TRUE;
3159 3166 int err;
3160 3167
3161 3168 ASSERT(MUTEX_HELD(&i40e->i40e_general_lock));
3162 3169
3163 3170 if (!i40e_chip_start(i40e)) {
3164 3171 i40e_fm_ereport(i40e, DDI_FM_DEVICE_INVAL_STATE);
3165 3172 rc = B_FALSE;
3166 3173 goto done;
3167 3174 }
3168 3175
3169 3176 /*
3170 3177 * Enable broadcast traffic; however, do not enable multicast traffic.
|
↓ open down ↓ |
1810 lines elided |
↑ open up ↑ |
3171 3178 * That's handle exclusively through MAC's mc_multicst routines.
3172 3179 */
3173 3180 err = i40e_aq_set_vsi_broadcast(hw, I40E_DEF_VSI_SEID(i40e), B_TRUE,
3174 3181 NULL);
3175 3182 if (err != I40E_SUCCESS) {
3176 3183 i40e_error(i40e, "failed to set default VSI: %d", err);
3177 3184 rc = B_FALSE;
3178 3185 goto done;
3179 3186 }
3180 3187
3181 - err = i40e_aq_set_mac_config(hw, i40e->i40e_frame_max, B_TRUE, 0, NULL);
3188 + err = i40e_aq_set_mac_config(hw, i40e->i40e_frame_max, B_TRUE, 0,
3189 + B_FALSE, NULL);
3182 3190 if (err != I40E_SUCCESS) {
3183 3191 i40e_error(i40e, "failed to set MAC config: %d", err);
3184 3192 rc = B_FALSE;
3185 3193 goto done;
3186 3194 }
3187 3195
3188 3196 /*
3189 3197 * Finally, make sure that we're happy from an FM perspective.
3190 3198 */
3191 3199 if (i40e_check_acc_handle(i40e->i40e_osdep_space.ios_reg_handle) !=
3192 3200 DDI_FM_OK) {
3193 3201 rc = B_FALSE;
3194 3202 goto done;
3195 3203 }
3196 3204
3197 3205 /* Clear state bits prior to final interrupt enabling. */
3198 3206 atomic_and_32(&i40e->i40e_state,
3199 3207 ~(I40E_ERROR | I40E_STALL | I40E_OVERTEMP));
3200 3208
3201 3209 i40e_intr_io_enable_all(i40e);
3202 3210
3203 3211 done:
3204 3212 if (rc == B_FALSE) {
3205 3213 i40e_stop(i40e);
3206 3214 ddi_fm_service_impact(i40e->i40e_dip, DDI_SERVICE_LOST);
3207 3215 }
3208 3216
3209 3217 return (rc);
3210 3218 }
3211 3219
3212 3220 /*
3213 3221 * We may have loaned up descriptors to the stack. As such, if we still have
3214 3222 * them outstanding, then we will not continue with detach.
3215 3223 */
3216 3224 static boolean_t
3217 3225 i40e_drain_rx(i40e_t *i40e)
3218 3226 {
3219 3227 mutex_enter(&i40e->i40e_rx_pending_lock);
3220 3228 while (i40e->i40e_rx_pending > 0) {
3221 3229 if (cv_reltimedwait(&i40e->i40e_rx_pending_cv,
3222 3230 &i40e->i40e_rx_pending_lock,
3223 3231 drv_usectohz(I40E_DRAIN_RX_WAIT), TR_CLOCK_TICK) == -1) {
3224 3232 mutex_exit(&i40e->i40e_rx_pending_lock);
3225 3233 return (B_FALSE);
3226 3234 }
3227 3235 }
3228 3236 mutex_exit(&i40e->i40e_rx_pending_lock);
3229 3237
3230 3238 return (B_TRUE);
3231 3239 }
3232 3240
3233 3241 /*
3234 3242 * DDI UFM Callbacks
3235 3243 */
3236 3244 static int
3237 3245 i40e_ufm_fill_image(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno,
3238 3246 ddi_ufm_image_t *img)
3239 3247 {
3240 3248 if (imgno != 0)
3241 3249 return (EINVAL);
3242 3250
3243 3251 ddi_ufm_image_set_desc(img, "Firmware");
3244 3252 ddi_ufm_image_set_nslots(img, 1);
3245 3253
3246 3254 return (0);
3247 3255 }
3248 3256
3249 3257 static int
3250 3258 i40e_ufm_fill_slot(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno,
3251 3259 uint_t slotno, ddi_ufm_slot_t *slot)
3252 3260 {
3253 3261 i40e_t *i40e = (i40e_t *)arg;
3254 3262 char *fw_ver = NULL, *fw_bld = NULL, *api_ver = NULL;
3255 3263 nvlist_t *misc = NULL;
3256 3264 uint_t flags = DDI_PROP_DONTPASS;
3257 3265 int err;
3258 3266
3259 3267 if (imgno != 0 || slotno != 0 ||
3260 3268 ddi_prop_lookup_string(DDI_DEV_T_ANY, i40e->i40e_dip, flags,
3261 3269 "firmware-version", &fw_ver) != DDI_PROP_SUCCESS ||
3262 3270 ddi_prop_lookup_string(DDI_DEV_T_ANY, i40e->i40e_dip, flags,
3263 3271 "firmware-build", &fw_bld) != DDI_PROP_SUCCESS ||
3264 3272 ddi_prop_lookup_string(DDI_DEV_T_ANY, i40e->i40e_dip, flags,
3265 3273 "api-version", &api_ver) != DDI_PROP_SUCCESS) {
3266 3274 err = EINVAL;
3267 3275 goto err;
3268 3276 }
3269 3277
3270 3278 ddi_ufm_slot_set_attrs(slot, DDI_UFM_ATTR_ACTIVE);
3271 3279 ddi_ufm_slot_set_version(slot, fw_ver);
3272 3280
3273 3281 (void) nvlist_alloc(&misc, NV_UNIQUE_NAME, KM_SLEEP);
3274 3282 if ((err = nvlist_add_string(misc, "firmware-build", fw_bld)) != 0 ||
3275 3283 (err = nvlist_add_string(misc, "api-version", api_ver)) != 0) {
3276 3284 goto err;
3277 3285 }
3278 3286 ddi_ufm_slot_set_misc(slot, misc);
3279 3287
3280 3288 ddi_prop_free(fw_ver);
3281 3289 ddi_prop_free(fw_bld);
3282 3290 ddi_prop_free(api_ver);
3283 3291
3284 3292 return (0);
3285 3293 err:
3286 3294 nvlist_free(misc);
3287 3295 if (fw_ver != NULL)
3288 3296 ddi_prop_free(fw_ver);
3289 3297 if (fw_bld != NULL)
3290 3298 ddi_prop_free(fw_bld);
3291 3299 if (api_ver != NULL)
3292 3300 ddi_prop_free(api_ver);
3293 3301
3294 3302 return (err);
3295 3303 }
3296 3304
3297 3305 static int
3298 3306 i40e_ufm_getcaps(ddi_ufm_handle_t *ufmh, void *arg, ddi_ufm_cap_t *caps)
3299 3307 {
3300 3308 *caps = DDI_UFM_CAP_REPORT;
3301 3309
3302 3310 return (0);
3303 3311 }
3304 3312
3305 3313 static ddi_ufm_ops_t i40e_ufm_ops = {
3306 3314 NULL,
3307 3315 i40e_ufm_fill_image,
3308 3316 i40e_ufm_fill_slot,
3309 3317 i40e_ufm_getcaps
3310 3318 };
3311 3319
3312 3320 static int
3313 3321 i40e_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
3314 3322 {
3315 3323 i40e_t *i40e;
3316 3324 struct i40e_osdep *osdep;
3317 3325 i40e_hw_t *hw;
3318 3326 int instance;
3319 3327
3320 3328 if (cmd != DDI_ATTACH)
3321 3329 return (DDI_FAILURE);
3322 3330
3323 3331 instance = ddi_get_instance(devinfo);
3324 3332 i40e = kmem_zalloc(sizeof (i40e_t), KM_SLEEP);
3325 3333
3326 3334 i40e->i40e_aqbuf = kmem_zalloc(I40E_ADMINQ_BUFSZ, KM_SLEEP);
3327 3335 i40e->i40e_instance = instance;
3328 3336 i40e->i40e_dip = devinfo;
3329 3337
3330 3338 hw = &i40e->i40e_hw_space;
3331 3339 osdep = &i40e->i40e_osdep_space;
3332 3340 hw->back = osdep;
3333 3341 osdep->ios_i40e = i40e;
3334 3342
3335 3343 ddi_set_driver_private(devinfo, i40e);
3336 3344
3337 3345 i40e_fm_init(i40e);
3338 3346 i40e->i40e_attach_progress |= I40E_ATTACH_FM_INIT;
3339 3347
3340 3348 if (pci_config_setup(devinfo, &osdep->ios_cfg_handle) != DDI_SUCCESS) {
3341 3349 i40e_error(i40e, "Failed to map PCI configurations.");
3342 3350 goto attach_fail;
3343 3351 }
3344 3352 i40e->i40e_attach_progress |= I40E_ATTACH_PCI_CONFIG;
3345 3353
3346 3354 i40e_identify_hardware(i40e);
3347 3355
3348 3356 if (!i40e_regs_map(i40e)) {
3349 3357 i40e_error(i40e, "Failed to map device registers.");
3350 3358 goto attach_fail;
3351 3359 }
3352 3360 i40e->i40e_attach_progress |= I40E_ATTACH_REGS_MAP;
3353 3361
3354 3362 i40e_init_properties(i40e);
3355 3363 i40e->i40e_attach_progress |= I40E_ATTACH_PROPS;
3356 3364
3357 3365 if (!i40e_common_code_init(i40e, hw))
3358 3366 goto attach_fail;
3359 3367 i40e->i40e_attach_progress |= I40E_ATTACH_COMMON_CODE;
3360 3368
3361 3369 /*
3362 3370 * When we participate in IRM, we should make sure that we register
3363 3371 * ourselves with it before callbacks.
3364 3372 */
3365 3373 if (!i40e_alloc_intrs(i40e, devinfo)) {
3366 3374 i40e_error(i40e, "Failed to allocate interrupts.");
3367 3375 goto attach_fail;
3368 3376 }
3369 3377 i40e->i40e_attach_progress |= I40E_ATTACH_ALLOC_INTR;
3370 3378
3371 3379 if (!i40e_alloc_trqpairs(i40e)) {
3372 3380 i40e_error(i40e,
3373 3381 "Failed to allocate receive & transmit rings.");
3374 3382 goto attach_fail;
3375 3383 }
3376 3384 i40e->i40e_attach_progress |= I40E_ATTACH_ALLOC_RINGSLOCKS;
3377 3385
3378 3386 if (!i40e_map_intrs_to_vectors(i40e)) {
3379 3387 i40e_error(i40e, "Failed to map interrupts to vectors.");
3380 3388 goto attach_fail;
3381 3389 }
3382 3390
3383 3391 if (!i40e_add_intr_handlers(i40e)) {
3384 3392 i40e_error(i40e, "Failed to add the interrupt handlers.");
3385 3393 goto attach_fail;
3386 3394 }
3387 3395 i40e->i40e_attach_progress |= I40E_ATTACH_ADD_INTR;
3388 3396
3389 3397 if (!i40e_final_init(i40e)) {
3390 3398 i40e_error(i40e, "Final initialization failed.");
3391 3399 goto attach_fail;
3392 3400 }
3393 3401 i40e->i40e_attach_progress |= I40E_ATTACH_INIT;
3394 3402
3395 3403 if (i40e_check_acc_handle(i40e->i40e_osdep_space.ios_cfg_handle) !=
3396 3404 DDI_FM_OK) {
3397 3405 ddi_fm_service_impact(i40e->i40e_dip, DDI_SERVICE_LOST);
3398 3406 goto attach_fail;
3399 3407 }
3400 3408
3401 3409 if (!i40e_stats_init(i40e)) {
3402 3410 i40e_error(i40e, "Stats initialization failed.");
3403 3411 goto attach_fail;
3404 3412 }
3405 3413 i40e->i40e_attach_progress |= I40E_ATTACH_STATS;
3406 3414
3407 3415 if (!i40e_register_mac(i40e)) {
3408 3416 i40e_error(i40e, "Failed to register to MAC/GLDv3");
3409 3417 goto attach_fail;
3410 3418 }
3411 3419 i40e->i40e_attach_progress |= I40E_ATTACH_MAC;
3412 3420
3413 3421 i40e->i40e_periodic_id = ddi_periodic_add(i40e_timer, i40e,
3414 3422 I40E_CYCLIC_PERIOD, DDI_IPL_0);
3415 3423 if (i40e->i40e_periodic_id == 0) {
3416 3424 i40e_error(i40e, "Failed to add the link-check timer");
3417 3425 goto attach_fail;
3418 3426 }
3419 3427 i40e->i40e_attach_progress |= I40E_ATTACH_LINK_TIMER;
3420 3428
3421 3429 if (!i40e_enable_interrupts(i40e)) {
3422 3430 i40e_error(i40e, "Failed to enable DDI interrupts");
3423 3431 goto attach_fail;
3424 3432 }
3425 3433 i40e->i40e_attach_progress |= I40E_ATTACH_ENABLE_INTR;
3426 3434
3427 3435 if (i40e->i40e_hw_space.bus.func == 0) {
3428 3436 if (ddi_ufm_init(i40e->i40e_dip, DDI_UFM_CURRENT_VERSION,
3429 3437 &i40e_ufm_ops, &i40e->i40e_ufmh, i40e) != 0) {
3430 3438 i40e_error(i40e, "failed to initialize UFM subsystem");
3431 3439 goto attach_fail;
3432 3440 }
3433 3441 ddi_ufm_update(i40e->i40e_ufmh);
3434 3442 i40e->i40e_attach_progress |= I40E_ATTACH_UFM_INIT;
3435 3443 }
3436 3444
3437 3445 atomic_or_32(&i40e->i40e_state, I40E_INITIALIZED);
3438 3446
3439 3447 mutex_enter(&i40e_glock);
3440 3448 list_insert_tail(&i40e_glist, i40e);
3441 3449 mutex_exit(&i40e_glock);
3442 3450
3443 3451 return (DDI_SUCCESS);
3444 3452
3445 3453 attach_fail:
3446 3454 i40e_unconfigure(devinfo, i40e);
3447 3455 return (DDI_FAILURE);
3448 3456 }
3449 3457
3450 3458 static int
3451 3459 i40e_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
3452 3460 {
3453 3461 i40e_t *i40e;
3454 3462
3455 3463 if (cmd != DDI_DETACH)
3456 3464 return (DDI_FAILURE);
3457 3465
3458 3466 i40e = (i40e_t *)ddi_get_driver_private(devinfo);
3459 3467 if (i40e == NULL) {
3460 3468 i40e_log(NULL, "i40e_detach() called with no i40e pointer!");
3461 3469 return (DDI_FAILURE);
3462 3470 }
3463 3471
3464 3472 if (i40e_drain_rx(i40e) == B_FALSE) {
3465 3473 i40e_log(i40e, "timed out draining DMA resources, %d buffers "
3466 3474 "remain", i40e->i40e_rx_pending);
3467 3475 return (DDI_FAILURE);
3468 3476 }
3469 3477
3470 3478 mutex_enter(&i40e_glock);
3471 3479 list_remove(&i40e_glist, i40e);
3472 3480 mutex_exit(&i40e_glock);
3473 3481
3474 3482 i40e_unconfigure(devinfo, i40e);
3475 3483
3476 3484 return (DDI_SUCCESS);
3477 3485 }
3478 3486
3479 3487 static struct cb_ops i40e_cb_ops = {
3480 3488 nulldev, /* cb_open */
3481 3489 nulldev, /* cb_close */
3482 3490 nodev, /* cb_strategy */
3483 3491 nodev, /* cb_print */
3484 3492 nodev, /* cb_dump */
3485 3493 nodev, /* cb_read */
3486 3494 nodev, /* cb_write */
3487 3495 nodev, /* cb_ioctl */
3488 3496 nodev, /* cb_devmap */
3489 3497 nodev, /* cb_mmap */
3490 3498 nodev, /* cb_segmap */
3491 3499 nochpoll, /* cb_chpoll */
3492 3500 ddi_prop_op, /* cb_prop_op */
3493 3501 NULL, /* cb_stream */
3494 3502 D_MP | D_HOTPLUG, /* cb_flag */
3495 3503 CB_REV, /* cb_rev */
3496 3504 nodev, /* cb_aread */
3497 3505 nodev /* cb_awrite */
3498 3506 };
3499 3507
3500 3508 static struct dev_ops i40e_dev_ops = {
3501 3509 DEVO_REV, /* devo_rev */
3502 3510 0, /* devo_refcnt */
3503 3511 NULL, /* devo_getinfo */
3504 3512 nulldev, /* devo_identify */
3505 3513 nulldev, /* devo_probe */
3506 3514 i40e_attach, /* devo_attach */
3507 3515 i40e_detach, /* devo_detach */
3508 3516 nodev, /* devo_reset */
3509 3517 &i40e_cb_ops, /* devo_cb_ops */
3510 3518 NULL, /* devo_bus_ops */
3511 3519 nulldev, /* devo_power */
3512 3520 ddi_quiesce_not_supported /* devo_quiesce */
3513 3521 };
3514 3522
3515 3523 static struct modldrv i40e_modldrv = {
3516 3524 &mod_driverops,
3517 3525 i40e_ident,
3518 3526 &i40e_dev_ops
3519 3527 };
3520 3528
3521 3529 static struct modlinkage i40e_modlinkage = {
3522 3530 MODREV_1,
3523 3531 &i40e_modldrv,
3524 3532 NULL
3525 3533 };
3526 3534
3527 3535 /*
3528 3536 * Module Initialization Functions.
3529 3537 */
3530 3538 int
3531 3539 _init(void)
3532 3540 {
3533 3541 int status;
3534 3542
3535 3543 list_create(&i40e_glist, sizeof (i40e_t), offsetof(i40e_t, i40e_glink));
3536 3544 list_create(&i40e_dlist, sizeof (i40e_device_t),
3537 3545 offsetof(i40e_device_t, id_link));
3538 3546 mutex_init(&i40e_glock, NULL, MUTEX_DRIVER, NULL);
3539 3547 mac_init_ops(&i40e_dev_ops, I40E_MODULE_NAME);
3540 3548
3541 3549 status = mod_install(&i40e_modlinkage);
3542 3550 if (status != DDI_SUCCESS) {
3543 3551 mac_fini_ops(&i40e_dev_ops);
3544 3552 mutex_destroy(&i40e_glock);
3545 3553 list_destroy(&i40e_dlist);
3546 3554 list_destroy(&i40e_glist);
3547 3555 }
3548 3556
3549 3557 return (status);
3550 3558 }
3551 3559
3552 3560 int
3553 3561 _info(struct modinfo *modinfop)
3554 3562 {
3555 3563 return (mod_info(&i40e_modlinkage, modinfop));
3556 3564 }
3557 3565
3558 3566 int
3559 3567 _fini(void)
3560 3568 {
3561 3569 int status;
3562 3570
3563 3571 status = mod_remove(&i40e_modlinkage);
3564 3572 if (status == DDI_SUCCESS) {
3565 3573 mac_fini_ops(&i40e_dev_ops);
3566 3574 mutex_destroy(&i40e_glock);
3567 3575 list_destroy(&i40e_dlist);
3568 3576 list_destroy(&i40e_glist);
3569 3577 }
3570 3578
3571 3579 return (status);
3572 3580 }
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