Print this page
re #13613 rb4516 Tunables needs volatile keyword
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/sun4v/vm/mach_vm_dep.c
+++ new/usr/src/uts/sun4v/vm/mach_vm_dep.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
|
↓ open down ↓ |
14 lines elided |
↑ open up ↑ |
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 +/*
26 + * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
27 + */
25 28
26 29 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
27 30 /* All Rights Reserved */
28 31
29 32 /*
30 33 * Portions of this source code were derived from Berkeley 4.3 BSD
31 34 * under license from the Regents of the University of California.
32 35 */
33 36
34 37 /*
35 38 * UNIX machine dependent virtual memory support.
36 39 */
37 40
38 41 #include <sys/vm.h>
39 42 #include <sys/exec.h>
40 43 #include <sys/cmn_err.h>
41 44 #include <sys/cpu_module.h>
42 45 #include <sys/cpu.h>
43 46 #include <sys/elf_SPARC.h>
44 47 #include <sys/archsystm.h>
45 48 #include <vm/hat_sfmmu.h>
46 49 #include <sys/memnode.h>
47 50 #include <sys/mem_cage.h>
48 51 #include <vm/vm_dep.h>
49 52 #include <sys/error.h>
|
↓ open down ↓ |
15 lines elided |
↑ open up ↑ |
50 53 #include <sys/machsystm.h>
51 54 #include <vm/seg_kmem.h>
52 55 #include <sys/stack.h>
53 56 #include <sys/atomic.h>
54 57 #include <sys/promif.h>
55 58 #include <sys/random.h>
56 59
57 60 uint_t page_colors = 0;
58 61 uint_t page_colors_mask = 0;
59 62 uint_t page_coloring_shift = 0;
60 -int consistent_coloring;
63 +volatile int consistent_coloring;
61 64 int update_proc_pgcolorbase_after_fork = 1;
62 65
63 66 uint_t mmu_page_sizes = MMU_PAGE_SIZES;
64 67 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES;
65 68 uint_t mmu_hashcnt = MAX_HASHCNT;
66 69 uint_t max_mmu_hashcnt = MAX_HASHCNT;
67 70 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE;
68 71
69 72 /*
70 73 * A bitmask of the page sizes supported by hardware based upon szc.
71 74 * The base pagesize (p_szc == 0) must always be supported by the hardware.
72 75 */
73 76 int mmu_exported_pagesize_mask;
74 77 uint_t mmu_exported_page_sizes;
75 78
76 79 uint_t szc_2_userszc[MMU_PAGE_SIZES];
77 80 uint_t userszc_2_szc[MMU_PAGE_SIZES];
78 81
79 82 extern uint_t vac_colors_mask;
80 83 extern int vac_shift;
81 84
82 85 hw_pagesize_t hw_page_array[] = {
83 86 {MMU_PAGESIZE, MMU_PAGESHIFT, 0, MMU_PAGESIZE >> MMU_PAGESHIFT},
84 87 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, 0,
85 88 MMU_PAGESIZE64K >> MMU_PAGESHIFT},
86 89 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 0,
87 90 MMU_PAGESIZE512K >> MMU_PAGESHIFT},
88 91 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, 0, MMU_PAGESIZE4M >> MMU_PAGESHIFT},
89 92 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, 0,
90 93 MMU_PAGESIZE32M >> MMU_PAGESHIFT},
91 94 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 0,
92 95 MMU_PAGESIZE256M >> MMU_PAGESHIFT},
93 96 {0, 0, 0, 0}
94 97 };
95 98
96 99 /*
97 100 * Maximum page size used to map 64-bit memory segment kmem64_base..kmem64_end
98 101 */
99 102 int max_bootlp_tteszc = TTE256M;
100 103
101 104 /*
102 105 * Maximum and default segment size tunables for user heap, stack, private
103 106 * and shared anonymous memory, and user text and initialized data.
104 107 */
105 108 size_t max_uheap_lpsize = MMU_PAGESIZE64K;
106 109 size_t default_uheap_lpsize = MMU_PAGESIZE64K;
107 110 size_t max_ustack_lpsize = MMU_PAGESIZE64K;
108 111 size_t default_ustack_lpsize = MMU_PAGESIZE64K;
109 112 size_t max_privmap_lpsize = MMU_PAGESIZE64K;
110 113 size_t max_uidata_lpsize = MMU_PAGESIZE64K;
111 114 size_t max_utext_lpsize = MMU_PAGESIZE4M;
112 115 size_t max_shm_lpsize = MMU_PAGESIZE4M;
113 116
114 117 /*
115 118 * Contiguous memory allocator data structures and variables.
116 119 *
117 120 * The sun4v kernel must provide a means to allocate physically
118 121 * contiguous, non-relocatable memory. The contig_mem_arena
119 122 * and contig_mem_slab_arena exist for this purpose. Allocations
120 123 * that require physically contiguous non-relocatable memory should
121 124 * be made using contig_mem_alloc() or contig_mem_alloc_align()
122 125 * which return memory from contig_mem_arena or contig_mem_reloc_arena.
123 126 * These arenas import memory from the contig_mem_slab_arena one
124 127 * contiguous chunk at a time.
125 128 *
126 129 * When importing slabs, an attempt is made to allocate a large page
127 130 * to use as backing. As a result of the non-relocatable requirement,
128 131 * slabs are allocated from the kernel cage freelists. If the cage does
129 132 * not contain any free contiguous chunks large enough to satisfy the
130 133 * slab allocation, the slab size will be downsized and the operation
131 134 * retried. Large slab sizes are tried first to minimize cage
132 135 * fragmentation. If the slab allocation is unsuccessful still, the slab
133 136 * is allocated from outside the kernel cage. This is undesirable because,
134 137 * until slabs are freed, it results in non-relocatable chunks scattered
135 138 * throughout physical memory.
136 139 *
137 140 * Allocations from the contig_mem_arena are backed by slabs from the
138 141 * cage. Allocations from the contig_mem_reloc_arena are backed by
139 142 * slabs allocated outside the cage. Slabs are left share locked while
140 143 * in use to prevent non-cage slabs from being relocated.
141 144 *
142 145 * Since there is no guarantee that large pages will be available in
143 146 * the kernel cage, contiguous memory is reserved and added to the
144 147 * contig_mem_arena at boot time, making it available for later
145 148 * contiguous memory allocations. This reserve will be used to satisfy
146 149 * contig_mem allocations first and it is only when the reserve is
147 150 * completely allocated that new slabs will need to be imported.
148 151 */
149 152 static vmem_t *contig_mem_slab_arena;
150 153 static vmem_t *contig_mem_arena;
151 154 static vmem_t *contig_mem_reloc_arena;
152 155 static kmutex_t contig_mem_lock;
153 156 #define CONTIG_MEM_ARENA_QUANTUM 64
154 157 #define CONTIG_MEM_SLAB_ARENA_QUANTUM MMU_PAGESIZE64K
155 158
156 159 /* contig_mem_arena import slab sizes, in decreasing size order */
157 160 static size_t contig_mem_import_sizes[] = {
158 161 MMU_PAGESIZE4M,
159 162 MMU_PAGESIZE512K,
160 163 MMU_PAGESIZE64K
161 164 };
162 165 #define NUM_IMPORT_SIZES \
163 166 (sizeof (contig_mem_import_sizes) / sizeof (size_t))
164 167 static size_t contig_mem_import_size_max = MMU_PAGESIZE4M;
165 168 size_t contig_mem_slab_size = MMU_PAGESIZE4M;
166 169
167 170 /* Boot-time allocated buffer to pre-populate the contig_mem_arena */
168 171 static size_t contig_mem_prealloc_size;
169 172 static void *contig_mem_prealloc_buf;
170 173
171 174 /*
172 175 * The maximum amount a randomized mapping will be slewed. We should perhaps
173 176 * arrange things so these tunables can be separate for mmap, mmapobj, and
174 177 * ld.so
175 178 */
176 179 size_t aslr_max_map_skew = 256 * 1024 * 1024; /* 256MB */
177 180
178 181 /*
179 182 * map_addr_proc() is the routine called when the system is to
180 183 * choose an address for the user. We will pick an address
181 184 * range which is just below the current stack limit. The
182 185 * algorithm used for cache consistency on machines with virtual
183 186 * address caches is such that offset 0 in the vnode is always
184 187 * on a shm_alignment'ed aligned address. Unfortunately, this
185 188 * means that vnodes which are demand paged will not be mapped
186 189 * cache consistently with the executable images. When the
187 190 * cache alignment for a given object is inconsistent, the
188 191 * lower level code must manage the translations so that this
189 192 * is not seen here (at the cost of efficiency, of course).
190 193 *
191 194 * Every mapping will have a redzone of a single page on either side of
192 195 * the request. This is done to leave one page unmapped between segments.
193 196 * This is not required, but it's useful for the user because if their
194 197 * program strays across a segment boundary, it will catch a fault
195 198 * immediately making debugging a little easier. Currently the redzone
196 199 * is mandatory.
197 200 *
198 201 * addrp is a value/result parameter.
199 202 * On input it is a hint from the user to be used in a completely
200 203 * machine dependent fashion. For MAP_ALIGN, addrp contains the
201 204 * minimal alignment, which must be some "power of two" multiple of
202 205 * pagesize.
203 206 *
204 207 * On output it is NULL if no address can be found in the current
205 208 * processes address space or else an address that is currently
206 209 * not mapped for len bytes with a page of red zone on either side.
207 210 * If vacalign is true, then the selected address will obey the alignment
208 211 * constraints of a vac machine based on the given off value.
209 212 */
210 213 /*ARGSUSED3*/
211 214 void
212 215 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign,
213 216 caddr_t userlimit, struct proc *p, uint_t flags)
214 217 {
215 218 struct as *as = p->p_as;
216 219 caddr_t addr;
217 220 caddr_t base;
218 221 size_t slen;
219 222 uintptr_t align_amount;
220 223 int allow_largepage_alignment = 1;
221 224
222 225 base = p->p_brkbase;
223 226 if (userlimit < as->a_userlimit) {
224 227 /*
225 228 * This happens when a program wants to map something in
226 229 * a range that's accessible to a program in a smaller
227 230 * address space. For example, a 64-bit program might
228 231 * be calling mmap32(2) to guarantee that the returned
229 232 * address is below 4Gbytes.
230 233 */
231 234 ASSERT(userlimit > base);
232 235 slen = userlimit - base;
233 236 } else {
234 237 slen = p->p_usrstack - base -
235 238 ((p->p_stk_ctl + PAGEOFFSET) & PAGEMASK);
236 239 }
237 240 /* Make len be a multiple of PAGESIZE */
238 241 len = (len + PAGEOFFSET) & PAGEMASK;
239 242
240 243 /*
241 244 * If the request is larger than the size of a particular
242 245 * mmu level, then we use that level to map the request.
243 246 * But this requires that both the virtual and the physical
244 247 * addresses be aligned with respect to that level, so we
245 248 * do the virtual bit of nastiness here.
246 249 *
247 250 * For 32-bit processes, only those which have specified
248 251 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise
249 252 * we can potentially waste up to 256MB of the 4G process address
250 253 * space just for alignment.
251 254 *
252 255 * XXXQ Should iterate trough hw_page_array here to catch
253 256 * all supported pagesizes
254 257 */
255 258 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 ||
256 259 ((uintptr_t)*addrp) != 0)) {
257 260 allow_largepage_alignment = 0;
258 261 }
259 262 if ((mmu_page_sizes == max_mmu_page_sizes) &&
260 263 allow_largepage_alignment &&
261 264 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */
262 265 align_amount = MMU_PAGESIZE256M;
263 266 } else if ((mmu_page_sizes == max_mmu_page_sizes) &&
264 267 allow_largepage_alignment &&
265 268 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */
266 269 align_amount = MMU_PAGESIZE32M;
267 270 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */
268 271 align_amount = MMU_PAGESIZE4M;
269 272 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */
270 273 align_amount = MMU_PAGESIZE512K;
271 274 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */
272 275 align_amount = MMU_PAGESIZE64K;
273 276 } else {
274 277 /*
275 278 * Align virtual addresses on a 64K boundary to ensure
276 279 * that ELF shared libraries are mapped with the appropriate
277 280 * alignment constraints by the run-time linker.
278 281 */
279 282 align_amount = ELF_SPARC_MAXPGSZ;
280 283 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) &&
281 284 ((uintptr_t)*addrp < align_amount))
282 285 align_amount = (uintptr_t)*addrp;
283 286 }
284 287
285 288 /*
286 289 * 64-bit processes require 1024K alignment of ELF shared libraries.
287 290 */
288 291 if (p->p_model == DATAMODEL_LP64)
289 292 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ);
290 293 #ifdef VAC
291 294 if (vac && vacalign && (align_amount < shm_alignment))
292 295 align_amount = shm_alignment;
293 296 #endif
294 297
295 298 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) {
296 299 align_amount = (uintptr_t)*addrp;
297 300 }
298 301
299 302 ASSERT(ISP2(align_amount));
300 303 ASSERT(align_amount == 0 || align_amount >= PAGESIZE);
301 304
302 305 /*
303 306 * Look for a large enough hole starting below the stack limit.
304 307 * After finding it, use the upper part.
305 308 */
306 309 as_purge(as);
307 310 off = off & (align_amount - 1);
308 311 if (as_gap_aligned(as, len, &base, &slen, AH_HI, NULL, align_amount,
309 312 PAGESIZE, off) == 0) {
310 313 caddr_t as_addr;
311 314
312 315 /*
313 316 * addr is the highest possible address to use since we have
314 317 * a PAGESIZE redzone at the beginning and end.
315 318 */
316 319 addr = base + slen - (PAGESIZE + len);
317 320 as_addr = addr;
318 321 /*
319 322 * Round address DOWN to the alignment amount and
320 323 * add the offset in.
321 324 * If addr is greater than as_addr, len would not be large
322 325 * enough to include the redzone, so we must adjust down
323 326 * by the alignment amount.
324 327 */
325 328 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l)));
326 329 addr += (long)off;
327 330 if (addr > as_addr) {
328 331 addr -= align_amount;
329 332 }
330 333
331 334 /*
332 335 * If randomization is requested, slew the allocation
333 336 * backwards, within the same gap, by a random amount.
334 337 */
335 338 if (flags & _MAP_RANDOMIZE) {
336 339 uint32_t slew;
337 340
338 341 (void) random_get_pseudo_bytes((uint8_t *)&slew,
339 342 sizeof (slew));
340 343
341 344 slew = slew % MIN(aslr_max_map_skew, (addr - base));
342 345 addr -= P2ALIGN(slew, align_amount);
343 346 }
344 347
345 348 ASSERT(addr > base);
346 349 ASSERT(addr + len < base + slen);
347 350 ASSERT(((uintptr_t)addr & (align_amount - 1l)) ==
348 351 ((uintptr_t)(off)));
349 352 *addrp = addr;
350 353
351 354 } else {
352 355 *addrp = NULL; /* no more virtual space */
353 356 }
354 357 }
355 358
356 359 /*
357 360 * Platform-dependent page scrub call.
358 361 * We call hypervisor to scrub the page.
359 362 */
360 363 void
361 364 pagescrub(page_t *pp, uint_t off, uint_t len)
362 365 {
363 366 uint64_t pa, length;
364 367
365 368 pa = (uint64_t)(pp->p_pagenum << MMU_PAGESHIFT + off);
366 369 length = (uint64_t)len;
367 370
368 371 (void) mem_scrub(pa, length);
369 372 }
370 373
371 374 void
372 375 sync_data_memory(caddr_t va, size_t len)
373 376 {
374 377 /* Call memory sync function */
375 378 (void) mem_sync(va, len);
376 379 }
377 380
378 381 size_t
379 382 mmu_get_kernel_lpsize(size_t lpsize)
380 383 {
381 384 extern int mmu_exported_pagesize_mask;
382 385 uint_t tte;
383 386
384 387 if (lpsize == 0) {
385 388 /* no setting for segkmem_lpsize in /etc/system: use default */
386 389 if (mmu_exported_pagesize_mask & (1 << TTE256M)) {
387 390 lpsize = MMU_PAGESIZE256M;
388 391 } else if (mmu_exported_pagesize_mask & (1 << TTE4M)) {
389 392 lpsize = MMU_PAGESIZE4M;
390 393 } else if (mmu_exported_pagesize_mask & (1 << TTE64K)) {
391 394 lpsize = MMU_PAGESIZE64K;
392 395 } else {
393 396 lpsize = MMU_PAGESIZE;
394 397 }
395 398
396 399 return (lpsize);
397 400 }
398 401
399 402 for (tte = TTE8K; tte <= TTE256M; tte++) {
400 403
401 404 if ((mmu_exported_pagesize_mask & (1 << tte)) == 0)
402 405 continue;
403 406
404 407 if (lpsize == TTEBYTES(tte))
405 408 return (lpsize);
406 409 }
407 410
408 411 lpsize = TTEBYTES(TTE8K);
409 412 return (lpsize);
410 413 }
411 414
412 415 void
413 416 mmu_init_kcontext()
414 417 {
415 418 }
416 419
417 420 /*ARGSUSED*/
418 421 void
419 422 mmu_init_kernel_pgsz(struct hat *hat)
420 423 {
421 424 }
422 425
423 426 static void *
424 427 contig_mem_span_alloc(vmem_t *vmp, size_t size, int vmflag)
425 428 {
426 429 page_t *ppl;
427 430 page_t *rootpp;
428 431 caddr_t addr = NULL;
429 432 pgcnt_t npages = btopr(size);
430 433 page_t **ppa;
431 434 int pgflags;
432 435 spgcnt_t i = 0;
433 436
434 437
435 438 ASSERT(size <= contig_mem_import_size_max);
436 439 ASSERT((size & (size - 1)) == 0);
437 440
438 441 if ((addr = vmem_xalloc(vmp, size, size, 0, 0,
439 442 NULL, NULL, vmflag)) == NULL) {
440 443 return (NULL);
441 444 }
442 445
443 446 /* The address should be slab-size aligned. */
444 447 ASSERT(((uintptr_t)addr & (size - 1)) == 0);
445 448
446 449 if (page_resv(npages, vmflag & VM_KMFLAGS) == 0) {
447 450 vmem_xfree(vmp, addr, size);
448 451 return (NULL);
449 452 }
450 453
451 454 pgflags = PG_EXCL;
452 455 if (vmflag & VM_NORELOC)
453 456 pgflags |= PG_NORELOC;
454 457
455 458 ppl = page_create_va_large(&kvp, (u_offset_t)(uintptr_t)addr, size,
456 459 pgflags, &kvseg, addr, NULL);
457 460
458 461 if (ppl == NULL) {
459 462 vmem_xfree(vmp, addr, size);
460 463 page_unresv(npages);
461 464 return (NULL);
462 465 }
463 466
464 467 rootpp = ppl;
465 468 ppa = kmem_zalloc(npages * sizeof (page_t *), KM_SLEEP);
466 469 while (ppl != NULL) {
467 470 page_t *pp = ppl;
468 471 ppa[i++] = pp;
469 472 page_sub(&ppl, pp);
470 473 ASSERT(page_iolock_assert(pp));
471 474 ASSERT(PAGE_EXCL(pp));
472 475 page_io_unlock(pp);
473 476 }
474 477
475 478 /*
476 479 * Load the locked entry. It's OK to preload the entry into
477 480 * the TSB since we now support large mappings in the kernel TSB.
478 481 */
479 482 hat_memload_array(kas.a_hat, (caddr_t)rootpp->p_offset, size,
480 483 ppa, (PROT_ALL & ~PROT_USER) | HAT_NOSYNC, HAT_LOAD_LOCK);
481 484
482 485 ASSERT(i == page_get_pagecnt(ppa[0]->p_szc));
483 486 for (--i; i >= 0; --i) {
484 487 ASSERT(ppa[i]->p_szc == ppa[0]->p_szc);
485 488 ASSERT(page_pptonum(ppa[i]) == page_pptonum(ppa[0]) + i);
486 489 (void) page_pp_lock(ppa[i], 0, 1);
487 490 /*
488 491 * Leave the page share locked. For non-cage pages,
489 492 * this would prevent memory DR if it were supported
490 493 * on sun4v.
491 494 */
492 495 page_downgrade(ppa[i]);
493 496 }
494 497
495 498 kmem_free(ppa, npages * sizeof (page_t *));
496 499 return (addr);
497 500 }
498 501
499 502 /*
500 503 * Allocates a slab by first trying to use the largest slab size
501 504 * in contig_mem_import_sizes and then falling back to smaller slab
502 505 * sizes still large enough for the allocation. The sizep argument
503 506 * is a pointer to the requested size. When a slab is successfully
504 507 * allocated, the slab size, which must be >= *sizep and <=
505 508 * contig_mem_import_size_max, is returned in the *sizep argument.
506 509 * Returns the virtual address of the new slab.
507 510 */
508 511 static void *
509 512 span_alloc_downsize(vmem_t *vmp, size_t *sizep, size_t align, int vmflag)
510 513 {
511 514 int i;
512 515
513 516 ASSERT(*sizep <= contig_mem_import_size_max);
514 517
515 518 for (i = 0; i < NUM_IMPORT_SIZES; i++) {
516 519 size_t page_size = contig_mem_import_sizes[i];
517 520
518 521 /*
519 522 * Check that the alignment is also less than the
520 523 * import (large page) size. In the case where the
521 524 * alignment is larger than the size, a large page
522 525 * large enough for the allocation is not necessarily
523 526 * physical-address aligned to satisfy the requested
524 527 * alignment. Since alignment is required to be a
525 528 * power-of-2, any large page >= size && >= align will
526 529 * suffice.
527 530 */
528 531 if (*sizep <= page_size && align <= page_size) {
529 532 void *addr;
530 533 addr = contig_mem_span_alloc(vmp, page_size, vmflag);
531 534 if (addr == NULL)
532 535 continue;
533 536 *sizep = page_size;
534 537 return (addr);
535 538 }
536 539 return (NULL);
537 540 }
538 541
539 542 return (NULL);
540 543 }
541 544
542 545 static void *
543 546 contig_mem_span_xalloc(vmem_t *vmp, size_t *sizep, size_t align, int vmflag)
544 547 {
545 548 return (span_alloc_downsize(vmp, sizep, align, vmflag | VM_NORELOC));
546 549 }
547 550
548 551 static void *
549 552 contig_mem_reloc_span_xalloc(vmem_t *vmp, size_t *sizep, size_t align,
550 553 int vmflag)
551 554 {
552 555 ASSERT((vmflag & VM_NORELOC) == 0);
553 556 return (span_alloc_downsize(vmp, sizep, align, vmflag));
554 557 }
555 558
556 559 /*
557 560 * Free a span, which is always exactly one large page.
558 561 */
559 562 static void
560 563 contig_mem_span_free(vmem_t *vmp, void *inaddr, size_t size)
561 564 {
562 565 page_t *pp;
563 566 caddr_t addr = inaddr;
564 567 caddr_t eaddr;
565 568 pgcnt_t npages = btopr(size);
566 569 page_t *rootpp = NULL;
567 570
568 571 ASSERT(size <= contig_mem_import_size_max);
569 572 /* All slabs should be size aligned */
570 573 ASSERT(((uintptr_t)addr & (size - 1)) == 0);
571 574
572 575 hat_unload(kas.a_hat, addr, size, HAT_UNLOAD_UNLOCK);
573 576
574 577 for (eaddr = addr + size; addr < eaddr; addr += PAGESIZE) {
575 578 pp = page_find(&kvp, (u_offset_t)(uintptr_t)addr);
576 579 if (pp == NULL) {
577 580 panic("contig_mem_span_free: page not found");
578 581 }
579 582 if (!page_tryupgrade(pp)) {
580 583 page_unlock(pp);
581 584 pp = page_lookup(&kvp,
582 585 (u_offset_t)(uintptr_t)addr, SE_EXCL);
583 586 if (pp == NULL)
584 587 panic("contig_mem_span_free: page not found");
585 588 }
586 589
587 590 ASSERT(PAGE_EXCL(pp));
588 591 ASSERT(size == page_get_pagesize(pp->p_szc));
589 592 ASSERT(rootpp == NULL || rootpp->p_szc == pp->p_szc);
590 593 ASSERT(rootpp == NULL || (page_pptonum(rootpp) +
591 594 (pgcnt_t)btop(addr - (caddr_t)inaddr) == page_pptonum(pp)));
592 595
593 596 page_pp_unlock(pp, 0, 1);
594 597
595 598 if (rootpp == NULL)
596 599 rootpp = pp;
597 600 }
598 601 page_destroy_pages(rootpp);
599 602 page_unresv(npages);
600 603
601 604 if (vmp != NULL)
602 605 vmem_xfree(vmp, inaddr, size);
603 606 }
604 607
605 608 static void *
606 609 contig_vmem_xalloc_aligned_wrapper(vmem_t *vmp, size_t *sizep, size_t align,
607 610 int vmflag)
608 611 {
609 612 ASSERT((align & (align - 1)) == 0);
610 613 return (vmem_xalloc(vmp, *sizep, align, 0, 0, NULL, NULL, vmflag));
611 614 }
612 615
613 616 /*
614 617 * contig_mem_alloc, contig_mem_alloc_align
615 618 *
616 619 * Caution: contig_mem_alloc and contig_mem_alloc_align should be
617 620 * used only when physically contiguous non-relocatable memory is
618 621 * required. Furthermore, use of these allocation routines should be
619 622 * minimized as well as should the allocation size. As described in the
620 623 * contig_mem_arena comment block above, slab allocations fall back to
621 624 * being outside of the cage. Therefore, overuse of these allocation
622 625 * routines can lead to non-relocatable large pages being allocated
623 626 * outside the cage. Such pages prevent the allocation of a larger page
624 627 * occupying overlapping pages. This can impact performance for
625 628 * applications that utilize e.g. 256M large pages.
626 629 */
627 630
628 631 /*
629 632 * Allocates size aligned contiguous memory up to contig_mem_import_size_max.
630 633 * Size must be a power of 2.
631 634 */
632 635 void *
633 636 contig_mem_alloc(size_t size)
634 637 {
635 638 ASSERT((size & (size - 1)) == 0);
636 639 return (contig_mem_alloc_align(size, size));
637 640 }
638 641
639 642 /*
640 643 * contig_mem_alloc_align allocates real contiguous memory with the
641 644 * specified alignment up to contig_mem_import_size_max. The alignment must
642 645 * be a power of 2 and no greater than contig_mem_import_size_max. We assert
643 646 * the aligment is a power of 2. For non-debug, vmem_xalloc will panic
644 647 * for non power of 2 alignments.
645 648 */
646 649 void *
647 650 contig_mem_alloc_align(size_t size, size_t align)
648 651 {
649 652 void *buf;
650 653
651 654 ASSERT(size <= contig_mem_import_size_max);
652 655 ASSERT(align <= contig_mem_import_size_max);
653 656 ASSERT((align & (align - 1)) == 0);
654 657
655 658 if (align < CONTIG_MEM_ARENA_QUANTUM)
656 659 align = CONTIG_MEM_ARENA_QUANTUM;
657 660
658 661 /*
659 662 * We take the lock here to serialize span allocations.
660 663 * We do not lose concurrency for the common case, since
661 664 * allocations that don't require new span allocations
662 665 * are serialized by vmem_xalloc. Serializing span
663 666 * allocations also prevents us from trying to allocate
664 667 * more spans than necessary.
665 668 */
666 669 mutex_enter(&contig_mem_lock);
667 670
668 671 buf = vmem_xalloc(contig_mem_arena, size, align, 0, 0,
669 672 NULL, NULL, VM_NOSLEEP | VM_NORELOC);
670 673
671 674 if ((buf == NULL) && (size <= MMU_PAGESIZE)) {
672 675 mutex_exit(&contig_mem_lock);
673 676 return (vmem_xalloc(static_alloc_arena, size, align, 0, 0,
674 677 NULL, NULL, VM_NOSLEEP));
675 678 }
676 679
677 680 if (buf == NULL) {
678 681 buf = vmem_xalloc(contig_mem_reloc_arena, size, align, 0, 0,
679 682 NULL, NULL, VM_NOSLEEP);
680 683 }
681 684
682 685 mutex_exit(&contig_mem_lock);
683 686
684 687 return (buf);
685 688 }
686 689
687 690 void
688 691 contig_mem_free(void *vaddr, size_t size)
689 692 {
690 693 if (vmem_contains(contig_mem_arena, vaddr, size)) {
691 694 vmem_xfree(contig_mem_arena, vaddr, size);
692 695 } else if (size > MMU_PAGESIZE) {
693 696 vmem_xfree(contig_mem_reloc_arena, vaddr, size);
694 697 } else {
695 698 vmem_xfree(static_alloc_arena, vaddr, size);
696 699 }
697 700 }
698 701
699 702 /*
700 703 * We create a set of stacked vmem arenas to enable us to
701 704 * allocate large >PAGESIZE chucks of contiguous Real Address space.
702 705 * The vmem_xcreate interface is used to create the contig_mem_arena
703 706 * allowing the import routine to downsize the requested slab size
704 707 * and return a smaller slab.
705 708 */
706 709 void
707 710 contig_mem_init(void)
708 711 {
709 712 mutex_init(&contig_mem_lock, NULL, MUTEX_DEFAULT, NULL);
710 713
711 714 contig_mem_slab_arena = vmem_xcreate("contig_mem_slab_arena", NULL, 0,
712 715 CONTIG_MEM_SLAB_ARENA_QUANTUM, contig_vmem_xalloc_aligned_wrapper,
713 716 vmem_xfree, heap_arena, 0, VM_SLEEP | VMC_XALIGN);
714 717
715 718 contig_mem_arena = vmem_xcreate("contig_mem_arena", NULL, 0,
716 719 CONTIG_MEM_ARENA_QUANTUM, contig_mem_span_xalloc,
717 720 contig_mem_span_free, contig_mem_slab_arena, 0,
718 721 VM_SLEEP | VM_BESTFIT | VMC_XALIGN);
719 722
720 723 contig_mem_reloc_arena = vmem_xcreate("contig_mem_reloc_arena", NULL, 0,
721 724 CONTIG_MEM_ARENA_QUANTUM, contig_mem_reloc_span_xalloc,
722 725 contig_mem_span_free, contig_mem_slab_arena, 0,
723 726 VM_SLEEP | VM_BESTFIT | VMC_XALIGN);
724 727
725 728 if (contig_mem_prealloc_buf == NULL || vmem_add(contig_mem_arena,
726 729 contig_mem_prealloc_buf, contig_mem_prealloc_size, VM_SLEEP)
727 730 == NULL) {
728 731 cmn_err(CE_WARN, "Failed to pre-populate contig_mem_arena");
729 732 }
730 733 }
731 734
732 735 /*
733 736 * In calculating how much memory to pre-allocate, we include a small
734 737 * amount per-CPU to account for per-CPU buffers in line with measured
735 738 * values for different size systems. contig_mem_prealloc_base_size is
736 739 * a cpu specific amount to be pre-allocated before considering per-CPU
737 740 * requirements and memory size. We always pre-allocate a minimum amount
738 741 * of memory determined by PREALLOC_MIN. Beyond that, we take the minimum
739 742 * of contig_mem_prealloc_base_size and a small percentage of physical
740 743 * memory to prevent allocating too much on smaller systems.
741 744 * contig_mem_prealloc_base_size is global, allowing for the CPU module
742 745 * to increase its value if necessary.
743 746 */
744 747 #define PREALLOC_PER_CPU (256 * 1024) /* 256K */
745 748 #define PREALLOC_PERCENT (4) /* 4% */
746 749 #define PREALLOC_MIN (16 * 1024 * 1024) /* 16M */
747 750 size_t contig_mem_prealloc_base_size = 0;
748 751
749 752 /*
750 753 * Called at boot-time allowing pre-allocation of contiguous memory.
751 754 * The argument 'alloc_base' is the requested base address for the
752 755 * allocation and originates in startup_memlist.
753 756 */
754 757 caddr_t
755 758 contig_mem_prealloc(caddr_t alloc_base, pgcnt_t npages)
756 759 {
757 760 caddr_t chunkp;
758 761
759 762 contig_mem_prealloc_size = MIN((PREALLOC_PER_CPU * ncpu_guest_max) +
760 763 contig_mem_prealloc_base_size,
761 764 (ptob(npages) * PREALLOC_PERCENT) / 100);
762 765 contig_mem_prealloc_size = MAX(contig_mem_prealloc_size, PREALLOC_MIN);
763 766 contig_mem_prealloc_size = P2ROUNDUP(contig_mem_prealloc_size,
764 767 MMU_PAGESIZE4M);
765 768
766 769 alloc_base = (caddr_t)roundup((uintptr_t)alloc_base, MMU_PAGESIZE4M);
767 770 if (prom_alloc(alloc_base, contig_mem_prealloc_size,
768 771 MMU_PAGESIZE4M) != alloc_base) {
769 772
770 773 /*
771 774 * Failed. This may mean the physical memory has holes in it
772 775 * and it will be more difficult to get large contiguous
773 776 * pieces of memory. Since we only guarantee contiguous
774 777 * pieces of memory contig_mem_import_size_max or smaller,
775 778 * loop, getting contig_mem_import_size_max at a time, until
776 779 * failure or contig_mem_prealloc_size is reached.
777 780 */
778 781 for (chunkp = alloc_base;
779 782 (chunkp - alloc_base) < contig_mem_prealloc_size;
780 783 chunkp += contig_mem_import_size_max) {
781 784
782 785 if (prom_alloc(chunkp, contig_mem_import_size_max,
783 786 MMU_PAGESIZE4M) != chunkp) {
784 787 break;
785 788 }
786 789 }
787 790 contig_mem_prealloc_size = chunkp - alloc_base;
788 791 ASSERT(contig_mem_prealloc_size != 0);
789 792 }
790 793
791 794 if (contig_mem_prealloc_size != 0) {
792 795 contig_mem_prealloc_buf = alloc_base;
793 796 } else {
794 797 contig_mem_prealloc_buf = NULL;
795 798 }
796 799 alloc_base += contig_mem_prealloc_size;
797 800
798 801 return (alloc_base);
799 802 }
|
↓ open down ↓ |
729 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX