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re #13613 rb4516 Tunables needs volatile keyword
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--- old/usr/src/uts/sun4u/vm/mach_vm_dep.c
+++ new/usr/src/uts/sun4u/vm/mach_vm_dep.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 +/*
26 + * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
27 + */
25 28
26 29 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
27 30 /* All Rights Reserved */
28 31
29 32 /*
30 33 * Portions of this source code were derived from Berkeley 4.3 BSD
31 34 * under license from the Regents of the University of California.
32 35 */
33 36
34 37 /*
35 38 * UNIX machine dependent virtual memory support.
36 39 */
37 40
38 41 #include <sys/vm.h>
39 42 #include <sys/exec.h>
40 43 #include <sys/cmn_err.h>
41 44 #include <sys/cpu_module.h>
42 45 #include <sys/cpu.h>
43 46 #include <sys/elf_SPARC.h>
44 47 #include <sys/archsystm.h>
45 48 #include <vm/hat_sfmmu.h>
46 49 #include <sys/memnode.h>
47 50 #include <sys/mem_cage.h>
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48 51 #include <vm/vm_dep.h>
49 52 #include <sys/random.h>
50 53
51 54 #if defined(__sparcv9) && defined(SF_ERRATA_57)
52 55 caddr_t errata57_limit;
53 56 #endif
54 57
55 58 uint_t page_colors = 0;
56 59 uint_t page_colors_mask = 0;
57 60 uint_t page_coloring_shift = 0;
58 -int consistent_coloring;
61 +volatile int consistent_coloring;
59 62 int update_proc_pgcolorbase_after_fork = 0;
60 63
61 64 uint_t mmu_page_sizes = DEFAULT_MMU_PAGE_SIZES;
62 65 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES;
63 66 uint_t mmu_hashcnt = DEFAULT_MAX_HASHCNT;
64 67 uint_t max_mmu_hashcnt = MAX_HASHCNT;
65 68 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE;
66 69
67 70 /*
68 71 * The sun4u hardware mapping sizes which will always be supported are
69 72 * 8K, 64K, 512K and 4M. If sun4u based machines need to support other
70 73 * page sizes, platform or cpu specific routines need to modify the value.
71 74 * The base pagesize (p_szc == 0) must always be supported by the hardware.
72 75 */
73 76 int mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) |
74 77 (1 << TTE512K) | (1 << TTE4M);
75 78 uint_t mmu_exported_page_sizes;
76 79
77 80 uint_t szc_2_userszc[MMU_PAGE_SIZES];
78 81 uint_t userszc_2_szc[MMU_PAGE_SIZES];
79 82
80 83 extern uint_t vac_colors_mask;
81 84 extern int vac_shift;
82 85
83 86 hw_pagesize_t hw_page_array[] = {
84 87 {MMU_PAGESIZE, MMU_PAGESHIFT, 0, MMU_PAGESIZE >> MMU_PAGESHIFT},
85 88 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, 0,
86 89 MMU_PAGESIZE64K >> MMU_PAGESHIFT},
87 90 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 0,
88 91 MMU_PAGESIZE512K >> MMU_PAGESHIFT},
89 92 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, 0, MMU_PAGESIZE4M >> MMU_PAGESHIFT},
90 93 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, 0,
91 94 MMU_PAGESIZE32M >> MMU_PAGESHIFT},
92 95 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 0,
93 96 MMU_PAGESIZE256M >> MMU_PAGESHIFT},
94 97 {0, 0, 0, 0}
95 98 };
96 99
97 100 /*
98 101 * Maximum page size used to map 64-bit memory segment kmem64_base..kmem64_end
99 102 */
100 103 int max_bootlp_tteszc = TTE4M;
101 104
102 105 /*
103 106 * use_text_pgsz64k and use_text_pgsz512k allow the user to turn on these
104 107 * additional text page sizes for USIII-IV+ and OPL by changing the default
105 108 * values via /etc/system.
106 109 */
107 110 int use_text_pgsz64K = 0;
108 111 int use_text_pgsz512K = 0;
109 112
110 113 /*
111 114 * Maximum and default segment size tunables for user heap, stack, private
112 115 * and shared anonymous memory, and user text and initialized data.
113 116 */
114 117 size_t max_uheap_lpsize = MMU_PAGESIZE4M;
115 118 size_t default_uheap_lpsize = MMU_PAGESIZE;
116 119 size_t max_ustack_lpsize = MMU_PAGESIZE4M;
117 120 size_t default_ustack_lpsize = MMU_PAGESIZE;
118 121 size_t max_privmap_lpsize = MMU_PAGESIZE4M;
119 122 size_t max_uidata_lpsize = MMU_PAGESIZE;
120 123 size_t max_utext_lpsize = MMU_PAGESIZE4M;
121 124 size_t max_shm_lpsize = MMU_PAGESIZE4M;
122 125
123 126 void
124 127 adjust_data_maxlpsize(size_t ismpagesize)
125 128 {
126 129 if (max_uheap_lpsize == MMU_PAGESIZE4M) {
127 130 max_uheap_lpsize = ismpagesize;
128 131 }
129 132 if (max_ustack_lpsize == MMU_PAGESIZE4M) {
130 133 max_ustack_lpsize = ismpagesize;
131 134 }
132 135 if (max_privmap_lpsize == MMU_PAGESIZE4M) {
133 136 max_privmap_lpsize = ismpagesize;
134 137 }
135 138 if (max_shm_lpsize == MMU_PAGESIZE4M) {
136 139 max_shm_lpsize = ismpagesize;
137 140 }
138 141 }
139 142
140 143 /*
141 144 * The maximum amount a randomized mapping will be slewed. We should perhaps
142 145 * arrange things so these tunables can be separate for mmap, mmapobj, and
143 146 * ld.so
144 147 */
145 148 size_t aslr_max_map_skew = 256 * 1024 * 1024; /* 256MB */
146 149
147 150 /*
148 151 * map_addr_proc() is the routine called when the system is to
149 152 * choose an address for the user. We will pick an address
150 153 * range which is just below the current stack limit. The
151 154 * algorithm used for cache consistency on machines with virtual
152 155 * address caches is such that offset 0 in the vnode is always
153 156 * on a shm_alignment'ed aligned address. Unfortunately, this
154 157 * means that vnodes which are demand paged will not be mapped
155 158 * cache consistently with the executable images. When the
156 159 * cache alignment for a given object is inconsistent, the
157 160 * lower level code must manage the translations so that this
158 161 * is not seen here (at the cost of efficiency, of course).
159 162 *
160 163 * Every mapping will have a redzone of a single page on either side of
161 164 * the request. This is done to leave one page unmapped between segments.
162 165 * This is not required, but it's useful for the user because if their
163 166 * program strays across a segment boundary, it will catch a fault
164 167 * immediately making debugging a little easier. Currently the redzone
165 168 * is mandatory.
166 169 *
167 170 *
168 171 * addrp is a value/result parameter.
169 172 * On input it is a hint from the user to be used in a completely
170 173 * machine dependent fashion. For MAP_ALIGN, addrp contains the
171 174 * minimal alignment, which must be some "power of two" multiple of
172 175 * pagesize.
173 176 *
174 177 * On output it is NULL if no address can be found in the current
175 178 * processes address space or else an address that is currently
176 179 * not mapped for len bytes with a page of red zone on either side.
177 180 * If vacalign is true, then the selected address will obey the alignment
178 181 * constraints of a vac machine based on the given off value.
179 182 */
180 183 /*ARGSUSED4*/
181 184 void
182 185 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign,
183 186 caddr_t userlimit, struct proc *p, uint_t flags)
184 187 {
185 188 struct as *as = p->p_as;
186 189 caddr_t addr;
187 190 caddr_t base;
188 191 size_t slen;
189 192 uintptr_t align_amount;
190 193 int allow_largepage_alignment = 1;
191 194
192 195 base = p->p_brkbase;
193 196 if (userlimit < as->a_userlimit) {
194 197 /*
195 198 * This happens when a program wants to map something in
196 199 * a range that's accessible to a program in a smaller
197 200 * address space. For example, a 64-bit program might
198 201 * be calling mmap32(2) to guarantee that the returned
199 202 * address is below 4Gbytes.
200 203 */
201 204 ASSERT(userlimit > base);
202 205 slen = userlimit - base;
203 206 } else {
204 207 slen = p->p_usrstack - base -
205 208 ((p->p_stk_ctl + PAGEOFFSET) & PAGEMASK);
206 209 }
207 210
208 211 /* Make len be a multiple of PAGESIZE */
209 212 len = (len + PAGEOFFSET) & PAGEMASK;
210 213
211 214 /*
212 215 * If the request is larger than the size of a particular
213 216 * mmu level, then we use that level to map the request.
214 217 * But this requires that both the virtual and the physical
215 218 * addresses be aligned with respect to that level, so we
216 219 * do the virtual bit of nastiness here.
217 220 *
218 221 * For 32-bit processes, only those which have specified
219 222 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise
220 223 * we can potentially waste up to 256MB of the 4G process address
221 224 * space just for alignment.
222 225 */
223 226 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 ||
224 227 ((uintptr_t)*addrp) != 0)) {
225 228 allow_largepage_alignment = 0;
226 229 }
227 230 if ((mmu_page_sizes == max_mmu_page_sizes) &&
228 231 allow_largepage_alignment &&
229 232 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */
230 233 align_amount = MMU_PAGESIZE256M;
231 234 } else if ((mmu_page_sizes == max_mmu_page_sizes) &&
232 235 allow_largepage_alignment &&
233 236 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */
234 237 align_amount = MMU_PAGESIZE32M;
235 238 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */
236 239 align_amount = MMU_PAGESIZE4M;
237 240 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */
238 241 align_amount = MMU_PAGESIZE512K;
239 242 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */
240 243 align_amount = MMU_PAGESIZE64K;
241 244 } else {
242 245 /*
243 246 * Align virtual addresses on a 64K boundary to ensure
244 247 * that ELF shared libraries are mapped with the appropriate
245 248 * alignment constraints by the run-time linker.
246 249 */
247 250 align_amount = ELF_SPARC_MAXPGSZ;
248 251 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) &&
249 252 ((uintptr_t)*addrp < align_amount))
250 253 align_amount = (uintptr_t)*addrp;
251 254 }
252 255
253 256 /*
254 257 * 64-bit processes require 1024K alignment of ELF shared libraries.
255 258 */
256 259 if (p->p_model == DATAMODEL_LP64)
257 260 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ);
258 261 #ifdef VAC
259 262 if (vac && vacalign && (align_amount < shm_alignment))
260 263 align_amount = shm_alignment;
261 264 #endif
262 265
263 266 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) {
264 267 align_amount = (uintptr_t)*addrp;
265 268 }
266 269
267 270 ASSERT(ISP2(align_amount));
268 271 ASSERT(align_amount == 0 || align_amount >= PAGESIZE);
269 272
270 273 /*
271 274 * Look for a large enough hole starting below the stack limit.
272 275 * After finding it, use the upper part.
273 276 */
274 277 as_purge(as);
275 278 off = off & (align_amount - 1);
276 279
277 280 if (as_gap_aligned(as, len, &base, &slen, AH_HI, NULL, align_amount,
278 281 PAGESIZE, off) == 0) {
279 282 caddr_t as_addr;
280 283
281 284 /*
282 285 * addr is the highest possible address to use since we have
283 286 * a PAGESIZE redzone at the beginning and end.
284 287 */
285 288 addr = base + slen - (PAGESIZE + len);
286 289 as_addr = addr;
287 290 /*
288 291 * Round address DOWN to the alignment amount and
289 292 * add the offset in.
290 293 * If addr is greater than as_addr, len would not be large
291 294 * enough to include the redzone, so we must adjust down
292 295 * by the alignment amount.
293 296 */
294 297 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l)));
295 298 addr += (long)off;
296 299 if (addr > as_addr) {
297 300 addr -= align_amount;
298 301 }
299 302
300 303 /*
301 304 * If randomization is requested, slew the allocation
302 305 * backwards, within the same gap, by a random amount.
303 306 */
304 307 if (flags & _MAP_RANDOMIZE) {
305 308 uint32_t slew;
306 309 uint32_t maxslew;
307 310
308 311 (void) random_get_pseudo_bytes((uint8_t *)&slew,
309 312 sizeof (slew));
310 313
311 314 maxslew = MIN(aslr_max_map_skew, (addr - base));
312 315 /*
313 316 * Don't allow ASLR to cause mappings to fail below
314 317 * because of SF erratum #57
315 318 */
316 319 maxslew = MIN(maxslew, (addr - errata57_limit));
317 320
318 321 slew = slew % maxslew;
319 322 addr -= P2ALIGN(slew, align_amount);
320 323 }
321 324
322 325 ASSERT(addr > base);
323 326 ASSERT(addr + len < base + slen);
324 327 ASSERT(((uintptr_t)addr & (align_amount - 1l)) ==
325 328 ((uintptr_t)(off)));
326 329 *addrp = addr;
327 330
328 331 #if defined(SF_ERRATA_57)
329 332 if (AS_TYPE_64BIT(as) && addr < errata57_limit) {
330 333 *addrp = NULL;
331 334 }
332 335 #endif
333 336 } else {
334 337 *addrp = NULL; /* no more virtual space */
335 338 }
336 339 }
337 340
338 341 /*
339 342 * Platform-dependent page scrub call.
340 343 */
341 344 void
342 345 pagescrub(page_t *pp, uint_t off, uint_t len)
343 346 {
344 347 /*
345 348 * For now, we rely on the fact that pagezero() will
346 349 * always clear UEs.
347 350 */
348 351 pagezero(pp, off, len);
349 352 }
350 353
351 354 /*ARGSUSED*/
352 355 void
353 356 sync_data_memory(caddr_t va, size_t len)
354 357 {
355 358 cpu_flush_ecache();
356 359 }
357 360
358 361 /*
359 362 * platform specific large pages for kernel heap support
360 363 */
361 364 void
362 365 mmu_init_kcontext()
363 366 {
364 367 extern void set_kcontextreg();
365 368
366 369 if (kcontextreg)
367 370 set_kcontextreg();
368 371 }
369 372
370 373 void
371 374 contig_mem_init(void)
372 375 {
373 376 /* not applicable to sun4u */
374 377 }
375 378
376 379 /*ARGSUSED*/
377 380 caddr_t
378 381 contig_mem_prealloc(caddr_t alloc_base, pgcnt_t npages)
379 382 {
380 383 /* not applicable to sun4u */
381 384 return (alloc_base);
382 385 }
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