Print this page
NEX-16600 "No SOF interrupts have been received" on HPE ProLiant DL380 Gen10, leading to non-working USB EHCI controller
Reviewed by: Evan Layton <evan.layton@nexenta.com>
Reviewed by: Roman Strashkin <roman.strashkin@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/sys/usb/hcd/ehci/ehcid.h
+++ new/usr/src/uts/common/sys/usb/hcd/ehci/ehcid.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
|
↓ open down ↓ |
10 lines elided |
↑ open up ↑ |
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 +
21 22 /*
22 23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
23 24 */
24 25
26 +/*
27 + * Copyright 2018 Nexenta Systems, Inc.
28 + */
29 +
25 30 #ifndef _SYS_USB_EHCID_H
26 31 #define _SYS_USB_EHCID_H
27 32
28 33
29 34 #ifdef __cplusplus
30 35 extern "C" {
31 36 #endif
32 37
33 38 /*
34 39 * Enchanced Host Controller Driver (EHCI)
35 40 *
36 41 * The EHCI driver is a software driver which interfaces to the Universal
37 42 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to
38 43 * the Host Controller is defined by the EHCI Host Controller Interface.
39 44 *
40 45 * This header file describes the data structures and function prototypes
41 46 * required for the EHCI Driver to maintain state of Host Controller (HC),
42 47 * to perform different USB transfers and for the bandwidth allocations.
43 48 */
44 49
45 50 #include <sys/usb/hcd/ehci/ehci.h>
46 51 #include <sys/usb/hcd/ehci/ehci_hub.h>
47 52
48 53
49 54 /*
50 55 * EHCI Bandwidth Maintainence Structure.
51 56 *
52 57 * The ehci_bandwidth array keeps track of allocated bandwidth for ehci
53 58 * host controller. There are 32 bandwidth lists corresponding to 32 ms
54 59 * periodic frame lists. Each bandwidth list inturn will contain eight
55 60 * micro frame bandwidth lists.
56 61 */
57 62 #define EHCI_MAX_UFRAMES 8 /* Max uframes 125us per frame */
58 63
59 64 typedef struct ehci_frame_bandwidth {
60 65 uint_t ehci_allocated_frame_bandwidth;
61 66 uint_t ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES];
62 67 } ehci_frame_bandwidth_t;
63 68
64 69
65 70 /*
66 71 * EHCI Host Controller state structure
67 72 *
68 73 * The Host Controller Driver (HCD) maintains the state of Host Controller
69 74 * (HC). There is an ehci_state structure per instance of the EHCI
70 75 * host controller.
71 76 */
72 77 typedef struct ehci_state {
73 78 dev_info_t *ehci_dip; /* Dip of HC */
74 79 uint_t ehci_instance;
75 80 usba_hcdi_ops_t *ehci_hcdi_ops; /* HCDI structure */
76 81 uint_t ehci_flags; /* Used for cleanup */
77 82 uint16_t ehci_vendor_id; /* chip vendor */
78 83 uint16_t ehci_device_id; /* chip device */
79 84 uint8_t ehci_rev_id; /* chip revison */
80 85
81 86 ddi_acc_handle_t ehci_caps_handle; /* Caps Reg Handle */
82 87 ehci_caps_t *ehci_capsp; /* Capability Regs */
83 88 ehci_regs_t *ehci_regsp; /* Operational Regs */
84 89
85 90 ddi_acc_handle_t ehci_config_handle; /* Config space hndle */
86 91 uint_t ehci_frame_interval; /* Frme inter reg */
87 92 ddi_dma_attr_t ehci_dma_attr; /* DMA attributes */
88 93
89 94 ddi_intr_handle_t *ehci_htable; /* intr handle */
90 95 int ehci_intr_type; /* intr type used */
91 96 int ehci_intr_cnt; /* # of intrs inuse */
92 97 uint_t ehci_intr_pri; /* intr priority */
93 98 int ehci_intr_cap; /* intr capabilities */
94 99 boolean_t ehci_msi_enabled; /* default to true */
95 100 kmutex_t ehci_int_mutex; /* Global EHCI mutex */
96 101
97 102 /* Periodic Frame List area */
98 103 ehci_periodic_frame_list_t *ehci_periodic_frame_list_tablep;
99 104 /* Virtual Periodic Frame List ptr */
100 105 ddi_dma_cookie_t ehci_pflt_cookie; /* DMA cookie */
101 106 ddi_dma_handle_t ehci_pflt_dma_handle; /* DMA handle */
102 107 ddi_acc_handle_t ehci_pflt_mem_handle; /* Memory handle */
103 108
104 109 /*
105 110 * There are two pools of memory. One pool contains the memory for
106 111 * the transfer descriptors and other pool contains the memory for
107 112 * the endpoint descriptors. The advantage of the pools is that it's
108 113 * easy to go back and forth between the iommu and the cpu addresses.
109 114 *
110 115 * The pools are protected by the ehci_int_mutex because the memory
111 116 * in the pools may be accessed by either the host controller or the
112 117 * host controller driver.
113 118 */
114 119
115 120 /* Endpoint descriptor pool */
116 121 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */
117 122 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */
118 123 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */
119 124 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */
120 125 uint_t ehci_dma_addr_bind_flag; /* DMA flag */
121 126
122 127 /* General transfer descriptor pool */
123 128 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */
|
↓ open down ↓ |
89 lines elided |
↑ open up ↑ |
124 129 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */
125 130 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */
126 131 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */
127 132
128 133 /* Isochronous transfer descriptor pool */
129 134 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */
130 135 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */
131 136 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */
132 137 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */
133 138
134 - /* Condition variable for advance on Asynchronous Schedule */
135 - kcondvar_t ehci_async_schedule_advance_cv;
136 -
137 139 /* Head of Asynchronous Schedule List */
138 140 ehci_qh_t *ehci_head_of_async_sched_list;
139 141
140 142 /*
141 143 * List of QTD inserted either into Asynchronous or Periodic
142 144 * Schedule lists.
143 145 */
144 146 ehci_qtd_t *ehci_active_qtd_list;
145 147 /*
146 148 * List of ITD active itd list.
147 149 */
148 150 ehci_itd_t *ehci_active_itd_list;
149 151
150 152 /*
151 153 * Bandwidth fields
152 154 *
153 155 * The ehci_bandwidth array keeps track of allocated bandwidth for
154 156 * ehci host controller. There are 32 bandwidth lists corresponding
155 157 * to 32 ms periodic frame lists. Each bandwidth list in turn will
156 158 * contain eight micro frame bandwidth lists.
157 159 *
158 160 * ehci_min_frame_bandwidth field indicates least allocated milli
159 161 * second bandwidth list.
160 162 */
161 163 ehci_frame_bandwidth_t ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS];
162 164
163 165 /* No. of open pipes, async qh, and periodic qh */
164 166 uint_t ehci_open_pipe_count;
165 167 uint_t ehci_open_async_count;
166 168 uint_t ehci_open_periodic_count;
167 169
168 170 /* No. of async and periodic requests */
169 171 uint_t ehci_async_req_count;
170 172 uint_t ehci_periodic_req_count;
171 173
172 174 /*
173 175 * Endpoint Reclamation List
174 176 *
175 177 * The interrupt list processing cannot be stopped when a periodic
176 178 * endpoint is removed from the list. The endpoints are detached
177 179 * from the interrupt lattice tree and put on to the reclaimation
178 180 * list. On next SOF interrupt all those endpoints, which are on
179 181 * the reclaimation list will be deallocated.
180 182 */
181 183 ehci_qh_t *ehci_reclaim_list; /* Reclaimation list */
182 184
183 185 ehci_root_hub_t ehci_root_hub; /* Root hub info */
184 186
185 187 /* Frame number overflow information */
186 188 usb_frame_number_t ehci_fno;
187 189
188 190 /* For host controller error counter */
189 191 uint_t ehci_hc_error;
190 192
191 193 /*
192 194 * ehci_missed_intr_sts is used to save the normal mode interrupt
193 195 * status information if an interrupt is pending for normal mode
194 196 * when polled code is entered.
195 197 */
196 198 uint_t ehci_missed_intr_sts;
197 199
198 200 /*
199 201 * Saved copy of the ehci registers of the normal mode & change
200 202 * required ehci registers values for the polled mode operation.
201 203 * Before returning from the polled mode to normal mode replace
202 204 * the required current registers with this saved ehci registers
203 205 * copy.
204 206 */
205 207 ehci_regs_t ehci_polled_save_regs;
206 208
207 209 /*
208 210 * Saved copy of the interrupt table used in normal ehci mode and
209 211 * replace this table by another interrupt table that used in the
210 212 * POLLED mode.
211 213 */
212 214 ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS];
213 215
214 216 /* ehci polled mode enter counter */
215 217 uint_t ehci_polled_enter_count;
216 218
217 219 /*
218 220 * counter for polled mode and used in suspend mode to see if
219 221 * there is a keyboard connected.
220 222 */
221 223 uint_t ehci_polled_kbd_count;
222 224
223 225 /* counter for polled read and use it to clean the interrupt status */
224 226 uint_t ehci_polled_read_count;
225 227
226 228 #if defined(__x86)
227 229 /* counter for polled root hub status */
228 230 uint_t ehci_polled_root_hub_count;
229 231 #endif /* __x86 */
230 232
231 233 /* EHCI Host Controller Software State information */
232 234 uint_t ehci_hc_soft_state;
233 235
234 236 /* Log handle for debug, console, log messages */
235 237 usb_log_handle_t ehci_log_hdl;
236 238
237 239 /* Kstat structures */
238 240 kstat_t *ehci_intrs_stats;
239 241 kstat_t *ehci_total_stats;
240 242 kstat_t *ehci_count_stats[USB_N_COUNT_KSTATS];
241 243 } ehci_state_t;
242 244
243 245 typedef struct ehci_intrs_stats {
244 246 struct kstat_named ehci_sts_async_sched_status;
245 247 struct kstat_named ehci_sts_periodic_sched_status;
246 248 struct kstat_named ehci_sts_empty_async_schedule;
247 249 struct kstat_named ehci_sts_host_ctrl_halted;
248 250 struct kstat_named ehci_sts_async_advance_intr;
249 251 struct kstat_named ehci_sts_host_system_error_intr;
250 252 struct kstat_named ehci_sts_frm_list_rollover_intr;
251 253 struct kstat_named ehci_sts_rh_port_change_intr;
252 254 struct kstat_named ehci_sts_usb_error_intr;
253 255 struct kstat_named ehci_sts_usb_intr;
254 256 struct kstat_named ehci_sts_not_claimed;
255 257 struct kstat_named ehci_sts_total;
256 258 } ehci_intrs_stats_t;
257 259
258 260 /*
259 261 * ehci kstat defines
260 262 */
261 263 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats)
262 264 #define EHCI_INTRS_STATS_DATA(ehci) \
263 265 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data)
264 266
265 267 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats)
266 268 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats))
267 269 #define EHCI_CTRL_STATS(ehci) \
268 270 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL]))
269 271 #define EHCI_BULK_STATS(ehci) \
270 272 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK]))
271 273 #define EHCI_INTR_STATS(ehci) \
272 274 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR]))
273 275 #define EHCI_ISOC_STATS(ehci) \
274 276 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH]))
275 277
276 278 /* warlock directives, stable data */
277 279 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t))
278 280 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri))
279 281 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip))
280 282 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp))
281 283 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance))
282 284 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id))
283 285 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id))
284 286 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id))
285 287
286 288 /* this may not be stable data in the future */
287 289 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr))
288 290 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle))
289 291 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie))
290 292 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr))
291 293 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle))
292 294 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie))
293 295 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr))
294 296 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle))
295 297 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie))
296 298 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag))
297 299 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl))
298 300
299 301 _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \
300 302 usba_pipe_handle_data::p_mutex \
301 303 usba_device::usb_mutex \
302 304 usba_ph_impl::usba_ph_mutex))
303 305
304 306 /*
305 307 * Host Contoller Software States
306 308 *
307 309 * EHCI_CTLR_INIT_STATE:
308 310 * The host controller soft state will be set to this during the
309 311 * ehci_attach.
310 312 *
311 313 * EHCI_CTLR_SUSPEND_STATE:
312 314 * The host controller soft state will be set to this during the
313 315 * ehci_cpr_suspend.
314 316 *
315 317 * EHCI_CTLR_OPERATIONAL_STATE:
316 318 * The host controller soft state will be set to this after moving
317 319 * host controller to operational state and host controller start
318 320 * generating SOF successfully.
319 321 *
320 322 * EHCI_CTLR_ERROR_STATE:
321 323 * The host controller soft state will be set to this during the
322 324 * no SOF or UE error conditions.
323 325 *
324 326 * Under this state or condition, only pipe stop polling, pipe reset
325 327 * and pipe close are allowed. But all other entry points like pipe
326 328 * open, get/set pipe policy, cotrol send/receive, bulk send/receive
327 329 * isoch send/receive, start polling etc. will fail.
328 330 *
329 331 * State Diagram for the host controller software state
330 332 *
331 333 *
332 334 * ehci_attach->[INIT_STATE]
333 335 * |
334 336 * | -------->----[ERROR_STATE]--<-----------<---
335 337 * | | Failure (UE/no SOF condition) |
336 338 * | ^ ^
337 339 * V | Success |
338 340 * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling
339 341 * ^ |
340 342 * | |
341 343 * | V
342 344 * -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend
343 345 */
344 346 #define EHCI_CTLR_INIT_STATE 0 /* Initilization state */
345 347 #define EHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */
346 348 #define EHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */
347 349 #define EHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */
348 350
349 351 /*
350 352 * Flags for initializatoin of host controller
351 353 */
352 354 #define EHCI_NORMAL_INITIALIZATION 0 /* Normal initialization */
353 355 #define EHCI_REINITIALIZATION 1 /* Re-initialization */
354 356
355 357 /*
356 358 * Periodic and non-periodic macros
357 359 */
358 360 #define EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
359 361 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\
360 362 ((endpoint->bmAttributes &\
361 363 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
362 364
363 365 #define EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
364 366 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\
365 367 ((endpoint->bmAttributes &\
366 368 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK))
367 369
368 370 #define EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
369 371 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
370 372
371 373 #define EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
372 374 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR))
373 375
374 376
375 377 /*
376 378 * EHCI QH and QTD Pool sizes.
377 379 */
378 380 #define EHCI_QH_POOL_SIZE 100
379 381 #define EHCI_QTD_POOL_SIZE 200
380 382 #define EHCI_ITD_POOL_SIZE 200
381 383
382 384 /*
383 385 * ehci_dma_addr_bind_flag values
384 386 *
385 387 * This flag indicates if the various DMA addresses allocated by the EHCI
386 388 * have been bound to their respective handles. This is needed to recover
387 389 * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle()
388 390 */
389 391 #define EHCI_QTD_POOL_BOUND 0x01 /* For QTD pools */
390 392 #define EHCI_QH_POOL_BOUND 0x02 /* For QH pools */
391 393 #define EHCI_PFLT_DMA_BOUND 0x04 /* For Periodic Frame List area */
392 394 #define EHCI_ITD_POOL_BOUND 0x08 /* For QTD pools */
393 395
394 396 /*
395 397 * Maximum SOF wait count
396 398 */
397 399 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */
398 400
399 401 /*
400 402 * One uFrame 125 micro seconds
401 403 * One Frame 1 milli second or 8 uFrames
402 404 */
403 405 #define EHCI_uFRAMES_PER_USB_FRAME 8
404 406 #define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3
405 407
406 408
407 409 /*
408 410 * Pipe private structure
409 411 *
410 412 * There is an instance of this structure per pipe. This structure holds
411 413 * HCD specific pipe information. A pointer to this structure is kept in
412 414 * the USBA pipe handle (usba_pipe_handle_data_t).
413 415 */
414 416 typedef struct ehci_pipe_private {
415 417 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */
416 418 ehci_qh_t *pp_qh; /* Pipe's qh */
417 419
418 420 /* State of the pipe */
419 421 uint_t pp_state; /* See below */
420 422
421 423 /* Local copy of the pipe policy */
422 424 usb_pipe_policy_t pp_policy;
423 425
424 426 /* For Periodic Pipes Only */
425 427 uint_t pp_pnode; /* periodic node */
426 428 uchar_t pp_smask; /* Start split mask */
427 429 uchar_t pp_cmask; /* Comp split mask */
428 430 uint_t pp_cur_periodic_req_cnt; /* Curr req count */
429 431 uint_t pp_max_periodic_req_cnt; /* Max req count */
430 432
431 433 /* For Isochronous pipes only */
432 434 usb_frame_number_t pp_next_frame_number; /* Next frame no */
433 435
434 436 /*
435 437 * Each pipe may have multiple transfer wrappers. Each transfer
436 438 * wrapper represents a USB transfer on the bus. A transfer is
437 439 * made up of one or more transactions.
438 440 */
439 441 struct ehci_trans_wrapper *pp_tw_head; /* Head of the list */
440 442 struct ehci_trans_wrapper *pp_tw_tail; /* Tail of the list */
441 443
442 444 struct ehci_isoc_xwrapper *pp_itw_head; /* Head of the list */
443 445 struct ehci_isoc_xwrapper *pp_itw_tail; /* Tail of the list */
444 446
445 447 /*
446 448 * Pipe's transfer timeout handling & this transfer timeout handling
447 449 * will be per pipe.
448 450 */
449 451 struct ehci_trans_wrapper *pp_timeout_list; /* Timeout list */
450 452 timeout_id_t pp_timer_id; /* Timer id */
451 453
452 454 /* Done td count */
453 455 uint_t pp_count_done_qtds; /* Done td count */
454 456
455 457 /* Errors */
456 458 usb_cr_t pp_error; /* Pipe error */
457 459
458 460 /* Condition variable for transfers completion event */
459 461 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */
460 462
461 463 /* Pipe flag */
462 464 uint_t pp_flag; /* For polled mode */
463 465
464 466 /* Halting States */
465 467 uint_t pp_halt_state; /* Is it halting */
466 468
467 469 /* Condition variable for halt completion event */
468 470 kcondvar_t pp_halt_cmpl_cv; /* Xfer completion */
469 471
470 472 /*
471 473 * HCD gets Interrupt/Isochronous IN polling request only once and
472 474 * it has to insert next polling requests after completion of first
473 475 * request until either stop polling/pipe close is called. So HCD
474 476 * has to take copy of the original Interrupt/Isochronous IN request.
475 477 */
476 478 usb_opaque_t pp_client_periodic_in_reqp;
477 479 } ehci_pipe_private_t;
478 480
479 481 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t))
480 482
481 483 /*
482 484 * Pipe states
483 485 *
484 486 * ehci pipe states will be similar to usba. Refer usbai.h.
485 487 */
486 488 #define EHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */
487 489 #define EHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */
488 490 #define EHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */
489 491
490 492 /* Additional ehci pipe states for the ehci_pipe_cleanup */
491 493 #define EHCI_PIPE_STATE_CLOSE 4 /* Pipe close */
492 494 #define EHCI_PIPE_STATE_RESET 5 /* Pipe reset */
493 495 #define EHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */
494 496
495 497 /*
496 498 * Pipe flag
497 499 *
498 500 * For polled mode flag.
499 501 */
500 502 #define EHCI_POLLED_MODE_FLAG 1 /* Polled mode flag */
501 503
502 504 /* Pipe specific flags */
503 505 #define EHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */
504 506
505 507 /*
506 508 * Halting States
507 509 * prevent halting from interleaving.
508 510 */
509 511 #define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */
510 512 #define EHCI_HALT_STATE_HALTING 1 /* Currently Halting */
511 513
512 514 /*
513 515 * Request values for Clear_TT_Buffer
514 516 */
515 517 #define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \
516 518 USB_DEV_REQ_RCPT_OTHER)
517 519 #define EHCI_CLEAR_TT_BUFFER_BREQ 8
518 520
519 521 /*
520 522 * USB frame offset
521 523 *
522 524 * Add appropriate frame offset to the current usb frame number and use it
523 525 * as a starting frame number for a given usb isochronous request.
524 526 */
525 527 #define EHCI_FRAME_OFFSET 2 /* Frame offset */
526 528
527 529 /*
528 530 * Different interrupt polling intervals supported for high speed
529 531 * devices and its range must be from 1 to 16 units. This value is
530 532 * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval
531 533 * of 4 means a period of 8us (2 ^ (4-1)).
532 534 *
533 535 * The following values are defined after above convertion in terms
534 536 * 125us units.
535 537 */
536 538 #define EHCI_INTR_1US_POLL 1 /* 1us poll interval */
537 539 #define EHCI_INTR_2US_POLL 2 /* 2us poll interval */
538 540 #define EHCI_INTR_4US_POLL 4 /* 4us poll interval */
539 541 #define EHCI_INTR_XUS_POLL 8 /* 8us and above */
540 542
541 543 /*
542 544 * The following indecies are are used to calculate Start and complete
543 545 * masks as per the polling interval.
544 546 */
545 547 #define EHCI_1US_MASK_INDEX 14 /* 1us mask index */
546 548 #define EHCI_2US_MASK_INDEX 12 /* 2us mask index */
547 549 #define EHCI_4US_MASK_INDEX 8 /* 4us mask index */
548 550 #define EHCI_XUS_MASK_INDEX 0 /* 8us and above */
549 551
550 552 /*
551 553 * Different interrupt polling intervals supported for low/full/high
552 554 * speed devices. For high speed devices, the following values are
553 555 * applicable after convertion.
554 556 */
555 557 #define EHCI_INTR_1MS_POLL 1 /* 1ms poll interval */
556 558 #define EHCI_INTR_2MS_POLL 2 /* 2ms poll interval */
557 559 #define EHCI_INTR_4MS_POLL 4 /* 4ms poll interval */
558 560 #define EHCI_INTR_8MS_POLL 8 /* 8ms poll interval */
559 561 #define EHCI_INTR_16MS_POLL 16 /* 16ms poll interval */
560 562 #define EHCI_INTR_32MS_POLL 32 /* 32ms poll interval */
561 563
562 564 /*
563 565 * Number of interrupt transfer requests that should be maintained on
564 566 * the interrupt endpoint corresponding to different polling intervals
565 567 * supported.
566 568 */
567 569 #define EHCI_INTR_1MS_REQS 4 /* 1ms polling interval */
568 570 #define EHCI_INTR_2MS_REQS 2 /* 2ms polling interval */
569 571 #define EHCI_INTR_XMS_REQS 1 /* Between 4ms and 32ms */
570 572
571 573 /* Function prototype */
572 574 typedef void (*ehci_handler_function_t)(
573 575 ehci_state_t *ehcip,
574 576 ehci_pipe_private_t *pp,
575 577 struct ehci_trans_wrapper *tw,
576 578 ehci_qtd_t *qtd,
577 579 void *ehci_handle_callback_value);
578 580
579 581
580 582 /*
581 583 * Transfer wrapper
582 584 *
583 585 * The transfer wrapper represents a USB transfer on the bus and there
584 586 * is one instance per USB transfer. A transfer is made up of one or
585 587 * more transactions. EHCI uses one QTD for one transaction. So one
586 588 * transfer wrapper may have one or more QTDs associated.
587 589 *
588 590 * The data to be transferred are contained in the TW buffer which is
589 591 * virtually contiguous but physically discontiguous. When preparing
590 592 * the QTDs for a USB transfer, the DMA cookies corresponding to the
591 593 * TW buffer need to be walked through to retrieve the DMA addresses.
592 594 *
593 595 * Control and bulk pipes will have one transfer wrapper per transfer
594 596 * and where as Isochronous and Interrupt pipes will only have one
595 597 * transfer wrapper. The transfers wrapper are continually reused for
596 598 * the Interrupt and Isochronous pipes as those pipes are polled.
597 599 */
598 600 typedef struct ehci_trans_wrapper {
599 601 struct ehci_trans_wrapper *tw_next; /* Next wrapper */
600 602 ehci_pipe_private_t *tw_pipe_private; /* Back ptr */
601 603 ddi_dma_handle_t tw_dmahandle; /* DMA handle */
602 604 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */
603 605 ddi_dma_cookie_t tw_cookie; /* DMA cookie */
604 606 uint_t tw_ncookies; /* DMA cookie count */
605 607 uint_t tw_cookie_idx; /* DMA cookie index */
606 608 size_t tw_dma_offs; /* DMA buffer offset */
607 609 uint32_t tw_id; /* 32bit ID */
608 610 size_t tw_length; /* Txfer length */
609 611 char *tw_buf; /* Buffer for Xfer */
610 612 usb_flags_t tw_flags; /* Flags */
611 613 uint_t tw_num_qtds; /* Number of QTDs */
612 614 ehci_qtd_t *tw_qtd_head; /* Head QTD */
613 615 ehci_qtd_t *tw_qtd_tail; /* Tail QTD */
614 616 uint_t tw_direction; /* Direction of QTD */
615 617
616 618 /* Current transfer request pointer */
617 619 usb_opaque_t tw_curr_xfer_reqp;
618 620
619 621 /* Transfer timeout information */
620 622 int tw_timeout; /* Timeout value */
621 623 struct ehci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */
622 624
623 625 /*
624 626 * This is the function to call when this td is done. This way
625 627 * we don't have to look in the td to figure out what kind it is.
626 628 */
627 629 ehci_handler_function_t tw_handle_qtd;
628 630
629 631 /*
630 632 * This is the callback value used when processing a done td.
631 633 */
632 634 usb_opaque_t tw_handle_callback_value;
633 635
634 636 /* We preallocate all the td's for each tw and place them here */
635 637 ehci_qtd_t *tw_qtd_free_list;
636 638 ehci_qtd_t *tw_alt_qtd;
637 639 } ehci_trans_wrapper_t;
638 640
639 641 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper))
640 642
641 643 /*
642 644 * Isochronous Transfer Wrapper
643 645 *
644 646 * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed
645 647 * isochronous transfers. A transfer wrapper consists of one or more
646 648 * transactionsl, but there is one one instance per USB transfer request.
647 649 *
648 650 * The isochrnous transfer wrapper are continiously reused because these
649 651 * pipes are polled.
650 652 */
651 653 typedef struct ehci_isoc_xwrapper {
652 654 struct ehci_isoc_xwrapper *itw_next; /* Next wrapper in pp */
653 655 ehci_pipe_private_t *itw_pipe_private;
654 656
655 657 /* DMA and memory pointers */
656 658 ddi_dma_handle_t itw_dmahandle; /* DMA handle ETT */
657 659 ddi_acc_handle_t itw_accesshandle; /* Acc hndle */
658 660 ddi_dma_cookie_t itw_cookie; /* DMA cookie */
659 661
660 662 /* Transfer information */
661 663 char *itw_buf; /* Buffer for Xfer */
662 664 size_t itw_length; /* Txfer length */
663 665 usb_flags_t itw_flags; /* Flags */
664 666 usb_port_status_t itw_port_status; /* Port Speed */
665 667 uint_t itw_direction; /* Direction of ITD */
666 668
667 669 /* ITD information */
668 670 uint_t itw_num_itds; /* Number of ITDs */
669 671 ehci_itd_t *itw_itd_head; /* Head ITD */
670 672 ehci_itd_t *itw_itd_tail; /* Tail ITD */
671 673 usb_isoc_req_t *itw_curr_xfer_reqp;
672 674 usb_isoc_pkt_descr_t *itw_curr_isoc_pktp;
673 675
674 676 /* We preallocate all the td's for each tw and place them here */
675 677 ehci_itd_t *itw_itd_free_list;
676 678
677 679 /* Device and hub information needed by every iTD */
678 680 uint_t itw_hub_addr;
679 681 uint_t itw_hub_port;
680 682 uint_t itw_endpoint_num;
681 683 uint_t itw_device_addr;
682 684
683 685 /*
684 686 * Callback handling function and arguement. Called when an iTD is
685 687 * is done.
686 688 */
687 689 usb_opaque_t itw_handle_callback_value;
688 690
689 691 /* 32bit ID */
690 692 uint32_t itw_id;
691 693 } ehci_isoc_xwrapper_t;
692 694
693 695 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t))
694 696
695 697 /*
696 698 * Time waits for the different EHCI specific operations.
697 699 * These timeout values are specified in terms of microseconds.
698 700 */
699 701 #define EHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */
700 702 #define EHCI_TIMEWAIT 10000 /* HC any other waiting time */
701 703 #define EHCI_SOF_TIMEWAIT 20000 /* SOF Wait time */
702 704 #define EHCI_TAKEOVER_DELAY 10000 /* HC take over waiting time */
703 705 #define EHCI_TAKEOVER_WAIT_COUNT 25 /* HC take over waiting count */
704 706
705 707 /* These timeout values are specified in seconds */
706 708 #define EHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */
707 709 #define EHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */
708 710
709 711 /* EHCI flags for general use */
710 712 #define EHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */
711 713 #define EHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */
712 714 #define EHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */
713 715
714 716 /*
715 717 * Maximum allowable data transfer size per transaction as supported
716 718 * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96)
717 719 *
718 720 * Also within QTD, there will be five buffer pointers abd each buffer
719 721 * pointer can transfer upto 4k bytes of data.
720 722 */
721 723 #define EHCI_MAX_QTD_XFER_SIZE 0x5000 /* Maxmum data per transaction */
722 724 #define EHCI_MAX_QTD_BUF_SIZE 0x1000 /* Maxmum data per buffer */
723 725
724 726 /*
725 727 * The maximum allowable bulk data transfer size. It can be different
726 728 * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will
727 729 * take care of breaking a bulk data request into multiples of ehci
728 730 * EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this
729 731 * value is set to 640k bytes.
730 732 */
731 733 #define EHCI_MAX_BULK_XFER_SIZE 0xA0000 /* Maximum bulk transfer size */
732 734
733 735 /*
734 736 * Timeout flags
735 737 *
736 738 * These flags will be used to stop the timer before timeout handler
737 739 * gets executed.
738 740 */
739 741 #define EHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last QTD */
740 742 #define EHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */
741 743
742 744
743 745 /*
744 746 * High speed bandwidth allocation
745 747 *
746 748 * The following definitions are used during bandwidth calculations
747 749 * for a given high speed endpoint or high speed split transactions.
748 750 */
749 751 #define HS_BUS_BANDWIDTH 7500 /* Up to 7500 bytes per 125us */
750 752 #define HS_MAX_POLL_INTERVAL 16 /* Max high speed polling interval */
751 753 #define HS_MIN_POLL_INTERVAL 1 /* Min high speed polling interval */
752 754 #define HS_SOF 12 /* Length in bytes of High speed SOF */
753 755 #define HS_EOF 70 /* Length in bytes of High speed EOF */
754 756 #define TREE_HEIGHT 5 /* Log base 2 of 32 */
755 757
756 758 /*
757 759 * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved
758 760 * for the non-periodic high-speed transfers. Where as peridoic high-speed
759 761 * transfers will get 80% of the bus time. In one micro-frame or 125us, we
760 762 * can transfer 7500 bytes or 60,000 bits.
761 763 */
762 764 #define HS_NON_PERIODIC_BANDWIDTH 1500
763 765 #define HS_PERIODIC_BANDWIDTH (HS_BUS_BANDWIDTH - HS_SOF - \
764 766 HS_EOF - HS_NON_PERIODIC_BANDWIDTH)
765 767
766 768 /*
767 769 * High speed periodic frame bandwidth will be eight times the micro frame
768 770 * high speed periodic bandwidth.
769 771 */
770 772 #define HS_PERIODIC_FRAME_BANDWIDTH HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES
771 773
772 774 /*
773 775 * The following are the protocol overheads in terms of Bytes for the
774 776 * different transfer types. All these protocol overhead values are
775 777 * derived from the 5.11.3 section of USB 2.0 Specification.
776 778 */
777 779 #define HS_NON_ISOC_PROTO_OVERHEAD 55
778 780 #define HS_ISOC_PROTO_OVERHEAD 38
779 781
780 782 /*
781 783 * The following are THE protocol overheads in terms of Bytes for the
782 784 * start and complete split transactions tokens overheads. All these
783 785 * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3
784 786 * of USB2.0 Specification.
785 787 */
786 788 #define START_SPLIT_OVERHEAD 04
787 789 #define COMPLETE_SPLIT_OVERHEAD 04
788 790
789 791 /*
790 792 * The Host Controller (HC) delays are the USB host controller specific
791 793 * delays. The value shown below is the host controller delay for the
792 794 * given EHCI host controller.
793 795 */
794 796 #define EHCI_HOST_CONTROLLER_DELAY 18
795 797
796 798 /*
797 799 * Low/Full speed bandwidth allocation
798 800 *
799 801 * The following definitions are used during bandwidth calculations for
800 802 * a given high speed hub or a transaction translator (TT) and for a
801 803 * given low/full speed device connected to high speed hub or TT using
802 804 * split transactions
803 805 */
804 806 #define FS_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per 1ms */
805 807 #define FS_MAX_POLL_INTERVAL 255 /* Max full speed poll interval */
806 808 #define FS_MIN_POLL_INTERVAL 1 /* Min full speed polling interval */
807 809 #define FS_SOF 6 /* Length in bytes of Full speed SOF */
808 810 #define FS_EOF 4 /* Length in bytes of Full speed EOF */
809 811
810 812 /*
811 813 * Minimum polling interval for low speed endpoint
812 814 *
813 815 * According USB 2.0 Specification, a full-speed endpoint can specify
814 816 * a desired polling interval 1ms to 255ms and a low speed endpoints
815 817 * are limited to specifying only 10ms to 255ms. But some old keyboards
816 818 * and mice uses polling interval of 8ms. For compatibility purpose,
817 819 * we are using polling interval between 8ms and 255ms for low speed
818 820 * endpoints. The ehci driver will use 8ms polling interval if a low
819 821 * speed device reports a polling interval that is less than 8ms.
820 822 */
821 823 #define LS_MAX_POLL_INTERVAL 255 /* Max low speed poll interval */
822 824 #define LS_MIN_POLL_INTERVAL 8 /* Min low speed polling interval */
823 825
824 826 /*
825 827 * For non-periodic transfers, reserve atleast for one low-speed device
826 828 * transaction. According to USB Bandwidth Analysis white paper and also
827 829 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed
828 830 * transaction takes 0x628h full speed bits (197 bytes), which comes to
829 831 * around 13% of USB frame time.
830 832 *
831 833 * The periodic transfers will get around 87% of USB frame time.
832 834 */
833 835 #define FS_NON_PERIODIC_BANDWIDTH 197
834 836 #define FS_PERIODIC_BANDWIDTH (FS_BUS_BANDWIDTH - FS_SOF - \
835 837 FS_EOF - FS_NON_PERIODIC_BANDWIDTH)
836 838
837 839 /*
838 840 * The following are the protocol overheads in terms of Bytes for the
839 841 * different transfer types. All these protocol overhead values are
840 842 * derived from the 5.11.3 section of USB Specification and with the
841 843 * help of Bandwidth Analysis white paper which is posted on the USB
842 844 * developer forum.
843 845 */
844 846 #define FS_NON_ISOC_PROTO_OVERHEAD 14
845 847 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11
846 848 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10
847 849 #define LOW_SPEED_PROTO_OVERHEAD 97
848 850 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01
849 851
850 852 /* The maximum amount of isoch data that can be transferred in one uFrame */
851 853 #define MAX_UFRAME_SITD_XFER 188
852 854
853 855 /*
854 856 * The low speed clock below represents that to transmit one low-speed
855 857 * bit takes eight times more than one full speed bit time.
856 858 */
857 859 #define LOW_SPEED_CLOCK 8
858 860
859 861 /*
860 862 * The Transaction Translator (TT) delay is the additional time needed
861 863 * to execute low/full speed transaction from high speed split transaction
862 864 * for the low/full device connected to the high speed extrenal hub.
863 865 */
864 866 #define TT_DELAY 18
865 867
866 868
867 869 /*
868 870 * Macros for setting/getting information
869 871 */
870 872 #define Get_QH(addr) ddi_get32(ehcip->ehci_qh_pool_mem_handle, \
871 873 (uint32_t *)&addr)
872 874
873 875 #define Set_QH(addr, val) ddi_put32(ehcip->ehci_qh_pool_mem_handle, \
874 876 ((uint32_t *)&addr), \
875 877 ((int32_t)(val)))
876 878
877 879 #define Get_QTD(addr) ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \
878 880 (uint32_t *)&addr)
879 881
880 882 #define Set_QTD(addr, val) ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \
881 883 ((uint32_t *)&addr), \
882 884 ((int32_t)(val)))
883 885
884 886 #define Get_ITD(addr) ddi_get32(ehcip->ehci_itd_pool_mem_handle, \
885 887 (uint32_t *)&addr)
886 888
887 889 #define Set_ITD(addr, val) ddi_put32(ehcip->ehci_itd_pool_mem_handle, \
888 890 ((uint32_t *)&addr), \
889 891 ((int32_t)(val)))
890 892
891 893 #define Get_ITD_BODY(ptr, addr) ddi_get32( \
892 894 ehcip->ehci_itd_pool_mem_handle, \
893 895 (uint32_t *)&ptr->itd_body[addr])
894 896
895 897 #define Set_ITD_BODY(ptr, addr, val) ddi_put32( \
896 898 ehcip->ehci_itd_pool_mem_handle, \
897 899 ((uint32_t *)&ptr->itd_body[addr]),\
898 900 ((int32_t)(val)))
899 901
900 902 #define Get_ITD_INDEX(ptr, pos) ddi_get32( \
901 903 ehcip->ehci_itd_pool_mem_handle, \
902 904 (uint32_t *)&ptr->itd_index[pos])
903 905
904 906 #define Set_ITD_INDEX(ptr, pos, val) ddi_put32( \
905 907 ehcip->ehci_itd_pool_mem_handle, \
906 908 ((uint32_t *)&ptr->itd_index[pos]),\
907 909 ((uint32_t)(val)))
908 910
909 911 #define Get_ITD_FRAME(addr) ddi_get64( \
910 912 ehcip->ehci_itd_pool_mem_handle, \
911 913 (uint64_t *)&addr)
912 914
913 915 #define Set_ITD_FRAME(addr, val) ddi_put64( \
914 916 ehcip->ehci_itd_pool_mem_handle, \
915 917 ((uint64_t *)&addr), \
916 918 (val))
917 919
918 920 #define Get_PFLT(addr) ddi_get32(ehcip->ehci_pflt_mem_handle, \
919 921 (uint32_t *)&addr)
920 922
921 923 #define Set_PFLT(addr, val) ddi_put32(ehcip->ehci_pflt_mem_handle, \
922 924 ((uint32_t *)&addr), \
923 925 ((int32_t)(uintptr_t)(val)))
924 926
925 927 #define Get_8Cap(addr) ddi_get8(ehcip->ehci_caps_handle, \
926 928 (uint8_t *)&ehcip->ehci_capsp->addr)
927 929
928 930 #define Get_16Cap(addr) ddi_get16(ehcip->ehci_caps_handle, \
929 931 (uint16_t *)&ehcip->ehci_capsp->addr)
930 932
931 933 #define Get_Cap(addr) ddi_get32(ehcip->ehci_caps_handle, \
932 934 (uint32_t *)&ehcip->ehci_capsp->addr)
933 935
934 936 #define Get_OpReg(addr) ddi_get32(ehcip->ehci_caps_handle, \
935 937 (uint32_t *)&ehcip->ehci_regsp->addr)
936 938
937 939 #define Set_OpReg(addr, val) ddi_put32(ehcip->ehci_caps_handle, \
938 940 ((uint32_t *)&ehcip->ehci_regsp->addr), \
939 941 ((int32_t)(val)))
940 942
941 943 #define CalculateITDMultiField(pkgSize) (1 + (((pkgSize)>>11) & 0x03))
942 944
943 945 #define EHCI_MAX_RETRY 10
944 946
945 947 #define Set_OpRegRetry(addr, val, r) \
946 948 while (Get_OpReg(addr) != val) { \
947 949 if (r >= EHCI_MAX_RETRY) \
948 950 break; \
949 951 r++; \
950 952 Set_OpReg(addr, val); \
951 953 }
952 954
953 955 #define Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \
954 956 ehcip->ehci_qh_pool_dma_handle, \
955 957 0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \
956 958 DDI_DMA_SYNC_FORCPU); \
957 959 (void) ddi_dma_sync( \
958 960 ehcip->ehci_qtd_pool_dma_handle, \
959 961 0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \
960 962 DDI_DMA_SYNC_FORCPU);
961 963
962 964 #define Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \
963 965 ehcip->ehci_itd_pool_dma_handle, \
964 966 0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \
965 967 DDI_DMA_SYNC_FORCPU);
966 968
967 969 #define Sync_IO_Buffer(dma_handle, length) \
968 970 (void) ddi_dma_sync(dma_handle, \
969 971 0, length, DDI_DMA_SYNC_FORCPU);
970 972
971 973 #define Sync_IO_Buffer_for_device(dma_handle, length) \
972 974 (void) ddi_dma_sync(dma_handle, \
973 975 0, length, DDI_DMA_SYNC_FORDEV);
974 976
975 977 /*
976 978 * Macros to speed handling of 32bit IDs
977 979 */
978 980 #define EHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP)
979 981 #define EHCI_LOOKUP_ID(x) id32_lookup((x))
980 982 #define EHCI_FREE_ID(x) id32_free((x))
981 983
982 984
983 985 /*
984 986 * Miscellaneous definitions.
985 987 */
986 988
987 989 /* Data toggle bits */
988 990 #define DATA0 0
989 991 #define DATA1 1
990 992
991 993 /* Halt bit actions */
992 994 #define CLEAR_HALT 0
993 995 #define SET_HALT 1
994 996
995 997 typedef uint_t halt_bit_t;
996 998
997 999 /*
998 1000 * Setup Packet
999 1001 */
1000 1002 typedef struct setup_pkt {
1001 1003 uchar_t bmRequestType;
1002 1004 uchar_t bRequest;
1003 1005 ushort_t wValue;
1004 1006 ushort_t wIndex;
1005 1007 ushort_t wLength;
1006 1008 }setup_pkt_t;
1007 1009
1008 1010 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */
1009 1011
1010 1012 #define REQUEST_TYPE_OFFSET 0
1011 1013 #define REQUEST_OFFSET 1
1012 1014 #define VALUE_OFFSET 2
1013 1015 #define INDEX_OFFSET 4
1014 1016 #define LENGTH_OFFSET 6
1015 1017
1016 1018 #define TYPE_DEV_TO_HOST 0x80000000
1017 1019 #define DEVICE 0x00000001
1018 1020 #define CONFIGURATION 0x00000002
1019 1021
1020 1022 /*
|
↓ open down ↓ |
874 lines elided |
↑ open up ↑ |
1021 1023 * The following are used in attach to indicate
1022 1024 * what has been succesfully allocated, so detach
1023 1025 * can remove them.
1024 1026 */
1025 1027 #define EHCI_ATTACH 0x01 /* ehci driver initilization */
1026 1028 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */
1027 1029 #define EHCI_INTR 0x04 /* Interrupt handler registered */
1028 1030 #define EHCI_USBAREG 0x08 /* USBA registered */
1029 1031 #define EHCI_RHREG 0x10 /* Root hub driver loaded */
1030 1032
1031 -/*
1032 - * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase
1033 - * the ehci_async_schedule_advance_cv when an intr occurs. It is used to
1034 - * make sure that EHCI is receiving interrupts.
1035 - */
1036 -#define EHCI_CV_INTR 0x20 /* Ask INTR to broadcast cv */
1037 -
1038 1033 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB)
1039 1034
1040 1035 /*
1041 1036 * Debug printing
1042 1037 * Masks
1043 1038 */
1044 1039 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */
1045 1040 #define PRINT_MASK_LISTS 0x00000002 /* List management */
1046 1041 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */
1047 1042 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */
1048 1043 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */
1049 1044 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */
1050 1045 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */
1051 1046 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */
1052 1047 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */
1053 1048 #define PRINT_MASK_ALL 0xFFFFFFFF
1054 1049
1055 1050 #define PCI_VENDOR_NVIDIA 0x10de /* PCI Vendor-id NVIDIA */
1056 1051 #define PCI_DEVICE_NVIDIA_CK804 0x5b
1057 1052 #define PCI_DEVICE_NVIDIA_MCP04 0x3c
1058 1053 /*
1059 1054 * workaround for ALI chips
1060 1055 */
1061 1056 #define PCI_VENDOR_ALI 0x10b9 /* PCI Vendor-id Acer */
1062 1057
1063 1058 /*
1064 1059 * NEC on COMBO and Uli M1575 can support PM
1065 1060 */
1066 1061 #define PCI_VENDOR_NEC_COMBO 0x1033
1067 1062 #define PCI_DEVICE_NEC_COMBO 0xe0
1068 1063 #define PCI_VENDOR_ULi_M1575 0x10b9
1069 1064 #define PCI_DEVICE_ULi_M1575 0x5239
1070 1065
1071 1066 /*
1072 1067 * VIA chips have some problems, the workaround can ensure those chips
1073 1068 * work reliably. Revisions >= 0x80 are part of a southbridge and appear
1074 1069 * to be reliable.
1075 1070 */
1076 1071 #define PCI_VENDOR_VIA 0x1106 /* PCI Vendor-id VIA */
1077 1072 #define PCI_VIA_REVISION_6212 0x80 /* VIA 6212 revision ID */
1078 1073
1079 1074 #define EHCI_VIA_LOST_INTERRUPTS 0x01
1080 1075 #define EHCI_VIA_ASYNC_SCHEDULE 0x02
1081 1076 #define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04
1082 1077
1083 1078 #define EHCI_VIA_WORKAROUNDS \
1084 1079 (EHCI_VIA_LOST_INTERRUPTS | \
1085 1080 EHCI_VIA_ASYNC_SCHEDULE | \
1086 1081 EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE)
1087 1082
1088 1083 #define EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */
1089 1084
1090 1085
1091 1086 /*
1092 1087 * EHCI HCDI entry points
1093 1088 *
1094 1089 * The Host Controller Driver Interfaces (HCDI) are the software interfaces
1095 1090 * between the Universal Serial Bus Driver (USBA) and the Host Controller
1096 1091 * Driver (HCD). The HCDI interfaces or entry points are subject to change.
1097 1092 */
1098 1093 int ehci_hcdi_pipe_open(
1099 1094 usba_pipe_handle_data_t *ph,
1100 1095 usb_flags_t usb_flags);
1101 1096 int ehci_hcdi_pipe_close(
1102 1097 usba_pipe_handle_data_t *ph,
1103 1098 usb_flags_t usb_flags);
1104 1099 int ehci_hcdi_pipe_reset(
1105 1100 usba_pipe_handle_data_t *ph,
1106 1101 usb_flags_t usb_flags);
1107 1102 void ehci_hcdi_pipe_reset_data_toggle(
1108 1103 usba_pipe_handle_data_t *ph);
1109 1104 int ehci_hcdi_pipe_ctrl_xfer(
1110 1105 usba_pipe_handle_data_t *ph,
1111 1106 usb_ctrl_req_t *ctrl_reqp,
1112 1107 usb_flags_t usb_flags);
1113 1108 int ehci_hcdi_bulk_transfer_size(
1114 1109 usba_device_t *usba_device,
1115 1110 size_t *size);
1116 1111 int ehci_hcdi_pipe_bulk_xfer(
1117 1112 usba_pipe_handle_data_t *ph,
1118 1113 usb_bulk_req_t *bulk_reqp,
1119 1114 usb_flags_t usb_flags);
1120 1115 int ehci_hcdi_pipe_intr_xfer(
1121 1116 usba_pipe_handle_data_t *ph,
1122 1117 usb_intr_req_t *intr_req,
1123 1118 usb_flags_t usb_flags);
1124 1119 int ehci_hcdi_pipe_stop_intr_polling(
1125 1120 usba_pipe_handle_data_t *ph,
1126 1121 usb_flags_t usb_flags);
1127 1122 int ehci_hcdi_get_current_frame_number(
1128 1123 usba_device_t *usba_device,
1129 1124 usb_frame_number_t *frame_number);
1130 1125 int ehci_hcdi_get_max_isoc_pkts(
1131 1126 usba_device_t *usba_device,
1132 1127 uint_t *max_isoc_pkts_per_request);
1133 1128 int ehci_hcdi_pipe_isoc_xfer(
1134 1129 usba_pipe_handle_data_t *ph,
1135 1130 usb_isoc_req_t *isoc_reqp,
1136 1131 usb_flags_t usb_flags);
1137 1132 int ehci_hcdi_pipe_stop_isoc_polling(
1138 1133 usba_pipe_handle_data_t *ph,
1139 1134 usb_flags_t usb_flags);
1140 1135
1141 1136 /*
1142 1137 * EHCI Polled entry points function prototypes.
1143 1138 */
1144 1139 int ehci_hcdi_polled_input_init(
1145 1140 usba_pipe_handle_data_t *ph,
1146 1141 uchar_t **polled_buf,
1147 1142 usb_console_info_impl_t *info);
1148 1143 int ehci_hcdi_polled_input_enter(
1149 1144 usb_console_info_impl_t *info);
1150 1145 int ehci_hcdi_polled_read(
1151 1146 usb_console_info_impl_t *info,
1152 1147 uint_t *num_characters);
1153 1148 int ehci_hcdi_polled_input_exit(
1154 1149 usb_console_info_impl_t *info);
1155 1150 int ehci_hcdi_polled_input_fini(
1156 1151 usb_console_info_impl_t *info);
1157 1152 int ehci_hcdi_polled_output_init(
1158 1153 usba_pipe_handle_data_t *ph,
1159 1154 usb_console_info_impl_t *console_output_info);
1160 1155 int ehci_hcdi_polled_output_enter(
1161 1156 usb_console_info_impl_t *info);
1162 1157 int ehci_hcdi_polled_write(
1163 1158 usb_console_info_impl_t *info,
1164 1159 uchar_t *buf,
1165 1160 uint_t num_characters,
1166 1161 uint_t *num_characters_written);
1167 1162 int ehci_hcdi_polled_output_exit(
1168 1163 usb_console_info_impl_t *info);
1169 1164 int ehci_hcdi_polled_output_fini(
1170 1165 usb_console_info_impl_t *info);
1171 1166 /*
1172 1167 * EHCI Root Hub entry points function prototypes.
1173 1168 */
1174 1169 int ehci_init_root_hub(
1175 1170 ehci_state_t *ehcip);
1176 1171 int ehci_load_root_hub_driver(
1177 1172 ehci_state_t *ehcip);
1178 1173 int ehci_unload_root_hub_driver(
1179 1174 ehci_state_t *ehcip);
1180 1175 int ehci_handle_root_hub_pipe_open(
1181 1176 usba_pipe_handle_data_t *ph,
1182 1177 usb_flags_t flags);
1183 1178 int ehci_handle_root_hub_pipe_close(
1184 1179 usba_pipe_handle_data_t *ph);
1185 1180 int ehci_handle_root_hub_pipe_reset(
1186 1181 usba_pipe_handle_data_t *ph,
1187 1182 usb_flags_t flags);
1188 1183 int ehci_handle_root_hub_request(
1189 1184 ehci_state_t *ehcip,
1190 1185 usba_pipe_handle_data_t *ph,
1191 1186 usb_ctrl_req_t *ctrl_reqp);
1192 1187 int ehci_handle_root_hub_pipe_start_intr_polling(
1193 1188 usba_pipe_handle_data_t *ph,
1194 1189 usb_intr_req_t *intr_reqp,
1195 1190 usb_flags_t flags);
1196 1191 void ehci_handle_root_hub_pipe_stop_intr_polling(
1197 1192 usba_pipe_handle_data_t *ph,
1198 1193 usb_flags_t flags);
1199 1194
1200 1195 /*
1201 1196 * EHCI Interrupt Handler entry point.
1202 1197 */
1203 1198 uint_t ehci_intr(caddr_t arg1,
1204 1199 caddr_t arg2);
1205 1200
1206 1201 #ifdef __cplusplus
1207 1202 }
1208 1203 #endif
1209 1204
1210 1205 #endif /* _SYS_USB_EHCID_H */
|
↓ open down ↓ |
163 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX