1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 #ifndef _SYS_USB_EHCID_H
26 #define _SYS_USB_EHCID_H
27
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /*
34 * Enchanced Host Controller Driver (EHCI)
35 *
36 * The EHCI driver is a software driver which interfaces to the Universal
37 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to
38 * the Host Controller is defined by the EHCI Host Controller Interface.
39 *
40 * This header file describes the data structures and function prototypes
41 * required for the EHCI Driver to maintain state of Host Controller (HC),
42 * to perform different USB transfers and for the bandwidth allocations.
43 */
44
114
115 /* Endpoint descriptor pool */
116 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */
117 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */
118 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */
119 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */
120 uint_t ehci_dma_addr_bind_flag; /* DMA flag */
121
122 /* General transfer descriptor pool */
123 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */
124 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */
125 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */
126 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */
127
128 /* Isochronous transfer descriptor pool */
129 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */
130 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */
131 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */
132 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */
133
134 /* Condition variable for advance on Asynchronous Schedule */
135 kcondvar_t ehci_async_schedule_advance_cv;
136
137 /* Head of Asynchronous Schedule List */
138 ehci_qh_t *ehci_head_of_async_sched_list;
139
140 /*
141 * List of QTD inserted either into Asynchronous or Periodic
142 * Schedule lists.
143 */
144 ehci_qtd_t *ehci_active_qtd_list;
145 /*
146 * List of ITD active itd list.
147 */
148 ehci_itd_t *ehci_active_itd_list;
149
150 /*
151 * Bandwidth fields
152 *
153 * The ehci_bandwidth array keeps track of allocated bandwidth for
154 * ehci host controller. There are 32 bandwidth lists corresponding
155 * to 32 ms periodic frame lists. Each bandwidth list in turn will
156 * contain eight micro frame bandwidth lists.
1011 #define REQUEST_OFFSET 1
1012 #define VALUE_OFFSET 2
1013 #define INDEX_OFFSET 4
1014 #define LENGTH_OFFSET 6
1015
1016 #define TYPE_DEV_TO_HOST 0x80000000
1017 #define DEVICE 0x00000001
1018 #define CONFIGURATION 0x00000002
1019
1020 /*
1021 * The following are used in attach to indicate
1022 * what has been succesfully allocated, so detach
1023 * can remove them.
1024 */
1025 #define EHCI_ATTACH 0x01 /* ehci driver initilization */
1026 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */
1027 #define EHCI_INTR 0x04 /* Interrupt handler registered */
1028 #define EHCI_USBAREG 0x08 /* USBA registered */
1029 #define EHCI_RHREG 0x10 /* Root hub driver loaded */
1030
1031 /*
1032 * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase
1033 * the ehci_async_schedule_advance_cv when an intr occurs. It is used to
1034 * make sure that EHCI is receiving interrupts.
1035 */
1036 #define EHCI_CV_INTR 0x20 /* Ask INTR to broadcast cv */
1037
1038 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB)
1039
1040 /*
1041 * Debug printing
1042 * Masks
1043 */
1044 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */
1045 #define PRINT_MASK_LISTS 0x00000002 /* List management */
1046 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */
1047 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */
1048 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */
1049 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */
1050 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */
1051 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */
1052 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */
1053 #define PRINT_MASK_ALL 0xFFFFFFFF
1054
1055 #define PCI_VENDOR_NVIDIA 0x10de /* PCI Vendor-id NVIDIA */
1056 #define PCI_DEVICE_NVIDIA_CK804 0x5b
1057 #define PCI_DEVICE_NVIDIA_MCP04 0x3c
|
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * Copyright 2018 Nexenta Systems, Inc.
28 */
29
30 #ifndef _SYS_USB_EHCID_H
31 #define _SYS_USB_EHCID_H
32
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /*
39 * Enchanced Host Controller Driver (EHCI)
40 *
41 * The EHCI driver is a software driver which interfaces to the Universal
42 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to
43 * the Host Controller is defined by the EHCI Host Controller Interface.
44 *
45 * This header file describes the data structures and function prototypes
46 * required for the EHCI Driver to maintain state of Host Controller (HC),
47 * to perform different USB transfers and for the bandwidth allocations.
48 */
49
119
120 /* Endpoint descriptor pool */
121 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */
122 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */
123 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */
124 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */
125 uint_t ehci_dma_addr_bind_flag; /* DMA flag */
126
127 /* General transfer descriptor pool */
128 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */
129 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */
130 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */
131 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */
132
133 /* Isochronous transfer descriptor pool */
134 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */
135 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */
136 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */
137 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */
138
139 /* Head of Asynchronous Schedule List */
140 ehci_qh_t *ehci_head_of_async_sched_list;
141
142 /*
143 * List of QTD inserted either into Asynchronous or Periodic
144 * Schedule lists.
145 */
146 ehci_qtd_t *ehci_active_qtd_list;
147 /*
148 * List of ITD active itd list.
149 */
150 ehci_itd_t *ehci_active_itd_list;
151
152 /*
153 * Bandwidth fields
154 *
155 * The ehci_bandwidth array keeps track of allocated bandwidth for
156 * ehci host controller. There are 32 bandwidth lists corresponding
157 * to 32 ms periodic frame lists. Each bandwidth list in turn will
158 * contain eight micro frame bandwidth lists.
1013 #define REQUEST_OFFSET 1
1014 #define VALUE_OFFSET 2
1015 #define INDEX_OFFSET 4
1016 #define LENGTH_OFFSET 6
1017
1018 #define TYPE_DEV_TO_HOST 0x80000000
1019 #define DEVICE 0x00000001
1020 #define CONFIGURATION 0x00000002
1021
1022 /*
1023 * The following are used in attach to indicate
1024 * what has been succesfully allocated, so detach
1025 * can remove them.
1026 */
1027 #define EHCI_ATTACH 0x01 /* ehci driver initilization */
1028 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */
1029 #define EHCI_INTR 0x04 /* Interrupt handler registered */
1030 #define EHCI_USBAREG 0x08 /* USBA registered */
1031 #define EHCI_RHREG 0x10 /* Root hub driver loaded */
1032
1033 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB)
1034
1035 /*
1036 * Debug printing
1037 * Masks
1038 */
1039 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */
1040 #define PRINT_MASK_LISTS 0x00000002 /* List management */
1041 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */
1042 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */
1043 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */
1044 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */
1045 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */
1046 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */
1047 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */
1048 #define PRINT_MASK_ALL 0xFFFFFFFF
1049
1050 #define PCI_VENDOR_NVIDIA 0x10de /* PCI Vendor-id NVIDIA */
1051 #define PCI_DEVICE_NVIDIA_CK804 0x5b
1052 #define PCI_DEVICE_NVIDIA_MCP04 0x3c
|