1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * Copyright 2018 Nexenta Systems, Inc.
28 */
29
30 #ifndef _SYS_USB_EHCID_H
31 #define _SYS_USB_EHCID_H
32
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /*
39 * Enchanced Host Controller Driver (EHCI)
40 *
41 * The EHCI driver is a software driver which interfaces to the Universal
42 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to
43 * the Host Controller is defined by the EHCI Host Controller Interface.
44 *
45 * This header file describes the data structures and function prototypes
46 * required for the EHCI Driver to maintain state of Host Controller (HC),
47 * to perform different USB transfers and for the bandwidth allocations.
48 */
49
50 #include <sys/usb/hcd/ehci/ehci.h>
51 #include <sys/usb/hcd/ehci/ehci_hub.h>
52
53
54 /*
55 * EHCI Bandwidth Maintainence Structure.
56 *
57 * The ehci_bandwidth array keeps track of allocated bandwidth for ehci
58 * host controller. There are 32 bandwidth lists corresponding to 32 ms
59 * periodic frame lists. Each bandwidth list inturn will contain eight
60 * micro frame bandwidth lists.
61 */
62 #define EHCI_MAX_UFRAMES 8 /* Max uframes 125us per frame */
63
64 typedef struct ehci_frame_bandwidth {
65 uint_t ehci_allocated_frame_bandwidth;
66 uint_t ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES];
67 } ehci_frame_bandwidth_t;
68
69
70 /*
71 * EHCI Host Controller state structure
72 *
73 * The Host Controller Driver (HCD) maintains the state of Host Controller
74 * (HC). There is an ehci_state structure per instance of the EHCI
75 * host controller.
76 */
77 typedef struct ehci_state {
78 dev_info_t *ehci_dip; /* Dip of HC */
79 uint_t ehci_instance;
80 usba_hcdi_ops_t *ehci_hcdi_ops; /* HCDI structure */
81 uint_t ehci_flags; /* Used for cleanup */
82 uint16_t ehci_vendor_id; /* chip vendor */
83 uint16_t ehci_device_id; /* chip device */
84 uint8_t ehci_rev_id; /* chip revison */
85
86 ddi_acc_handle_t ehci_caps_handle; /* Caps Reg Handle */
87 ehci_caps_t *ehci_capsp; /* Capability Regs */
88 ehci_regs_t *ehci_regsp; /* Operational Regs */
89
90 ddi_acc_handle_t ehci_config_handle; /* Config space hndle */
91 uint_t ehci_frame_interval; /* Frme inter reg */
92 ddi_dma_attr_t ehci_dma_attr; /* DMA attributes */
93
94 ddi_intr_handle_t *ehci_htable; /* intr handle */
95 int ehci_intr_type; /* intr type used */
96 int ehci_intr_cnt; /* # of intrs inuse */
97 uint_t ehci_intr_pri; /* intr priority */
98 int ehci_intr_cap; /* intr capabilities */
99 boolean_t ehci_msi_enabled; /* default to true */
100 kmutex_t ehci_int_mutex; /* Global EHCI mutex */
101
102 /* Periodic Frame List area */
103 ehci_periodic_frame_list_t *ehci_periodic_frame_list_tablep;
104 /* Virtual Periodic Frame List ptr */
105 ddi_dma_cookie_t ehci_pflt_cookie; /* DMA cookie */
106 ddi_dma_handle_t ehci_pflt_dma_handle; /* DMA handle */
107 ddi_acc_handle_t ehci_pflt_mem_handle; /* Memory handle */
108
109 /*
110 * There are two pools of memory. One pool contains the memory for
111 * the transfer descriptors and other pool contains the memory for
112 * the endpoint descriptors. The advantage of the pools is that it's
113 * easy to go back and forth between the iommu and the cpu addresses.
114 *
115 * The pools are protected by the ehci_int_mutex because the memory
116 * in the pools may be accessed by either the host controller or the
117 * host controller driver.
118 */
119
120 /* Endpoint descriptor pool */
121 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */
122 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */
123 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */
124 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */
125 uint_t ehci_dma_addr_bind_flag; /* DMA flag */
126
127 /* General transfer descriptor pool */
128 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */
129 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */
130 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */
131 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */
132
133 /* Isochronous transfer descriptor pool */
134 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */
135 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */
136 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */
137 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */
138
139 /* Head of Asynchronous Schedule List */
140 ehci_qh_t *ehci_head_of_async_sched_list;
141
142 /*
143 * List of QTD inserted either into Asynchronous or Periodic
144 * Schedule lists.
145 */
146 ehci_qtd_t *ehci_active_qtd_list;
147 /*
148 * List of ITD active itd list.
149 */
150 ehci_itd_t *ehci_active_itd_list;
151
152 /*
153 * Bandwidth fields
154 *
155 * The ehci_bandwidth array keeps track of allocated bandwidth for
156 * ehci host controller. There are 32 bandwidth lists corresponding
157 * to 32 ms periodic frame lists. Each bandwidth list in turn will
158 * contain eight micro frame bandwidth lists.
159 *
160 * ehci_min_frame_bandwidth field indicates least allocated milli
161 * second bandwidth list.
162 */
163 ehci_frame_bandwidth_t ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS];
164
165 /* No. of open pipes, async qh, and periodic qh */
166 uint_t ehci_open_pipe_count;
167 uint_t ehci_open_async_count;
168 uint_t ehci_open_periodic_count;
169
170 /* No. of async and periodic requests */
171 uint_t ehci_async_req_count;
172 uint_t ehci_periodic_req_count;
173
174 /*
175 * Endpoint Reclamation List
176 *
177 * The interrupt list processing cannot be stopped when a periodic
178 * endpoint is removed from the list. The endpoints are detached
179 * from the interrupt lattice tree and put on to the reclaimation
180 * list. On next SOF interrupt all those endpoints, which are on
181 * the reclaimation list will be deallocated.
182 */
183 ehci_qh_t *ehci_reclaim_list; /* Reclaimation list */
184
185 ehci_root_hub_t ehci_root_hub; /* Root hub info */
186
187 /* Frame number overflow information */
188 usb_frame_number_t ehci_fno;
189
190 /* For host controller error counter */
191 uint_t ehci_hc_error;
192
193 /*
194 * ehci_missed_intr_sts is used to save the normal mode interrupt
195 * status information if an interrupt is pending for normal mode
196 * when polled code is entered.
197 */
198 uint_t ehci_missed_intr_sts;
199
200 /*
201 * Saved copy of the ehci registers of the normal mode & change
202 * required ehci registers values for the polled mode operation.
203 * Before returning from the polled mode to normal mode replace
204 * the required current registers with this saved ehci registers
205 * copy.
206 */
207 ehci_regs_t ehci_polled_save_regs;
208
209 /*
210 * Saved copy of the interrupt table used in normal ehci mode and
211 * replace this table by another interrupt table that used in the
212 * POLLED mode.
213 */
214 ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS];
215
216 /* ehci polled mode enter counter */
217 uint_t ehci_polled_enter_count;
218
219 /*
220 * counter for polled mode and used in suspend mode to see if
221 * there is a keyboard connected.
222 */
223 uint_t ehci_polled_kbd_count;
224
225 /* counter for polled read and use it to clean the interrupt status */
226 uint_t ehci_polled_read_count;
227
228 #if defined(__x86)
229 /* counter for polled root hub status */
230 uint_t ehci_polled_root_hub_count;
231 #endif /* __x86 */
232
233 /* EHCI Host Controller Software State information */
234 uint_t ehci_hc_soft_state;
235
236 /* Log handle for debug, console, log messages */
237 usb_log_handle_t ehci_log_hdl;
238
239 /* Kstat structures */
240 kstat_t *ehci_intrs_stats;
241 kstat_t *ehci_total_stats;
242 kstat_t *ehci_count_stats[USB_N_COUNT_KSTATS];
243 } ehci_state_t;
244
245 typedef struct ehci_intrs_stats {
246 struct kstat_named ehci_sts_async_sched_status;
247 struct kstat_named ehci_sts_periodic_sched_status;
248 struct kstat_named ehci_sts_empty_async_schedule;
249 struct kstat_named ehci_sts_host_ctrl_halted;
250 struct kstat_named ehci_sts_async_advance_intr;
251 struct kstat_named ehci_sts_host_system_error_intr;
252 struct kstat_named ehci_sts_frm_list_rollover_intr;
253 struct kstat_named ehci_sts_rh_port_change_intr;
254 struct kstat_named ehci_sts_usb_error_intr;
255 struct kstat_named ehci_sts_usb_intr;
256 struct kstat_named ehci_sts_not_claimed;
257 struct kstat_named ehci_sts_total;
258 } ehci_intrs_stats_t;
259
260 /*
261 * ehci kstat defines
262 */
263 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats)
264 #define EHCI_INTRS_STATS_DATA(ehci) \
265 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data)
266
267 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats)
268 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats))
269 #define EHCI_CTRL_STATS(ehci) \
270 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL]))
271 #define EHCI_BULK_STATS(ehci) \
272 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK]))
273 #define EHCI_INTR_STATS(ehci) \
274 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR]))
275 #define EHCI_ISOC_STATS(ehci) \
276 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH]))
277
278 /* warlock directives, stable data */
279 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t))
280 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri))
281 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip))
282 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp))
283 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance))
284 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id))
285 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id))
286 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id))
287
288 /* this may not be stable data in the future */
289 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr))
290 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle))
291 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie))
292 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr))
293 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle))
294 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie))
295 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr))
296 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle))
297 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie))
298 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag))
299 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl))
300
301 _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \
302 usba_pipe_handle_data::p_mutex \
303 usba_device::usb_mutex \
304 usba_ph_impl::usba_ph_mutex))
305
306 /*
307 * Host Contoller Software States
308 *
309 * EHCI_CTLR_INIT_STATE:
310 * The host controller soft state will be set to this during the
311 * ehci_attach.
312 *
313 * EHCI_CTLR_SUSPEND_STATE:
314 * The host controller soft state will be set to this during the
315 * ehci_cpr_suspend.
316 *
317 * EHCI_CTLR_OPERATIONAL_STATE:
318 * The host controller soft state will be set to this after moving
319 * host controller to operational state and host controller start
320 * generating SOF successfully.
321 *
322 * EHCI_CTLR_ERROR_STATE:
323 * The host controller soft state will be set to this during the
324 * no SOF or UE error conditions.
325 *
326 * Under this state or condition, only pipe stop polling, pipe reset
327 * and pipe close are allowed. But all other entry points like pipe
328 * open, get/set pipe policy, cotrol send/receive, bulk send/receive
329 * isoch send/receive, start polling etc. will fail.
330 *
331 * State Diagram for the host controller software state
332 *
333 *
334 * ehci_attach->[INIT_STATE]
335 * |
336 * | -------->----[ERROR_STATE]--<-----------<---
337 * | | Failure (UE/no SOF condition) |
338 * | ^ ^
339 * V | Success |
340 * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling
341 * ^ |
342 * | |
343 * | V
344 * -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend
345 */
346 #define EHCI_CTLR_INIT_STATE 0 /* Initilization state */
347 #define EHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */
348 #define EHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */
349 #define EHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */
350
351 /*
352 * Flags for initializatoin of host controller
353 */
354 #define EHCI_NORMAL_INITIALIZATION 0 /* Normal initialization */
355 #define EHCI_REINITIALIZATION 1 /* Re-initialization */
356
357 /*
358 * Periodic and non-periodic macros
359 */
360 #define EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
361 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\
362 ((endpoint->bmAttributes &\
363 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
364
365 #define EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
366 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\
367 ((endpoint->bmAttributes &\
368 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK))
369
370 #define EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
371 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
372
373 #define EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\
374 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR))
375
376
377 /*
378 * EHCI QH and QTD Pool sizes.
379 */
380 #define EHCI_QH_POOL_SIZE 100
381 #define EHCI_QTD_POOL_SIZE 200
382 #define EHCI_ITD_POOL_SIZE 200
383
384 /*
385 * ehci_dma_addr_bind_flag values
386 *
387 * This flag indicates if the various DMA addresses allocated by the EHCI
388 * have been bound to their respective handles. This is needed to recover
389 * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle()
390 */
391 #define EHCI_QTD_POOL_BOUND 0x01 /* For QTD pools */
392 #define EHCI_QH_POOL_BOUND 0x02 /* For QH pools */
393 #define EHCI_PFLT_DMA_BOUND 0x04 /* For Periodic Frame List area */
394 #define EHCI_ITD_POOL_BOUND 0x08 /* For QTD pools */
395
396 /*
397 * Maximum SOF wait count
398 */
399 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */
400
401 /*
402 * One uFrame 125 micro seconds
403 * One Frame 1 milli second or 8 uFrames
404 */
405 #define EHCI_uFRAMES_PER_USB_FRAME 8
406 #define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3
407
408
409 /*
410 * Pipe private structure
411 *
412 * There is an instance of this structure per pipe. This structure holds
413 * HCD specific pipe information. A pointer to this structure is kept in
414 * the USBA pipe handle (usba_pipe_handle_data_t).
415 */
416 typedef struct ehci_pipe_private {
417 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */
418 ehci_qh_t *pp_qh; /* Pipe's qh */
419
420 /* State of the pipe */
421 uint_t pp_state; /* See below */
422
423 /* Local copy of the pipe policy */
424 usb_pipe_policy_t pp_policy;
425
426 /* For Periodic Pipes Only */
427 uint_t pp_pnode; /* periodic node */
428 uchar_t pp_smask; /* Start split mask */
429 uchar_t pp_cmask; /* Comp split mask */
430 uint_t pp_cur_periodic_req_cnt; /* Curr req count */
431 uint_t pp_max_periodic_req_cnt; /* Max req count */
432
433 /* For Isochronous pipes only */
434 usb_frame_number_t pp_next_frame_number; /* Next frame no */
435
436 /*
437 * Each pipe may have multiple transfer wrappers. Each transfer
438 * wrapper represents a USB transfer on the bus. A transfer is
439 * made up of one or more transactions.
440 */
441 struct ehci_trans_wrapper *pp_tw_head; /* Head of the list */
442 struct ehci_trans_wrapper *pp_tw_tail; /* Tail of the list */
443
444 struct ehci_isoc_xwrapper *pp_itw_head; /* Head of the list */
445 struct ehci_isoc_xwrapper *pp_itw_tail; /* Tail of the list */
446
447 /*
448 * Pipe's transfer timeout handling & this transfer timeout handling
449 * will be per pipe.
450 */
451 struct ehci_trans_wrapper *pp_timeout_list; /* Timeout list */
452 timeout_id_t pp_timer_id; /* Timer id */
453
454 /* Done td count */
455 uint_t pp_count_done_qtds; /* Done td count */
456
457 /* Errors */
458 usb_cr_t pp_error; /* Pipe error */
459
460 /* Condition variable for transfers completion event */
461 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */
462
463 /* Pipe flag */
464 uint_t pp_flag; /* For polled mode */
465
466 /* Halting States */
467 uint_t pp_halt_state; /* Is it halting */
468
469 /* Condition variable for halt completion event */
470 kcondvar_t pp_halt_cmpl_cv; /* Xfer completion */
471
472 /*
473 * HCD gets Interrupt/Isochronous IN polling request only once and
474 * it has to insert next polling requests after completion of first
475 * request until either stop polling/pipe close is called. So HCD
476 * has to take copy of the original Interrupt/Isochronous IN request.
477 */
478 usb_opaque_t pp_client_periodic_in_reqp;
479 } ehci_pipe_private_t;
480
481 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t))
482
483 /*
484 * Pipe states
485 *
486 * ehci pipe states will be similar to usba. Refer usbai.h.
487 */
488 #define EHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */
489 #define EHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */
490 #define EHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */
491
492 /* Additional ehci pipe states for the ehci_pipe_cleanup */
493 #define EHCI_PIPE_STATE_CLOSE 4 /* Pipe close */
494 #define EHCI_PIPE_STATE_RESET 5 /* Pipe reset */
495 #define EHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */
496
497 /*
498 * Pipe flag
499 *
500 * For polled mode flag.
501 */
502 #define EHCI_POLLED_MODE_FLAG 1 /* Polled mode flag */
503
504 /* Pipe specific flags */
505 #define EHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */
506
507 /*
508 * Halting States
509 * prevent halting from interleaving.
510 */
511 #define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */
512 #define EHCI_HALT_STATE_HALTING 1 /* Currently Halting */
513
514 /*
515 * Request values for Clear_TT_Buffer
516 */
517 #define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \
518 USB_DEV_REQ_RCPT_OTHER)
519 #define EHCI_CLEAR_TT_BUFFER_BREQ 8
520
521 /*
522 * USB frame offset
523 *
524 * Add appropriate frame offset to the current usb frame number and use it
525 * as a starting frame number for a given usb isochronous request.
526 */
527 #define EHCI_FRAME_OFFSET 2 /* Frame offset */
528
529 /*
530 * Different interrupt polling intervals supported for high speed
531 * devices and its range must be from 1 to 16 units. This value is
532 * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval
533 * of 4 means a period of 8us (2 ^ (4-1)).
534 *
535 * The following values are defined after above convertion in terms
536 * 125us units.
537 */
538 #define EHCI_INTR_1US_POLL 1 /* 1us poll interval */
539 #define EHCI_INTR_2US_POLL 2 /* 2us poll interval */
540 #define EHCI_INTR_4US_POLL 4 /* 4us poll interval */
541 #define EHCI_INTR_XUS_POLL 8 /* 8us and above */
542
543 /*
544 * The following indecies are are used to calculate Start and complete
545 * masks as per the polling interval.
546 */
547 #define EHCI_1US_MASK_INDEX 14 /* 1us mask index */
548 #define EHCI_2US_MASK_INDEX 12 /* 2us mask index */
549 #define EHCI_4US_MASK_INDEX 8 /* 4us mask index */
550 #define EHCI_XUS_MASK_INDEX 0 /* 8us and above */
551
552 /*
553 * Different interrupt polling intervals supported for low/full/high
554 * speed devices. For high speed devices, the following values are
555 * applicable after convertion.
556 */
557 #define EHCI_INTR_1MS_POLL 1 /* 1ms poll interval */
558 #define EHCI_INTR_2MS_POLL 2 /* 2ms poll interval */
559 #define EHCI_INTR_4MS_POLL 4 /* 4ms poll interval */
560 #define EHCI_INTR_8MS_POLL 8 /* 8ms poll interval */
561 #define EHCI_INTR_16MS_POLL 16 /* 16ms poll interval */
562 #define EHCI_INTR_32MS_POLL 32 /* 32ms poll interval */
563
564 /*
565 * Number of interrupt transfer requests that should be maintained on
566 * the interrupt endpoint corresponding to different polling intervals
567 * supported.
568 */
569 #define EHCI_INTR_1MS_REQS 4 /* 1ms polling interval */
570 #define EHCI_INTR_2MS_REQS 2 /* 2ms polling interval */
571 #define EHCI_INTR_XMS_REQS 1 /* Between 4ms and 32ms */
572
573 /* Function prototype */
574 typedef void (*ehci_handler_function_t)(
575 ehci_state_t *ehcip,
576 ehci_pipe_private_t *pp,
577 struct ehci_trans_wrapper *tw,
578 ehci_qtd_t *qtd,
579 void *ehci_handle_callback_value);
580
581
582 /*
583 * Transfer wrapper
584 *
585 * The transfer wrapper represents a USB transfer on the bus and there
586 * is one instance per USB transfer. A transfer is made up of one or
587 * more transactions. EHCI uses one QTD for one transaction. So one
588 * transfer wrapper may have one or more QTDs associated.
589 *
590 * The data to be transferred are contained in the TW buffer which is
591 * virtually contiguous but physically discontiguous. When preparing
592 * the QTDs for a USB transfer, the DMA cookies corresponding to the
593 * TW buffer need to be walked through to retrieve the DMA addresses.
594 *
595 * Control and bulk pipes will have one transfer wrapper per transfer
596 * and where as Isochronous and Interrupt pipes will only have one
597 * transfer wrapper. The transfers wrapper are continually reused for
598 * the Interrupt and Isochronous pipes as those pipes are polled.
599 */
600 typedef struct ehci_trans_wrapper {
601 struct ehci_trans_wrapper *tw_next; /* Next wrapper */
602 ehci_pipe_private_t *tw_pipe_private; /* Back ptr */
603 ddi_dma_handle_t tw_dmahandle; /* DMA handle */
604 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */
605 ddi_dma_cookie_t tw_cookie; /* DMA cookie */
606 uint_t tw_ncookies; /* DMA cookie count */
607 uint_t tw_cookie_idx; /* DMA cookie index */
608 size_t tw_dma_offs; /* DMA buffer offset */
609 uint32_t tw_id; /* 32bit ID */
610 size_t tw_length; /* Txfer length */
611 char *tw_buf; /* Buffer for Xfer */
612 usb_flags_t tw_flags; /* Flags */
613 uint_t tw_num_qtds; /* Number of QTDs */
614 ehci_qtd_t *tw_qtd_head; /* Head QTD */
615 ehci_qtd_t *tw_qtd_tail; /* Tail QTD */
616 uint_t tw_direction; /* Direction of QTD */
617
618 /* Current transfer request pointer */
619 usb_opaque_t tw_curr_xfer_reqp;
620
621 /* Transfer timeout information */
622 int tw_timeout; /* Timeout value */
623 struct ehci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */
624
625 /*
626 * This is the function to call when this td is done. This way
627 * we don't have to look in the td to figure out what kind it is.
628 */
629 ehci_handler_function_t tw_handle_qtd;
630
631 /*
632 * This is the callback value used when processing a done td.
633 */
634 usb_opaque_t tw_handle_callback_value;
635
636 /* We preallocate all the td's for each tw and place them here */
637 ehci_qtd_t *tw_qtd_free_list;
638 ehci_qtd_t *tw_alt_qtd;
639 } ehci_trans_wrapper_t;
640
641 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper))
642
643 /*
644 * Isochronous Transfer Wrapper
645 *
646 * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed
647 * isochronous transfers. A transfer wrapper consists of one or more
648 * transactionsl, but there is one one instance per USB transfer request.
649 *
650 * The isochrnous transfer wrapper are continiously reused because these
651 * pipes are polled.
652 */
653 typedef struct ehci_isoc_xwrapper {
654 struct ehci_isoc_xwrapper *itw_next; /* Next wrapper in pp */
655 ehci_pipe_private_t *itw_pipe_private;
656
657 /* DMA and memory pointers */
658 ddi_dma_handle_t itw_dmahandle; /* DMA handle ETT */
659 ddi_acc_handle_t itw_accesshandle; /* Acc hndle */
660 ddi_dma_cookie_t itw_cookie; /* DMA cookie */
661
662 /* Transfer information */
663 char *itw_buf; /* Buffer for Xfer */
664 size_t itw_length; /* Txfer length */
665 usb_flags_t itw_flags; /* Flags */
666 usb_port_status_t itw_port_status; /* Port Speed */
667 uint_t itw_direction; /* Direction of ITD */
668
669 /* ITD information */
670 uint_t itw_num_itds; /* Number of ITDs */
671 ehci_itd_t *itw_itd_head; /* Head ITD */
672 ehci_itd_t *itw_itd_tail; /* Tail ITD */
673 usb_isoc_req_t *itw_curr_xfer_reqp;
674 usb_isoc_pkt_descr_t *itw_curr_isoc_pktp;
675
676 /* We preallocate all the td's for each tw and place them here */
677 ehci_itd_t *itw_itd_free_list;
678
679 /* Device and hub information needed by every iTD */
680 uint_t itw_hub_addr;
681 uint_t itw_hub_port;
682 uint_t itw_endpoint_num;
683 uint_t itw_device_addr;
684
685 /*
686 * Callback handling function and arguement. Called when an iTD is
687 * is done.
688 */
689 usb_opaque_t itw_handle_callback_value;
690
691 /* 32bit ID */
692 uint32_t itw_id;
693 } ehci_isoc_xwrapper_t;
694
695 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t))
696
697 /*
698 * Time waits for the different EHCI specific operations.
699 * These timeout values are specified in terms of microseconds.
700 */
701 #define EHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */
702 #define EHCI_TIMEWAIT 10000 /* HC any other waiting time */
703 #define EHCI_SOF_TIMEWAIT 20000 /* SOF Wait time */
704 #define EHCI_TAKEOVER_DELAY 10000 /* HC take over waiting time */
705 #define EHCI_TAKEOVER_WAIT_COUNT 25 /* HC take over waiting count */
706
707 /* These timeout values are specified in seconds */
708 #define EHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */
709 #define EHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */
710
711 /* EHCI flags for general use */
712 #define EHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */
713 #define EHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */
714 #define EHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */
715
716 /*
717 * Maximum allowable data transfer size per transaction as supported
718 * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96)
719 *
720 * Also within QTD, there will be five buffer pointers abd each buffer
721 * pointer can transfer upto 4k bytes of data.
722 */
723 #define EHCI_MAX_QTD_XFER_SIZE 0x5000 /* Maxmum data per transaction */
724 #define EHCI_MAX_QTD_BUF_SIZE 0x1000 /* Maxmum data per buffer */
725
726 /*
727 * The maximum allowable bulk data transfer size. It can be different
728 * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will
729 * take care of breaking a bulk data request into multiples of ehci
730 * EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this
731 * value is set to 640k bytes.
732 */
733 #define EHCI_MAX_BULK_XFER_SIZE 0xA0000 /* Maximum bulk transfer size */
734
735 /*
736 * Timeout flags
737 *
738 * These flags will be used to stop the timer before timeout handler
739 * gets executed.
740 */
741 #define EHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last QTD */
742 #define EHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */
743
744
745 /*
746 * High speed bandwidth allocation
747 *
748 * The following definitions are used during bandwidth calculations
749 * for a given high speed endpoint or high speed split transactions.
750 */
751 #define HS_BUS_BANDWIDTH 7500 /* Up to 7500 bytes per 125us */
752 #define HS_MAX_POLL_INTERVAL 16 /* Max high speed polling interval */
753 #define HS_MIN_POLL_INTERVAL 1 /* Min high speed polling interval */
754 #define HS_SOF 12 /* Length in bytes of High speed SOF */
755 #define HS_EOF 70 /* Length in bytes of High speed EOF */
756 #define TREE_HEIGHT 5 /* Log base 2 of 32 */
757
758 /*
759 * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved
760 * for the non-periodic high-speed transfers. Where as peridoic high-speed
761 * transfers will get 80% of the bus time. In one micro-frame or 125us, we
762 * can transfer 7500 bytes or 60,000 bits.
763 */
764 #define HS_NON_PERIODIC_BANDWIDTH 1500
765 #define HS_PERIODIC_BANDWIDTH (HS_BUS_BANDWIDTH - HS_SOF - \
766 HS_EOF - HS_NON_PERIODIC_BANDWIDTH)
767
768 /*
769 * High speed periodic frame bandwidth will be eight times the micro frame
770 * high speed periodic bandwidth.
771 */
772 #define HS_PERIODIC_FRAME_BANDWIDTH HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES
773
774 /*
775 * The following are the protocol overheads in terms of Bytes for the
776 * different transfer types. All these protocol overhead values are
777 * derived from the 5.11.3 section of USB 2.0 Specification.
778 */
779 #define HS_NON_ISOC_PROTO_OVERHEAD 55
780 #define HS_ISOC_PROTO_OVERHEAD 38
781
782 /*
783 * The following are THE protocol overheads in terms of Bytes for the
784 * start and complete split transactions tokens overheads. All these
785 * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3
786 * of USB2.0 Specification.
787 */
788 #define START_SPLIT_OVERHEAD 04
789 #define COMPLETE_SPLIT_OVERHEAD 04
790
791 /*
792 * The Host Controller (HC) delays are the USB host controller specific
793 * delays. The value shown below is the host controller delay for the
794 * given EHCI host controller.
795 */
796 #define EHCI_HOST_CONTROLLER_DELAY 18
797
798 /*
799 * Low/Full speed bandwidth allocation
800 *
801 * The following definitions are used during bandwidth calculations for
802 * a given high speed hub or a transaction translator (TT) and for a
803 * given low/full speed device connected to high speed hub or TT using
804 * split transactions
805 */
806 #define FS_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per 1ms */
807 #define FS_MAX_POLL_INTERVAL 255 /* Max full speed poll interval */
808 #define FS_MIN_POLL_INTERVAL 1 /* Min full speed polling interval */
809 #define FS_SOF 6 /* Length in bytes of Full speed SOF */
810 #define FS_EOF 4 /* Length in bytes of Full speed EOF */
811
812 /*
813 * Minimum polling interval for low speed endpoint
814 *
815 * According USB 2.0 Specification, a full-speed endpoint can specify
816 * a desired polling interval 1ms to 255ms and a low speed endpoints
817 * are limited to specifying only 10ms to 255ms. But some old keyboards
818 * and mice uses polling interval of 8ms. For compatibility purpose,
819 * we are using polling interval between 8ms and 255ms for low speed
820 * endpoints. The ehci driver will use 8ms polling interval if a low
821 * speed device reports a polling interval that is less than 8ms.
822 */
823 #define LS_MAX_POLL_INTERVAL 255 /* Max low speed poll interval */
824 #define LS_MIN_POLL_INTERVAL 8 /* Min low speed polling interval */
825
826 /*
827 * For non-periodic transfers, reserve atleast for one low-speed device
828 * transaction. According to USB Bandwidth Analysis white paper and also
829 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed
830 * transaction takes 0x628h full speed bits (197 bytes), which comes to
831 * around 13% of USB frame time.
832 *
833 * The periodic transfers will get around 87% of USB frame time.
834 */
835 #define FS_NON_PERIODIC_BANDWIDTH 197
836 #define FS_PERIODIC_BANDWIDTH (FS_BUS_BANDWIDTH - FS_SOF - \
837 FS_EOF - FS_NON_PERIODIC_BANDWIDTH)
838
839 /*
840 * The following are the protocol overheads in terms of Bytes for the
841 * different transfer types. All these protocol overhead values are
842 * derived from the 5.11.3 section of USB Specification and with the
843 * help of Bandwidth Analysis white paper which is posted on the USB
844 * developer forum.
845 */
846 #define FS_NON_ISOC_PROTO_OVERHEAD 14
847 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11
848 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10
849 #define LOW_SPEED_PROTO_OVERHEAD 97
850 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01
851
852 /* The maximum amount of isoch data that can be transferred in one uFrame */
853 #define MAX_UFRAME_SITD_XFER 188
854
855 /*
856 * The low speed clock below represents that to transmit one low-speed
857 * bit takes eight times more than one full speed bit time.
858 */
859 #define LOW_SPEED_CLOCK 8
860
861 /*
862 * The Transaction Translator (TT) delay is the additional time needed
863 * to execute low/full speed transaction from high speed split transaction
864 * for the low/full device connected to the high speed extrenal hub.
865 */
866 #define TT_DELAY 18
867
868
869 /*
870 * Macros for setting/getting information
871 */
872 #define Get_QH(addr) ddi_get32(ehcip->ehci_qh_pool_mem_handle, \
873 (uint32_t *)&addr)
874
875 #define Set_QH(addr, val) ddi_put32(ehcip->ehci_qh_pool_mem_handle, \
876 ((uint32_t *)&addr), \
877 ((int32_t)(val)))
878
879 #define Get_QTD(addr) ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \
880 (uint32_t *)&addr)
881
882 #define Set_QTD(addr, val) ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \
883 ((uint32_t *)&addr), \
884 ((int32_t)(val)))
885
886 #define Get_ITD(addr) ddi_get32(ehcip->ehci_itd_pool_mem_handle, \
887 (uint32_t *)&addr)
888
889 #define Set_ITD(addr, val) ddi_put32(ehcip->ehci_itd_pool_mem_handle, \
890 ((uint32_t *)&addr), \
891 ((int32_t)(val)))
892
893 #define Get_ITD_BODY(ptr, addr) ddi_get32( \
894 ehcip->ehci_itd_pool_mem_handle, \
895 (uint32_t *)&ptr->itd_body[addr])
896
897 #define Set_ITD_BODY(ptr, addr, val) ddi_put32( \
898 ehcip->ehci_itd_pool_mem_handle, \
899 ((uint32_t *)&ptr->itd_body[addr]),\
900 ((int32_t)(val)))
901
902 #define Get_ITD_INDEX(ptr, pos) ddi_get32( \
903 ehcip->ehci_itd_pool_mem_handle, \
904 (uint32_t *)&ptr->itd_index[pos])
905
906 #define Set_ITD_INDEX(ptr, pos, val) ddi_put32( \
907 ehcip->ehci_itd_pool_mem_handle, \
908 ((uint32_t *)&ptr->itd_index[pos]),\
909 ((uint32_t)(val)))
910
911 #define Get_ITD_FRAME(addr) ddi_get64( \
912 ehcip->ehci_itd_pool_mem_handle, \
913 (uint64_t *)&addr)
914
915 #define Set_ITD_FRAME(addr, val) ddi_put64( \
916 ehcip->ehci_itd_pool_mem_handle, \
917 ((uint64_t *)&addr), \
918 (val))
919
920 #define Get_PFLT(addr) ddi_get32(ehcip->ehci_pflt_mem_handle, \
921 (uint32_t *)&addr)
922
923 #define Set_PFLT(addr, val) ddi_put32(ehcip->ehci_pflt_mem_handle, \
924 ((uint32_t *)&addr), \
925 ((int32_t)(uintptr_t)(val)))
926
927 #define Get_8Cap(addr) ddi_get8(ehcip->ehci_caps_handle, \
928 (uint8_t *)&ehcip->ehci_capsp->addr)
929
930 #define Get_16Cap(addr) ddi_get16(ehcip->ehci_caps_handle, \
931 (uint16_t *)&ehcip->ehci_capsp->addr)
932
933 #define Get_Cap(addr) ddi_get32(ehcip->ehci_caps_handle, \
934 (uint32_t *)&ehcip->ehci_capsp->addr)
935
936 #define Get_OpReg(addr) ddi_get32(ehcip->ehci_caps_handle, \
937 (uint32_t *)&ehcip->ehci_regsp->addr)
938
939 #define Set_OpReg(addr, val) ddi_put32(ehcip->ehci_caps_handle, \
940 ((uint32_t *)&ehcip->ehci_regsp->addr), \
941 ((int32_t)(val)))
942
943 #define CalculateITDMultiField(pkgSize) (1 + (((pkgSize)>>11) & 0x03))
944
945 #define EHCI_MAX_RETRY 10
946
947 #define Set_OpRegRetry(addr, val, r) \
948 while (Get_OpReg(addr) != val) { \
949 if (r >= EHCI_MAX_RETRY) \
950 break; \
951 r++; \
952 Set_OpReg(addr, val); \
953 }
954
955 #define Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \
956 ehcip->ehci_qh_pool_dma_handle, \
957 0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \
958 DDI_DMA_SYNC_FORCPU); \
959 (void) ddi_dma_sync( \
960 ehcip->ehci_qtd_pool_dma_handle, \
961 0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \
962 DDI_DMA_SYNC_FORCPU);
963
964 #define Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \
965 ehcip->ehci_itd_pool_dma_handle, \
966 0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \
967 DDI_DMA_SYNC_FORCPU);
968
969 #define Sync_IO_Buffer(dma_handle, length) \
970 (void) ddi_dma_sync(dma_handle, \
971 0, length, DDI_DMA_SYNC_FORCPU);
972
973 #define Sync_IO_Buffer_for_device(dma_handle, length) \
974 (void) ddi_dma_sync(dma_handle, \
975 0, length, DDI_DMA_SYNC_FORDEV);
976
977 /*
978 * Macros to speed handling of 32bit IDs
979 */
980 #define EHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP)
981 #define EHCI_LOOKUP_ID(x) id32_lookup((x))
982 #define EHCI_FREE_ID(x) id32_free((x))
983
984
985 /*
986 * Miscellaneous definitions.
987 */
988
989 /* Data toggle bits */
990 #define DATA0 0
991 #define DATA1 1
992
993 /* Halt bit actions */
994 #define CLEAR_HALT 0
995 #define SET_HALT 1
996
997 typedef uint_t halt_bit_t;
998
999 /*
1000 * Setup Packet
1001 */
1002 typedef struct setup_pkt {
1003 uchar_t bmRequestType;
1004 uchar_t bRequest;
1005 ushort_t wValue;
1006 ushort_t wIndex;
1007 ushort_t wLength;
1008 }setup_pkt_t;
1009
1010 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */
1011
1012 #define REQUEST_TYPE_OFFSET 0
1013 #define REQUEST_OFFSET 1
1014 #define VALUE_OFFSET 2
1015 #define INDEX_OFFSET 4
1016 #define LENGTH_OFFSET 6
1017
1018 #define TYPE_DEV_TO_HOST 0x80000000
1019 #define DEVICE 0x00000001
1020 #define CONFIGURATION 0x00000002
1021
1022 /*
1023 * The following are used in attach to indicate
1024 * what has been succesfully allocated, so detach
1025 * can remove them.
1026 */
1027 #define EHCI_ATTACH 0x01 /* ehci driver initilization */
1028 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */
1029 #define EHCI_INTR 0x04 /* Interrupt handler registered */
1030 #define EHCI_USBAREG 0x08 /* USBA registered */
1031 #define EHCI_RHREG 0x10 /* Root hub driver loaded */
1032
1033 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB)
1034
1035 /*
1036 * Debug printing
1037 * Masks
1038 */
1039 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */
1040 #define PRINT_MASK_LISTS 0x00000002 /* List management */
1041 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */
1042 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */
1043 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */
1044 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */
1045 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */
1046 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */
1047 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */
1048 #define PRINT_MASK_ALL 0xFFFFFFFF
1049
1050 #define PCI_VENDOR_NVIDIA 0x10de /* PCI Vendor-id NVIDIA */
1051 #define PCI_DEVICE_NVIDIA_CK804 0x5b
1052 #define PCI_DEVICE_NVIDIA_MCP04 0x3c
1053 /*
1054 * workaround for ALI chips
1055 */
1056 #define PCI_VENDOR_ALI 0x10b9 /* PCI Vendor-id Acer */
1057
1058 /*
1059 * NEC on COMBO and Uli M1575 can support PM
1060 */
1061 #define PCI_VENDOR_NEC_COMBO 0x1033
1062 #define PCI_DEVICE_NEC_COMBO 0xe0
1063 #define PCI_VENDOR_ULi_M1575 0x10b9
1064 #define PCI_DEVICE_ULi_M1575 0x5239
1065
1066 /*
1067 * VIA chips have some problems, the workaround can ensure those chips
1068 * work reliably. Revisions >= 0x80 are part of a southbridge and appear
1069 * to be reliable.
1070 */
1071 #define PCI_VENDOR_VIA 0x1106 /* PCI Vendor-id VIA */
1072 #define PCI_VIA_REVISION_6212 0x80 /* VIA 6212 revision ID */
1073
1074 #define EHCI_VIA_LOST_INTERRUPTS 0x01
1075 #define EHCI_VIA_ASYNC_SCHEDULE 0x02
1076 #define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04
1077
1078 #define EHCI_VIA_WORKAROUNDS \
1079 (EHCI_VIA_LOST_INTERRUPTS | \
1080 EHCI_VIA_ASYNC_SCHEDULE | \
1081 EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE)
1082
1083 #define EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */
1084
1085
1086 /*
1087 * EHCI HCDI entry points
1088 *
1089 * The Host Controller Driver Interfaces (HCDI) are the software interfaces
1090 * between the Universal Serial Bus Driver (USBA) and the Host Controller
1091 * Driver (HCD). The HCDI interfaces or entry points are subject to change.
1092 */
1093 int ehci_hcdi_pipe_open(
1094 usba_pipe_handle_data_t *ph,
1095 usb_flags_t usb_flags);
1096 int ehci_hcdi_pipe_close(
1097 usba_pipe_handle_data_t *ph,
1098 usb_flags_t usb_flags);
1099 int ehci_hcdi_pipe_reset(
1100 usba_pipe_handle_data_t *ph,
1101 usb_flags_t usb_flags);
1102 void ehci_hcdi_pipe_reset_data_toggle(
1103 usba_pipe_handle_data_t *ph);
1104 int ehci_hcdi_pipe_ctrl_xfer(
1105 usba_pipe_handle_data_t *ph,
1106 usb_ctrl_req_t *ctrl_reqp,
1107 usb_flags_t usb_flags);
1108 int ehci_hcdi_bulk_transfer_size(
1109 usba_device_t *usba_device,
1110 size_t *size);
1111 int ehci_hcdi_pipe_bulk_xfer(
1112 usba_pipe_handle_data_t *ph,
1113 usb_bulk_req_t *bulk_reqp,
1114 usb_flags_t usb_flags);
1115 int ehci_hcdi_pipe_intr_xfer(
1116 usba_pipe_handle_data_t *ph,
1117 usb_intr_req_t *intr_req,
1118 usb_flags_t usb_flags);
1119 int ehci_hcdi_pipe_stop_intr_polling(
1120 usba_pipe_handle_data_t *ph,
1121 usb_flags_t usb_flags);
1122 int ehci_hcdi_get_current_frame_number(
1123 usba_device_t *usba_device,
1124 usb_frame_number_t *frame_number);
1125 int ehci_hcdi_get_max_isoc_pkts(
1126 usba_device_t *usba_device,
1127 uint_t *max_isoc_pkts_per_request);
1128 int ehci_hcdi_pipe_isoc_xfer(
1129 usba_pipe_handle_data_t *ph,
1130 usb_isoc_req_t *isoc_reqp,
1131 usb_flags_t usb_flags);
1132 int ehci_hcdi_pipe_stop_isoc_polling(
1133 usba_pipe_handle_data_t *ph,
1134 usb_flags_t usb_flags);
1135
1136 /*
1137 * EHCI Polled entry points function prototypes.
1138 */
1139 int ehci_hcdi_polled_input_init(
1140 usba_pipe_handle_data_t *ph,
1141 uchar_t **polled_buf,
1142 usb_console_info_impl_t *info);
1143 int ehci_hcdi_polled_input_enter(
1144 usb_console_info_impl_t *info);
1145 int ehci_hcdi_polled_read(
1146 usb_console_info_impl_t *info,
1147 uint_t *num_characters);
1148 int ehci_hcdi_polled_input_exit(
1149 usb_console_info_impl_t *info);
1150 int ehci_hcdi_polled_input_fini(
1151 usb_console_info_impl_t *info);
1152 int ehci_hcdi_polled_output_init(
1153 usba_pipe_handle_data_t *ph,
1154 usb_console_info_impl_t *console_output_info);
1155 int ehci_hcdi_polled_output_enter(
1156 usb_console_info_impl_t *info);
1157 int ehci_hcdi_polled_write(
1158 usb_console_info_impl_t *info,
1159 uchar_t *buf,
1160 uint_t num_characters,
1161 uint_t *num_characters_written);
1162 int ehci_hcdi_polled_output_exit(
1163 usb_console_info_impl_t *info);
1164 int ehci_hcdi_polled_output_fini(
1165 usb_console_info_impl_t *info);
1166 /*
1167 * EHCI Root Hub entry points function prototypes.
1168 */
1169 int ehci_init_root_hub(
1170 ehci_state_t *ehcip);
1171 int ehci_load_root_hub_driver(
1172 ehci_state_t *ehcip);
1173 int ehci_unload_root_hub_driver(
1174 ehci_state_t *ehcip);
1175 int ehci_handle_root_hub_pipe_open(
1176 usba_pipe_handle_data_t *ph,
1177 usb_flags_t flags);
1178 int ehci_handle_root_hub_pipe_close(
1179 usba_pipe_handle_data_t *ph);
1180 int ehci_handle_root_hub_pipe_reset(
1181 usba_pipe_handle_data_t *ph,
1182 usb_flags_t flags);
1183 int ehci_handle_root_hub_request(
1184 ehci_state_t *ehcip,
1185 usba_pipe_handle_data_t *ph,
1186 usb_ctrl_req_t *ctrl_reqp);
1187 int ehci_handle_root_hub_pipe_start_intr_polling(
1188 usba_pipe_handle_data_t *ph,
1189 usb_intr_req_t *intr_reqp,
1190 usb_flags_t flags);
1191 void ehci_handle_root_hub_pipe_stop_intr_polling(
1192 usba_pipe_handle_data_t *ph,
1193 usb_flags_t flags);
1194
1195 /*
1196 * EHCI Interrupt Handler entry point.
1197 */
1198 uint_t ehci_intr(caddr_t arg1,
1199 caddr_t arg2);
1200
1201 #ifdef __cplusplus
1202 }
1203 #endif
1204
1205 #endif /* _SYS_USB_EHCID_H */