263 #define EHCI_RH_PORT_ENABLE_CHANGE 0x00000008 /* Port enable change */
264 #define EHCI_RH_PORT_ENABLE 0x00000004 /* Port enable */
265 #define EHCI_RH_PORT_CONNECT_STS_CHANGE 0x00000002 /* Connect status change */
266 #define EHCI_RH_PORT_CONNECT_STATUS 0x00000001 /* Connect status */
267
268 /* Root hub port change bits mask */
269 #define EHCI_RH_PORT_CLEAR_MASK 0x0000002A /* Clear bits mask */
270
271
272 /*
273 * EHCI Extended Capability Registers
274 *
275 * Currently this register only specifies BIOS handoff information.
276 */
277 #define EHCI_EX_CAP_SPECIFICS 0xFFFF0000
278 #define EHCI_EX_CAP_SPECIFICS_SHIFT 16
279 #define EHCI_EX_CAP_NEXT_PTR 0x0000FF00
280 #define EHCI_EX_CAP_NEXT_PTR_SHIFT 8
281 #define EHCI_EX_CAP_ID 0x000000FF
282 #define EHCI_EX_CAP_ID_SHIFT 0
283 #define EHCI_EX_CAP_ID_BIOS_HANDOFF 1
284
285 #define EHCI_LEGSUP_OS_OWNED_SEM 0x01000000
286 #define EHCI_LEGSUP_BIOS_OWNED_SEM 0x00010000
287
288
289 /*
290 * Host Controller Periodic Frame List Area
291 *
292 * The Host Controller Periodic Frame List Area is a 4K structre of system
293 * memory that is established by the Host Controller Driver (HCD) and this
294 * structre is used for communication between HCD and HC. The HCD maintains
295 * a pointer to this structure in the Host Controller (HC). This structure
296 * must be aligned to a 4K boundary. There are 1024 periodic frame list
297 * entries.
298 */
299
300 #define EHCI_NUM_INTR_QH_LISTS 32 /* No of intr lists */
301 #define EHCI_NUM_STATIC_NODES 63 /* No of static QHs */
302 #define EHCI_NUM_PERIODIC_FRAME_LISTS 1024 /* No of entries */
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263 #define EHCI_RH_PORT_ENABLE_CHANGE 0x00000008 /* Port enable change */
264 #define EHCI_RH_PORT_ENABLE 0x00000004 /* Port enable */
265 #define EHCI_RH_PORT_CONNECT_STS_CHANGE 0x00000002 /* Connect status change */
266 #define EHCI_RH_PORT_CONNECT_STATUS 0x00000001 /* Connect status */
267
268 /* Root hub port change bits mask */
269 #define EHCI_RH_PORT_CLEAR_MASK 0x0000002A /* Clear bits mask */
270
271
272 /*
273 * EHCI Extended Capability Registers
274 *
275 * Currently this register only specifies BIOS handoff information.
276 */
277 #define EHCI_EX_CAP_SPECIFICS 0xFFFF0000
278 #define EHCI_EX_CAP_SPECIFICS_SHIFT 16
279 #define EHCI_EX_CAP_NEXT_PTR 0x0000FF00
280 #define EHCI_EX_CAP_NEXT_PTR_SHIFT 8
281 #define EHCI_EX_CAP_ID 0x000000FF
282 #define EHCI_EX_CAP_ID_SHIFT 0
283 #define EHCI_EX_CAP_ID_RESERVED 0
284 #define EHCI_EX_CAP_ID_BIOS_HANDOFF 1
285
286 #define EHCI_LEGSUP_OS_OWNED_SEM 0x01000000
287 #define EHCI_LEGSUP_BIOS_OWNED_SEM 0x00010000
288
289
290 /*
291 * Host Controller Periodic Frame List Area
292 *
293 * The Host Controller Periodic Frame List Area is a 4K structre of system
294 * memory that is established by the Host Controller Driver (HCD) and this
295 * structre is used for communication between HCD and HC. The HCD maintains
296 * a pointer to this structure in the Host Controller (HC). This structure
297 * must be aligned to a 4K boundary. There are 1024 periodic frame list
298 * entries.
299 */
300
301 #define EHCI_NUM_INTR_QH_LISTS 32 /* No of intr lists */
302 #define EHCI_NUM_STATIC_NODES 63 /* No of static QHs */
303 #define EHCI_NUM_PERIODIC_FRAME_LISTS 1024 /* No of entries */
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