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NEX-19691 Unsuccessful mpt_sas IOC reset leads to the panic in no I/O to the pool - days later
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
NEX-20282 Add disk target queue depth tunable to mpt_sas
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Rob Gittins <rob.gittins@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
9048 mpt_sas should not require targets to send SEP messages
Reviewed by: Dan McDonald <danmcd@joyent.com>
Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
Approved by: Gordon Ross <gwr@nexenta.com>
NEX-14838 Support 24 port version of SAS adapters
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-2100 vmem_hash_delete(ffffff5b5dee0000, 0, 1): bad free
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
Reviewed by: Marcel Telka <marcel@telka.sk>
NEX-3717 mptsas doesn't handle timeouts in mptsas_get_sata_guid()
Reviewed by: Gordon Ross <gordon.ross@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
NEX-2103 12G mpt_sas needs additional minor enhancements
Revert OS-73 do not do IO complettions in the ISR
NEX-1889 mpt_sas should support 12G HBAs
4500 mptsas_hash_traverse() is unsafe, leads to missing devices
Reviewed by: Hans Rosenfeld <hans.rosenfeld@nexenta.com>
Approved by: Albert Lee <trisk@nexenta.com>
backout 4500 mptsas_hash_traverse() is unsafe, leads to missing devices
4500 mptsas_hash_traverse() is unsafe, leads to missing devices
Reviewed by: Hans Rosenfeld <hans.rosenfeld@nexenta.com>
Approved by: Albert Lee <trisk@nexenta.com>
OS-73 do not do IO complettions in the ISR
OS-61 Need ability for fault injection in mptsas
OS-60 mptsas watchdog resolution considered way to long for accurate CMD timeouts.
OS-59 remove automated target removal mechanism from mpt_sas.
re #9517 rb4120 After single disk fault patch installed single disk fault still causes process hangs
re #8346 rb2639 KT disk failures
re #9636 rb2836 - mpt_sas should attempt an MUR reset at attach time.
--HG--
branch : stable-4.0
re #9636 rb2836 - mpt_sas should attempt an MUR reset at attach time.
re #6530 mpt_sas crash when more than 1 Initiator involved - ie HA
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 - * Copyright 2015 Nexenta Systems, Inc. All rights reserved.
24 + * Copyright 2017 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright (c) 2017, Joyent, Inc.
26 26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 27 */
28 28
29 29 /*
30 30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 31 * All rights reserved.
32 32 *
33 33 * Redistribution and use in source and binary forms of all code within
34 34 * this file that is exclusively owned by LSI, with or without
35 35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 36 * License requirements, the following conditions are met:
37 37 *
38 38 * Neither the name of the author nor the names of its contributors may be
39 39 * used to endorse or promote products derived from this software without
40 40 * specific prior written permission.
41 41 *
42 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
45 45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
46 46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
47 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
48 48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
49 49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
50 50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
51 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
52 52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
53 53 * DAMAGE.
54 54 */
55 55
56 56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
57 57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
58 58
59 59 #include <sys/byteorder.h>
60 60 #include <sys/queue.h>
61 61 #include <sys/isa_defs.h>
62 62 #include <sys/sunmdi.h>
63 63 #include <sys/mdi_impldefs.h>
64 64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
65 65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
66 66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
67 67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
68 68
69 69 #ifdef __cplusplus
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70 70 extern "C" {
71 71 #endif
72 72
73 73 /*
74 74 * Compile options
75 75 */
76 76 #ifdef DEBUG
77 77 #define MPTSAS_DEBUG /* turn on debugging code */
78 78 #endif /* DEBUG */
79 79
80 +
81 +#if defined(DEBUG) || lint
82 +#define MPTSAS_FAULTINJECTION
83 +#endif
84 +
80 85 #define MPTSAS_INITIAL_SOFT_SPACE 4
81 86
82 87 /*
83 88 * Note below macro definition and data type definition
84 89 * are used for phy mask handling, it should be changed
85 90 * simultaneously.
86 91 */
87 92 #define MPTSAS_MAX_PHYS 24
88 93 typedef uint32_t mptsas_phymask_t;
89 94
90 95 #define MPTSAS_INVALID_DEVHDL 0xffff
91 96 #define MPTSAS_SATA_GUID "sata-guid"
92 97
93 98 /*
94 99 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
95 100 * targets. There's no need to go overboard here, as the ordinary paths for
96 101 * I/O do not normally require hashed target lookups. These should be good
97 102 * enough and then some for any fabric within the hardware's capabilities.
98 103 */
99 104 #define MPTSAS_SMP_BUCKET_COUNT 23
100 105 #define MPTSAS_TARGET_BUCKET_COUNT 97
101 106 #define MPTSAS_TMP_TARGET_BUCKET_COUNT 13
102 107
103 108 /*
104 109 * MPT HW defines
105 110 */
106 111 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
107 112 #define MPTSAS_MAX_DISKS_IN_VOL 10
108 113 #define MPTSAS_MAX_HOTSPARES 2
109 114 #define MPTSAS_MAX_RAIDVOLS 2
110 115 #define MPTSAS_MAX_RAIDCONFIGS 5
111 116
112 117 /*
113 118 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
114 119 * plus two means the prefix 'w' and end of the string '\0'.
115 120 */
116 121 #define MPTSAS_WWN_STRLEN (16 + 2)
117 122 #define MPTSAS_MAX_GUID_LEN 64
118 123
119 124 /*
120 125 * DMA routine flags
121 126 */
122 127 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
123 128 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
124 129 #define MPTSAS_DMA_HANDLE_BOUND 0x8
125 130
126 131 /*
127 132 * If the HBA supports DMA or bus-mastering, you may have your own
128 133 * scatter-gather list for physically non-contiguous memory in one
129 134 * I/O operation; if so, there's probably a size for that list.
130 135 * It must be placed in the ddi_dma_lim_t structure, so that the system
131 136 * DMA-support routines can use it to break up the I/O request, so we
132 137 * define it here.
133 138 */
134 139 #if defined(__sparc)
135 140 #define MPTSAS_MAX_DMA_SEGS 1
136 141 #define MPTSAS_MAX_CMD_SEGS 1
137 142 #else
138 143 #define MPTSAS_MAX_DMA_SEGS 256
139 144 #define MPTSAS_MAX_CMD_SEGS 257
140 145 #endif
141 146 #define MPTSAS_MAX_FRAME_SGES(mpt) \
142 147 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
143 148
144 149 #define MPTSAS_SGE_SIZE(mpt) \
145 150 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \
146 151 sizeof (MPI2_SGE_SIMPLE64))
147 152
148 153 /*
149 154 * Calculating how many 64-bit DMA simple elements can be stored in the first
150 155 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
151 156 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
152 157 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
153 158 * (16 bytes).
154 159 */
155 160 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
156 161 ((mpt->m_req_frame_size - \
157 162 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
158 163 MPTSAS_SGE_SIZE(mpt))
159 164
160 165 /*
161 166 * Scatter-gather list structure defined by HBA hardware
162 167 */
163 168 typedef struct NcrTableIndirect { /* Table Indirect entries */
164 169 uint32_t count; /* 24 bit count */
165 170 union {
166 171 uint32_t address32; /* 32 bit address */
167 172 struct {
168 173 uint32_t Low;
169 174 uint32_t High;
170 175 } address64; /* 64 bit address */
171 176 } addr;
172 177 } mptti_t;
173 178
174 179 /*
175 180 * preferred pkt_private length in 64-bit quantities
176 181 */
177 182 #ifdef _LP64
178 183 #define PKT_PRIV_SIZE 2
179 184 #define PKT_PRIV_LEN 16 /* in bytes */
180 185 #else /* _ILP32 */
181 186 #define PKT_PRIV_SIZE 1
182 187 #define PKT_PRIV_LEN 8 /* in bytes */
183 188 #endif
184 189
185 190 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
186 191 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
187 192 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
188 193
189 194 /*
190 195 * get offset of item in structure
191 196 */
192 197 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
193 198
194 199 /*
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195 200 * WWID provided by LSI firmware is generated by firmware but the WWID is not
196 201 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
197 202 * address. According LSI's confirmation, the top nibble of RAID WWID is
198 203 * meanless, so the consensus between Solaris and OBP is to replace top nibble
199 204 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
200 205 * format unit address.
201 206 */
202 207 #define MPTSAS_RAID_WWID(wwid) \
203 208 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
204 209
210 +TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
211 +typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
212 +
205 213 typedef struct mptsas_target_addr {
206 214 uint64_t mta_wwn;
207 215 mptsas_phymask_t mta_phymask;
208 216 } mptsas_target_addr_t;
209 217
210 -TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
211 -typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
212 -
213 218 typedef struct mptsas_target {
214 219 mptsas_target_addr_t m_addr;
215 220 refhash_link_t m_link;
216 221 uint8_t m_dr_flag;
217 222 uint16_t m_devhdl;
218 223 uint32_t m_deviceinfo;
219 224 uint8_t m_phynum;
220 225 uint32_t m_dups;
221 226 mptsas_active_cmdq_t m_active_cmdq;
222 227 int32_t m_t_throttle;
223 228 int32_t m_t_ncmds;
224 229 int32_t m_reset_delay;
225 230 int32_t m_t_nwait;
226 231
227 232 uint16_t m_qfull_retry_interval;
228 233 uint8_t m_qfull_retries;
229 234 uint16_t m_io_flags;
230 235 uint16_t m_enclosure;
231 236 uint16_t m_slot_num;
232 237 uint32_t m_tgt_unconfigured;
233 - uint8_t m_led_status;
234 - uint8_t m_scsi_req_desc_type;
235 -
236 238 } mptsas_target_t;
237 239
238 240 /*
239 241 * If you change this structure, be sure that mptsas_smp_target_copy()
240 242 * does the right thing.
241 243 */
242 244 typedef struct mptsas_smp {
243 245 mptsas_target_addr_t m_addr;
244 246 refhash_link_t m_link;
245 247 uint16_t m_devhdl;
246 248 uint32_t m_deviceinfo;
247 249 uint16_t m_pdevhdl;
248 250 uint32_t m_pdevinfo;
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249 251 } mptsas_smp_t;
250 252
251 253 /*
252 254 * This represents a single enclosure. Targets point to an enclosure through
253 255 * their m_enclosure member.
254 256 */
255 257 typedef struct mptsas_enclosure {
256 258 list_node_t me_link;
257 259 uint16_t me_enchdl;
258 260 uint16_t me_flags;
261 + uint16_t me_nslots;
262 + uint16_t me_fslot;
263 + uint8_t *me_slotleds;
259 264 } mptsas_enclosure_t;
260 265
261 266 typedef struct mptsas_cache_frames {
262 267 ddi_dma_handle_t m_dma_hdl;
263 268 ddi_acc_handle_t m_acc_hdl;
264 269 caddr_t m_frames_addr;
265 270 uint64_t m_phys_addr;
266 271 } mptsas_cache_frames_t;
267 272
268 273 typedef struct mptsas_cmd {
269 274 uint_t cmd_flags; /* flags from scsi_init_pkt */
270 275 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
271 276 ddi_dma_cookie_t cmd_cookie;
272 277 uint_t cmd_cookiec;
273 278 uint_t cmd_winindex;
274 279 uint_t cmd_nwin;
275 280 uint_t cmd_cur_cookie;
276 281 off_t cmd_dma_offset;
277 282 size_t cmd_dma_len;
278 283 uint32_t cmd_totaldmacount;
279 284 caddr_t cmd_arq_buf;
280 285
281 286 int cmd_pkt_flags;
282 287
283 288 /* pending expiration time for command in active slot */
284 289 hrtime_t cmd_active_expiration;
285 290 TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
286 291
287 292 struct scsi_pkt *cmd_pkt;
288 293 struct scsi_arq_status cmd_scb;
289 294 uchar_t cmd_cdblen; /* length of cdb */
290 295 uchar_t cmd_rqslen; /* len of requested rqsense */
291 296 uchar_t cmd_privlen;
292 297 uint16_t cmd_extrqslen; /* len of extended rqsense */
293 298 uint16_t cmd_extrqschunks; /* len in map chunks */
294 299 uint16_t cmd_extrqsidx; /* Index into map */
295 300 uint_t cmd_scblen;
296 301 uint32_t cmd_dmacount;
297 302 uint64_t cmd_dma_addr;
298 303 uchar_t cmd_age;
299 304 ushort_t cmd_qfull_retries;
300 305 uchar_t cmd_queued; /* true if queued */
301 306 struct mptsas_cmd *cmd_linkp;
302 307 mptti_t *cmd_sg; /* Scatter/Gather structure */
303 308 uchar_t cmd_cdb[SCSI_CDB_SIZE];
304 309 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
305 310 uint32_t cmd_slot;
306 311 uint32_t ioc_cmd_slot;
307 312
308 313 mptsas_cache_frames_t *cmd_extra_frames;
309 314
310 315 uint32_t cmd_rfm;
311 316 mptsas_target_t *cmd_tgt_addr;
312 317 } mptsas_cmd_t;
313 318
314 319 /*
315 320 * These are the defined cmd_flags for this structure.
316 321 */
317 322 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
318 323 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
319 324 #define CFLAG_FINISHED 0x000004 /* command completed */
320 325 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
321 326 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
322 327 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
323 328 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
324 329 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
325 330 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
326 331 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
327 332 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
328 333 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
329 334 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
330 335 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
331 336 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
332 337 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
333 338 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
334 339 #define CFLAG_FREE 0x010000 /* packet is on free list */
335 340 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
336 341 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
337 342 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
338 343 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
339 344 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
340 345 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
341 346 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
342 347 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
343 348 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
344 349 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
345 350 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
346 351 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
347 352 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
348 353 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
349 354
350 355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
351 356 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
352 357 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
353 358 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
354 359 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
355 360 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
356 361 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
357 362 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
358 363 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
359 364 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
360 365 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
361 366
362 367 #define MPTSAS_HASH_ARRAY_SIZE 16
363 368 /*
364 369 * hash table definition
365 370 */
366 371
367 372 #define MPTSAS_HASH_FIRST 0xffff
368 373 #define MPTSAS_HASH_NEXT 0x0000
369 374
370 375 typedef struct mptsas_dma_alloc_state
371 376 {
372 377 ddi_dma_handle_t handle;
373 378 caddr_t memp;
374 379 size_t size;
375 380 ddi_acc_handle_t accessp;
376 381 ddi_dma_cookie_t cookie;
377 382 } mptsas_dma_alloc_state_t;
378 383
379 384 /*
380 385 * passthrough request structure
381 386 */
382 387 typedef struct mptsas_pt_request {
383 388 uint8_t *request;
384 389 uint32_t request_size;
385 390 uint32_t data_size;
386 391 uint32_t dataout_size;
387 392 uint32_t direction;
388 393 uint8_t simple;
389 394 uint16_t sgl_offset;
390 395 ddi_dma_cookie_t data_cookie;
391 396 ddi_dma_cookie_t dataout_cookie;
392 397 } mptsas_pt_request_t;
393 398
394 399 /*
395 400 * config page request structure
396 401 */
397 402 typedef struct mptsas_config_request {
398 403 uint32_t page_address;
399 404 uint8_t action;
400 405 uint8_t page_type;
401 406 uint8_t page_number;
402 407 uint8_t page_length;
403 408 uint8_t page_version;
404 409 uint8_t ext_page_type;
405 410 uint16_t ext_page_length;
406 411 } mptsas_config_request_t;
407 412
408 413 typedef struct mptsas_fw_diagnostic_buffer {
409 414 mptsas_dma_alloc_state_t buffer_data;
410 415 uint8_t extended_type;
411 416 uint8_t buffer_type;
412 417 uint8_t force_release;
413 418 uint32_t product_specific[23];
414 419 uint8_t immediate;
415 420 uint8_t enabled;
416 421 uint8_t valid_data;
417 422 uint8_t owned_by_firmware;
418 423 uint32_t unique_id;
419 424 } mptsas_fw_diagnostic_buffer_t;
420 425
421 426 /*
422 427 * FW diag request structure
423 428 */
424 429 typedef struct mptsas_diag_request {
425 430 mptsas_fw_diagnostic_buffer_t *pBuffer;
426 431 uint8_t function;
427 432 } mptsas_diag_request_t;
428 433
429 434 typedef struct mptsas_hash_node {
430 435 void *data;
431 436 struct mptsas_hash_node *next;
432 437 } mptsas_hash_node_t;
433 438
434 439 typedef struct mptsas_hash_table {
435 440 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
436 441 /*
437 442 * last position in traverse
438 443 */
439 444 struct mptsas_hash_node *cur;
440 445 uint16_t line;
441 446
442 447 } mptsas_hash_table_t;
443 448
444 449 /*
445 450 * RAID volume information
446 451 */
447 452 typedef struct mptsas_raidvol {
448 453 ushort_t m_israid;
449 454 uint16_t m_raidhandle;
450 455 uint64_t m_raidwwid;
451 456 uint8_t m_state;
452 457 uint32_t m_statusflags;
453 458 uint32_t m_settings;
454 459 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
455 460 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
456 461 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
457 462 uint64_t m_raidsize;
458 463 int m_raidlevel;
459 464 int m_ndisks;
460 465 mptsas_target_t *m_raidtgt;
461 466 } mptsas_raidvol_t;
462 467
463 468 /*
464 469 * RAID configurations
465 470 */
466 471 typedef struct mptsas_raidconfig {
467 472 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
468 473 uint16_t m_physdisk_devhdl[
469 474 MPTSAS_MAX_DISKS_IN_CONFIG];
470 475 uint8_t m_native;
471 476 } m_raidconfig_t;
472 477
473 478 /*
474 479 * Track outstanding commands. The index into the m_slot array is the SMID
475 480 * (system message ID) of the outstanding command. SMID 0 is reserved by the
476 481 * software/firmware protocol and is never used for any command we generate;
477 482 * as such, the assertion m_slot[0] == NULL is universally true. The last
478 483 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
479 484 * task management commands. No normal SCSI or ATA command will ever occupy
480 485 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any
481 486 * time that a consistent view of the target array is obtainable.
482 487 *
483 488 * As such, m_n_normal is the maximum number of slots available to ordinary
484 489 * commands, and the relationship:
485 490 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
486 491 * always holds after initialisation.
487 492 */
488 493 typedef struct mptsas_slots {
489 494 size_t m_size; /* size of struct, bytes */
490 495 uint_t m_n_normal; /* see above */
491 496 uint_t m_rotor; /* next slot idx to consider */
492 497 mptsas_cmd_t *m_slot[1];
493 498 } mptsas_slots_t;
494 499
495 500 /*
496 501 * Structure to hold command and packets for event ack
497 502 * and task management commands.
498 503 */
499 504 typedef struct m_event_struct {
500 505 struct mptsas_cmd m_event_cmd;
501 506 struct m_event_struct *m_event_linkp;
502 507 /*
503 508 * event member record the failure event and eventcntx
504 509 * event member would be used in send ack pending process
505 510 */
506 511 uint32_t m_event;
507 512 uint32_t m_eventcntx;
508 513 uint_t in_use;
509 514 struct scsi_pkt m_event_pkt; /* must be last */
510 515 /* ... scsi_pkt_size() */
511 516 } m_event_struct_t;
512 517 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
513 518 sizeof (struct scsi_pkt) + scsi_pkt_size())
514 519
515 520 #define MAX_IOC_COMMANDS 8
516 521
517 522 /*
518 523 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
519 524 * A new event ack command requests mptsas_cmd and scsi_pkt structures
520 525 * from this pool, and returns it back when done.
521 526 */
522 527
523 528 typedef struct m_replyh_arg {
524 529 void *mpt;
525 530 uint32_t rfm;
526 531 } m_replyh_arg_t;
527 532 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
528 533 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
529 534
530 535 /*
531 536 * Flags for DR handler topology change
532 537 */
533 538 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
534 539 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
535 540 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
536 541 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
537 542 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
538 543 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
539 544
540 545 typedef struct mptsas_topo_change_list {
541 546 void *mpt;
542 547 uint_t event;
543 548 union {
544 549 uint8_t physport;
545 550 mptsas_phymask_t phymask;
546 551 } un;
547 552 uint16_t devhdl;
548 553 void *object;
549 554 uint8_t flags;
550 555 struct mptsas_topo_change_list *next;
551 556 } mptsas_topo_change_list_t;
552 557
553 558
554 559 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
555 560 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
556 561 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
557 562 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
558 563 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
559 564 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
560 565
561 566 /*
562 567 * Status types when calling mptsas_get_target_device_info
563 568 */
564 569 #define DEV_INFO_SUCCESS 0x0
565 570 #define DEV_INFO_FAIL_PAGE0 0x1
566 571 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
567 572 #define DEV_INFO_PHYS_DISK 0x3
568 573 #define DEV_INFO_FAIL_ALLOC 0x4
569 574 #define DEV_INFO_FAIL_GUID 0x5
570 575
571 576 /*
572 577 * mpt hotplug event defines
573 578 */
574 579 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
575 580 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
576 581 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
577 582
578 583 /*
579 584 * SMP target hotplug events
580 585 */
581 586 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
582 587 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
583 588 #define MPTSAS_DR_EVENT_MASK 0x3F
584 589
585 590 /*
586 591 * mpt hotplug status definition for m_dr_flag
587 592 */
588 593
589 594 /*
590 595 * MPTSAS_DR_INACTIVE
591 596 *
592 597 * The target is in a normal operating state.
593 598 * No dynamic reconfiguration operation is in progress.
594 599 */
595 600 #define MPTSAS_DR_INACTIVE 0x0
596 601 /*
597 602 * MPTSAS_DR_INTRANSITION
598 603 *
599 604 * The target is in a transition mode since
600 605 * hotplug event happens and offline procedure has not
601 606 * been finished
602 607 */
603 608 #define MPTSAS_DR_INTRANSITION 0x1
604 609
605 610 typedef struct mptsas_tgt_private {
606 611 int t_lun;
607 612 struct mptsas_target *t_private;
608 613 } mptsas_tgt_private_t;
609 614
610 615 /*
611 616 * The following defines are used in mptsas_set_init_mode to track the current
612 617 * state as we progress through reprogramming the HBA from target mode into
613 618 * initiator mode.
614 619 */
615 620
616 621 #define IOUC_READ_PAGE0 0x00000100
617 622 #define IOUC_READ_PAGE1 0x00000200
618 623 #define IOUC_WRITE_PAGE1 0x00000400
619 624 #define IOUC_DONE 0x00000800
620 625 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
621 626 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
622 627
623 628 /*
624 629 * Last allocated slot is used for TM requests. Since only m_max_requests
625 630 * frames are allocated, the last SMID will be m_max_requests - 1.
626 631 */
627 632 #define MPTSAS_SLOTS_SIZE(mpt) \
628 633 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
629 634 mpt->m_max_requests))
630 635 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
631 636
632 637 /*
633 638 * Macro for phy_flags
634 639 */
635 640
636 641 typedef struct smhba_info {
637 642 kmutex_t phy_mutex;
638 643 uint8_t phy_id;
639 644 uint64_t sas_addr;
640 645 char path[8];
641 646 uint16_t owner_devhdl;
642 647 uint16_t attached_devhdl;
643 648 uint8_t attached_phy_identify;
644 649 uint32_t attached_phy_info;
645 650 uint8_t programmed_link_rate;
646 651 uint8_t hw_link_rate;
647 652 uint8_t change_count;
648 653 uint32_t phy_info;
649 654 uint8_t negotiated_link_rate;
650 655 uint8_t port_num;
651 656 kstat_t *phy_stats;
652 657 uint32_t invalid_dword_count;
653 658 uint32_t running_disparity_error_count;
654 659 uint32_t loss_of_dword_sync_count;
655 660 uint32_t phy_reset_problem_count;
656 661 void *mpt;
657 662 } smhba_info_t;
658 663
659 664 typedef struct mptsas_phy_info {
660 665 uint8_t port_num;
661 666 uint8_t port_flags;
662 667 uint16_t ctrl_devhdl;
663 668 uint32_t phy_device_type;
664 669 uint16_t attached_devhdl;
665 670 mptsas_phymask_t phy_mask;
666 671 smhba_info_t smhba_info;
667 672 } mptsas_phy_info_t;
668 673
669 674
670 675 typedef struct mptsas_doneq_thread_arg {
671 676 void *mpt;
672 677 uint64_t t;
673 678 } mptsas_doneq_thread_arg_t;
674 679
675 680 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
676 681 typedef struct mptsas_doneq_thread_list {
677 682 mptsas_cmd_t *doneq;
678 683 mptsas_cmd_t **donetail;
679 684 kthread_t *threadp;
680 685 kcondvar_t cv;
681 686 ushort_t reserv1;
682 687 uint32_t reserv2;
683 688 kmutex_t mutex;
684 689 uint32_t flag;
685 690 uint32_t len;
686 691 mptsas_doneq_thread_arg_t arg;
687 692 } mptsas_doneq_thread_list_t;
688 693
689 694 typedef struct mptsas {
690 695 int m_instance;
691 696
692 697 struct mptsas *m_next;
693 698
694 699 scsi_hba_tran_t *m_tran;
695 700 smp_hba_tran_t *m_smptran;
696 701 kmutex_t m_mutex;
697 702 kmutex_t m_passthru_mutex;
698 703 kcondvar_t m_cv;
699 704 kcondvar_t m_passthru_cv;
700 705 kcondvar_t m_fw_cv;
701 706 kcondvar_t m_config_cv;
702 707 kcondvar_t m_fw_diag_cv;
703 708 dev_info_t *m_dip;
704 709
705 710 /*
706 711 * soft state flags
707 712 */
708 713 uint_t m_softstate;
709 714
710 715 refhash_t *m_targets;
711 716 refhash_t *m_smp_targets;
712 717 list_t m_enclosures;
713 718 refhash_t *m_tmp_targets;
714 719
715 720 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
716 721 uint8_t m_num_raid_configs;
717 722
718 723 struct mptsas_slots *m_active; /* outstanding cmds */
719 724
720 725 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
721 726 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
722 727
723 728 kmutex_t m_tx_waitq_mutex;
724 729 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
725 730 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
726 731 int m_tx_draining; /* TX queue draining flag */
727 732
728 733 mptsas_cmd_t *m_doneq; /* queue of completed commands */
729 734 mptsas_cmd_t **m_donetail; /* queue tail ptr */
730 735
731 736 /*
732 737 * variables for helper threads (fan-out interrupts)
733 738 */
734 739 mptsas_doneq_thread_list_t *m_doneq_thread_id;
735 740 uint32_t m_doneq_thread_n;
736 741 uint32_t m_doneq_thread_threshold;
737 742 uint32_t m_doneq_length_threshold;
738 743 uint32_t m_doneq_len;
739 744 kcondvar_t m_doneq_thread_cv;
740 745 kmutex_t m_doneq_mutex;
741 746
742 747 int m_ncmds; /* number of outstanding commands */
743 748 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
744 749 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
745 750
746 751 ddi_acc_handle_t m_datap; /* operating regs data access handle */
747 752
748 753 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
749 754
750 755 ushort_t m_devid; /* device id of chip. */
751 756 uchar_t m_revid; /* revision of chip. */
752 757 uint16_t m_svid; /* subsystem Vendor ID of chip */
753 758 uint16_t m_ssid; /* subsystem Device ID of chip */
754 759
755 760 uchar_t m_sync_offset; /* default offset for this chip. */
756 761
757 762 timeout_id_t m_quiesce_timeid;
758 763
759 764 ddi_dma_handle_t m_dma_req_frame_hdl;
760 765 ddi_acc_handle_t m_acc_req_frame_hdl;
761 766 ddi_dma_handle_t m_dma_req_sense_hdl;
762 767 ddi_acc_handle_t m_acc_req_sense_hdl;
763 768 ddi_dma_handle_t m_dma_reply_frame_hdl;
764 769 ddi_acc_handle_t m_acc_reply_frame_hdl;
765 770 ddi_dma_handle_t m_dma_free_queue_hdl;
766 771 ddi_acc_handle_t m_acc_free_queue_hdl;
767 772 ddi_dma_handle_t m_dma_post_queue_hdl;
768 773 ddi_acc_handle_t m_acc_post_queue_hdl;
769 774
770 775 /*
771 776 * list of reset notification requests
772 777 */
773 778 struct scsi_reset_notify_entry *m_reset_notify_listf;
774 779
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775 780 /*
776 781 * qfull handling
777 782 */
778 783 timeout_id_t m_restart_cmd_timeid;
779 784
780 785 /*
781 786 * scsi reset delay per bus
782 787 */
783 788 uint_t m_scsi_reset_delay;
784 789
790 + /*
791 + * Tuneable for the throttle control
792 + */
793 + uint_t m_max_tune_throttle;
794 +
785 795 int m_pm_idle_delay;
786 796
787 797 uchar_t m_polled_intr; /* intr was polled. */
788 798 uchar_t m_suspended; /* true if driver is suspended */
789 799
790 800 struct kmem_cache *m_kmem_cache;
791 801 struct kmem_cache *m_cache_frames;
792 802
793 803 /*
794 804 * hba options.
795 805 */
796 806 uint_t m_options;
797 807
798 808 int m_in_callback;
799 809
800 810 int m_power_level; /* current power level */
801 811
802 812 int m_busy; /* power management busy state */
803 813
804 814 off_t m_pmcsr_offset; /* PMCSR offset */
805 815
806 816 ddi_acc_handle_t m_config_handle;
807 817
808 818 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
809 819 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
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810 820 ddi_device_acc_attr_t m_dev_acc_attr;
811 821 ddi_device_acc_attr_t m_reg_acc_attr;
812 822
813 823 /*
814 824 * request/reply variables
815 825 */
816 826 caddr_t m_req_frame;
817 827 uint64_t m_req_frame_dma_addr;
818 828 caddr_t m_req_sense;
819 829 caddr_t m_extreq_sense;
820 - uint_t m_extreq_sense_refcount;
821 - kcondvar_t m_extreq_sense_refcount_cv;
822 830 uint64_t m_req_sense_dma_addr;
823 831 caddr_t m_reply_frame;
824 832 uint64_t m_reply_frame_dma_addr;
825 833 caddr_t m_free_queue;
826 834 uint64_t m_free_queue_dma_addr;
827 835 caddr_t m_post_queue;
828 836 uint64_t m_post_queue_dma_addr;
829 837 struct map *m_erqsense_map;
830 838
831 839 m_replyh_arg_t *m_replyh_args;
832 840
833 841 uint16_t m_max_requests;
834 842 uint16_t m_req_frame_size;
835 843 uint16_t m_req_sense_size;
836 844
837 845 /*
838 846 * Max frames per request reprted in IOC Facts
839 847 */
840 848 uint8_t m_max_chain_depth;
841 849 /*
842 850 * Max frames per request which is used in reality. It's adjusted
843 851 * according DMA SG length attribute, and shall not exceed the
844 852 * m_max_chain_depth.
845 853 */
846 854 uint8_t m_max_request_frames;
847 855
848 856 uint16_t m_free_queue_depth;
849 857 uint16_t m_post_queue_depth;
850 858 uint16_t m_max_replies;
851 859 uint32_t m_free_index;
852 860 uint32_t m_post_index;
853 861 uint8_t m_reply_frame_size;
854 862 uint32_t m_ioc_capabilities;
855 863
856 864 /*
857 865 * indicates if the firmware was upload by the driver
858 866 * at boot time
859 867 */
860 868 ushort_t m_fwupload;
861 869
862 870 uint16_t m_productid;
863 871
864 872 /*
865 873 * per instance data structures for dma memory resources for
866 874 * MPI handshake protocol. only one handshake cmd can run at a time.
867 875 */
868 876 ddi_dma_handle_t m_hshk_dma_hdl;
869 877 ddi_acc_handle_t m_hshk_acc_hdl;
870 878 caddr_t m_hshk_memp;
871 879 size_t m_hshk_dma_size;
872 880
873 881 /* Firmware version on the card at boot time */
874 882 uint32_t m_fwversion;
875 883
876 884 /* MSI specific fields */
877 885 ddi_intr_handle_t *m_htable; /* For array of interrupts */
878 886 int m_intr_type; /* What type of interrupt */
879 887 int m_intr_cnt; /* # of intrs count returned */
880 888 size_t m_intr_size; /* Size of intr array */
881 889 uint_t m_intr_pri; /* Interrupt priority */
882 890 int m_intr_cap; /* Interrupt capabilities */
883 891 ddi_taskq_t *m_event_taskq;
884 892
885 893 /* SAS specific information */
886 894
887 895 union {
888 896 uint64_t m_base_wwid; /* Base WWID */
889 897 struct {
890 898 #ifdef _BIG_ENDIAN
891 899 uint32_t m_base_wwid_hi;
892 900 uint32_t m_base_wwid_lo;
893 901 #else
894 902 uint32_t m_base_wwid_lo;
895 903 uint32_t m_base_wwid_hi;
896 904 #endif
897 905 } sasaddr;
898 906 } un;
899 907
900 908 uint8_t m_num_phys; /* # of PHYs */
901 909 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
902 910 uint8_t m_port_chng; /* initiator port changes */
903 911 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
904 912 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
905 913
906 914 /* FMA Capabilities */
907 915 int m_fm_capabilities;
908 916 ddi_taskq_t *m_dr_taskq;
909 917 int m_mpxio_enable;
910 918 uint8_t m_done_traverse_dev;
911 919 uint8_t m_done_traverse_smp;
912 920 uint8_t m_done_traverse_enc;
913 921 int m_diag_action_in_progress;
914 922 uint16_t m_dev_handle;
915 923 uint16_t m_smp_devhdl;
916 924
917 925 /*
918 926 * Event recording
919 927 */
920 928 uint8_t m_event_index;
921 929 uint32_t m_event_number;
922 930 uint32_t m_event_mask[4];
923 931 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
924 932
925 933 /*
926 934 * FW diag Buffer List
927 935 */
928 936 mptsas_fw_diagnostic_buffer_t
929 937 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
930 938
931 939 /* GEN3 support */
932 940 uint8_t m_MPI25;
933 941
934 942 /*
935 943 * Event Replay flag (MUR support)
936 944 */
937 945 uint8_t m_event_replay;
938 946
939 947 /*
940 948 * IR Capable flag
941 949 */
942 950 uint8_t m_ir_capable;
943 951
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944 952 /*
945 953 * Is HBA processing a diag reset?
946 954 */
947 955 uint8_t m_in_reset;
948 956
949 957 /*
950 958 * per instance cmd data structures for task management cmds
951 959 */
952 960 m_event_struct_t m_event_task_mgmt; /* must be last */
953 961 /* ... scsi_pkt_size */
962 +
963 +#ifdef MPTSAS_FAULTINJECTION
964 + struct mptsas_active_cmdq m_fminj_cmdq;
965 +#endif
954 966 } mptsas_t;
955 967 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
956 968 sizeof (struct scsi_pkt) + scsi_pkt_size())
957 969 /*
958 970 * Only one of below two conditions is satisfied, we
959 971 * think the target is associated to the iport and
960 972 * allow call into mptsas_probe_lun().
961 973 * 1. physicalsport == physport
962 974 * 2. (phymask & (1 << physport)) == 0
963 975 * The condition #2 is because LSI uses lowest PHY
964 976 * number as the value of physical port when auto port
965 977 * configuration.
966 978 */
967 979 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
968 980 ((physicalport == physport) || (dynamicport && (phymask & \
969 981 (1 << physport))))
970 982
971 983 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
972 984 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
973 985 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
974 986 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
975 987 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
976 988 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
977 989 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
978 990 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
979 991 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
980 992
981 993 /*
982 994 * These should eventually migrate into the mpt header files
983 995 * that may become the /kernel/misc/mpt module...
984 996 */
985 997 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
986 998 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
987 999 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
988 1000 mptsas_put_msg_Function(hdl, mp, Function); \
989 1001 mptsas_put_msg_Lun(hdl, mp, Lun)
990 1002
991 1003 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
992 1004 ddi_put16(hdl, &(mp)->DevHandle, (val))
993 1005 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
994 1006 ddi_put8(hdl, &(mp)->ChainOffset, (val))
995 1007 #define mptsas_put_msg_Function(hdl, mp, val) \
996 1008 ddi_put8(hdl, &(mp)->Function, (val))
997 1009 #define mptsas_put_msg_Lun(hdl, mp, val) \
998 1010 ddi_put8(hdl, &(mp)->LUN[1], (val))
999 1011
1000 1012 #define mptsas_get_msg_Function(hdl, mp) \
1001 1013 ddi_get8(hdl, &(mp)->Function)
1002 1014
1003 1015 #define mptsas_get_msg_MsgFlags(hdl, mp) \
1004 1016 ddi_get8(hdl, &(mp)->MsgFlags)
1005 1017
1006 1018 #define MPTSAS_ENABLE_DRWE(hdl) \
1007 1019 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1008 1020 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
1009 1021 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1010 1022 MPI2_WRSEQ_1ST_KEY_VALUE); \
1011 1023 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1012 1024 MPI2_WRSEQ_2ND_KEY_VALUE); \
1013 1025 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1014 1026 MPI2_WRSEQ_3RD_KEY_VALUE); \
1015 1027 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1016 1028 MPI2_WRSEQ_4TH_KEY_VALUE); \
1017 1029 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1018 1030 MPI2_WRSEQ_5TH_KEY_VALUE); \
1019 1031 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1020 1032 MPI2_WRSEQ_6TH_KEY_VALUE);
1021 1033
1022 1034 /*
1023 1035 * m_options flags
1024 1036 */
1025 1037 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1026 1038
1027 1039 /*
1028 1040 * m_softstate flags
1029 1041 */
1030 1042 #define MPTSAS_SS_DRAINING 0x02
1031 1043 #define MPTSAS_SS_QUIESCED 0x04
1032 1044 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
1033 1045 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
1034 1046
1035 1047 /*
1036 1048 * regspec defines.
1037 1049 */
1038 1050 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1039 1051 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1040 1052 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1041 1053 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1042 1054
1043 1055 /*
1044 1056 * Handy constants
1045 1057 */
1046 1058 #define FALSE 0
1047 1059 #define TRUE 1
1048 1060 #define UNDEFINED -1
1049 1061 #define FAILED -2
1050 1062
1051 1063 /*
1052 1064 * power management.
1053 1065 */
1054 1066 #define MPTSAS_POWER_ON(mpt) { \
1055 1067 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1056 1068 PCI_PMCSR_D0); \
1057 1069 delay(drv_usectohz(10000)); \
1058 1070 (void) pci_restore_config_regs(mpt->m_dip); \
1059 1071 mptsas_setup_cmd_reg(mpt); \
1060 1072 }
1061 1073
1062 1074 #define MPTSAS_POWER_OFF(mpt) { \
1063 1075 (void) pci_save_config_regs(mpt->m_dip); \
1064 1076 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1065 1077 PCI_PMCSR_D3HOT); \
1066 1078 mpt->m_power_level = PM_LEVEL_D3; \
1067 1079 }
1068 1080
1069 1081 /*
1070 1082 * inq_dtype:
1071 1083 * Bits 5 through 7 are the Peripheral Device Qualifier
1072 1084 * 001b: device not connected to the LUN
1073 1085 * Bits 0 through 4 are the Peripheral Device Type
1074 1086 * 1fh: Unknown or no device type
1075 1087 *
1076 1088 * Although the inquiry may return success, the following value
1077 1089 * means no valid LUN connected.
1078 1090 */
1079 1091 #define MPTSAS_VALID_LUN(sd_inq) \
1080 1092 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1081 1093 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1082 1094
1083 1095 /*
1084 1096 * Default is to have 10 retries on receiving QFULL status and
1085 1097 * each retry to be after 100 ms.
1086 1098 */
1087 1099 #define QFULL_RETRIES 10
1088 1100 #define QFULL_RETRY_INTERVAL 100
1089 1101
1090 1102 /*
1091 1103 * Handy macros
1092 1104 */
1093 1105 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1094 1106 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1095 1107
1096 1108 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1097 1109 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1098 1110
1099 1111 /*
1100 1112 * poll time for mptsas_pollret() and mptsas_wait_intr()
1101 1113 */
1102 1114 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1103 1115
1104 1116 /*
1105 1117 * default time for mptsas_do_passthru
1106 1118 */
1107 1119 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1108 1120
1109 1121 /*
1110 1122 * macro to return the effective address of a given per-target field
1111 1123 */
1112 1124 #define EFF_ADDR(start, offset) ((start) + (offset))
1113 1125
1114 1126 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1115 1127 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1116 1128 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1117 1129 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1118 1130 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1119 1131
1120 1132
1121 1133 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1122 1134 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1123 1135 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1124 1136 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1125 1137
1126 1138 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1127 1139
1128 1140 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1129 1141 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1130 1142 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1131 1143 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1132 1144
1133 1145 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1134 1146 &(mpt)->m_reg->HostInterruptStatus))
1135 1147
1136 1148 #define MPTSAS_SET_SIGP(P) \
1137 1149 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1138 1150
1139 1151 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1140 1152 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1141 1153
1142 1154 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1143 1155 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1144 1156
1145 1157
1146 1158 #define MPTSAS_START_CMD(mpt, req_desc) \
1147 1159 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \
1148 1160 req_desc & 0xffffffffu); \
1149 1161 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \
1150 1162 (req_desc >> 32) & 0xffffffffu);
1151 1163
1152 1164 #define INTPENDING(mpt) \
1153 1165 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1154 1166
1155 1167 /*
1156 1168 * Mask all interrupts to disable
1157 1169 */
1158 1170 #define MPTSAS_DISABLE_INTR(mpt) \
1159 1171 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1160 1172 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1161 1173
1162 1174 /*
1163 1175 * Mask Doorbell and Reset interrupts to enable reply desc int.
1164 1176 */
1165 1177 #define MPTSAS_ENABLE_INTR(mpt) \
1166 1178 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1167 1179 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1168 1180
1169 1181 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1170 1182 &((uint64_t *)(void *)mpt->m_post_queue)[index]
1171 1183
1172 1184 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1173 1185 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1174 1186
1175 1187 #define ClrSetBits32(hdl, reg, clr, set) \
1176 1188 ddi_put32(hdl, (reg), \
1177 1189 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1178 1190
1179 1191 #define ClrSetBits(reg, clr, set) \
1180 1192 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1181 1193 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1182 1194
1183 1195 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1184 1196 if ((cmdp = mpt->m_waitq) != NULL) { \
1185 1197 /* If the queue is now empty fix the tail pointer */ \
1186 1198 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1187 1199 mpt->m_waitqtail = &mpt->m_waitq; \
1188 1200 cmdp->cmd_linkp = NULL; \
1189 1201 cmdp->cmd_queued = FALSE; \
1190 1202 }
1191 1203
1192 1204 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1193 1205 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1194 1206 /* If the queue is now empty fix the tail pointer */ \
1195 1207 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1196 1208 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1197 1209 cmdp->cmd_linkp = NULL; \
1198 1210 cmdp->cmd_queued = FALSE; \
1199 1211 }
1200 1212
1201 1213 /*
1202 1214 * defaults for the global properties
1203 1215 */
1204 1216 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1205 1217 #define DEFAULT_TAG_AGE_LIMIT 2
1206 1218 #define DEFAULT_WD_TICK 1
1207 1219
1208 1220 /*
1209 1221 * invalid hostid.
1210 1222 */
1211 1223 #define MPTSAS_INVALID_HOSTID -1
1212 1224
1213 1225 /*
1214 1226 * Get/Set hostid from SCSI port configuration page
1215 1227 */
1216 1228 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1217 1229 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1218 1230
1219 1231 /*
1220 1232 * Config space.
1221 1233 */
1222 1234 #define MPTSAS_LATENCY_TIMER 0x40
1223 1235
1224 1236 /*
1225 1237 * Offset to firmware version
1226 1238 */
1227 1239 #define MPTSAS_FW_VERSION_OFFSET 9
1228 1240
1229 1241 /*
1230 1242 * Offset and masks to get at the ProductId field
1231 1243 */
1232 1244 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1233 1245 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1234 1246 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1235 1247
1236 1248 /*
1237 1249 * Subsystem ID for HBAs.
1238 1250 */
1239 1251 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1240 1252 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1241 1253
1242 1254 /*
1243 1255 * reset delay tick
1244 1256 */
1245 1257 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1246 1258
1247 1259 /*
|
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284 lines elided |
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1248 1260 * Ioc reset return values
1249 1261 */
1250 1262 #define MPTSAS_RESET_FAIL -1
1251 1263 #define MPTSAS_NO_RESET 0
1252 1264 #define MPTSAS_SUCCESS_HARDRESET 1
1253 1265 #define MPTSAS_SUCCESS_MUR 2
1254 1266
1255 1267 /*
1256 1268 * throttle support.
1257 1269 */
1258 -#define MAX_THROTTLE 32
1270 +
1271 +#define THROTTLE_HI 4096
1272 +#define THROTTLE_LO 32
1273 +#define MAX_THROTTLE THROTTLE_LO
1259 1274 #define HOLD_THROTTLE 0
1260 1275 #define DRAIN_THROTTLE -1
1261 1276 #define QFULL_THROTTLE -2
1262 1277
1263 1278 /*
1264 1279 * Passthrough/config request flags
1265 1280 */
1266 1281 #define MPTSAS_DATA_ALLOCATED 0x0001
1267 1282 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1268 1283 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1269 1284 #define MPTSAS_ADDRESS_REPLY 0x0008
1270 1285 #define MPTSAS_CMD_TIMEOUT 0x0010
1271 1286
1272 1287 /*
1273 1288 * response code tlr flag
1274 1289 */
1275 1290 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1276 1291
1277 1292 /*
1278 1293 * System Events
1279 1294 */
1280 1295 #ifndef DDI_VENDOR_LSI
1281 1296 #define DDI_VENDOR_LSI "LSI"
1282 1297 #endif /* DDI_VENDOR_LSI */
1283 1298
1284 1299 /*
1285 1300 * Shared functions
1286 1301 */
1287 1302 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1288 1303 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1289 1304 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1290 1305 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1291 1306 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1292 1307 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1293 1308 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1294 1309 uint8_t type, int mode);
1295 1310 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1296 1311 uint8_t type, int mode);
1297 1312 int mptsas_download_firmware();
1298 1313 int mptsas_can_download_firmware();
1299 1314 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1300 1315 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1301 1316 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1302 1317 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1303 1318 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1304 1319 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1305 1320 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1306 1321 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1307 1322 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1308 1323 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1309 1324 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1310 1325
1311 1326 /*
1312 1327 * impl functions
1313 1328 */
1314 1329 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1315 1330 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1316 1331 int mptsas_ioc_reset(mptsas_t *mpt, int);
1317 1332 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1318 1333 ddi_acc_handle_t accessp);
1319 1334 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1320 1335 ddi_acc_handle_t accessp);
1321 1336 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1322 1337 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1323 1338 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1324 1339 uint64_t SGEaddress);
1325 1340 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1326 1341 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1327 1342 uint8_t pageversion, uint16_t extpagelength,
1328 1343 uint32_t SGEflagslength, uint64_t SGEaddress);
1329 1344
1330 1345 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1331 1346 struct scsi_pkt **pkt);
1332 1347 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1333 1348 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1334 1349 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1335 1350 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1336 1351 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1337 1352 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1338 1353
1339 1354 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1340 1355 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1341 1356 int mode);
1342 1357 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1343 1358 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1344 1359 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1345 1360 int mptsas_restart_ioc(mptsas_t *mpt);
1346 1361 void mptsas_update_driver_data(struct mptsas *mpt);
1347 1362 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1348 1363
1349 1364 /*
1350 1365 * init functions
1351 1366 */
1352 1367 int mptsas_ioc_get_facts(mptsas_t *mpt);
1353 1368 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1354 1369 int mptsas_ioc_enable_port(mptsas_t *mpt);
1355 1370 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1356 1371 int mptsas_ioc_init(mptsas_t *mpt);
1357 1372
1358 1373 /*
1359 1374 * configuration pages operation
1360 1375 */
1361 1376 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1362 1377 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1363 1378 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1364 1379 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
1365 1380 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1366 1381 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1367 1382 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1368 1383 mptsas_smp_t *info);
1369 1384 int mptsas_set_ioc_params(mptsas_t *mpt);
1370 1385 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1371 1386 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1372 1387 uint64_t *sas_wwn, uint8_t *portwidth);
1373 1388 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1374 1389 int mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1375 1390 smhba_info_t *info);
1376 1391 int mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1377 1392 smhba_info_t *info);
1378 1393 int mptsas_get_manufacture_page0(mptsas_t *mpt);
1379 1394 int mptsas_get_enclosure_page0(mptsas_t *mpt, uint32_t page_address,
1380 1395 mptsas_enclosure_t *mpe);
1381 1396 void mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1382 1397 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1383 1398 int mptsas_smhba_phy_init(mptsas_t *mpt);
1384 1399 /*
1385 1400 * RAID functions
1386 1401 */
1387 1402 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1388 1403 int mptsas_get_raid_info(mptsas_t *mpt);
1389 1404 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1390 1405 uint8_t physdisknum);
1391 1406 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1392 1407 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1393 1408
1394 1409 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1395 1410 /*
1396 1411 * debugging.
1397 1412 * MPTSAS_DBGLOG_LINECNT must be a power of 2.
1398 1413 */
1399 1414 #define MPTSAS_DBGLOG_LINECNT 128
1400 1415 #define MPTSAS_DBGLOG_LINELEN 256
1401 1416 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN)
1402 1417
1403 1418 #if defined(MPTSAS_DEBUG)
1404 1419
1405 1420 extern uint32_t mptsas_debugprt_flags;
1406 1421 extern uint32_t mptsas_debuglog_flags;
1407 1422
1408 1423 void mptsas_printf(char *fmt, ...);
1409 1424 void mptsas_debug_log(char *fmt, ...);
1410 1425
1411 1426 #define MPTSAS_DBGPR(m, args) \
1412 1427 if (mptsas_debugprt_flags & (m)) \
1413 1428 mptsas_printf args; \
1414 1429 if (mptsas_debuglog_flags & (m)) \
1415 1430 mptsas_debug_log args
1416 1431 #else /* ! defined(MPTSAS_DEBUG) */
1417 1432 #define MPTSAS_DBGPR(m, args)
1418 1433 #endif /* defined(MPTSAS_DEBUG) */
1419 1434
1420 1435 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1421 1436 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1422 1437 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1423 1438 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1424 1439
1425 1440 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1426 1441 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1427 1442 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1428 1443 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1429 1444
1430 1445 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1431 1446 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1432 1447 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1433 1448 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1434 1449
1435 1450 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1436 1451 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1437 1452 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1438 1453 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */
1439 1454
1440 1455 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */
1441 1456 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1442 1457 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1443 1458 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1444 1459
1445 1460 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1446 1461 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1447 1462 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1448 1463 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1449 1464
1450 1465 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1451 1466 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1452 1467 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1453 1468 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */
1454 1469
1455 1470 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1456 1471 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1457 1472 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1458 1473 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1459 1474
1460 1475 /*
1461 1476 * auto request sense
1462 1477 */
1463 1478 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1464 1479 (pkt)->pkt_flags = (flag), \
1465 1480 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1466 1481 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1467 1482 (pkt)->pkt_address.a_lun
1468 1483
1469 1484 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1470 1485 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1471 1486 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1472 1487 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1473 1488
1474 1489
1475 1490 #ifdef __cplusplus
1476 1491 }
1477 1492 #endif
1478 1493
1479 1494 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */
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