4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2015 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2017, Joyent, Inc.
26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 */
28
29 /*
30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms of all code within
34 * this file that is exclusively owned by LSI, with or without
35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 * License requirements, the following conditions are met:
37 *
38 * Neither the name of the author nor the names of its contributors may be
39 * used to endorse or promote products derived from this software without
40 * specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
60 #include <sys/queue.h>
61 #include <sys/isa_defs.h>
62 #include <sys/sunmdi.h>
63 #include <sys/mdi_impldefs.h>
64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
68
69 #ifdef __cplusplus
70 extern "C" {
71 #endif
72
73 /*
74 * Compile options
75 */
76 #ifdef DEBUG
77 #define MPTSAS_DEBUG /* turn on debugging code */
78 #endif /* DEBUG */
79
80 #define MPTSAS_INITIAL_SOFT_SPACE 4
81
82 /*
83 * Note below macro definition and data type definition
84 * are used for phy mask handling, it should be changed
85 * simultaneously.
86 */
87 #define MPTSAS_MAX_PHYS 24
88 typedef uint32_t mptsas_phymask_t;
89
90 #define MPTSAS_INVALID_DEVHDL 0xffff
91 #define MPTSAS_SATA_GUID "sata-guid"
92
93 /*
94 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
95 * targets. There's no need to go overboard here, as the ordinary paths for
96 * I/O do not normally require hashed target lookups. These should be good
97 * enough and then some for any fabric within the hardware's capabilities.
98 */
99 #define MPTSAS_SMP_BUCKET_COUNT 23
185 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
186 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
187 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
188
189 /*
190 * get offset of item in structure
191 */
192 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
193
194 /*
195 * WWID provided by LSI firmware is generated by firmware but the WWID is not
196 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
197 * address. According LSI's confirmation, the top nibble of RAID WWID is
198 * meanless, so the consensus between Solaris and OBP is to replace top nibble
199 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
200 * format unit address.
201 */
202 #define MPTSAS_RAID_WWID(wwid) \
203 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
204
205 typedef struct mptsas_target_addr {
206 uint64_t mta_wwn;
207 mptsas_phymask_t mta_phymask;
208 } mptsas_target_addr_t;
209
210 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
211 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
212
213 typedef struct mptsas_target {
214 mptsas_target_addr_t m_addr;
215 refhash_link_t m_link;
216 uint8_t m_dr_flag;
217 uint16_t m_devhdl;
218 uint32_t m_deviceinfo;
219 uint8_t m_phynum;
220 uint32_t m_dups;
221 mptsas_active_cmdq_t m_active_cmdq;
222 int32_t m_t_throttle;
223 int32_t m_t_ncmds;
224 int32_t m_reset_delay;
225 int32_t m_t_nwait;
226
227 uint16_t m_qfull_retry_interval;
228 uint8_t m_qfull_retries;
229 uint16_t m_io_flags;
230 uint16_t m_enclosure;
231 uint16_t m_slot_num;
232 uint32_t m_tgt_unconfigured;
233 uint8_t m_led_status;
234 uint8_t m_scsi_req_desc_type;
235
236 } mptsas_target_t;
237
238 /*
239 * If you change this structure, be sure that mptsas_smp_target_copy()
240 * does the right thing.
241 */
242 typedef struct mptsas_smp {
243 mptsas_target_addr_t m_addr;
244 refhash_link_t m_link;
245 uint16_t m_devhdl;
246 uint32_t m_deviceinfo;
247 uint16_t m_pdevhdl;
248 uint32_t m_pdevinfo;
249 } mptsas_smp_t;
250
251 /*
252 * This represents a single enclosure. Targets point to an enclosure through
253 * their m_enclosure member.
254 */
255 typedef struct mptsas_enclosure {
256 list_node_t me_link;
257 uint16_t me_enchdl;
258 uint16_t me_flags;
259 } mptsas_enclosure_t;
260
261 typedef struct mptsas_cache_frames {
262 ddi_dma_handle_t m_dma_hdl;
263 ddi_acc_handle_t m_acc_hdl;
264 caddr_t m_frames_addr;
265 uint64_t m_phys_addr;
266 } mptsas_cache_frames_t;
267
268 typedef struct mptsas_cmd {
269 uint_t cmd_flags; /* flags from scsi_init_pkt */
270 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
271 ddi_dma_cookie_t cmd_cookie;
272 uint_t cmd_cookiec;
273 uint_t cmd_winindex;
274 uint_t cmd_nwin;
275 uint_t cmd_cur_cookie;
276 off_t cmd_dma_offset;
277 size_t cmd_dma_len;
278 uint32_t cmd_totaldmacount;
765 ddi_dma_handle_t m_dma_free_queue_hdl;
766 ddi_acc_handle_t m_acc_free_queue_hdl;
767 ddi_dma_handle_t m_dma_post_queue_hdl;
768 ddi_acc_handle_t m_acc_post_queue_hdl;
769
770 /*
771 * list of reset notification requests
772 */
773 struct scsi_reset_notify_entry *m_reset_notify_listf;
774
775 /*
776 * qfull handling
777 */
778 timeout_id_t m_restart_cmd_timeid;
779
780 /*
781 * scsi reset delay per bus
782 */
783 uint_t m_scsi_reset_delay;
784
785 int m_pm_idle_delay;
786
787 uchar_t m_polled_intr; /* intr was polled. */
788 uchar_t m_suspended; /* true if driver is suspended */
789
790 struct kmem_cache *m_kmem_cache;
791 struct kmem_cache *m_cache_frames;
792
793 /*
794 * hba options.
795 */
796 uint_t m_options;
797
798 int m_in_callback;
799
800 int m_power_level; /* current power level */
801
802 int m_busy; /* power management busy state */
803
804 off_t m_pmcsr_offset; /* PMCSR offset */
805
806 ddi_acc_handle_t m_config_handle;
807
808 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
809 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
810 ddi_device_acc_attr_t m_dev_acc_attr;
811 ddi_device_acc_attr_t m_reg_acc_attr;
812
813 /*
814 * request/reply variables
815 */
816 caddr_t m_req_frame;
817 uint64_t m_req_frame_dma_addr;
818 caddr_t m_req_sense;
819 caddr_t m_extreq_sense;
820 uint_t m_extreq_sense_refcount;
821 kcondvar_t m_extreq_sense_refcount_cv;
822 uint64_t m_req_sense_dma_addr;
823 caddr_t m_reply_frame;
824 uint64_t m_reply_frame_dma_addr;
825 caddr_t m_free_queue;
826 uint64_t m_free_queue_dma_addr;
827 caddr_t m_post_queue;
828 uint64_t m_post_queue_dma_addr;
829 struct map *m_erqsense_map;
830
831 m_replyh_arg_t *m_replyh_args;
832
833 uint16_t m_max_requests;
834 uint16_t m_req_frame_size;
835 uint16_t m_req_sense_size;
836
837 /*
838 * Max frames per request reprted in IOC Facts
839 */
840 uint8_t m_max_chain_depth;
841 /*
934 /*
935 * Event Replay flag (MUR support)
936 */
937 uint8_t m_event_replay;
938
939 /*
940 * IR Capable flag
941 */
942 uint8_t m_ir_capable;
943
944 /*
945 * Is HBA processing a diag reset?
946 */
947 uint8_t m_in_reset;
948
949 /*
950 * per instance cmd data structures for task management cmds
951 */
952 m_event_struct_t m_event_task_mgmt; /* must be last */
953 /* ... scsi_pkt_size */
954 } mptsas_t;
955 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
956 sizeof (struct scsi_pkt) + scsi_pkt_size())
957 /*
958 * Only one of below two conditions is satisfied, we
959 * think the target is associated to the iport and
960 * allow call into mptsas_probe_lun().
961 * 1. physicalsport == physport
962 * 2. (phymask & (1 << physport)) == 0
963 * The condition #2 is because LSI uses lowest PHY
964 * number as the value of physical port when auto port
965 * configuration.
966 */
967 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
968 ((physicalport == physport) || (dynamicport && (phymask & \
969 (1 << physport))))
970
971 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
972 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
973 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
1238 */
1239 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1240 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1241
1242 /*
1243 * reset delay tick
1244 */
1245 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1246
1247 /*
1248 * Ioc reset return values
1249 */
1250 #define MPTSAS_RESET_FAIL -1
1251 #define MPTSAS_NO_RESET 0
1252 #define MPTSAS_SUCCESS_HARDRESET 1
1253 #define MPTSAS_SUCCESS_MUR 2
1254
1255 /*
1256 * throttle support.
1257 */
1258 #define MAX_THROTTLE 32
1259 #define HOLD_THROTTLE 0
1260 #define DRAIN_THROTTLE -1
1261 #define QFULL_THROTTLE -2
1262
1263 /*
1264 * Passthrough/config request flags
1265 */
1266 #define MPTSAS_DATA_ALLOCATED 0x0001
1267 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1268 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1269 #define MPTSAS_ADDRESS_REPLY 0x0008
1270 #define MPTSAS_CMD_TIMEOUT 0x0010
1271
1272 /*
1273 * response code tlr flag
1274 */
1275 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1276
1277 /*
1278 * System Events
|
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2017 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2017, Joyent, Inc.
26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 */
28
29 /*
30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms of all code within
34 * this file that is exclusively owned by LSI, with or without
35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 * License requirements, the following conditions are met:
37 *
38 * Neither the name of the author nor the names of its contributors may be
39 * used to endorse or promote products derived from this software without
40 * specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
60 #include <sys/queue.h>
61 #include <sys/isa_defs.h>
62 #include <sys/sunmdi.h>
63 #include <sys/mdi_impldefs.h>
64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
68
69 #ifdef __cplusplus
70 extern "C" {
71 #endif
72
73 /*
74 * Compile options
75 */
76 #ifdef DEBUG
77 #define MPTSAS_DEBUG /* turn on debugging code */
78 #endif /* DEBUG */
79
80
81 #if defined(DEBUG) || lint
82 #define MPTSAS_FAULTINJECTION
83 #endif
84
85 #define MPTSAS_INITIAL_SOFT_SPACE 4
86
87 /*
88 * Note below macro definition and data type definition
89 * are used for phy mask handling, it should be changed
90 * simultaneously.
91 */
92 #define MPTSAS_MAX_PHYS 24
93 typedef uint32_t mptsas_phymask_t;
94
95 #define MPTSAS_INVALID_DEVHDL 0xffff
96 #define MPTSAS_SATA_GUID "sata-guid"
97
98 /*
99 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
100 * targets. There's no need to go overboard here, as the ordinary paths for
101 * I/O do not normally require hashed target lookups. These should be good
102 * enough and then some for any fabric within the hardware's capabilities.
103 */
104 #define MPTSAS_SMP_BUCKET_COUNT 23
190 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
191 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
192 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
193
194 /*
195 * get offset of item in structure
196 */
197 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
198
199 /*
200 * WWID provided by LSI firmware is generated by firmware but the WWID is not
201 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
202 * address. According LSI's confirmation, the top nibble of RAID WWID is
203 * meanless, so the consensus between Solaris and OBP is to replace top nibble
204 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
205 * format unit address.
206 */
207 #define MPTSAS_RAID_WWID(wwid) \
208 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
209
210 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
211 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
212
213 typedef struct mptsas_target_addr {
214 uint64_t mta_wwn;
215 mptsas_phymask_t mta_phymask;
216 } mptsas_target_addr_t;
217
218 typedef struct mptsas_target {
219 mptsas_target_addr_t m_addr;
220 refhash_link_t m_link;
221 uint8_t m_dr_flag;
222 uint16_t m_devhdl;
223 uint32_t m_deviceinfo;
224 uint8_t m_phynum;
225 uint32_t m_dups;
226 mptsas_active_cmdq_t m_active_cmdq;
227 int32_t m_t_throttle;
228 int32_t m_t_ncmds;
229 int32_t m_reset_delay;
230 int32_t m_t_nwait;
231
232 uint16_t m_qfull_retry_interval;
233 uint8_t m_qfull_retries;
234 uint16_t m_io_flags;
235 uint16_t m_enclosure;
236 uint16_t m_slot_num;
237 uint32_t m_tgt_unconfigured;
238 } mptsas_target_t;
239
240 /*
241 * If you change this structure, be sure that mptsas_smp_target_copy()
242 * does the right thing.
243 */
244 typedef struct mptsas_smp {
245 mptsas_target_addr_t m_addr;
246 refhash_link_t m_link;
247 uint16_t m_devhdl;
248 uint32_t m_deviceinfo;
249 uint16_t m_pdevhdl;
250 uint32_t m_pdevinfo;
251 } mptsas_smp_t;
252
253 /*
254 * This represents a single enclosure. Targets point to an enclosure through
255 * their m_enclosure member.
256 */
257 typedef struct mptsas_enclosure {
258 list_node_t me_link;
259 uint16_t me_enchdl;
260 uint16_t me_flags;
261 uint16_t me_nslots;
262 uint16_t me_fslot;
263 uint8_t *me_slotleds;
264 } mptsas_enclosure_t;
265
266 typedef struct mptsas_cache_frames {
267 ddi_dma_handle_t m_dma_hdl;
268 ddi_acc_handle_t m_acc_hdl;
269 caddr_t m_frames_addr;
270 uint64_t m_phys_addr;
271 } mptsas_cache_frames_t;
272
273 typedef struct mptsas_cmd {
274 uint_t cmd_flags; /* flags from scsi_init_pkt */
275 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
276 ddi_dma_cookie_t cmd_cookie;
277 uint_t cmd_cookiec;
278 uint_t cmd_winindex;
279 uint_t cmd_nwin;
280 uint_t cmd_cur_cookie;
281 off_t cmd_dma_offset;
282 size_t cmd_dma_len;
283 uint32_t cmd_totaldmacount;
770 ddi_dma_handle_t m_dma_free_queue_hdl;
771 ddi_acc_handle_t m_acc_free_queue_hdl;
772 ddi_dma_handle_t m_dma_post_queue_hdl;
773 ddi_acc_handle_t m_acc_post_queue_hdl;
774
775 /*
776 * list of reset notification requests
777 */
778 struct scsi_reset_notify_entry *m_reset_notify_listf;
779
780 /*
781 * qfull handling
782 */
783 timeout_id_t m_restart_cmd_timeid;
784
785 /*
786 * scsi reset delay per bus
787 */
788 uint_t m_scsi_reset_delay;
789
790 /*
791 * Tuneable for the throttle control
792 */
793 uint_t m_max_tune_throttle;
794
795 int m_pm_idle_delay;
796
797 uchar_t m_polled_intr; /* intr was polled. */
798 uchar_t m_suspended; /* true if driver is suspended */
799
800 struct kmem_cache *m_kmem_cache;
801 struct kmem_cache *m_cache_frames;
802
803 /*
804 * hba options.
805 */
806 uint_t m_options;
807
808 int m_in_callback;
809
810 int m_power_level; /* current power level */
811
812 int m_busy; /* power management busy state */
813
814 off_t m_pmcsr_offset; /* PMCSR offset */
815
816 ddi_acc_handle_t m_config_handle;
817
818 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
819 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
820 ddi_device_acc_attr_t m_dev_acc_attr;
821 ddi_device_acc_attr_t m_reg_acc_attr;
822
823 /*
824 * request/reply variables
825 */
826 caddr_t m_req_frame;
827 uint64_t m_req_frame_dma_addr;
828 caddr_t m_req_sense;
829 caddr_t m_extreq_sense;
830 uint64_t m_req_sense_dma_addr;
831 caddr_t m_reply_frame;
832 uint64_t m_reply_frame_dma_addr;
833 caddr_t m_free_queue;
834 uint64_t m_free_queue_dma_addr;
835 caddr_t m_post_queue;
836 uint64_t m_post_queue_dma_addr;
837 struct map *m_erqsense_map;
838
839 m_replyh_arg_t *m_replyh_args;
840
841 uint16_t m_max_requests;
842 uint16_t m_req_frame_size;
843 uint16_t m_req_sense_size;
844
845 /*
846 * Max frames per request reprted in IOC Facts
847 */
848 uint8_t m_max_chain_depth;
849 /*
942 /*
943 * Event Replay flag (MUR support)
944 */
945 uint8_t m_event_replay;
946
947 /*
948 * IR Capable flag
949 */
950 uint8_t m_ir_capable;
951
952 /*
953 * Is HBA processing a diag reset?
954 */
955 uint8_t m_in_reset;
956
957 /*
958 * per instance cmd data structures for task management cmds
959 */
960 m_event_struct_t m_event_task_mgmt; /* must be last */
961 /* ... scsi_pkt_size */
962
963 #ifdef MPTSAS_FAULTINJECTION
964 struct mptsas_active_cmdq m_fminj_cmdq;
965 #endif
966 } mptsas_t;
967 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
968 sizeof (struct scsi_pkt) + scsi_pkt_size())
969 /*
970 * Only one of below two conditions is satisfied, we
971 * think the target is associated to the iport and
972 * allow call into mptsas_probe_lun().
973 * 1. physicalsport == physport
974 * 2. (phymask & (1 << physport)) == 0
975 * The condition #2 is because LSI uses lowest PHY
976 * number as the value of physical port when auto port
977 * configuration.
978 */
979 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
980 ((physicalport == physport) || (dynamicport && (phymask & \
981 (1 << physport))))
982
983 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
984 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
985 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
1250 */
1251 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1252 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1253
1254 /*
1255 * reset delay tick
1256 */
1257 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1258
1259 /*
1260 * Ioc reset return values
1261 */
1262 #define MPTSAS_RESET_FAIL -1
1263 #define MPTSAS_NO_RESET 0
1264 #define MPTSAS_SUCCESS_HARDRESET 1
1265 #define MPTSAS_SUCCESS_MUR 2
1266
1267 /*
1268 * throttle support.
1269 */
1270
1271 #define THROTTLE_HI 4096
1272 #define THROTTLE_LO 32
1273 #define MAX_THROTTLE THROTTLE_LO
1274 #define HOLD_THROTTLE 0
1275 #define DRAIN_THROTTLE -1
1276 #define QFULL_THROTTLE -2
1277
1278 /*
1279 * Passthrough/config request flags
1280 */
1281 #define MPTSAS_DATA_ALLOCATED 0x0001
1282 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1283 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1284 #define MPTSAS_ADDRESS_REPLY 0x0008
1285 #define MPTSAS_CMD_TIMEOUT 0x0010
1286
1287 /*
1288 * response code tlr flag
1289 */
1290 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1291
1292 /*
1293 * System Events
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