1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2017 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2017, Joyent, Inc.
26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 */
28
29 /*
30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms of all code within
34 * this file that is exclusively owned by LSI, with or without
35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 * License requirements, the following conditions are met:
37 *
38 * Neither the name of the author nor the names of its contributors may be
39 * used to endorse or promote products derived from this software without
40 * specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
53 * DAMAGE.
54 */
55
56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
58
59 #include <sys/byteorder.h>
60 #include <sys/queue.h>
61 #include <sys/isa_defs.h>
62 #include <sys/sunmdi.h>
63 #include <sys/mdi_impldefs.h>
64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
68
69 #ifdef __cplusplus
70 extern "C" {
71 #endif
72
73 /*
74 * Compile options
75 */
76 #ifdef DEBUG
77 #define MPTSAS_DEBUG /* turn on debugging code */
78 #endif /* DEBUG */
79
80
81 #if defined(DEBUG) || lint
82 #define MPTSAS_FAULTINJECTION
83 #endif
84
85 #define MPTSAS_INITIAL_SOFT_SPACE 4
86
87 /*
88 * Note below macro definition and data type definition
89 * are used for phy mask handling, it should be changed
90 * simultaneously.
91 */
92 #define MPTSAS_MAX_PHYS 24
93 typedef uint32_t mptsas_phymask_t;
94
95 #define MPTSAS_INVALID_DEVHDL 0xffff
96 #define MPTSAS_SATA_GUID "sata-guid"
97
98 /*
99 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
100 * targets. There's no need to go overboard here, as the ordinary paths for
101 * I/O do not normally require hashed target lookups. These should be good
102 * enough and then some for any fabric within the hardware's capabilities.
103 */
104 #define MPTSAS_SMP_BUCKET_COUNT 23
105 #define MPTSAS_TARGET_BUCKET_COUNT 97
106 #define MPTSAS_TMP_TARGET_BUCKET_COUNT 13
107
108 /*
109 * MPT HW defines
110 */
111 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
112 #define MPTSAS_MAX_DISKS_IN_VOL 10
113 #define MPTSAS_MAX_HOTSPARES 2
114 #define MPTSAS_MAX_RAIDVOLS 2
115 #define MPTSAS_MAX_RAIDCONFIGS 5
116
117 /*
118 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
119 * plus two means the prefix 'w' and end of the string '\0'.
120 */
121 #define MPTSAS_WWN_STRLEN (16 + 2)
122 #define MPTSAS_MAX_GUID_LEN 64
123
124 /*
125 * DMA routine flags
126 */
127 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
128 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
129 #define MPTSAS_DMA_HANDLE_BOUND 0x8
130
131 /*
132 * If the HBA supports DMA or bus-mastering, you may have your own
133 * scatter-gather list for physically non-contiguous memory in one
134 * I/O operation; if so, there's probably a size for that list.
135 * It must be placed in the ddi_dma_lim_t structure, so that the system
136 * DMA-support routines can use it to break up the I/O request, so we
137 * define it here.
138 */
139 #if defined(__sparc)
140 #define MPTSAS_MAX_DMA_SEGS 1
141 #define MPTSAS_MAX_CMD_SEGS 1
142 #else
143 #define MPTSAS_MAX_DMA_SEGS 256
144 #define MPTSAS_MAX_CMD_SEGS 257
145 #endif
146 #define MPTSAS_MAX_FRAME_SGES(mpt) \
147 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
148
149 #define MPTSAS_SGE_SIZE(mpt) \
150 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \
151 sizeof (MPI2_SGE_SIMPLE64))
152
153 /*
154 * Calculating how many 64-bit DMA simple elements can be stored in the first
155 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
156 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
157 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
158 * (16 bytes).
159 */
160 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
161 ((mpt->m_req_frame_size - \
162 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
163 MPTSAS_SGE_SIZE(mpt))
164
165 /*
166 * Scatter-gather list structure defined by HBA hardware
167 */
168 typedef struct NcrTableIndirect { /* Table Indirect entries */
169 uint32_t count; /* 24 bit count */
170 union {
171 uint32_t address32; /* 32 bit address */
172 struct {
173 uint32_t Low;
174 uint32_t High;
175 } address64; /* 64 bit address */
176 } addr;
177 } mptti_t;
178
179 /*
180 * preferred pkt_private length in 64-bit quantities
181 */
182 #ifdef _LP64
183 #define PKT_PRIV_SIZE 2
184 #define PKT_PRIV_LEN 16 /* in bytes */
185 #else /* _ILP32 */
186 #define PKT_PRIV_SIZE 1
187 #define PKT_PRIV_LEN 8 /* in bytes */
188 #endif
189
190 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
191 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
192 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
193
194 /*
195 * get offset of item in structure
196 */
197 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
198
199 /*
200 * WWID provided by LSI firmware is generated by firmware but the WWID is not
201 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
202 * address. According LSI's confirmation, the top nibble of RAID WWID is
203 * meanless, so the consensus between Solaris and OBP is to replace top nibble
204 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
205 * format unit address.
206 */
207 #define MPTSAS_RAID_WWID(wwid) \
208 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
209
210 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
211 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
212
213 typedef struct mptsas_target_addr {
214 uint64_t mta_wwn;
215 mptsas_phymask_t mta_phymask;
216 } mptsas_target_addr_t;
217
218 typedef struct mptsas_target {
219 mptsas_target_addr_t m_addr;
220 refhash_link_t m_link;
221 uint8_t m_dr_flag;
222 uint16_t m_devhdl;
223 uint32_t m_deviceinfo;
224 uint8_t m_phynum;
225 uint32_t m_dups;
226 mptsas_active_cmdq_t m_active_cmdq;
227 int32_t m_t_throttle;
228 int32_t m_t_ncmds;
229 int32_t m_reset_delay;
230 int32_t m_t_nwait;
231
232 uint16_t m_qfull_retry_interval;
233 uint8_t m_qfull_retries;
234 uint16_t m_io_flags;
235 uint16_t m_enclosure;
236 uint16_t m_slot_num;
237 uint32_t m_tgt_unconfigured;
238 } mptsas_target_t;
239
240 /*
241 * If you change this structure, be sure that mptsas_smp_target_copy()
242 * does the right thing.
243 */
244 typedef struct mptsas_smp {
245 mptsas_target_addr_t m_addr;
246 refhash_link_t m_link;
247 uint16_t m_devhdl;
248 uint32_t m_deviceinfo;
249 uint16_t m_pdevhdl;
250 uint32_t m_pdevinfo;
251 } mptsas_smp_t;
252
253 /*
254 * This represents a single enclosure. Targets point to an enclosure through
255 * their m_enclosure member.
256 */
257 typedef struct mptsas_enclosure {
258 list_node_t me_link;
259 uint16_t me_enchdl;
260 uint16_t me_flags;
261 uint16_t me_nslots;
262 uint16_t me_fslot;
263 uint8_t *me_slotleds;
264 } mptsas_enclosure_t;
265
266 typedef struct mptsas_cache_frames {
267 ddi_dma_handle_t m_dma_hdl;
268 ddi_acc_handle_t m_acc_hdl;
269 caddr_t m_frames_addr;
270 uint64_t m_phys_addr;
271 } mptsas_cache_frames_t;
272
273 typedef struct mptsas_cmd {
274 uint_t cmd_flags; /* flags from scsi_init_pkt */
275 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
276 ddi_dma_cookie_t cmd_cookie;
277 uint_t cmd_cookiec;
278 uint_t cmd_winindex;
279 uint_t cmd_nwin;
280 uint_t cmd_cur_cookie;
281 off_t cmd_dma_offset;
282 size_t cmd_dma_len;
283 uint32_t cmd_totaldmacount;
284 caddr_t cmd_arq_buf;
285
286 int cmd_pkt_flags;
287
288 /* pending expiration time for command in active slot */
289 hrtime_t cmd_active_expiration;
290 TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
291
292 struct scsi_pkt *cmd_pkt;
293 struct scsi_arq_status cmd_scb;
294 uchar_t cmd_cdblen; /* length of cdb */
295 uchar_t cmd_rqslen; /* len of requested rqsense */
296 uchar_t cmd_privlen;
297 uint16_t cmd_extrqslen; /* len of extended rqsense */
298 uint16_t cmd_extrqschunks; /* len in map chunks */
299 uint16_t cmd_extrqsidx; /* Index into map */
300 uint_t cmd_scblen;
301 uint32_t cmd_dmacount;
302 uint64_t cmd_dma_addr;
303 uchar_t cmd_age;
304 ushort_t cmd_qfull_retries;
305 uchar_t cmd_queued; /* true if queued */
306 struct mptsas_cmd *cmd_linkp;
307 mptti_t *cmd_sg; /* Scatter/Gather structure */
308 uchar_t cmd_cdb[SCSI_CDB_SIZE];
309 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
310 uint32_t cmd_slot;
311 uint32_t ioc_cmd_slot;
312
313 mptsas_cache_frames_t *cmd_extra_frames;
314
315 uint32_t cmd_rfm;
316 mptsas_target_t *cmd_tgt_addr;
317 } mptsas_cmd_t;
318
319 /*
320 * These are the defined cmd_flags for this structure.
321 */
322 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
323 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
324 #define CFLAG_FINISHED 0x000004 /* command completed */
325 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
326 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
327 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
328 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
329 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
330 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
331 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
332 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
333 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
334 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
335 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
336 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
337 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
338 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
339 #define CFLAG_FREE 0x010000 /* packet is on free list */
340 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
341 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
342 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
343 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
344 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
345 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
346 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
347 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
348 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
349 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
350 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
351 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
352 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
353 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
354
355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
356 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
357 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
358 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
359 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
360 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
361 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
362 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
363 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
364 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
365 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
366
367 #define MPTSAS_HASH_ARRAY_SIZE 16
368 /*
369 * hash table definition
370 */
371
372 #define MPTSAS_HASH_FIRST 0xffff
373 #define MPTSAS_HASH_NEXT 0x0000
374
375 typedef struct mptsas_dma_alloc_state
376 {
377 ddi_dma_handle_t handle;
378 caddr_t memp;
379 size_t size;
380 ddi_acc_handle_t accessp;
381 ddi_dma_cookie_t cookie;
382 } mptsas_dma_alloc_state_t;
383
384 /*
385 * passthrough request structure
386 */
387 typedef struct mptsas_pt_request {
388 uint8_t *request;
389 uint32_t request_size;
390 uint32_t data_size;
391 uint32_t dataout_size;
392 uint32_t direction;
393 uint8_t simple;
394 uint16_t sgl_offset;
395 ddi_dma_cookie_t data_cookie;
396 ddi_dma_cookie_t dataout_cookie;
397 } mptsas_pt_request_t;
398
399 /*
400 * config page request structure
401 */
402 typedef struct mptsas_config_request {
403 uint32_t page_address;
404 uint8_t action;
405 uint8_t page_type;
406 uint8_t page_number;
407 uint8_t page_length;
408 uint8_t page_version;
409 uint8_t ext_page_type;
410 uint16_t ext_page_length;
411 } mptsas_config_request_t;
412
413 typedef struct mptsas_fw_diagnostic_buffer {
414 mptsas_dma_alloc_state_t buffer_data;
415 uint8_t extended_type;
416 uint8_t buffer_type;
417 uint8_t force_release;
418 uint32_t product_specific[23];
419 uint8_t immediate;
420 uint8_t enabled;
421 uint8_t valid_data;
422 uint8_t owned_by_firmware;
423 uint32_t unique_id;
424 } mptsas_fw_diagnostic_buffer_t;
425
426 /*
427 * FW diag request structure
428 */
429 typedef struct mptsas_diag_request {
430 mptsas_fw_diagnostic_buffer_t *pBuffer;
431 uint8_t function;
432 } mptsas_diag_request_t;
433
434 typedef struct mptsas_hash_node {
435 void *data;
436 struct mptsas_hash_node *next;
437 } mptsas_hash_node_t;
438
439 typedef struct mptsas_hash_table {
440 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
441 /*
442 * last position in traverse
443 */
444 struct mptsas_hash_node *cur;
445 uint16_t line;
446
447 } mptsas_hash_table_t;
448
449 /*
450 * RAID volume information
451 */
452 typedef struct mptsas_raidvol {
453 ushort_t m_israid;
454 uint16_t m_raidhandle;
455 uint64_t m_raidwwid;
456 uint8_t m_state;
457 uint32_t m_statusflags;
458 uint32_t m_settings;
459 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
460 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
461 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
462 uint64_t m_raidsize;
463 int m_raidlevel;
464 int m_ndisks;
465 mptsas_target_t *m_raidtgt;
466 } mptsas_raidvol_t;
467
468 /*
469 * RAID configurations
470 */
471 typedef struct mptsas_raidconfig {
472 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
473 uint16_t m_physdisk_devhdl[
474 MPTSAS_MAX_DISKS_IN_CONFIG];
475 uint8_t m_native;
476 } m_raidconfig_t;
477
478 /*
479 * Track outstanding commands. The index into the m_slot array is the SMID
480 * (system message ID) of the outstanding command. SMID 0 is reserved by the
481 * software/firmware protocol and is never used for any command we generate;
482 * as such, the assertion m_slot[0] == NULL is universally true. The last
483 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
484 * task management commands. No normal SCSI or ATA command will ever occupy
485 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any
486 * time that a consistent view of the target array is obtainable.
487 *
488 * As such, m_n_normal is the maximum number of slots available to ordinary
489 * commands, and the relationship:
490 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
491 * always holds after initialisation.
492 */
493 typedef struct mptsas_slots {
494 size_t m_size; /* size of struct, bytes */
495 uint_t m_n_normal; /* see above */
496 uint_t m_rotor; /* next slot idx to consider */
497 mptsas_cmd_t *m_slot[1];
498 } mptsas_slots_t;
499
500 /*
501 * Structure to hold command and packets for event ack
502 * and task management commands.
503 */
504 typedef struct m_event_struct {
505 struct mptsas_cmd m_event_cmd;
506 struct m_event_struct *m_event_linkp;
507 /*
508 * event member record the failure event and eventcntx
509 * event member would be used in send ack pending process
510 */
511 uint32_t m_event;
512 uint32_t m_eventcntx;
513 uint_t in_use;
514 struct scsi_pkt m_event_pkt; /* must be last */
515 /* ... scsi_pkt_size() */
516 } m_event_struct_t;
517 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
518 sizeof (struct scsi_pkt) + scsi_pkt_size())
519
520 #define MAX_IOC_COMMANDS 8
521
522 /*
523 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
524 * A new event ack command requests mptsas_cmd and scsi_pkt structures
525 * from this pool, and returns it back when done.
526 */
527
528 typedef struct m_replyh_arg {
529 void *mpt;
530 uint32_t rfm;
531 } m_replyh_arg_t;
532 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
533 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
534
535 /*
536 * Flags for DR handler topology change
537 */
538 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
539 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
540 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
541 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
542 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
543 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
544
545 typedef struct mptsas_topo_change_list {
546 void *mpt;
547 uint_t event;
548 union {
549 uint8_t physport;
550 mptsas_phymask_t phymask;
551 } un;
552 uint16_t devhdl;
553 void *object;
554 uint8_t flags;
555 struct mptsas_topo_change_list *next;
556 } mptsas_topo_change_list_t;
557
558
559 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
560 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
561 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
562 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
563 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
564 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
565
566 /*
567 * Status types when calling mptsas_get_target_device_info
568 */
569 #define DEV_INFO_SUCCESS 0x0
570 #define DEV_INFO_FAIL_PAGE0 0x1
571 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
572 #define DEV_INFO_PHYS_DISK 0x3
573 #define DEV_INFO_FAIL_ALLOC 0x4
574 #define DEV_INFO_FAIL_GUID 0x5
575
576 /*
577 * mpt hotplug event defines
578 */
579 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
580 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
581 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
582
583 /*
584 * SMP target hotplug events
585 */
586 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
587 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
588 #define MPTSAS_DR_EVENT_MASK 0x3F
589
590 /*
591 * mpt hotplug status definition for m_dr_flag
592 */
593
594 /*
595 * MPTSAS_DR_INACTIVE
596 *
597 * The target is in a normal operating state.
598 * No dynamic reconfiguration operation is in progress.
599 */
600 #define MPTSAS_DR_INACTIVE 0x0
601 /*
602 * MPTSAS_DR_INTRANSITION
603 *
604 * The target is in a transition mode since
605 * hotplug event happens and offline procedure has not
606 * been finished
607 */
608 #define MPTSAS_DR_INTRANSITION 0x1
609
610 typedef struct mptsas_tgt_private {
611 int t_lun;
612 struct mptsas_target *t_private;
613 } mptsas_tgt_private_t;
614
615 /*
616 * The following defines are used in mptsas_set_init_mode to track the current
617 * state as we progress through reprogramming the HBA from target mode into
618 * initiator mode.
619 */
620
621 #define IOUC_READ_PAGE0 0x00000100
622 #define IOUC_READ_PAGE1 0x00000200
623 #define IOUC_WRITE_PAGE1 0x00000400
624 #define IOUC_DONE 0x00000800
625 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
626 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
627
628 /*
629 * Last allocated slot is used for TM requests. Since only m_max_requests
630 * frames are allocated, the last SMID will be m_max_requests - 1.
631 */
632 #define MPTSAS_SLOTS_SIZE(mpt) \
633 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
634 mpt->m_max_requests))
635 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
636
637 /*
638 * Macro for phy_flags
639 */
640
641 typedef struct smhba_info {
642 kmutex_t phy_mutex;
643 uint8_t phy_id;
644 uint64_t sas_addr;
645 char path[8];
646 uint16_t owner_devhdl;
647 uint16_t attached_devhdl;
648 uint8_t attached_phy_identify;
649 uint32_t attached_phy_info;
650 uint8_t programmed_link_rate;
651 uint8_t hw_link_rate;
652 uint8_t change_count;
653 uint32_t phy_info;
654 uint8_t negotiated_link_rate;
655 uint8_t port_num;
656 kstat_t *phy_stats;
657 uint32_t invalid_dword_count;
658 uint32_t running_disparity_error_count;
659 uint32_t loss_of_dword_sync_count;
660 uint32_t phy_reset_problem_count;
661 void *mpt;
662 } smhba_info_t;
663
664 typedef struct mptsas_phy_info {
665 uint8_t port_num;
666 uint8_t port_flags;
667 uint16_t ctrl_devhdl;
668 uint32_t phy_device_type;
669 uint16_t attached_devhdl;
670 mptsas_phymask_t phy_mask;
671 smhba_info_t smhba_info;
672 } mptsas_phy_info_t;
673
674
675 typedef struct mptsas_doneq_thread_arg {
676 void *mpt;
677 uint64_t t;
678 } mptsas_doneq_thread_arg_t;
679
680 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
681 typedef struct mptsas_doneq_thread_list {
682 mptsas_cmd_t *doneq;
683 mptsas_cmd_t **donetail;
684 kthread_t *threadp;
685 kcondvar_t cv;
686 ushort_t reserv1;
687 uint32_t reserv2;
688 kmutex_t mutex;
689 uint32_t flag;
690 uint32_t len;
691 mptsas_doneq_thread_arg_t arg;
692 } mptsas_doneq_thread_list_t;
693
694 typedef struct mptsas {
695 int m_instance;
696
697 struct mptsas *m_next;
698
699 scsi_hba_tran_t *m_tran;
700 smp_hba_tran_t *m_smptran;
701 kmutex_t m_mutex;
702 kmutex_t m_passthru_mutex;
703 kcondvar_t m_cv;
704 kcondvar_t m_passthru_cv;
705 kcondvar_t m_fw_cv;
706 kcondvar_t m_config_cv;
707 kcondvar_t m_fw_diag_cv;
708 dev_info_t *m_dip;
709
710 /*
711 * soft state flags
712 */
713 uint_t m_softstate;
714
715 refhash_t *m_targets;
716 refhash_t *m_smp_targets;
717 list_t m_enclosures;
718 refhash_t *m_tmp_targets;
719
720 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
721 uint8_t m_num_raid_configs;
722
723 struct mptsas_slots *m_active; /* outstanding cmds */
724
725 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
726 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
727
728 kmutex_t m_tx_waitq_mutex;
729 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
730 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
731 int m_tx_draining; /* TX queue draining flag */
732
733 mptsas_cmd_t *m_doneq; /* queue of completed commands */
734 mptsas_cmd_t **m_donetail; /* queue tail ptr */
735
736 /*
737 * variables for helper threads (fan-out interrupts)
738 */
739 mptsas_doneq_thread_list_t *m_doneq_thread_id;
740 uint32_t m_doneq_thread_n;
741 uint32_t m_doneq_thread_threshold;
742 uint32_t m_doneq_length_threshold;
743 uint32_t m_doneq_len;
744 kcondvar_t m_doneq_thread_cv;
745 kmutex_t m_doneq_mutex;
746
747 int m_ncmds; /* number of outstanding commands */
748 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
749 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
750
751 ddi_acc_handle_t m_datap; /* operating regs data access handle */
752
753 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
754
755 ushort_t m_devid; /* device id of chip. */
756 uchar_t m_revid; /* revision of chip. */
757 uint16_t m_svid; /* subsystem Vendor ID of chip */
758 uint16_t m_ssid; /* subsystem Device ID of chip */
759
760 uchar_t m_sync_offset; /* default offset for this chip. */
761
762 timeout_id_t m_quiesce_timeid;
763
764 ddi_dma_handle_t m_dma_req_frame_hdl;
765 ddi_acc_handle_t m_acc_req_frame_hdl;
766 ddi_dma_handle_t m_dma_req_sense_hdl;
767 ddi_acc_handle_t m_acc_req_sense_hdl;
768 ddi_dma_handle_t m_dma_reply_frame_hdl;
769 ddi_acc_handle_t m_acc_reply_frame_hdl;
770 ddi_dma_handle_t m_dma_free_queue_hdl;
771 ddi_acc_handle_t m_acc_free_queue_hdl;
772 ddi_dma_handle_t m_dma_post_queue_hdl;
773 ddi_acc_handle_t m_acc_post_queue_hdl;
774
775 /*
776 * list of reset notification requests
777 */
778 struct scsi_reset_notify_entry *m_reset_notify_listf;
779
780 /*
781 * qfull handling
782 */
783 timeout_id_t m_restart_cmd_timeid;
784
785 /*
786 * scsi reset delay per bus
787 */
788 uint_t m_scsi_reset_delay;
789
790 /*
791 * Tuneable for the throttle control
792 */
793 uint_t m_max_tune_throttle;
794
795 int m_pm_idle_delay;
796
797 uchar_t m_polled_intr; /* intr was polled. */
798 uchar_t m_suspended; /* true if driver is suspended */
799
800 struct kmem_cache *m_kmem_cache;
801 struct kmem_cache *m_cache_frames;
802
803 /*
804 * hba options.
805 */
806 uint_t m_options;
807
808 int m_in_callback;
809
810 int m_power_level; /* current power level */
811
812 int m_busy; /* power management busy state */
813
814 off_t m_pmcsr_offset; /* PMCSR offset */
815
816 ddi_acc_handle_t m_config_handle;
817
818 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
819 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
820 ddi_device_acc_attr_t m_dev_acc_attr;
821 ddi_device_acc_attr_t m_reg_acc_attr;
822
823 /*
824 * request/reply variables
825 */
826 caddr_t m_req_frame;
827 uint64_t m_req_frame_dma_addr;
828 caddr_t m_req_sense;
829 caddr_t m_extreq_sense;
830 uint64_t m_req_sense_dma_addr;
831 caddr_t m_reply_frame;
832 uint64_t m_reply_frame_dma_addr;
833 caddr_t m_free_queue;
834 uint64_t m_free_queue_dma_addr;
835 caddr_t m_post_queue;
836 uint64_t m_post_queue_dma_addr;
837 struct map *m_erqsense_map;
838
839 m_replyh_arg_t *m_replyh_args;
840
841 uint16_t m_max_requests;
842 uint16_t m_req_frame_size;
843 uint16_t m_req_sense_size;
844
845 /*
846 * Max frames per request reprted in IOC Facts
847 */
848 uint8_t m_max_chain_depth;
849 /*
850 * Max frames per request which is used in reality. It's adjusted
851 * according DMA SG length attribute, and shall not exceed the
852 * m_max_chain_depth.
853 */
854 uint8_t m_max_request_frames;
855
856 uint16_t m_free_queue_depth;
857 uint16_t m_post_queue_depth;
858 uint16_t m_max_replies;
859 uint32_t m_free_index;
860 uint32_t m_post_index;
861 uint8_t m_reply_frame_size;
862 uint32_t m_ioc_capabilities;
863
864 /*
865 * indicates if the firmware was upload by the driver
866 * at boot time
867 */
868 ushort_t m_fwupload;
869
870 uint16_t m_productid;
871
872 /*
873 * per instance data structures for dma memory resources for
874 * MPI handshake protocol. only one handshake cmd can run at a time.
875 */
876 ddi_dma_handle_t m_hshk_dma_hdl;
877 ddi_acc_handle_t m_hshk_acc_hdl;
878 caddr_t m_hshk_memp;
879 size_t m_hshk_dma_size;
880
881 /* Firmware version on the card at boot time */
882 uint32_t m_fwversion;
883
884 /* MSI specific fields */
885 ddi_intr_handle_t *m_htable; /* For array of interrupts */
886 int m_intr_type; /* What type of interrupt */
887 int m_intr_cnt; /* # of intrs count returned */
888 size_t m_intr_size; /* Size of intr array */
889 uint_t m_intr_pri; /* Interrupt priority */
890 int m_intr_cap; /* Interrupt capabilities */
891 ddi_taskq_t *m_event_taskq;
892
893 /* SAS specific information */
894
895 union {
896 uint64_t m_base_wwid; /* Base WWID */
897 struct {
898 #ifdef _BIG_ENDIAN
899 uint32_t m_base_wwid_hi;
900 uint32_t m_base_wwid_lo;
901 #else
902 uint32_t m_base_wwid_lo;
903 uint32_t m_base_wwid_hi;
904 #endif
905 } sasaddr;
906 } un;
907
908 uint8_t m_num_phys; /* # of PHYs */
909 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
910 uint8_t m_port_chng; /* initiator port changes */
911 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
912 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
913
914 /* FMA Capabilities */
915 int m_fm_capabilities;
916 ddi_taskq_t *m_dr_taskq;
917 int m_mpxio_enable;
918 uint8_t m_done_traverse_dev;
919 uint8_t m_done_traverse_smp;
920 uint8_t m_done_traverse_enc;
921 int m_diag_action_in_progress;
922 uint16_t m_dev_handle;
923 uint16_t m_smp_devhdl;
924
925 /*
926 * Event recording
927 */
928 uint8_t m_event_index;
929 uint32_t m_event_number;
930 uint32_t m_event_mask[4];
931 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
932
933 /*
934 * FW diag Buffer List
935 */
936 mptsas_fw_diagnostic_buffer_t
937 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
938
939 /* GEN3 support */
940 uint8_t m_MPI25;
941
942 /*
943 * Event Replay flag (MUR support)
944 */
945 uint8_t m_event_replay;
946
947 /*
948 * IR Capable flag
949 */
950 uint8_t m_ir_capable;
951
952 /*
953 * Is HBA processing a diag reset?
954 */
955 uint8_t m_in_reset;
956
957 /*
958 * per instance cmd data structures for task management cmds
959 */
960 m_event_struct_t m_event_task_mgmt; /* must be last */
961 /* ... scsi_pkt_size */
962
963 #ifdef MPTSAS_FAULTINJECTION
964 struct mptsas_active_cmdq m_fminj_cmdq;
965 #endif
966 } mptsas_t;
967 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
968 sizeof (struct scsi_pkt) + scsi_pkt_size())
969 /*
970 * Only one of below two conditions is satisfied, we
971 * think the target is associated to the iport and
972 * allow call into mptsas_probe_lun().
973 * 1. physicalsport == physport
974 * 2. (phymask & (1 << physport)) == 0
975 * The condition #2 is because LSI uses lowest PHY
976 * number as the value of physical port when auto port
977 * configuration.
978 */
979 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
980 ((physicalport == physport) || (dynamicport && (phymask & \
981 (1 << physport))))
982
983 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
984 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
985 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
986 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
987 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
988 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
989 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
990 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
991 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
992
993 /*
994 * These should eventually migrate into the mpt header files
995 * that may become the /kernel/misc/mpt module...
996 */
997 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
998 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
999 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
1000 mptsas_put_msg_Function(hdl, mp, Function); \
1001 mptsas_put_msg_Lun(hdl, mp, Lun)
1002
1003 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
1004 ddi_put16(hdl, &(mp)->DevHandle, (val))
1005 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
1006 ddi_put8(hdl, &(mp)->ChainOffset, (val))
1007 #define mptsas_put_msg_Function(hdl, mp, val) \
1008 ddi_put8(hdl, &(mp)->Function, (val))
1009 #define mptsas_put_msg_Lun(hdl, mp, val) \
1010 ddi_put8(hdl, &(mp)->LUN[1], (val))
1011
1012 #define mptsas_get_msg_Function(hdl, mp) \
1013 ddi_get8(hdl, &(mp)->Function)
1014
1015 #define mptsas_get_msg_MsgFlags(hdl, mp) \
1016 ddi_get8(hdl, &(mp)->MsgFlags)
1017
1018 #define MPTSAS_ENABLE_DRWE(hdl) \
1019 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1020 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
1021 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1022 MPI2_WRSEQ_1ST_KEY_VALUE); \
1023 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1024 MPI2_WRSEQ_2ND_KEY_VALUE); \
1025 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1026 MPI2_WRSEQ_3RD_KEY_VALUE); \
1027 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1028 MPI2_WRSEQ_4TH_KEY_VALUE); \
1029 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1030 MPI2_WRSEQ_5TH_KEY_VALUE); \
1031 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1032 MPI2_WRSEQ_6TH_KEY_VALUE);
1033
1034 /*
1035 * m_options flags
1036 */
1037 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1038
1039 /*
1040 * m_softstate flags
1041 */
1042 #define MPTSAS_SS_DRAINING 0x02
1043 #define MPTSAS_SS_QUIESCED 0x04
1044 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
1045 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
1046
1047 /*
1048 * regspec defines.
1049 */
1050 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1051 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1052 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1053 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1054
1055 /*
1056 * Handy constants
1057 */
1058 #define FALSE 0
1059 #define TRUE 1
1060 #define UNDEFINED -1
1061 #define FAILED -2
1062
1063 /*
1064 * power management.
1065 */
1066 #define MPTSAS_POWER_ON(mpt) { \
1067 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1068 PCI_PMCSR_D0); \
1069 delay(drv_usectohz(10000)); \
1070 (void) pci_restore_config_regs(mpt->m_dip); \
1071 mptsas_setup_cmd_reg(mpt); \
1072 }
1073
1074 #define MPTSAS_POWER_OFF(mpt) { \
1075 (void) pci_save_config_regs(mpt->m_dip); \
1076 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1077 PCI_PMCSR_D3HOT); \
1078 mpt->m_power_level = PM_LEVEL_D3; \
1079 }
1080
1081 /*
1082 * inq_dtype:
1083 * Bits 5 through 7 are the Peripheral Device Qualifier
1084 * 001b: device not connected to the LUN
1085 * Bits 0 through 4 are the Peripheral Device Type
1086 * 1fh: Unknown or no device type
1087 *
1088 * Although the inquiry may return success, the following value
1089 * means no valid LUN connected.
1090 */
1091 #define MPTSAS_VALID_LUN(sd_inq) \
1092 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1093 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1094
1095 /*
1096 * Default is to have 10 retries on receiving QFULL status and
1097 * each retry to be after 100 ms.
1098 */
1099 #define QFULL_RETRIES 10
1100 #define QFULL_RETRY_INTERVAL 100
1101
1102 /*
1103 * Handy macros
1104 */
1105 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1106 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1107
1108 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1109 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1110
1111 /*
1112 * poll time for mptsas_pollret() and mptsas_wait_intr()
1113 */
1114 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1115
1116 /*
1117 * default time for mptsas_do_passthru
1118 */
1119 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1120
1121 /*
1122 * macro to return the effective address of a given per-target field
1123 */
1124 #define EFF_ADDR(start, offset) ((start) + (offset))
1125
1126 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1127 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1128 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1129 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1130 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1131
1132
1133 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1134 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1135 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1136 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1137
1138 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1139
1140 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1141 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1142 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1143 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1144
1145 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1146 &(mpt)->m_reg->HostInterruptStatus))
1147
1148 #define MPTSAS_SET_SIGP(P) \
1149 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1150
1151 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1152 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1153
1154 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1155 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1156
1157
1158 #define MPTSAS_START_CMD(mpt, req_desc) \
1159 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \
1160 req_desc & 0xffffffffu); \
1161 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \
1162 (req_desc >> 32) & 0xffffffffu);
1163
1164 #define INTPENDING(mpt) \
1165 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1166
1167 /*
1168 * Mask all interrupts to disable
1169 */
1170 #define MPTSAS_DISABLE_INTR(mpt) \
1171 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1172 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1173
1174 /*
1175 * Mask Doorbell and Reset interrupts to enable reply desc int.
1176 */
1177 #define MPTSAS_ENABLE_INTR(mpt) \
1178 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1179 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1180
1181 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1182 &((uint64_t *)(void *)mpt->m_post_queue)[index]
1183
1184 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1185 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1186
1187 #define ClrSetBits32(hdl, reg, clr, set) \
1188 ddi_put32(hdl, (reg), \
1189 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1190
1191 #define ClrSetBits(reg, clr, set) \
1192 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1193 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1194
1195 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1196 if ((cmdp = mpt->m_waitq) != NULL) { \
1197 /* If the queue is now empty fix the tail pointer */ \
1198 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1199 mpt->m_waitqtail = &mpt->m_waitq; \
1200 cmdp->cmd_linkp = NULL; \
1201 cmdp->cmd_queued = FALSE; \
1202 }
1203
1204 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1205 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1206 /* If the queue is now empty fix the tail pointer */ \
1207 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1208 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1209 cmdp->cmd_linkp = NULL; \
1210 cmdp->cmd_queued = FALSE; \
1211 }
1212
1213 /*
1214 * defaults for the global properties
1215 */
1216 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1217 #define DEFAULT_TAG_AGE_LIMIT 2
1218 #define DEFAULT_WD_TICK 1
1219
1220 /*
1221 * invalid hostid.
1222 */
1223 #define MPTSAS_INVALID_HOSTID -1
1224
1225 /*
1226 * Get/Set hostid from SCSI port configuration page
1227 */
1228 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1229 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1230
1231 /*
1232 * Config space.
1233 */
1234 #define MPTSAS_LATENCY_TIMER 0x40
1235
1236 /*
1237 * Offset to firmware version
1238 */
1239 #define MPTSAS_FW_VERSION_OFFSET 9
1240
1241 /*
1242 * Offset and masks to get at the ProductId field
1243 */
1244 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1245 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1246 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1247
1248 /*
1249 * Subsystem ID for HBAs.
1250 */
1251 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1252 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1253
1254 /*
1255 * reset delay tick
1256 */
1257 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1258
1259 /*
1260 * Ioc reset return values
1261 */
1262 #define MPTSAS_RESET_FAIL -1
1263 #define MPTSAS_NO_RESET 0
1264 #define MPTSAS_SUCCESS_HARDRESET 1
1265 #define MPTSAS_SUCCESS_MUR 2
1266
1267 /*
1268 * throttle support.
1269 */
1270
1271 #define THROTTLE_HI 4096
1272 #define THROTTLE_LO 32
1273 #define MAX_THROTTLE THROTTLE_LO
1274 #define HOLD_THROTTLE 0
1275 #define DRAIN_THROTTLE -1
1276 #define QFULL_THROTTLE -2
1277
1278 /*
1279 * Passthrough/config request flags
1280 */
1281 #define MPTSAS_DATA_ALLOCATED 0x0001
1282 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1283 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1284 #define MPTSAS_ADDRESS_REPLY 0x0008
1285 #define MPTSAS_CMD_TIMEOUT 0x0010
1286
1287 /*
1288 * response code tlr flag
1289 */
1290 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1291
1292 /*
1293 * System Events
1294 */
1295 #ifndef DDI_VENDOR_LSI
1296 #define DDI_VENDOR_LSI "LSI"
1297 #endif /* DDI_VENDOR_LSI */
1298
1299 /*
1300 * Shared functions
1301 */
1302 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1303 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1304 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1305 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1306 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1307 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1308 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1309 uint8_t type, int mode);
1310 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1311 uint8_t type, int mode);
1312 int mptsas_download_firmware();
1313 int mptsas_can_download_firmware();
1314 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1315 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1316 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1317 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1318 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1319 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1320 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1321 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1322 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1323 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1324 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1325
1326 /*
1327 * impl functions
1328 */
1329 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1330 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1331 int mptsas_ioc_reset(mptsas_t *mpt, int);
1332 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1333 ddi_acc_handle_t accessp);
1334 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1335 ddi_acc_handle_t accessp);
1336 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1337 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1338 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1339 uint64_t SGEaddress);
1340 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1341 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1342 uint8_t pageversion, uint16_t extpagelength,
1343 uint32_t SGEflagslength, uint64_t SGEaddress);
1344
1345 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1346 struct scsi_pkt **pkt);
1347 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1348 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1349 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1350 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1351 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1352 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1353
1354 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1355 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1356 int mode);
1357 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1358 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1359 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1360 int mptsas_restart_ioc(mptsas_t *mpt);
1361 void mptsas_update_driver_data(struct mptsas *mpt);
1362 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1363
1364 /*
1365 * init functions
1366 */
1367 int mptsas_ioc_get_facts(mptsas_t *mpt);
1368 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1369 int mptsas_ioc_enable_port(mptsas_t *mpt);
1370 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1371 int mptsas_ioc_init(mptsas_t *mpt);
1372
1373 /*
1374 * configuration pages operation
1375 */
1376 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1377 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1378 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1379 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
1380 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1381 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1382 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1383 mptsas_smp_t *info);
1384 int mptsas_set_ioc_params(mptsas_t *mpt);
1385 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1386 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1387 uint64_t *sas_wwn, uint8_t *portwidth);
1388 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1389 int mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1390 smhba_info_t *info);
1391 int mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1392 smhba_info_t *info);
1393 int mptsas_get_manufacture_page0(mptsas_t *mpt);
1394 int mptsas_get_enclosure_page0(mptsas_t *mpt, uint32_t page_address,
1395 mptsas_enclosure_t *mpe);
1396 void mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1397 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1398 int mptsas_smhba_phy_init(mptsas_t *mpt);
1399 /*
1400 * RAID functions
1401 */
1402 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1403 int mptsas_get_raid_info(mptsas_t *mpt);
1404 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1405 uint8_t physdisknum);
1406 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1407 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1408
1409 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1410 /*
1411 * debugging.
1412 * MPTSAS_DBGLOG_LINECNT must be a power of 2.
1413 */
1414 #define MPTSAS_DBGLOG_LINECNT 128
1415 #define MPTSAS_DBGLOG_LINELEN 256
1416 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN)
1417
1418 #if defined(MPTSAS_DEBUG)
1419
1420 extern uint32_t mptsas_debugprt_flags;
1421 extern uint32_t mptsas_debuglog_flags;
1422
1423 void mptsas_printf(char *fmt, ...);
1424 void mptsas_debug_log(char *fmt, ...);
1425
1426 #define MPTSAS_DBGPR(m, args) \
1427 if (mptsas_debugprt_flags & (m)) \
1428 mptsas_printf args; \
1429 if (mptsas_debuglog_flags & (m)) \
1430 mptsas_debug_log args
1431 #else /* ! defined(MPTSAS_DEBUG) */
1432 #define MPTSAS_DBGPR(m, args)
1433 #endif /* defined(MPTSAS_DEBUG) */
1434
1435 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1436 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1437 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1438 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1439
1440 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1441 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1442 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1443 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1444
1445 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1446 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1447 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1448 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1449
1450 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1451 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1452 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1453 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */
1454
1455 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */
1456 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1457 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1458 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1459
1460 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1461 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1462 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1463 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1464
1465 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1466 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1467 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1468 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */
1469
1470 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1471 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1472 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1473 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1474
1475 /*
1476 * auto request sense
1477 */
1478 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1479 (pkt)->pkt_flags = (flag), \
1480 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1481 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1482 (pkt)->pkt_address.a_lun
1483
1484 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1485 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1486 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1487 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1488
1489
1490 #ifdef __cplusplus
1491 }
1492 #endif
1493
1494 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */