1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2015 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2017, Joyent, Inc.
26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 */
28
29 /*
30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms of all code within
34 * this file that is exclusively owned by LSI, with or without
35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 * License requirements, the following conditions are met:
37 *
38 * Neither the name of the author nor the names of its contributors may be
39 * used to endorse or promote products derived from this software without
40 * specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
53 * DAMAGE.
54 */
55
56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
58
59 #include <sys/byteorder.h>
60 #include <sys/queue.h>
61 #include <sys/isa_defs.h>
62 #include <sys/sunmdi.h>
63 #include <sys/mdi_impldefs.h>
64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
68
69 #ifdef __cplusplus
70 extern "C" {
71 #endif
72
73 /*
74 * Compile options
75 */
76 #ifdef DEBUG
77 #define MPTSAS_DEBUG /* turn on debugging code */
78 #endif /* DEBUG */
79
80 #define MPTSAS_INITIAL_SOFT_SPACE 4
81
82 /*
83 * Note below macro definition and data type definition
84 * are used for phy mask handling, it should be changed
85 * simultaneously.
86 */
87 #define MPTSAS_MAX_PHYS 24
88 typedef uint32_t mptsas_phymask_t;
89
90 #define MPTSAS_INVALID_DEVHDL 0xffff
91 #define MPTSAS_SATA_GUID "sata-guid"
92
93 /*
94 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
95 * targets. There's no need to go overboard here, as the ordinary paths for
96 * I/O do not normally require hashed target lookups. These should be good
97 * enough and then some for any fabric within the hardware's capabilities.
98 */
99 #define MPTSAS_SMP_BUCKET_COUNT 23
100 #define MPTSAS_TARGET_BUCKET_COUNT 97
101 #define MPTSAS_TMP_TARGET_BUCKET_COUNT 13
102
103 /*
104 * MPT HW defines
105 */
106 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
107 #define MPTSAS_MAX_DISKS_IN_VOL 10
108 #define MPTSAS_MAX_HOTSPARES 2
109 #define MPTSAS_MAX_RAIDVOLS 2
110 #define MPTSAS_MAX_RAIDCONFIGS 5
111
112 /*
113 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
114 * plus two means the prefix 'w' and end of the string '\0'.
115 */
116 #define MPTSAS_WWN_STRLEN (16 + 2)
117 #define MPTSAS_MAX_GUID_LEN 64
118
119 /*
120 * DMA routine flags
121 */
122 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
123 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
124 #define MPTSAS_DMA_HANDLE_BOUND 0x8
125
126 /*
127 * If the HBA supports DMA or bus-mastering, you may have your own
128 * scatter-gather list for physically non-contiguous memory in one
129 * I/O operation; if so, there's probably a size for that list.
130 * It must be placed in the ddi_dma_lim_t structure, so that the system
131 * DMA-support routines can use it to break up the I/O request, so we
132 * define it here.
133 */
134 #if defined(__sparc)
135 #define MPTSAS_MAX_DMA_SEGS 1
136 #define MPTSAS_MAX_CMD_SEGS 1
137 #else
138 #define MPTSAS_MAX_DMA_SEGS 256
139 #define MPTSAS_MAX_CMD_SEGS 257
140 #endif
141 #define MPTSAS_MAX_FRAME_SGES(mpt) \
142 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
143
144 #define MPTSAS_SGE_SIZE(mpt) \
145 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \
146 sizeof (MPI2_SGE_SIMPLE64))
147
148 /*
149 * Calculating how many 64-bit DMA simple elements can be stored in the first
150 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
151 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
152 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
153 * (16 bytes).
154 */
155 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
156 ((mpt->m_req_frame_size - \
157 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
158 MPTSAS_SGE_SIZE(mpt))
159
160 /*
161 * Scatter-gather list structure defined by HBA hardware
162 */
163 typedef struct NcrTableIndirect { /* Table Indirect entries */
164 uint32_t count; /* 24 bit count */
165 union {
166 uint32_t address32; /* 32 bit address */
167 struct {
168 uint32_t Low;
169 uint32_t High;
170 } address64; /* 64 bit address */
171 } addr;
172 } mptti_t;
173
174 /*
175 * preferred pkt_private length in 64-bit quantities
176 */
177 #ifdef _LP64
178 #define PKT_PRIV_SIZE 2
179 #define PKT_PRIV_LEN 16 /* in bytes */
180 #else /* _ILP32 */
181 #define PKT_PRIV_SIZE 1
182 #define PKT_PRIV_LEN 8 /* in bytes */
183 #endif
184
185 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
186 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
187 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
188
189 /*
190 * get offset of item in structure
191 */
192 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
193
194 /*
195 * WWID provided by LSI firmware is generated by firmware but the WWID is not
196 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
197 * address. According LSI's confirmation, the top nibble of RAID WWID is
198 * meanless, so the consensus between Solaris and OBP is to replace top nibble
199 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
200 * format unit address.
201 */
202 #define MPTSAS_RAID_WWID(wwid) \
203 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
204
205 typedef struct mptsas_target_addr {
206 uint64_t mta_wwn;
207 mptsas_phymask_t mta_phymask;
208 } mptsas_target_addr_t;
209
210 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
211 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
212
213 typedef struct mptsas_target {
214 mptsas_target_addr_t m_addr;
215 refhash_link_t m_link;
216 uint8_t m_dr_flag;
217 uint16_t m_devhdl;
218 uint32_t m_deviceinfo;
219 uint8_t m_phynum;
220 uint32_t m_dups;
221 mptsas_active_cmdq_t m_active_cmdq;
222 int32_t m_t_throttle;
223 int32_t m_t_ncmds;
224 int32_t m_reset_delay;
225 int32_t m_t_nwait;
226
227 uint16_t m_qfull_retry_interval;
228 uint8_t m_qfull_retries;
229 uint16_t m_io_flags;
230 uint16_t m_enclosure;
231 uint16_t m_slot_num;
232 uint32_t m_tgt_unconfigured;
233 uint8_t m_led_status;
234 uint8_t m_scsi_req_desc_type;
235
236 } mptsas_target_t;
237
238 /*
239 * If you change this structure, be sure that mptsas_smp_target_copy()
240 * does the right thing.
241 */
242 typedef struct mptsas_smp {
243 mptsas_target_addr_t m_addr;
244 refhash_link_t m_link;
245 uint16_t m_devhdl;
246 uint32_t m_deviceinfo;
247 uint16_t m_pdevhdl;
248 uint32_t m_pdevinfo;
249 } mptsas_smp_t;
250
251 /*
252 * This represents a single enclosure. Targets point to an enclosure through
253 * their m_enclosure member.
254 */
255 typedef struct mptsas_enclosure {
256 list_node_t me_link;
257 uint16_t me_enchdl;
258 uint16_t me_flags;
259 } mptsas_enclosure_t;
260
261 typedef struct mptsas_cache_frames {
262 ddi_dma_handle_t m_dma_hdl;
263 ddi_acc_handle_t m_acc_hdl;
264 caddr_t m_frames_addr;
265 uint64_t m_phys_addr;
266 } mptsas_cache_frames_t;
267
268 typedef struct mptsas_cmd {
269 uint_t cmd_flags; /* flags from scsi_init_pkt */
270 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
271 ddi_dma_cookie_t cmd_cookie;
272 uint_t cmd_cookiec;
273 uint_t cmd_winindex;
274 uint_t cmd_nwin;
275 uint_t cmd_cur_cookie;
276 off_t cmd_dma_offset;
277 size_t cmd_dma_len;
278 uint32_t cmd_totaldmacount;
279 caddr_t cmd_arq_buf;
280
281 int cmd_pkt_flags;
282
283 /* pending expiration time for command in active slot */
284 hrtime_t cmd_active_expiration;
285 TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
286
287 struct scsi_pkt *cmd_pkt;
288 struct scsi_arq_status cmd_scb;
289 uchar_t cmd_cdblen; /* length of cdb */
290 uchar_t cmd_rqslen; /* len of requested rqsense */
291 uchar_t cmd_privlen;
292 uint16_t cmd_extrqslen; /* len of extended rqsense */
293 uint16_t cmd_extrqschunks; /* len in map chunks */
294 uint16_t cmd_extrqsidx; /* Index into map */
295 uint_t cmd_scblen;
296 uint32_t cmd_dmacount;
297 uint64_t cmd_dma_addr;
298 uchar_t cmd_age;
299 ushort_t cmd_qfull_retries;
300 uchar_t cmd_queued; /* true if queued */
301 struct mptsas_cmd *cmd_linkp;
302 mptti_t *cmd_sg; /* Scatter/Gather structure */
303 uchar_t cmd_cdb[SCSI_CDB_SIZE];
304 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
305 uint32_t cmd_slot;
306 uint32_t ioc_cmd_slot;
307
308 mptsas_cache_frames_t *cmd_extra_frames;
309
310 uint32_t cmd_rfm;
311 mptsas_target_t *cmd_tgt_addr;
312 } mptsas_cmd_t;
313
314 /*
315 * These are the defined cmd_flags for this structure.
316 */
317 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
318 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
319 #define CFLAG_FINISHED 0x000004 /* command completed */
320 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
321 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
322 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
323 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
324 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
325 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
326 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
327 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
328 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
329 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
330 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
331 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
332 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
333 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
334 #define CFLAG_FREE 0x010000 /* packet is on free list */
335 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
336 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
337 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
338 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
339 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
340 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
341 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
342 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
343 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
344 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
345 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
346 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
347 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
348 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
349
350 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
352 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
353 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
354 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
356 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
357 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
358 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
359 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
360 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
361
362 #define MPTSAS_HASH_ARRAY_SIZE 16
363 /*
364 * hash table definition
365 */
366
367 #define MPTSAS_HASH_FIRST 0xffff
368 #define MPTSAS_HASH_NEXT 0x0000
369
370 typedef struct mptsas_dma_alloc_state
371 {
372 ddi_dma_handle_t handle;
373 caddr_t memp;
374 size_t size;
375 ddi_acc_handle_t accessp;
376 ddi_dma_cookie_t cookie;
377 } mptsas_dma_alloc_state_t;
378
379 /*
380 * passthrough request structure
381 */
382 typedef struct mptsas_pt_request {
383 uint8_t *request;
384 uint32_t request_size;
385 uint32_t data_size;
386 uint32_t dataout_size;
387 uint32_t direction;
388 uint8_t simple;
389 uint16_t sgl_offset;
390 ddi_dma_cookie_t data_cookie;
391 ddi_dma_cookie_t dataout_cookie;
392 } mptsas_pt_request_t;
393
394 /*
395 * config page request structure
396 */
397 typedef struct mptsas_config_request {
398 uint32_t page_address;
399 uint8_t action;
400 uint8_t page_type;
401 uint8_t page_number;
402 uint8_t page_length;
403 uint8_t page_version;
404 uint8_t ext_page_type;
405 uint16_t ext_page_length;
406 } mptsas_config_request_t;
407
408 typedef struct mptsas_fw_diagnostic_buffer {
409 mptsas_dma_alloc_state_t buffer_data;
410 uint8_t extended_type;
411 uint8_t buffer_type;
412 uint8_t force_release;
413 uint32_t product_specific[23];
414 uint8_t immediate;
415 uint8_t enabled;
416 uint8_t valid_data;
417 uint8_t owned_by_firmware;
418 uint32_t unique_id;
419 } mptsas_fw_diagnostic_buffer_t;
420
421 /*
422 * FW diag request structure
423 */
424 typedef struct mptsas_diag_request {
425 mptsas_fw_diagnostic_buffer_t *pBuffer;
426 uint8_t function;
427 } mptsas_diag_request_t;
428
429 typedef struct mptsas_hash_node {
430 void *data;
431 struct mptsas_hash_node *next;
432 } mptsas_hash_node_t;
433
434 typedef struct mptsas_hash_table {
435 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
436 /*
437 * last position in traverse
438 */
439 struct mptsas_hash_node *cur;
440 uint16_t line;
441
442 } mptsas_hash_table_t;
443
444 /*
445 * RAID volume information
446 */
447 typedef struct mptsas_raidvol {
448 ushort_t m_israid;
449 uint16_t m_raidhandle;
450 uint64_t m_raidwwid;
451 uint8_t m_state;
452 uint32_t m_statusflags;
453 uint32_t m_settings;
454 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
455 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
456 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
457 uint64_t m_raidsize;
458 int m_raidlevel;
459 int m_ndisks;
460 mptsas_target_t *m_raidtgt;
461 } mptsas_raidvol_t;
462
463 /*
464 * RAID configurations
465 */
466 typedef struct mptsas_raidconfig {
467 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
468 uint16_t m_physdisk_devhdl[
469 MPTSAS_MAX_DISKS_IN_CONFIG];
470 uint8_t m_native;
471 } m_raidconfig_t;
472
473 /*
474 * Track outstanding commands. The index into the m_slot array is the SMID
475 * (system message ID) of the outstanding command. SMID 0 is reserved by the
476 * software/firmware protocol and is never used for any command we generate;
477 * as such, the assertion m_slot[0] == NULL is universally true. The last
478 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
479 * task management commands. No normal SCSI or ATA command will ever occupy
480 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any
481 * time that a consistent view of the target array is obtainable.
482 *
483 * As such, m_n_normal is the maximum number of slots available to ordinary
484 * commands, and the relationship:
485 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
486 * always holds after initialisation.
487 */
488 typedef struct mptsas_slots {
489 size_t m_size; /* size of struct, bytes */
490 uint_t m_n_normal; /* see above */
491 uint_t m_rotor; /* next slot idx to consider */
492 mptsas_cmd_t *m_slot[1];
493 } mptsas_slots_t;
494
495 /*
496 * Structure to hold command and packets for event ack
497 * and task management commands.
498 */
499 typedef struct m_event_struct {
500 struct mptsas_cmd m_event_cmd;
501 struct m_event_struct *m_event_linkp;
502 /*
503 * event member record the failure event and eventcntx
504 * event member would be used in send ack pending process
505 */
506 uint32_t m_event;
507 uint32_t m_eventcntx;
508 uint_t in_use;
509 struct scsi_pkt m_event_pkt; /* must be last */
510 /* ... scsi_pkt_size() */
511 } m_event_struct_t;
512 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
513 sizeof (struct scsi_pkt) + scsi_pkt_size())
514
515 #define MAX_IOC_COMMANDS 8
516
517 /*
518 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
519 * A new event ack command requests mptsas_cmd and scsi_pkt structures
520 * from this pool, and returns it back when done.
521 */
522
523 typedef struct m_replyh_arg {
524 void *mpt;
525 uint32_t rfm;
526 } m_replyh_arg_t;
527 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
528 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
529
530 /*
531 * Flags for DR handler topology change
532 */
533 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
534 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
535 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
536 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
537 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
538 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
539
540 typedef struct mptsas_topo_change_list {
541 void *mpt;
542 uint_t event;
543 union {
544 uint8_t physport;
545 mptsas_phymask_t phymask;
546 } un;
547 uint16_t devhdl;
548 void *object;
549 uint8_t flags;
550 struct mptsas_topo_change_list *next;
551 } mptsas_topo_change_list_t;
552
553
554 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
555 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
556 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
557 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
558 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
559 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
560
561 /*
562 * Status types when calling mptsas_get_target_device_info
563 */
564 #define DEV_INFO_SUCCESS 0x0
565 #define DEV_INFO_FAIL_PAGE0 0x1
566 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
567 #define DEV_INFO_PHYS_DISK 0x3
568 #define DEV_INFO_FAIL_ALLOC 0x4
569 #define DEV_INFO_FAIL_GUID 0x5
570
571 /*
572 * mpt hotplug event defines
573 */
574 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
575 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
576 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
577
578 /*
579 * SMP target hotplug events
580 */
581 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
582 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
583 #define MPTSAS_DR_EVENT_MASK 0x3F
584
585 /*
586 * mpt hotplug status definition for m_dr_flag
587 */
588
589 /*
590 * MPTSAS_DR_INACTIVE
591 *
592 * The target is in a normal operating state.
593 * No dynamic reconfiguration operation is in progress.
594 */
595 #define MPTSAS_DR_INACTIVE 0x0
596 /*
597 * MPTSAS_DR_INTRANSITION
598 *
599 * The target is in a transition mode since
600 * hotplug event happens and offline procedure has not
601 * been finished
602 */
603 #define MPTSAS_DR_INTRANSITION 0x1
604
605 typedef struct mptsas_tgt_private {
606 int t_lun;
607 struct mptsas_target *t_private;
608 } mptsas_tgt_private_t;
609
610 /*
611 * The following defines are used in mptsas_set_init_mode to track the current
612 * state as we progress through reprogramming the HBA from target mode into
613 * initiator mode.
614 */
615
616 #define IOUC_READ_PAGE0 0x00000100
617 #define IOUC_READ_PAGE1 0x00000200
618 #define IOUC_WRITE_PAGE1 0x00000400
619 #define IOUC_DONE 0x00000800
620 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
621 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
622
623 /*
624 * Last allocated slot is used for TM requests. Since only m_max_requests
625 * frames are allocated, the last SMID will be m_max_requests - 1.
626 */
627 #define MPTSAS_SLOTS_SIZE(mpt) \
628 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
629 mpt->m_max_requests))
630 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
631
632 /*
633 * Macro for phy_flags
634 */
635
636 typedef struct smhba_info {
637 kmutex_t phy_mutex;
638 uint8_t phy_id;
639 uint64_t sas_addr;
640 char path[8];
641 uint16_t owner_devhdl;
642 uint16_t attached_devhdl;
643 uint8_t attached_phy_identify;
644 uint32_t attached_phy_info;
645 uint8_t programmed_link_rate;
646 uint8_t hw_link_rate;
647 uint8_t change_count;
648 uint32_t phy_info;
649 uint8_t negotiated_link_rate;
650 uint8_t port_num;
651 kstat_t *phy_stats;
652 uint32_t invalid_dword_count;
653 uint32_t running_disparity_error_count;
654 uint32_t loss_of_dword_sync_count;
655 uint32_t phy_reset_problem_count;
656 void *mpt;
657 } smhba_info_t;
658
659 typedef struct mptsas_phy_info {
660 uint8_t port_num;
661 uint8_t port_flags;
662 uint16_t ctrl_devhdl;
663 uint32_t phy_device_type;
664 uint16_t attached_devhdl;
665 mptsas_phymask_t phy_mask;
666 smhba_info_t smhba_info;
667 } mptsas_phy_info_t;
668
669
670 typedef struct mptsas_doneq_thread_arg {
671 void *mpt;
672 uint64_t t;
673 } mptsas_doneq_thread_arg_t;
674
675 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
676 typedef struct mptsas_doneq_thread_list {
677 mptsas_cmd_t *doneq;
678 mptsas_cmd_t **donetail;
679 kthread_t *threadp;
680 kcondvar_t cv;
681 ushort_t reserv1;
682 uint32_t reserv2;
683 kmutex_t mutex;
684 uint32_t flag;
685 uint32_t len;
686 mptsas_doneq_thread_arg_t arg;
687 } mptsas_doneq_thread_list_t;
688
689 typedef struct mptsas {
690 int m_instance;
691
692 struct mptsas *m_next;
693
694 scsi_hba_tran_t *m_tran;
695 smp_hba_tran_t *m_smptran;
696 kmutex_t m_mutex;
697 kmutex_t m_passthru_mutex;
698 kcondvar_t m_cv;
699 kcondvar_t m_passthru_cv;
700 kcondvar_t m_fw_cv;
701 kcondvar_t m_config_cv;
702 kcondvar_t m_fw_diag_cv;
703 dev_info_t *m_dip;
704
705 /*
706 * soft state flags
707 */
708 uint_t m_softstate;
709
710 refhash_t *m_targets;
711 refhash_t *m_smp_targets;
712 list_t m_enclosures;
713 refhash_t *m_tmp_targets;
714
715 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
716 uint8_t m_num_raid_configs;
717
718 struct mptsas_slots *m_active; /* outstanding cmds */
719
720 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
721 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
722
723 kmutex_t m_tx_waitq_mutex;
724 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
725 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
726 int m_tx_draining; /* TX queue draining flag */
727
728 mptsas_cmd_t *m_doneq; /* queue of completed commands */
729 mptsas_cmd_t **m_donetail; /* queue tail ptr */
730
731 /*
732 * variables for helper threads (fan-out interrupts)
733 */
734 mptsas_doneq_thread_list_t *m_doneq_thread_id;
735 uint32_t m_doneq_thread_n;
736 uint32_t m_doneq_thread_threshold;
737 uint32_t m_doneq_length_threshold;
738 uint32_t m_doneq_len;
739 kcondvar_t m_doneq_thread_cv;
740 kmutex_t m_doneq_mutex;
741
742 int m_ncmds; /* number of outstanding commands */
743 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
744 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
745
746 ddi_acc_handle_t m_datap; /* operating regs data access handle */
747
748 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
749
750 ushort_t m_devid; /* device id of chip. */
751 uchar_t m_revid; /* revision of chip. */
752 uint16_t m_svid; /* subsystem Vendor ID of chip */
753 uint16_t m_ssid; /* subsystem Device ID of chip */
754
755 uchar_t m_sync_offset; /* default offset for this chip. */
756
757 timeout_id_t m_quiesce_timeid;
758
759 ddi_dma_handle_t m_dma_req_frame_hdl;
760 ddi_acc_handle_t m_acc_req_frame_hdl;
761 ddi_dma_handle_t m_dma_req_sense_hdl;
762 ddi_acc_handle_t m_acc_req_sense_hdl;
763 ddi_dma_handle_t m_dma_reply_frame_hdl;
764 ddi_acc_handle_t m_acc_reply_frame_hdl;
765 ddi_dma_handle_t m_dma_free_queue_hdl;
766 ddi_acc_handle_t m_acc_free_queue_hdl;
767 ddi_dma_handle_t m_dma_post_queue_hdl;
768 ddi_acc_handle_t m_acc_post_queue_hdl;
769
770 /*
771 * list of reset notification requests
772 */
773 struct scsi_reset_notify_entry *m_reset_notify_listf;
774
775 /*
776 * qfull handling
777 */
778 timeout_id_t m_restart_cmd_timeid;
779
780 /*
781 * scsi reset delay per bus
782 */
783 uint_t m_scsi_reset_delay;
784
785 int m_pm_idle_delay;
786
787 uchar_t m_polled_intr; /* intr was polled. */
788 uchar_t m_suspended; /* true if driver is suspended */
789
790 struct kmem_cache *m_kmem_cache;
791 struct kmem_cache *m_cache_frames;
792
793 /*
794 * hba options.
795 */
796 uint_t m_options;
797
798 int m_in_callback;
799
800 int m_power_level; /* current power level */
801
802 int m_busy; /* power management busy state */
803
804 off_t m_pmcsr_offset; /* PMCSR offset */
805
806 ddi_acc_handle_t m_config_handle;
807
808 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
809 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
810 ddi_device_acc_attr_t m_dev_acc_attr;
811 ddi_device_acc_attr_t m_reg_acc_attr;
812
813 /*
814 * request/reply variables
815 */
816 caddr_t m_req_frame;
817 uint64_t m_req_frame_dma_addr;
818 caddr_t m_req_sense;
819 caddr_t m_extreq_sense;
820 uint_t m_extreq_sense_refcount;
821 kcondvar_t m_extreq_sense_refcount_cv;
822 uint64_t m_req_sense_dma_addr;
823 caddr_t m_reply_frame;
824 uint64_t m_reply_frame_dma_addr;
825 caddr_t m_free_queue;
826 uint64_t m_free_queue_dma_addr;
827 caddr_t m_post_queue;
828 uint64_t m_post_queue_dma_addr;
829 struct map *m_erqsense_map;
830
831 m_replyh_arg_t *m_replyh_args;
832
833 uint16_t m_max_requests;
834 uint16_t m_req_frame_size;
835 uint16_t m_req_sense_size;
836
837 /*
838 * Max frames per request reprted in IOC Facts
839 */
840 uint8_t m_max_chain_depth;
841 /*
842 * Max frames per request which is used in reality. It's adjusted
843 * according DMA SG length attribute, and shall not exceed the
844 * m_max_chain_depth.
845 */
846 uint8_t m_max_request_frames;
847
848 uint16_t m_free_queue_depth;
849 uint16_t m_post_queue_depth;
850 uint16_t m_max_replies;
851 uint32_t m_free_index;
852 uint32_t m_post_index;
853 uint8_t m_reply_frame_size;
854 uint32_t m_ioc_capabilities;
855
856 /*
857 * indicates if the firmware was upload by the driver
858 * at boot time
859 */
860 ushort_t m_fwupload;
861
862 uint16_t m_productid;
863
864 /*
865 * per instance data structures for dma memory resources for
866 * MPI handshake protocol. only one handshake cmd can run at a time.
867 */
868 ddi_dma_handle_t m_hshk_dma_hdl;
869 ddi_acc_handle_t m_hshk_acc_hdl;
870 caddr_t m_hshk_memp;
871 size_t m_hshk_dma_size;
872
873 /* Firmware version on the card at boot time */
874 uint32_t m_fwversion;
875
876 /* MSI specific fields */
877 ddi_intr_handle_t *m_htable; /* For array of interrupts */
878 int m_intr_type; /* What type of interrupt */
879 int m_intr_cnt; /* # of intrs count returned */
880 size_t m_intr_size; /* Size of intr array */
881 uint_t m_intr_pri; /* Interrupt priority */
882 int m_intr_cap; /* Interrupt capabilities */
883 ddi_taskq_t *m_event_taskq;
884
885 /* SAS specific information */
886
887 union {
888 uint64_t m_base_wwid; /* Base WWID */
889 struct {
890 #ifdef _BIG_ENDIAN
891 uint32_t m_base_wwid_hi;
892 uint32_t m_base_wwid_lo;
893 #else
894 uint32_t m_base_wwid_lo;
895 uint32_t m_base_wwid_hi;
896 #endif
897 } sasaddr;
898 } un;
899
900 uint8_t m_num_phys; /* # of PHYs */
901 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
902 uint8_t m_port_chng; /* initiator port changes */
903 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
904 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
905
906 /* FMA Capabilities */
907 int m_fm_capabilities;
908 ddi_taskq_t *m_dr_taskq;
909 int m_mpxio_enable;
910 uint8_t m_done_traverse_dev;
911 uint8_t m_done_traverse_smp;
912 uint8_t m_done_traverse_enc;
913 int m_diag_action_in_progress;
914 uint16_t m_dev_handle;
915 uint16_t m_smp_devhdl;
916
917 /*
918 * Event recording
919 */
920 uint8_t m_event_index;
921 uint32_t m_event_number;
922 uint32_t m_event_mask[4];
923 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
924
925 /*
926 * FW diag Buffer List
927 */
928 mptsas_fw_diagnostic_buffer_t
929 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
930
931 /* GEN3 support */
932 uint8_t m_MPI25;
933
934 /*
935 * Event Replay flag (MUR support)
936 */
937 uint8_t m_event_replay;
938
939 /*
940 * IR Capable flag
941 */
942 uint8_t m_ir_capable;
943
944 /*
945 * Is HBA processing a diag reset?
946 */
947 uint8_t m_in_reset;
948
949 /*
950 * per instance cmd data structures for task management cmds
951 */
952 m_event_struct_t m_event_task_mgmt; /* must be last */
953 /* ... scsi_pkt_size */
954 } mptsas_t;
955 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
956 sizeof (struct scsi_pkt) + scsi_pkt_size())
957 /*
958 * Only one of below two conditions is satisfied, we
959 * think the target is associated to the iport and
960 * allow call into mptsas_probe_lun().
961 * 1. physicalsport == physport
962 * 2. (phymask & (1 << physport)) == 0
963 * The condition #2 is because LSI uses lowest PHY
964 * number as the value of physical port when auto port
965 * configuration.
966 */
967 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
968 ((physicalport == physport) || (dynamicport && (phymask & \
969 (1 << physport))))
970
971 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
972 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
973 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
974 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
975 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
976 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
977 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
978 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
979 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
980
981 /*
982 * These should eventually migrate into the mpt header files
983 * that may become the /kernel/misc/mpt module...
984 */
985 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
986 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
987 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
988 mptsas_put_msg_Function(hdl, mp, Function); \
989 mptsas_put_msg_Lun(hdl, mp, Lun)
990
991 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
992 ddi_put16(hdl, &(mp)->DevHandle, (val))
993 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
994 ddi_put8(hdl, &(mp)->ChainOffset, (val))
995 #define mptsas_put_msg_Function(hdl, mp, val) \
996 ddi_put8(hdl, &(mp)->Function, (val))
997 #define mptsas_put_msg_Lun(hdl, mp, val) \
998 ddi_put8(hdl, &(mp)->LUN[1], (val))
999
1000 #define mptsas_get_msg_Function(hdl, mp) \
1001 ddi_get8(hdl, &(mp)->Function)
1002
1003 #define mptsas_get_msg_MsgFlags(hdl, mp) \
1004 ddi_get8(hdl, &(mp)->MsgFlags)
1005
1006 #define MPTSAS_ENABLE_DRWE(hdl) \
1007 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1008 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
1009 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1010 MPI2_WRSEQ_1ST_KEY_VALUE); \
1011 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1012 MPI2_WRSEQ_2ND_KEY_VALUE); \
1013 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1014 MPI2_WRSEQ_3RD_KEY_VALUE); \
1015 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1016 MPI2_WRSEQ_4TH_KEY_VALUE); \
1017 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1018 MPI2_WRSEQ_5TH_KEY_VALUE); \
1019 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1020 MPI2_WRSEQ_6TH_KEY_VALUE);
1021
1022 /*
1023 * m_options flags
1024 */
1025 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1026
1027 /*
1028 * m_softstate flags
1029 */
1030 #define MPTSAS_SS_DRAINING 0x02
1031 #define MPTSAS_SS_QUIESCED 0x04
1032 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
1033 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
1034
1035 /*
1036 * regspec defines.
1037 */
1038 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1039 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1040 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1041 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1042
1043 /*
1044 * Handy constants
1045 */
1046 #define FALSE 0
1047 #define TRUE 1
1048 #define UNDEFINED -1
1049 #define FAILED -2
1050
1051 /*
1052 * power management.
1053 */
1054 #define MPTSAS_POWER_ON(mpt) { \
1055 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1056 PCI_PMCSR_D0); \
1057 delay(drv_usectohz(10000)); \
1058 (void) pci_restore_config_regs(mpt->m_dip); \
1059 mptsas_setup_cmd_reg(mpt); \
1060 }
1061
1062 #define MPTSAS_POWER_OFF(mpt) { \
1063 (void) pci_save_config_regs(mpt->m_dip); \
1064 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1065 PCI_PMCSR_D3HOT); \
1066 mpt->m_power_level = PM_LEVEL_D3; \
1067 }
1068
1069 /*
1070 * inq_dtype:
1071 * Bits 5 through 7 are the Peripheral Device Qualifier
1072 * 001b: device not connected to the LUN
1073 * Bits 0 through 4 are the Peripheral Device Type
1074 * 1fh: Unknown or no device type
1075 *
1076 * Although the inquiry may return success, the following value
1077 * means no valid LUN connected.
1078 */
1079 #define MPTSAS_VALID_LUN(sd_inq) \
1080 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1081 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1082
1083 /*
1084 * Default is to have 10 retries on receiving QFULL status and
1085 * each retry to be after 100 ms.
1086 */
1087 #define QFULL_RETRIES 10
1088 #define QFULL_RETRY_INTERVAL 100
1089
1090 /*
1091 * Handy macros
1092 */
1093 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1094 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1095
1096 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1097 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1098
1099 /*
1100 * poll time for mptsas_pollret() and mptsas_wait_intr()
1101 */
1102 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1103
1104 /*
1105 * default time for mptsas_do_passthru
1106 */
1107 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1108
1109 /*
1110 * macro to return the effective address of a given per-target field
1111 */
1112 #define EFF_ADDR(start, offset) ((start) + (offset))
1113
1114 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1115 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1116 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1117 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1118 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1119
1120
1121 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1122 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1123 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1124 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1125
1126 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1127
1128 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1129 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1130 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1131 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1132
1133 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1134 &(mpt)->m_reg->HostInterruptStatus))
1135
1136 #define MPTSAS_SET_SIGP(P) \
1137 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1138
1139 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1140 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1141
1142 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1143 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1144
1145
1146 #define MPTSAS_START_CMD(mpt, req_desc) \
1147 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \
1148 req_desc & 0xffffffffu); \
1149 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \
1150 (req_desc >> 32) & 0xffffffffu);
1151
1152 #define INTPENDING(mpt) \
1153 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1154
1155 /*
1156 * Mask all interrupts to disable
1157 */
1158 #define MPTSAS_DISABLE_INTR(mpt) \
1159 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1160 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1161
1162 /*
1163 * Mask Doorbell and Reset interrupts to enable reply desc int.
1164 */
1165 #define MPTSAS_ENABLE_INTR(mpt) \
1166 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1167 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1168
1169 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1170 &((uint64_t *)(void *)mpt->m_post_queue)[index]
1171
1172 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1173 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1174
1175 #define ClrSetBits32(hdl, reg, clr, set) \
1176 ddi_put32(hdl, (reg), \
1177 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1178
1179 #define ClrSetBits(reg, clr, set) \
1180 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1181 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1182
1183 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1184 if ((cmdp = mpt->m_waitq) != NULL) { \
1185 /* If the queue is now empty fix the tail pointer */ \
1186 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1187 mpt->m_waitqtail = &mpt->m_waitq; \
1188 cmdp->cmd_linkp = NULL; \
1189 cmdp->cmd_queued = FALSE; \
1190 }
1191
1192 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1193 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1194 /* If the queue is now empty fix the tail pointer */ \
1195 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1196 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1197 cmdp->cmd_linkp = NULL; \
1198 cmdp->cmd_queued = FALSE; \
1199 }
1200
1201 /*
1202 * defaults for the global properties
1203 */
1204 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1205 #define DEFAULT_TAG_AGE_LIMIT 2
1206 #define DEFAULT_WD_TICK 1
1207
1208 /*
1209 * invalid hostid.
1210 */
1211 #define MPTSAS_INVALID_HOSTID -1
1212
1213 /*
1214 * Get/Set hostid from SCSI port configuration page
1215 */
1216 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1217 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1218
1219 /*
1220 * Config space.
1221 */
1222 #define MPTSAS_LATENCY_TIMER 0x40
1223
1224 /*
1225 * Offset to firmware version
1226 */
1227 #define MPTSAS_FW_VERSION_OFFSET 9
1228
1229 /*
1230 * Offset and masks to get at the ProductId field
1231 */
1232 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1233 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1234 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1235
1236 /*
1237 * Subsystem ID for HBAs.
1238 */
1239 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1240 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1241
1242 /*
1243 * reset delay tick
1244 */
1245 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1246
1247 /*
1248 * Ioc reset return values
1249 */
1250 #define MPTSAS_RESET_FAIL -1
1251 #define MPTSAS_NO_RESET 0
1252 #define MPTSAS_SUCCESS_HARDRESET 1
1253 #define MPTSAS_SUCCESS_MUR 2
1254
1255 /*
1256 * throttle support.
1257 */
1258 #define MAX_THROTTLE 32
1259 #define HOLD_THROTTLE 0
1260 #define DRAIN_THROTTLE -1
1261 #define QFULL_THROTTLE -2
1262
1263 /*
1264 * Passthrough/config request flags
1265 */
1266 #define MPTSAS_DATA_ALLOCATED 0x0001
1267 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1268 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1269 #define MPTSAS_ADDRESS_REPLY 0x0008
1270 #define MPTSAS_CMD_TIMEOUT 0x0010
1271
1272 /*
1273 * response code tlr flag
1274 */
1275 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1276
1277 /*
1278 * System Events
1279 */
1280 #ifndef DDI_VENDOR_LSI
1281 #define DDI_VENDOR_LSI "LSI"
1282 #endif /* DDI_VENDOR_LSI */
1283
1284 /*
1285 * Shared functions
1286 */
1287 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1288 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1289 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1290 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1291 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1292 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1293 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1294 uint8_t type, int mode);
1295 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1296 uint8_t type, int mode);
1297 int mptsas_download_firmware();
1298 int mptsas_can_download_firmware();
1299 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1300 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1301 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1302 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1303 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1304 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1305 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1306 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1307 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1308 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1309 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1310
1311 /*
1312 * impl functions
1313 */
1314 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1315 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1316 int mptsas_ioc_reset(mptsas_t *mpt, int);
1317 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1318 ddi_acc_handle_t accessp);
1319 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1320 ddi_acc_handle_t accessp);
1321 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1322 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1323 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1324 uint64_t SGEaddress);
1325 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1326 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1327 uint8_t pageversion, uint16_t extpagelength,
1328 uint32_t SGEflagslength, uint64_t SGEaddress);
1329
1330 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1331 struct scsi_pkt **pkt);
1332 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1333 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1334 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1335 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1336 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1337 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1338
1339 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1340 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1341 int mode);
1342 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1343 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1344 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1345 int mptsas_restart_ioc(mptsas_t *mpt);
1346 void mptsas_update_driver_data(struct mptsas *mpt);
1347 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1348
1349 /*
1350 * init functions
1351 */
1352 int mptsas_ioc_get_facts(mptsas_t *mpt);
1353 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1354 int mptsas_ioc_enable_port(mptsas_t *mpt);
1355 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1356 int mptsas_ioc_init(mptsas_t *mpt);
1357
1358 /*
1359 * configuration pages operation
1360 */
1361 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1362 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1363 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1364 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
1365 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1366 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1367 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1368 mptsas_smp_t *info);
1369 int mptsas_set_ioc_params(mptsas_t *mpt);
1370 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1371 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1372 uint64_t *sas_wwn, uint8_t *portwidth);
1373 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1374 int mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1375 smhba_info_t *info);
1376 int mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1377 smhba_info_t *info);
1378 int mptsas_get_manufacture_page0(mptsas_t *mpt);
1379 int mptsas_get_enclosure_page0(mptsas_t *mpt, uint32_t page_address,
1380 mptsas_enclosure_t *mpe);
1381 void mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1382 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1383 int mptsas_smhba_phy_init(mptsas_t *mpt);
1384 /*
1385 * RAID functions
1386 */
1387 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1388 int mptsas_get_raid_info(mptsas_t *mpt);
1389 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1390 uint8_t physdisknum);
1391 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1392 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1393
1394 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1395 /*
1396 * debugging.
1397 * MPTSAS_DBGLOG_LINECNT must be a power of 2.
1398 */
1399 #define MPTSAS_DBGLOG_LINECNT 128
1400 #define MPTSAS_DBGLOG_LINELEN 256
1401 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN)
1402
1403 #if defined(MPTSAS_DEBUG)
1404
1405 extern uint32_t mptsas_debugprt_flags;
1406 extern uint32_t mptsas_debuglog_flags;
1407
1408 void mptsas_printf(char *fmt, ...);
1409 void mptsas_debug_log(char *fmt, ...);
1410
1411 #define MPTSAS_DBGPR(m, args) \
1412 if (mptsas_debugprt_flags & (m)) \
1413 mptsas_printf args; \
1414 if (mptsas_debuglog_flags & (m)) \
1415 mptsas_debug_log args
1416 #else /* ! defined(MPTSAS_DEBUG) */
1417 #define MPTSAS_DBGPR(m, args)
1418 #endif /* defined(MPTSAS_DEBUG) */
1419
1420 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1421 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1422 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1423 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1424
1425 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1426 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1427 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1428 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1429
1430 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1431 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1432 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1433 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1434
1435 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1436 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1437 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1438 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */
1439
1440 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */
1441 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1442 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1443 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1444
1445 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1446 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1447 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1448 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1449
1450 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1451 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1452 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1453 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */
1454
1455 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1456 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1457 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1458 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1459
1460 /*
1461 * auto request sense
1462 */
1463 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1464 (pkt)->pkt_flags = (flag), \
1465 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1466 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1467 (pkt)->pkt_address.a_lun
1468
1469 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1470 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1471 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1472 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1473
1474
1475 #ifdef __cplusplus
1476 }
1477 #endif
1478
1479 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */