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NEX-17006 backport mpt_sas tri-mode parts support change
9044 Need support for mpt_sas tri-mode parts
9045 Clean up mpt_sas compiler warnings
9046 mptsas_handle_topo_change can return without its locks held
9047 workaround SAS3408 firmware issue
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
Reviewed by: Albert Lee <trisk@forkgnu.org>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Approved by: Richard Lowe <richlowe@richlowe.net>
NEX-1888 import latest mpi2 headers from LSIs FreeBSD driver
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h
1 1 /*-
2 - * Copyright (c) 2013 LSI Corp.
2 + * Copyright (c) 2012-2015 LSI Corp.
3 + * Copyright (c) 2013-2016 Avago Technologies
3 4 * All rights reserved.
4 5 *
5 6 * Redistribution and use in source and binary forms, with or without
6 7 * modification, are permitted provided that the following conditions
7 8 * are met:
8 9 * 1. Redistributions of source code must retain the above copyright
9 10 * notice, this list of conditions and the following disclaimer.
10 11 * 2. Redistributions in binary form must reproduce the above copyright
11 12 * notice, this list of conditions and the following disclaimer in the
12 13 * documentation and/or other materials provided with the distribution.
13 14 * 3. Neither the name of the author nor the names of any co-contributors
14 15 * may be used to endorse or promote products derived from this software
15 16 * without specific prior written permission.
16 17 *
17 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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21 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 28 * SUCH DAMAGE.
28 29 */
29 30
30 31 /*
31 - * Copyright (c) 2000-2013 LSI Corporation.
32 + * Copyright (c) 2000-2015 LSI Corporation.
33 + * Copyright (c) 2013-2016 Avago Technologies
34 + * All rights reserved.
32 35 *
33 36 *
34 37 * Name: mpi2.h
35 38 * Title: MPI Message independent structures and definitions
36 39 * including System Interface Register Set and
37 40 * scatter/gather formats.
38 41 * Creation Date: June 21, 2006
39 42 *
40 - * mpi2.h Version: 02.00.33
43 + * mpi2.h Version: 02.00.46
41 44 *
42 45 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
43 46 * prefix are for use only on MPI v2.5 products, and must not be used
44 47 * with MPI v2.0 products. Unless otherwise noted, names beginning with
45 48 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
46 49 *
47 50 * Version History
48 51 * ---------------
49 52 *
50 53 * Date Version Description
51 54 * -------- -------- ------------------------------------------------------
52 55 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
53 56 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
54 57 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
55 58 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
56 59 * Moved ReplyPostHostIndex register to offset 0x6C of the
57 60 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
58 61 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
59 62 * Added union of request descriptors.
60 63 * Added union of reply descriptors.
61 64 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
62 65 * Added define for MPI2_VERSION_02_00.
63 66 * Fixed the size of the FunctionDependent5 field in the
64 67 * MPI2_DEFAULT_REPLY structure.
65 68 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
66 69 * Removed the MPI-defined Fault Codes and extended the
67 70 * product specific codes up to 0xEFFF.
68 71 * Added a sixth key value for the WriteSequence register
69 72 * and changed the flush value to 0x0.
70 73 * Added message function codes for Diagnostic Buffer Post
71 74 * and Diagnsotic Release.
72 75 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
73 76 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
74 77 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
75 78 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
76 79 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
77 80 * Added #defines for marking a reply descriptor as unused.
78 81 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
79 82 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
80 83 * Moved LUN field defines from mpi2_init.h.
81 84 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
82 85 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
83 86 * In all request and reply descriptors, replaced VF_ID
84 87 * field with MSIxIndex field.
85 88 * Removed DevHandle field from
86 89 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
87 90 * bytes reserved.
88 91 * Added RAID Accelerator functionality.
89 92 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
90 93 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
91 94 * Added MSI-x index mask and shift for Reply Post Host
92 95 * Index register.
93 96 * Added function code for Host Based Discovery Action.
94 97 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
95 98 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
96 99 * Added defines for product-specific range of message
97 100 * function codes, 0xF0 to 0xFF.
98 101 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
99 102 * Added alternative defines for the SGE Direction bit.
100 103 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
101 104 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
102 105 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
103 106 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
104 107 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
105 108 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
106 109 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
107 110 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
108 111 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
109 112 * Incorporating additions for MPI v2.5.
110 113 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
111 114 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
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112 115 * Added Hard Reset delay timings.
113 116 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
114 117 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
115 118 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
116 119 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
117 120 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
118 121 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
119 122 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
120 123 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
121 124 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
125 + * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT.
126 + * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
127 + * 11-18-14 02.00.36 Updated copyright information.
128 + * Bumped MPI2_HEADER_VERSION_UNIT.
129 + * 03-16-15 02.00.37 Updated for MPI v2.6.
130 + * Bumped MPI2_HEADER_VERSION_UNIT.
131 + * Added Scratchpad registers and
132 + * AtomicRequestDescriptorPost register to
133 + * MPI2_SYSTEM_INTERFACE_REGS.
134 + * Added MPI2_DIAG_SBR_RELOAD.
135 + * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER.
136 + * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
137 + * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT
138 + * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
139 + * Added V7 HostDiagnostic register defines
140 + * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
141 + * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
142 + * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines
143 + * to be unique within first 32 characters.
144 + * Removed AHCI support.
145 + * Removed SOP support.
146 + * Bumped MPI2_HEADER_VERSION_UNIT.
147 + * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT.
148 + * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT.
149 + * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT.
122 150 * --------------------------------------------------------------------------
123 151 */
124 152
125 153 #ifndef MPI2_H
126 154 #define MPI2_H
127 155
128 156
129 157 /*****************************************************************************
130 158 *
131 159 * MPI Version Definitions
132 160 *
133 161 *****************************************************************************/
134 162
135 163 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
136 164 #define MPI2_VERSION_MAJOR_SHIFT (8)
137 165 #define MPI2_VERSION_MINOR_MASK (0x00FF)
138 166 #define MPI2_VERSION_MINOR_SHIFT (0)
139 167
140 168 /* major version for all MPI v2.x */
141 169 #define MPI2_VERSION_MAJOR (0x02)
142 170
143 171 /* minor version for MPI v2.0 compatible products */
144 172 #define MPI2_VERSION_MINOR (0x00)
145 173 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
146 174 MPI2_VERSION_MINOR)
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147 175 #define MPI2_VERSION_02_00 (0x0200)
148 176
149 177
150 178 /* minor version for MPI v2.5 compatible products */
151 179 #define MPI25_VERSION_MINOR (0x05)
152 180 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
153 181 MPI25_VERSION_MINOR)
154 182 #define MPI2_VERSION_02_05 (0x0205)
155 183
156 184
185 +/* minor version for MPI v2.6 compatible products */
186 +#define MPI26_VERSION_MINOR (0x06)
187 +#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
188 + MPI26_VERSION_MINOR)
189 +#define MPI2_VERSION_02_06 (0x0206)
190 +
191 +
157 192 /* Unit and Dev versioning for this MPI header set */
158 -#define MPI2_HEADER_VERSION_UNIT (0x21)
193 +#define MPI2_HEADER_VERSION_UNIT (0x2E)
159 194 #define MPI2_HEADER_VERSION_DEV (0x00)
160 195 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
161 196 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
162 197 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
163 198 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
164 199 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
165 200
166 201
167 202 /*****************************************************************************
168 203 *
169 204 * IOC State Definitions
170 205 *
171 206 *****************************************************************************/
172 207
173 208 #define MPI2_IOC_STATE_RESET (0x00000000)
174 209 #define MPI2_IOC_STATE_READY (0x10000000)
175 210 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
176 211 #define MPI2_IOC_STATE_FAULT (0x40000000)
177 212
178 213 #define MPI2_IOC_STATE_MASK (0xF0000000)
179 214 #define MPI2_IOC_STATE_SHIFT (28)
180 215
181 216 /* Fault state range for prodcut specific codes */
182 217 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
183 218 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
184 219
185 220
186 221 /*****************************************************************************
187 222 *
188 223 * System Interface Register Definitions
189 224 *
190 225 *****************************************************************************/
191 226
192 227 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
193 228 {
194 229 U32 Doorbell; /* 0x00 */
195 230 U32 WriteSequence; /* 0x04 */
196 231 U32 HostDiagnostic; /* 0x08 */
197 232 U32 Reserved1; /* 0x0C */
198 233 U32 DiagRWData; /* 0x10 */
199 234 U32 DiagRWAddressLow; /* 0x14 */
200 235 U32 DiagRWAddressHigh; /* 0x18 */
201 236 U32 Reserved2[5]; /* 0x1C */
202 237 U32 HostInterruptStatus; /* 0x30 */
203 238 U32 HostInterruptMask; /* 0x34 */
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204 239 U32 DCRData; /* 0x38 */
205 240 U32 DCRAddress; /* 0x3C */
206 241 U32 Reserved3[2]; /* 0x40 */
207 242 U32 ReplyFreeHostIndex; /* 0x48 */
208 243 U32 Reserved4[8]; /* 0x4C */
209 244 U32 ReplyPostHostIndex; /* 0x6C */
210 245 U32 Reserved5; /* 0x70 */
211 246 U32 HCBSize; /* 0x74 */
212 247 U32 HCBAddressLow; /* 0x78 */
213 248 U32 HCBAddressHigh; /* 0x7C */
214 - U32 Reserved6[16]; /* 0x80 */
249 + U32 Reserved6[12]; /* 0x80 */
250 + U32 Scratchpad[4]; /* 0xB0 */
215 251 U32 RequestDescriptorPostLow; /* 0xC0 */
216 252 U32 RequestDescriptorPostHigh; /* 0xC4 */
217 - U32 Reserved7[14]; /* 0xC8 */
253 + U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */
254 + U32 Reserved7[13]; /* 0xCC */
218 255 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
219 256 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
220 257
221 258 /*
222 259 * Defines for working with the Doorbell register.
223 260 */
224 261 #define MPI2_DOORBELL_OFFSET (0x00000000)
225 262
226 263 /* IOC --> System values */
227 264 #define MPI2_DOORBELL_USED (0x08000000)
228 265 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
229 266 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
230 267 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
231 268 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
232 269
233 270 /* System --> IOC values */
234 271 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
235 272 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
236 273 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
237 274 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
238 275
239 276
240 277 /*
241 278 * Defines for the WriteSequence register
242 279 */
243 280 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
244 281 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
245 282 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
246 283 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
247 284 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
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248 285 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
249 286 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
250 287 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
251 288 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
252 289
253 290 /*
254 291 * Defines for the HostDiagnostic register
255 292 */
256 293 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
257 294
295 +#define MPI2_DIAG_SBR_RELOAD (0x00002000)
296 +
258 297 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
259 298 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
260 299 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
261 300
301 +/* Defines for V7A/V7R HostDiagnostic Register */
302 +#define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
303 +#define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
304 +#define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
305 +#define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
306 +
262 307 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
263 308 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
264 309 #define MPI2_DIAG_HCB_MODE (0x00000100)
265 310 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
266 311 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
267 312 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
268 313 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
269 314 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
270 315 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
271 316
272 317 /*
273 318 * Offsets for DiagRWData and address
274 319 */
275 320 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
276 321 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
277 322 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
278 323
279 324 /*
280 325 * Defines for the HostInterruptStatus register
281 326 */
282 327 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
283 328 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
284 329 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
285 330 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
286 331 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
287 332 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
288 333 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
289 334
290 335 /*
291 336 * Defines for the HostInterruptMask register
292 337 */
293 338 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
294 339 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
295 340 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
296 341 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
297 342 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
298 343 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
299 344
300 345 /*
301 346 * Offsets for DCRData and address
302 347 */
303 348 #define MPI2_DCR_DATA_OFFSET (0x00000038)
304 349 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
305 350
306 351 /*
307 352 * Offset for the Reply Free Queue
308 353 */
309 354 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
310 355
311 356 /*
312 357 * Defines for the Reply Descriptor Post Queue
313 358 */
314 359 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
315 360 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
316 361 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
317 362 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
318 363 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
319 364
320 365
321 366 /*
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322 367 * Defines for the HCBSize and address
323 368 */
324 369 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
325 370 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
326 371 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
327 372
328 373 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
329 374 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
330 375
331 376 /*
332 - * Offsets for the Request Queue
377 + * Offsets for the Scratchpad registers
333 378 */
379 +#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
380 +#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
381 +#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
382 +#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
383 +
384 +/*
385 + * Offsets for the Request Descriptor Post Queue
386 + */
334 387 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
335 388 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
389 +#define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
336 390
337 391
338 392 /* Hard Reset delay timings */
339 393 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
340 394 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
341 395 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
342 396
343 397 /*****************************************************************************
344 398 *
345 399 * Message Descriptors
346 400 *
347 401 *****************************************************************************/
348 402
349 403 /* Request Descriptors */
350 404
351 405 /* Default Request Descriptor */
352 406 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
353 407 {
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354 408 U8 RequestFlags; /* 0x00 */
355 409 U8 MSIxIndex; /* 0x01 */
356 410 U16 SMID; /* 0x02 */
357 411 U16 LMID; /* 0x04 */
358 412 U16 DescriptorTypeDependent; /* 0x06 */
359 413 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
360 414 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
361 415 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
362 416
363 417 /* defines for the RequestFlags field */
364 -#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
418 +#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
419 +#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */
365 420 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
366 421 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
367 422 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
368 423 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
369 424 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
370 425 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
426 +#define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
371 427
372 428 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
373 429
374 430
375 431 /* High Priority Request Descriptor */
376 432 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
377 433 {
378 434 U8 RequestFlags; /* 0x00 */
379 435 U8 MSIxIndex; /* 0x01 */
380 436 U16 SMID; /* 0x02 */
381 437 U16 LMID; /* 0x04 */
382 438 U16 Reserved1; /* 0x06 */
383 439 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
384 440 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
385 441 Mpi2HighPriorityRequestDescriptor_t,
386 442 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
387 443
388 444
389 445 /* SCSI IO Request Descriptor */
390 446 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
391 447 {
392 448 U8 RequestFlags; /* 0x00 */
393 449 U8 MSIxIndex; /* 0x01 */
394 450 U16 SMID; /* 0x02 */
395 451 U16 LMID; /* 0x04 */
396 452 U16 DevHandle; /* 0x06 */
397 453 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
398 454 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
399 455 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
400 456
401 457
402 458 /* SCSI Target Request Descriptor */
403 459 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
404 460 {
405 461 U8 RequestFlags; /* 0x00 */
406 462 U8 MSIxIndex; /* 0x01 */
407 463 U16 SMID; /* 0x02 */
408 464 U16 LMID; /* 0x04 */
409 465 U16 IoIndex; /* 0x06 */
410 466 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
411 467 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
412 468 Mpi2SCSITargetRequestDescriptor_t,
413 469 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
414 470
415 471
416 472 /* RAID Accelerator Request Descriptor */
417 473 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
418 474 {
419 475 U8 RequestFlags; /* 0x00 */
420 476 U8 MSIxIndex; /* 0x01 */
421 477 U16 SMID; /* 0x02 */
422 478 U16 LMID; /* 0x04 */
423 479 U16 Reserved; /* 0x06 */
424 480 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
425 481 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
426 482 Mpi2RAIDAcceleratorRequestDescriptor_t,
427 483 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
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428 484
429 485
430 486 /* Fast Path SCSI IO Request Descriptor */
431 487 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
432 488 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
433 489 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
434 490 Mpi25FastPathSCSIIORequestDescriptor_t,
435 491 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t;
436 492
437 493
494 +/* PCIe Encapsulated Request Descriptor */
495 +typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
496 + MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
497 + MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
498 + Mpi26PCIeEncapsulatedRequestDescriptor_t,
499 + MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t;
500 +
501 +
438 502 /* union of Request Descriptors */
439 503 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
440 504 {
441 505 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
442 506 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
443 507 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
444 508 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
445 509 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
446 510 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
511 + MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
447 512 U64 Words;
448 513 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
449 514 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
450 515
451 516
517 +/* Atomic Request Descriptors */
518 +
519 +/*
520 + * All Atomic Request Descriptors have the same format, so the following
521 + * structure is used for all Atomic Request Descriptors:
522 + * Atomic Default Request Descriptor
523 + * Atomic High Priority Request Descriptor
524 + * Atomic SCSI IO Request Descriptor
525 + * Atomic SCSI Target Request Descriptor
526 + * Atomic RAID Accelerator Request Descriptor
527 + * Atomic Fast Path SCSI IO Request Descriptor
528 + * Atomic PCIe Encapsulated Request Descriptor
529 + */
530 +
531 +/* Atomic Request Descriptor */
532 +typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR
533 +{
534 + U8 RequestFlags; /* 0x00 */
535 + U8 MSIxIndex; /* 0x01 */
536 + U16 SMID; /* 0x02 */
537 +} MPI26_ATOMIC_REQUEST_DESCRIPTOR,
538 + MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
539 + Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t;
540 +
541 +/* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */
542 +
543 +
452 544 /* Reply Descriptors */
453 545
454 546 /* Default Reply Descriptor */
455 547 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
456 548 {
457 549 U8 ReplyFlags; /* 0x00 */
458 550 U8 MSIxIndex; /* 0x01 */
459 551 U16 DescriptorTypeDependent1; /* 0x02 */
460 552 U32 DescriptorTypeDependent2; /* 0x04 */
461 553 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
462 554 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
463 555
464 556 /* defines for the ReplyFlags field */
465 557 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
466 558 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
467 559 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
468 560 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
469 561 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
470 562 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
471 563 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
564 +#define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
472 565 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
473 566
474 567 /* values for marking a reply descriptor as unused */
475 568 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
476 569 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
477 570
478 571 /* Address Reply Descriptor */
479 572 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
480 573 {
481 574 U8 ReplyFlags; /* 0x00 */
482 575 U8 MSIxIndex; /* 0x01 */
483 576 U16 SMID; /* 0x02 */
484 577 U32 ReplyFrameAddress; /* 0x04 */
485 578 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
486 579 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
487 580
488 581 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
489 582
490 583
491 584 /* SCSI IO Success Reply Descriptor */
492 585 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
493 586 {
494 587 U8 ReplyFlags; /* 0x00 */
495 588 U8 MSIxIndex; /* 0x01 */
496 589 U16 SMID; /* 0x02 */
497 590 U16 TaskTag; /* 0x04 */
498 591 U16 Reserved1; /* 0x06 */
499 592 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
500 593 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
501 594 Mpi2SCSIIOSuccessReplyDescriptor_t,
502 595 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
503 596
504 597
505 598 /* TargetAssist Success Reply Descriptor */
506 599 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
507 600 {
508 601 U8 ReplyFlags; /* 0x00 */
509 602 U8 MSIxIndex; /* 0x01 */
510 603 U16 SMID; /* 0x02 */
511 604 U8 SequenceNumber; /* 0x04 */
512 605 U8 Reserved1; /* 0x05 */
513 606 U16 IoIndex; /* 0x06 */
514 607 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
515 608 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
516 609 Mpi2TargetAssistSuccessReplyDescriptor_t,
517 610 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
518 611
519 612
520 613 /* Target Command Buffer Reply Descriptor */
521 614 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
522 615 {
523 616 U8 ReplyFlags; /* 0x00 */
524 617 U8 MSIxIndex; /* 0x01 */
525 618 U8 VP_ID; /* 0x02 */
526 619 U8 Flags; /* 0x03 */
527 620 U16 InitiatorDevHandle; /* 0x04 */
528 621 U16 IoIndex; /* 0x06 */
529 622 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
530 623 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
531 624 Mpi2TargetCommandBufferReplyDescriptor_t,
532 625 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
533 626
534 627 /* defines for Flags field */
535 628 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
536 629
537 630
538 631 /* RAID Accelerator Success Reply Descriptor */
539 632 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
540 633 {
541 634 U8 ReplyFlags; /* 0x00 */
542 635 U8 MSIxIndex; /* 0x01 */
543 636 U16 SMID; /* 0x02 */
544 637 U32 Reserved; /* 0x04 */
545 638 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
546 639 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
547 640 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
548 641 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
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549 642
550 643
551 644 /* Fast Path SCSI IO Success Reply Descriptor */
552 645 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
553 646 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
554 647 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
555 648 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
556 649 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
557 650
558 651
652 +/* PCIe Encapsulated Success Reply Descriptor */
653 +typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
654 + MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
655 + MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
656 + Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
657 + MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
658 +
659 +
559 660 /* union of Reply Descriptors */
560 661 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
561 662 {
562 663 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
563 664 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
564 665 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
565 666 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
566 667 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
567 668 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
568 669 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
670 + MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess;
569 671 U64 Words;
570 672 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
571 673 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
572 674
573 675
574 676
575 677 /*****************************************************************************
576 678 *
577 679 * Message Functions
578 680 *
579 681 *****************************************************************************/
580 682
581 683 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
582 684 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
583 685 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
584 686 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
585 687 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
586 688 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
587 689 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
588 690 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
589 691 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
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590 692 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
591 693 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
592 694 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
593 695 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
594 696 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
595 697 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
596 698 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
597 699 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
598 700 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
599 701 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
600 -#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
702 +#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */
703 +#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */
601 704 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
602 705 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
603 706 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
604 707 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
605 708 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
606 709 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
607 710 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
608 711 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
609 712 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */
713 +#define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */
610 714 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
611 715 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
612 716
613 717
614 718
615 719 /* Doorbell functions */
616 720 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
617 721 #define MPI2_FUNCTION_HANDSHAKE (0x42)
618 722
619 723
620 724 /*****************************************************************************
621 725 *
622 726 * IOC Status Values
623 727 *
624 728 *****************************************************************************/
625 729
626 730 /* mask for IOCStatus status value */
627 731 #define MPI2_IOCSTATUS_MASK (0x7FFF)
628 732
629 733 /****************************************************************************
630 734 * Common IOCStatus values for all replies
631 735 ****************************************************************************/
632 736
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633 737 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
634 738 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
635 739 #define MPI2_IOCSTATUS_BUSY (0x0002)
636 740 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
637 741 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
638 742 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
639 743 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
640 744 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
641 745 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
642 746 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
747 +#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */
643 748
644 749 /****************************************************************************
645 750 * Config IOCStatus values
646 751 ****************************************************************************/
647 752
648 753 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
649 754 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
650 755 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
651 756 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
652 757 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
653 758 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
654 759
655 760 /****************************************************************************
656 761 * SCSI IO Reply
657 762 ****************************************************************************/
658 763
659 764 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
660 765 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
661 766 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
662 767 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
663 768 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
664 769 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
665 770 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
666 771 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
667 772 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
668 773 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
669 774 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
670 775 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
671 776
672 777 /****************************************************************************
673 778 * For use by SCSI Initiator and SCSI Target end-to-end data protection
674 779 ****************************************************************************/
675 780
676 781 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
677 782 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
678 783 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
679 784
680 785 /****************************************************************************
681 786 * SCSI Target values
682 787 ****************************************************************************/
683 788
684 789 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
685 790 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
686 791 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
687 792 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
688 793 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
689 794 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
690 795 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
691 796 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
692 797 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
693 798 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
694 799
695 800 /****************************************************************************
696 801 * Serial Attached SCSI values
697 802 ****************************************************************************/
698 803
699 804 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
700 805 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
701 806
702 807 /****************************************************************************
703 808 * Diagnostic Buffer Post / Diagnostic Release values
704 809 ****************************************************************************/
705 810
706 811 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
707 812
708 813 /****************************************************************************
709 814 * RAID Accelerator values
710 815 ****************************************************************************/
711 816
712 817 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
713 818
714 819 /****************************************************************************
715 820 * IOCStatus flag to indicate that log info is available
716 821 ****************************************************************************/
717 822
718 823 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
719 824
720 825 /****************************************************************************
721 826 * IOCLogInfo Types
722 827 ****************************************************************************/
723 828
724 829 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
725 830 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
726 831 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
727 832 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
728 833 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
729 834 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
730 835 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
731 836 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
732 837
733 838
734 839 /*****************************************************************************
735 840 *
736 841 * Standard Message Structures
737 842 *
738 843 *****************************************************************************/
739 844
740 845 /****************************************************************************
741 846 * Request Message Header for all request messages
742 847 ****************************************************************************/
743 848
744 849 typedef struct _MPI2_REQUEST_HEADER
745 850 {
746 851 U16 FunctionDependent1; /* 0x00 */
747 852 U8 ChainOffset; /* 0x02 */
748 853 U8 Function; /* 0x03 */
749 854 U16 FunctionDependent2; /* 0x04 */
750 855 U8 FunctionDependent3; /* 0x06 */
751 856 U8 MsgFlags; /* 0x07 */
752 857 U8 VP_ID; /* 0x08 */
753 858 U8 VF_ID; /* 0x09 */
754 859 U16 Reserved1; /* 0x0A */
755 860 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
756 861 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
757 862
758 863
759 864 /****************************************************************************
760 865 * Default Reply
761 866 ****************************************************************************/
762 867
763 868 typedef struct _MPI2_DEFAULT_REPLY
764 869 {
765 870 U16 FunctionDependent1; /* 0x00 */
766 871 U8 MsgLength; /* 0x02 */
767 872 U8 Function; /* 0x03 */
768 873 U16 FunctionDependent2; /* 0x04 */
769 874 U8 FunctionDependent3; /* 0x06 */
770 875 U8 MsgFlags; /* 0x07 */
771 876 U8 VP_ID; /* 0x08 */
772 877 U8 VF_ID; /* 0x09 */
773 878 U16 Reserved1; /* 0x0A */
774 879 U16 FunctionDependent5; /* 0x0C */
775 880 U16 IOCStatus; /* 0x0E */
776 881 U32 IOCLogInfo; /* 0x10 */
777 882 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
778 883 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
779 884
780 885
781 886 /* common version structure/union used in messages and configuration pages */
782 887
783 888 typedef struct _MPI2_VERSION_STRUCT
784 889 {
785 890 U8 Dev; /* 0x00 */
786 891 U8 Unit; /* 0x01 */
787 892 U8 Minor; /* 0x02 */
788 893 U8 Major; /* 0x03 */
789 894 } MPI2_VERSION_STRUCT;
790 895
791 896 typedef union _MPI2_VERSION_UNION
792 897 {
793 898 MPI2_VERSION_STRUCT Struct;
794 899 U32 Word;
795 900 } MPI2_VERSION_UNION;
796 901
797 902
798 903 /* LUN field defines, common to many structures */
799 904 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
800 905 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
801 906 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
802 907 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
803 908 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
804 909 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
805 910
806 911
807 912 /*****************************************************************************
808 913 *
809 914 * Fusion-MPT MPI Scatter Gather Elements
810 915 *
811 916 *****************************************************************************/
812 917
813 918 /****************************************************************************
814 919 * MPI Simple Element structures
815 920 ****************************************************************************/
816 921
817 922 typedef struct _MPI2_SGE_SIMPLE32
818 923 {
819 924 U32 FlagsLength;
820 925 U32 Address;
821 926 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
822 927 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
823 928
824 929 typedef struct _MPI2_SGE_SIMPLE64
825 930 {
826 931 U32 FlagsLength;
827 932 U64 Address;
828 933 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
829 934 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
830 935
831 936 typedef struct _MPI2_SGE_SIMPLE_UNION
832 937 {
833 938 U32 FlagsLength;
834 939 union
835 940 {
836 941 U32 Address32;
837 942 U64 Address64;
838 943 } u;
839 944 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
840 945 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
841 946
842 947
843 948 /****************************************************************************
844 949 * MPI Chain Element structures - for MPI v2.0 products only
845 950 ****************************************************************************/
846 951
847 952 typedef struct _MPI2_SGE_CHAIN32
848 953 {
849 954 U16 Length;
850 955 U8 NextChainOffset;
851 956 U8 Flags;
852 957 U32 Address;
853 958 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
854 959 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
855 960
856 961 typedef struct _MPI2_SGE_CHAIN64
857 962 {
858 963 U16 Length;
859 964 U8 NextChainOffset;
860 965 U8 Flags;
861 966 U64 Address;
862 967 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
863 968 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
864 969
865 970 typedef struct _MPI2_SGE_CHAIN_UNION
866 971 {
867 972 U16 Length;
868 973 U8 NextChainOffset;
869 974 U8 Flags;
870 975 union
871 976 {
872 977 U32 Address32;
873 978 U64 Address64;
874 979 } u;
875 980 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
876 981 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
877 982
878 983
879 984 /****************************************************************************
880 985 * MPI Transaction Context Element structures - for MPI v2.0 products only
881 986 ****************************************************************************/
882 987
883 988 typedef struct _MPI2_SGE_TRANSACTION32
884 989 {
885 990 U8 Reserved;
886 991 U8 ContextSize;
887 992 U8 DetailsLength;
888 993 U8 Flags;
889 994 U32 TransactionContext[1];
890 995 U32 TransactionDetails[1];
891 996 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
892 997 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
893 998
894 999 typedef struct _MPI2_SGE_TRANSACTION64
895 1000 {
896 1001 U8 Reserved;
897 1002 U8 ContextSize;
898 1003 U8 DetailsLength;
899 1004 U8 Flags;
900 1005 U32 TransactionContext[2];
901 1006 U32 TransactionDetails[1];
902 1007 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
903 1008 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
904 1009
905 1010 typedef struct _MPI2_SGE_TRANSACTION96
906 1011 {
907 1012 U8 Reserved;
908 1013 U8 ContextSize;
909 1014 U8 DetailsLength;
910 1015 U8 Flags;
911 1016 U32 TransactionContext[3];
912 1017 U32 TransactionDetails[1];
913 1018 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
914 1019 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
915 1020
916 1021 typedef struct _MPI2_SGE_TRANSACTION128
917 1022 {
918 1023 U8 Reserved;
919 1024 U8 ContextSize;
920 1025 U8 DetailsLength;
921 1026 U8 Flags;
922 1027 U32 TransactionContext[4];
923 1028 U32 TransactionDetails[1];
924 1029 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
925 1030 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
926 1031
927 1032 typedef struct _MPI2_SGE_TRANSACTION_UNION
928 1033 {
929 1034 U8 Reserved;
930 1035 U8 ContextSize;
931 1036 U8 DetailsLength;
932 1037 U8 Flags;
933 1038 union
934 1039 {
935 1040 U32 TransactionContext32[1];
936 1041 U32 TransactionContext64[2];
937 1042 U32 TransactionContext96[3];
938 1043 U32 TransactionContext128[4];
939 1044 } u;
940 1045 U32 TransactionDetails[1];
941 1046 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
942 1047 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
943 1048
944 1049
945 1050 /****************************************************************************
946 1051 * MPI SGE union for IO SGL's - for MPI v2.0 products only
947 1052 ****************************************************************************/
948 1053
949 1054 typedef struct _MPI2_MPI_SGE_IO_UNION
950 1055 {
951 1056 union
952 1057 {
953 1058 MPI2_SGE_SIMPLE_UNION Simple;
954 1059 MPI2_SGE_CHAIN_UNION Chain;
955 1060 } u;
956 1061 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
957 1062 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
958 1063
959 1064
960 1065 /****************************************************************************
961 1066 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
962 1067 ****************************************************************************/
963 1068
964 1069 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
965 1070 {
966 1071 union
967 1072 {
968 1073 MPI2_SGE_SIMPLE_UNION Simple;
969 1074 MPI2_SGE_TRANSACTION_UNION Transaction;
970 1075 } u;
971 1076 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
972 1077 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
973 1078
974 1079
975 1080 /****************************************************************************
976 1081 * All MPI SGE types union
977 1082 ****************************************************************************/
978 1083
979 1084 typedef struct _MPI2_MPI_SGE_UNION
980 1085 {
981 1086 union
982 1087 {
983 1088 MPI2_SGE_SIMPLE_UNION Simple;
984 1089 MPI2_SGE_CHAIN_UNION Chain;
985 1090 MPI2_SGE_TRANSACTION_UNION Transaction;
986 1091 } u;
987 1092 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
988 1093 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
989 1094
990 1095
991 1096 /****************************************************************************
992 1097 * MPI SGE field definition and masks
993 1098 ****************************************************************************/
994 1099
995 1100 /* Flags field bit definitions */
996 1101
997 1102 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
998 1103 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
999 1104 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1000 1105 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1001 1106 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
1002 1107 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1003 1108 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1004 1109
1005 1110 #define MPI2_SGE_FLAGS_SHIFT (24)
1006 1111
1007 1112 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1008 1113 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1009 1114
1010 1115 /* Element Type */
1011 1116
1012 1117 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */
1013 1118 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1014 1119 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */
1015 1120 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1016 1121
1017 1122 /* Address location */
1018 1123
1019 1124 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1020 1125
1021 1126 /* Direction */
1022 1127
1023 1128 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1024 1129 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1025 1130
1026 1131 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1027 1132 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1028 1133
1029 1134 /* Address Size */
1030 1135
1031 1136 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1032 1137 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1033 1138
1034 1139 /* Context Size */
1035 1140
1036 1141 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1037 1142 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1038 1143 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1039 1144 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1040 1145
1041 1146 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1042 1147 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1043 1148
1044 1149 /****************************************************************************
1045 1150 * MPI SGE operation Macros
1046 1151 ****************************************************************************/
1047 1152
1048 1153 /* SIMPLE FlagsLength manipulations... */
1049 1154 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1050 1155 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
1051 1156 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1052 1157 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1053 1158
1054 1159 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
1055 1160
1056 1161 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1057 1162 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1058 1163 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
1059 1164
1060 1165 /* CAUTION - The following are READ-MODIFY-WRITE! */
1061 1166 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
1062 1167 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
1063 1168
1064 1169 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
1065 1170
1066 1171
1067 1172 /*****************************************************************************
1068 1173 *
1069 1174 * Fusion-MPT IEEE Scatter Gather Elements
1070 1175 *
1071 1176 *****************************************************************************/
1072 1177
1073 1178 /****************************************************************************
1074 1179 * IEEE Simple Element structures
1075 1180 ****************************************************************************/
1076 1181
1077 1182 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1078 1183 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1079 1184 {
1080 1185 U32 Address;
1081 1186 U32 FlagsLength;
1082 1187 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1083 1188 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1084 1189
1085 1190 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1086 1191 {
1087 1192 U64 Address;
1088 1193 U32 Length;
1089 1194 U16 Reserved1;
1090 1195 U8 Reserved2;
1091 1196 U8 Flags;
1092 1197 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1093 1198 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1094 1199
1095 1200 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1096 1201 {
1097 1202 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1098 1203 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1099 1204 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1100 1205 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1101 1206
1102 1207
1103 1208 /****************************************************************************
1104 1209 * IEEE Chain Element structures
1105 1210 ****************************************************************************/
1106 1211
1107 1212 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1108 1213 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1109 1214
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1110 1215 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1111 1216 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1112 1217
1113 1218 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1114 1219 {
1115 1220 MPI2_IEEE_SGE_CHAIN32 Chain32;
1116 1221 MPI2_IEEE_SGE_CHAIN64 Chain64;
1117 1222 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1118 1223 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1119 1224
1120 -/* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1225 +/* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1121 1226 typedef struct _MPI25_IEEE_SGE_CHAIN64
1122 1227 {
1123 1228 U64 Address;
1124 1229 U32 Length;
1125 1230 U16 Reserved1;
1126 1231 U8 NextChainOffset;
1127 1232 U8 Flags;
1128 1233 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
1129 1234 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
1130 1235
1131 1236
1132 1237 /****************************************************************************
1133 1238 * All IEEE SGE types union
1134 1239 ****************************************************************************/
1135 1240
1136 1241 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1137 1242 typedef struct _MPI2_IEEE_SGE_UNION
1138 1243 {
1139 1244 union
1140 1245 {
1141 1246 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1142 1247 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1143 1248 } u;
1144 1249 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1145 1250 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1146 1251
1147 1252
1148 1253 /****************************************************************************
1149 1254 * IEEE SGE union for IO SGL's
1150 1255 ****************************************************************************/
1151 1256
1152 1257 typedef union _MPI25_SGE_IO_UNION
1153 1258 {
1154 1259 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1155 1260 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1156 1261 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION,
1157 1262 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t;
1158 1263
1159 1264
1160 1265 /****************************************************************************
1161 1266 * IEEE SGE field definitions and masks
1162 1267 ****************************************************************************/
1163 1268
1164 1269 /* Flags field bit definitions */
1165 1270
1166 1271 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1167 1272 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
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1168 1273
1169 1274 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1170 1275
1171 1276 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1172 1277
1173 1278 /* Element Type */
1174 1279
1175 1280 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1176 1281 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1177 1282
1283 +/* Next Segment Format */
1284 +
1285 +#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1286 +#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1287 +#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1288 +#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1289 +
1178 1290 /* Data Location Address Space */
1179 1291
1180 1292 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1181 -#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */
1293 +#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */
1182 1294 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */
1183 1295 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1184 1296 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */
1185 1297 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */
1186 1298 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1187 1299
1300 +#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */
1301 +
1188 1302 /****************************************************************************
1189 1303 * IEEE SGE operation Macros
1190 1304 ****************************************************************************/
1191 1305
1192 1306 /* SIMPLE FlagsLength manipulations... */
1193 1307 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1194 1308 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1195 1309 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1196 1310
1197 1311 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1198 1312
1199 1313 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1200 1314 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1201 1315 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1202 1316
1203 1317 /* CAUTION - The following are READ-MODIFY-WRITE! */
1204 1318 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1205 1319 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1206 1320
1207 1321
1208 1322
1209 1323 /*****************************************************************************
1210 1324 *
1211 1325 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1212 1326 *
1213 1327 *****************************************************************************/
1214 1328
1215 1329 typedef union _MPI2_SIMPLE_SGE_UNION
1216 1330 {
1217 1331 MPI2_SGE_SIMPLE_UNION MpiSimple;
1218 1332 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1219 1333 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1220 1334 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1221 1335
1222 1336
1223 1337 typedef union _MPI2_SGE_IO_UNION
1224 1338 {
1225 1339 MPI2_SGE_SIMPLE_UNION MpiSimple;
1226 1340 MPI2_SGE_CHAIN_UNION MpiChain;
1227 1341 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1228 1342 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1229 1343 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1230 1344 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1231 1345
1232 1346
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1233 1347 /****************************************************************************
1234 1348 *
1235 1349 * Values for SGLFlags field, used in many request messages with an SGL
1236 1350 *
1237 1351 ****************************************************************************/
1238 1352
1239 1353 /* values for MPI SGL Data Location Address Space subfield */
1240 1354 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1241 1355 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1242 1356 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1243 -#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1244 -#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1357 +#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */
1358 +#define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */
1359 +#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */
1245 1360 /* values for SGL Type subfield */
1246 1361 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1247 1362 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1248 1363 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */
1249 1364 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1250 1365
1251 1366
1252 1367 #endif
1253 1368
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