1 /*-
2 * Copyright (c) 2013 LSI Corp.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Copyright (c) 2000-2013 LSI Corporation.
32 *
33 *
34 * Name: mpi2.h
35 * Title: MPI Message independent structures and definitions
36 * including System Interface Register Set and
37 * scatter/gather formats.
38 * Creation Date: June 21, 2006
39 *
40 * mpi2.h Version: 02.00.33
41 *
42 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
43 * prefix are for use only on MPI v2.5 products, and must not be used
44 * with MPI v2.0 products. Unless otherwise noted, names beginning with
45 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
46 *
47 * Version History
48 * ---------------
49 *
50 * Date Version Description
51 * -------- -------- ------------------------------------------------------
52 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
53 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
54 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
55 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
56 * Moved ReplyPostHostIndex register to offset 0x6C of the
57 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
58 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
59 * Added union of request descriptors.
60 * Added union of reply descriptors.
102 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
103 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
104 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
105 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
106 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
107 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
108 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
109 * Incorporating additions for MPI v2.5.
110 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
111 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
112 * Added Hard Reset delay timings.
113 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
115 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
116 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
117 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
118 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
119 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
120 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
121 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
122 * --------------------------------------------------------------------------
123 */
124
125 #ifndef MPI2_H
126 #define MPI2_H
127
128
129 /*****************************************************************************
130 *
131 * MPI Version Definitions
132 *
133 *****************************************************************************/
134
135 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
136 #define MPI2_VERSION_MAJOR_SHIFT (8)
137 #define MPI2_VERSION_MINOR_MASK (0x00FF)
138 #define MPI2_VERSION_MINOR_SHIFT (0)
139
140 /* major version for all MPI v2.x */
141 #define MPI2_VERSION_MAJOR (0x02)
142
143 /* minor version for MPI v2.0 compatible products */
144 #define MPI2_VERSION_MINOR (0x00)
145 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
146 MPI2_VERSION_MINOR)
147 #define MPI2_VERSION_02_00 (0x0200)
148
149
150 /* minor version for MPI v2.5 compatible products */
151 #define MPI25_VERSION_MINOR (0x05)
152 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
153 MPI25_VERSION_MINOR)
154 #define MPI2_VERSION_02_05 (0x0205)
155
156
157 /* Unit and Dev versioning for this MPI header set */
158 #define MPI2_HEADER_VERSION_UNIT (0x21)
159 #define MPI2_HEADER_VERSION_DEV (0x00)
160 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
161 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
162 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
163 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
164 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
165
166
167 /*****************************************************************************
168 *
169 * IOC State Definitions
170 *
171 *****************************************************************************/
172
173 #define MPI2_IOC_STATE_RESET (0x00000000)
174 #define MPI2_IOC_STATE_READY (0x10000000)
175 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
176 #define MPI2_IOC_STATE_FAULT (0x40000000)
177
178 #define MPI2_IOC_STATE_MASK (0xF0000000)
194 U32 Doorbell; /* 0x00 */
195 U32 WriteSequence; /* 0x04 */
196 U32 HostDiagnostic; /* 0x08 */
197 U32 Reserved1; /* 0x0C */
198 U32 DiagRWData; /* 0x10 */
199 U32 DiagRWAddressLow; /* 0x14 */
200 U32 DiagRWAddressHigh; /* 0x18 */
201 U32 Reserved2[5]; /* 0x1C */
202 U32 HostInterruptStatus; /* 0x30 */
203 U32 HostInterruptMask; /* 0x34 */
204 U32 DCRData; /* 0x38 */
205 U32 DCRAddress; /* 0x3C */
206 U32 Reserved3[2]; /* 0x40 */
207 U32 ReplyFreeHostIndex; /* 0x48 */
208 U32 Reserved4[8]; /* 0x4C */
209 U32 ReplyPostHostIndex; /* 0x6C */
210 U32 Reserved5; /* 0x70 */
211 U32 HCBSize; /* 0x74 */
212 U32 HCBAddressLow; /* 0x78 */
213 U32 HCBAddressHigh; /* 0x7C */
214 U32 Reserved6[16]; /* 0x80 */
215 U32 RequestDescriptorPostLow; /* 0xC0 */
216 U32 RequestDescriptorPostHigh; /* 0xC4 */
217 U32 Reserved7[14]; /* 0xC8 */
218 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
219 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
220
221 /*
222 * Defines for working with the Doorbell register.
223 */
224 #define MPI2_DOORBELL_OFFSET (0x00000000)
225
226 /* IOC --> System values */
227 #define MPI2_DOORBELL_USED (0x08000000)
228 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
229 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
230 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
231 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
232
233 /* System --> IOC values */
234 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
235 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
236 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
237 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
238
239
240 /*
241 * Defines for the WriteSequence register
242 */
243 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
244 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
245 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
246 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
247 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
248 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
249 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
250 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
251 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
252
253 /*
254 * Defines for the HostDiagnostic register
255 */
256 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
257
258 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
259 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
260 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
261
262 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
263 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
264 #define MPI2_DIAG_HCB_MODE (0x00000100)
265 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
266 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
267 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
268 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
269 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
270 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
271
272 /*
273 * Offsets for DiagRWData and address
274 */
275 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
276 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
277 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
278
279 /*
280 * Defines for the HostInterruptStatus register
281 */
312 * Defines for the Reply Descriptor Post Queue
313 */
314 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
315 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
316 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
317 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
318 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
319
320
321 /*
322 * Defines for the HCBSize and address
323 */
324 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
325 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
326 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
327
328 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
329 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
330
331 /*
332 * Offsets for the Request Queue
333 */
334 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
335 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
336
337
338 /* Hard Reset delay timings */
339 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
340 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
341 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
342
343 /*****************************************************************************
344 *
345 * Message Descriptors
346 *
347 *****************************************************************************/
348
349 /* Request Descriptors */
350
351 /* Default Request Descriptor */
352 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
353 {
354 U8 RequestFlags; /* 0x00 */
355 U8 MSIxIndex; /* 0x01 */
356 U16 SMID; /* 0x02 */
357 U16 LMID; /* 0x04 */
358 U16 DescriptorTypeDependent; /* 0x06 */
359 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
360 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
361 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
362
363 /* defines for the RequestFlags field */
364 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
365 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
366 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
367 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
368 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
369 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
370 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
371
372 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
373
374
375 /* High Priority Request Descriptor */
376 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
377 {
378 U8 RequestFlags; /* 0x00 */
379 U8 MSIxIndex; /* 0x01 */
380 U16 SMID; /* 0x02 */
381 U16 LMID; /* 0x04 */
382 U16 Reserved1; /* 0x06 */
383 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
384 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
385 Mpi2HighPriorityRequestDescriptor_t,
386 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
387
388
389 /* SCSI IO Request Descriptor */
390 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
418 {
419 U8 RequestFlags; /* 0x00 */
420 U8 MSIxIndex; /* 0x01 */
421 U16 SMID; /* 0x02 */
422 U16 LMID; /* 0x04 */
423 U16 Reserved; /* 0x06 */
424 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
425 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
426 Mpi2RAIDAcceleratorRequestDescriptor_t,
427 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
428
429
430 /* Fast Path SCSI IO Request Descriptor */
431 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
432 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
433 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
434 Mpi25FastPathSCSIIORequestDescriptor_t,
435 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t;
436
437
438 /* union of Request Descriptors */
439 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
440 {
441 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
442 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
443 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
444 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
445 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
446 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
447 U64 Words;
448 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
449 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
450
451
452 /* Reply Descriptors */
453
454 /* Default Reply Descriptor */
455 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
456 {
457 U8 ReplyFlags; /* 0x00 */
458 U8 MSIxIndex; /* 0x01 */
459 U16 DescriptorTypeDependent1; /* 0x02 */
460 U32 DescriptorTypeDependent2; /* 0x04 */
461 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
462 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
463
464 /* defines for the ReplyFlags field */
465 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
466 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
467 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
468 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
469 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
470 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
471 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
472 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
473
474 /* values for marking a reply descriptor as unused */
475 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
476 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
477
478 /* Address Reply Descriptor */
479 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
480 {
481 U8 ReplyFlags; /* 0x00 */
482 U8 MSIxIndex; /* 0x01 */
483 U16 SMID; /* 0x02 */
484 U32 ReplyFrameAddress; /* 0x04 */
485 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
486 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
487
488 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
489
490
491 /* SCSI IO Success Reply Descriptor */
539 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
540 {
541 U8 ReplyFlags; /* 0x00 */
542 U8 MSIxIndex; /* 0x01 */
543 U16 SMID; /* 0x02 */
544 U32 Reserved; /* 0x04 */
545 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
546 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
547 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
548 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
549
550
551 /* Fast Path SCSI IO Success Reply Descriptor */
552 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
553 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
554 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
555 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
556 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
557
558
559 /* union of Reply Descriptors */
560 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
561 {
562 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
563 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
564 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
565 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
566 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
567 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
568 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
569 U64 Words;
570 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
571 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
572
573
574
575 /*****************************************************************************
576 *
577 * Message Functions
578 *
579 *****************************************************************************/
580
581 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
582 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
583 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
584 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
585 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
586 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
587 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
588 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
589 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
590 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
591 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
592 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
593 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
594 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
595 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
596 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
597 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
598 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
599 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
600 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
601 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
602 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
603 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
604 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
605 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
606 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
607 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
608 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
609 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */
610 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
611 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
612
613
614
615 /* Doorbell functions */
616 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
617 #define MPI2_FUNCTION_HANDSHAKE (0x42)
618
619
620 /*****************************************************************************
621 *
622 * IOC Status Values
623 *
624 *****************************************************************************/
625
626 /* mask for IOCStatus status value */
627 #define MPI2_IOCSTATUS_MASK (0x7FFF)
628
629 /****************************************************************************
630 * Common IOCStatus values for all replies
631 ****************************************************************************/
632
633 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
634 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
635 #define MPI2_IOCSTATUS_BUSY (0x0002)
636 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
637 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
638 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
639 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
640 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
641 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
642 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
643
644 /****************************************************************************
645 * Config IOCStatus values
646 ****************************************************************************/
647
648 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
649 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
650 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
651 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
652 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
653 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
654
655 /****************************************************************************
656 * SCSI IO Reply
657 ****************************************************************************/
658
659 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
660 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
661 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
662 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
1100 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1101
1102
1103 /****************************************************************************
1104 * IEEE Chain Element structures
1105 ****************************************************************************/
1106
1107 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1108 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1109
1110 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1111 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1112
1113 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1114 {
1115 MPI2_IEEE_SGE_CHAIN32 Chain32;
1116 MPI2_IEEE_SGE_CHAIN64 Chain64;
1117 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1118 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1119
1120 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1121 typedef struct _MPI25_IEEE_SGE_CHAIN64
1122 {
1123 U64 Address;
1124 U32 Length;
1125 U16 Reserved1;
1126 U8 NextChainOffset;
1127 U8 Flags;
1128 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
1129 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
1130
1131
1132 /****************************************************************************
1133 * All IEEE SGE types union
1134 ****************************************************************************/
1135
1136 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1137 typedef struct _MPI2_IEEE_SGE_UNION
1138 {
1139 union
1140 {
1158
1159
1160 /****************************************************************************
1161 * IEEE SGE field definitions and masks
1162 ****************************************************************************/
1163
1164 /* Flags field bit definitions */
1165
1166 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1167 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1168
1169 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1170
1171 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1172
1173 /* Element Type */
1174
1175 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1176 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1177
1178 /* Data Location Address Space */
1179
1180 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1181 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */
1182 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */
1183 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1184 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */
1185 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */
1186 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1187
1188 /****************************************************************************
1189 * IEEE SGE operation Macros
1190 ****************************************************************************/
1191
1192 /* SIMPLE FlagsLength manipulations... */
1193 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1194 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1195 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1196
1197 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1198
1199 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1200 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1201 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1202
1203 /* CAUTION - The following are READ-MODIFY-WRITE! */
1204 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1205 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1206
1207
1223 typedef union _MPI2_SGE_IO_UNION
1224 {
1225 MPI2_SGE_SIMPLE_UNION MpiSimple;
1226 MPI2_SGE_CHAIN_UNION MpiChain;
1227 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1228 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1229 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1230 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1231
1232
1233 /****************************************************************************
1234 *
1235 * Values for SGLFlags field, used in many request messages with an SGL
1236 *
1237 ****************************************************************************/
1238
1239 /* values for MPI SGL Data Location Address Space subfield */
1240 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1241 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1242 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1243 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1244 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1245 /* values for SGL Type subfield */
1246 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1247 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1248 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */
1249 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1250
1251
1252 #endif
1253
|
1 /*-
2 * Copyright (c) 2012-2015 LSI Corp.
3 * Copyright (c) 2013-2016 Avago Technologies
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Copyright (c) 2000-2015 LSI Corporation.
33 * Copyright (c) 2013-2016 Avago Technologies
34 * All rights reserved.
35 *
36 *
37 * Name: mpi2.h
38 * Title: MPI Message independent structures and definitions
39 * including System Interface Register Set and
40 * scatter/gather formats.
41 * Creation Date: June 21, 2006
42 *
43 * mpi2.h Version: 02.00.46
44 *
45 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
46 * prefix are for use only on MPI v2.5 products, and must not be used
47 * with MPI v2.0 products. Unless otherwise noted, names beginning with
48 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
49 *
50 * Version History
51 * ---------------
52 *
53 * Date Version Description
54 * -------- -------- ------------------------------------------------------
55 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
56 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
57 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
58 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
59 * Moved ReplyPostHostIndex register to offset 0x6C of the
60 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
61 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
62 * Added union of request descriptors.
63 * Added union of reply descriptors.
105 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
106 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
107 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
108 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
109 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
110 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
111 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
112 * Incorporating additions for MPI v2.5.
113 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
115 * Added Hard Reset delay timings.
116 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
117 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
118 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
119 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
120 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
121 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
122 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
123 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
124 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
125 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT.
126 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
127 * 11-18-14 02.00.36 Updated copyright information.
128 * Bumped MPI2_HEADER_VERSION_UNIT.
129 * 03-16-15 02.00.37 Updated for MPI v2.6.
130 * Bumped MPI2_HEADER_VERSION_UNIT.
131 * Added Scratchpad registers and
132 * AtomicRequestDescriptorPost register to
133 * MPI2_SYSTEM_INTERFACE_REGS.
134 * Added MPI2_DIAG_SBR_RELOAD.
135 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER.
136 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
137 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT
138 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
139 * Added V7 HostDiagnostic register defines
140 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
141 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
142 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines
143 * to be unique within first 32 characters.
144 * Removed AHCI support.
145 * Removed SOP support.
146 * Bumped MPI2_HEADER_VERSION_UNIT.
147 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT.
148 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT.
149 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT.
150 * --------------------------------------------------------------------------
151 */
152
153 #ifndef MPI2_H
154 #define MPI2_H
155
156
157 /*****************************************************************************
158 *
159 * MPI Version Definitions
160 *
161 *****************************************************************************/
162
163 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
164 #define MPI2_VERSION_MAJOR_SHIFT (8)
165 #define MPI2_VERSION_MINOR_MASK (0x00FF)
166 #define MPI2_VERSION_MINOR_SHIFT (0)
167
168 /* major version for all MPI v2.x */
169 #define MPI2_VERSION_MAJOR (0x02)
170
171 /* minor version for MPI v2.0 compatible products */
172 #define MPI2_VERSION_MINOR (0x00)
173 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
174 MPI2_VERSION_MINOR)
175 #define MPI2_VERSION_02_00 (0x0200)
176
177
178 /* minor version for MPI v2.5 compatible products */
179 #define MPI25_VERSION_MINOR (0x05)
180 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
181 MPI25_VERSION_MINOR)
182 #define MPI2_VERSION_02_05 (0x0205)
183
184
185 /* minor version for MPI v2.6 compatible products */
186 #define MPI26_VERSION_MINOR (0x06)
187 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
188 MPI26_VERSION_MINOR)
189 #define MPI2_VERSION_02_06 (0x0206)
190
191
192 /* Unit and Dev versioning for this MPI header set */
193 #define MPI2_HEADER_VERSION_UNIT (0x2E)
194 #define MPI2_HEADER_VERSION_DEV (0x00)
195 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
196 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
197 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
198 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
199 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
200
201
202 /*****************************************************************************
203 *
204 * IOC State Definitions
205 *
206 *****************************************************************************/
207
208 #define MPI2_IOC_STATE_RESET (0x00000000)
209 #define MPI2_IOC_STATE_READY (0x10000000)
210 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
211 #define MPI2_IOC_STATE_FAULT (0x40000000)
212
213 #define MPI2_IOC_STATE_MASK (0xF0000000)
229 U32 Doorbell; /* 0x00 */
230 U32 WriteSequence; /* 0x04 */
231 U32 HostDiagnostic; /* 0x08 */
232 U32 Reserved1; /* 0x0C */
233 U32 DiagRWData; /* 0x10 */
234 U32 DiagRWAddressLow; /* 0x14 */
235 U32 DiagRWAddressHigh; /* 0x18 */
236 U32 Reserved2[5]; /* 0x1C */
237 U32 HostInterruptStatus; /* 0x30 */
238 U32 HostInterruptMask; /* 0x34 */
239 U32 DCRData; /* 0x38 */
240 U32 DCRAddress; /* 0x3C */
241 U32 Reserved3[2]; /* 0x40 */
242 U32 ReplyFreeHostIndex; /* 0x48 */
243 U32 Reserved4[8]; /* 0x4C */
244 U32 ReplyPostHostIndex; /* 0x6C */
245 U32 Reserved5; /* 0x70 */
246 U32 HCBSize; /* 0x74 */
247 U32 HCBAddressLow; /* 0x78 */
248 U32 HCBAddressHigh; /* 0x7C */
249 U32 Reserved6[12]; /* 0x80 */
250 U32 Scratchpad[4]; /* 0xB0 */
251 U32 RequestDescriptorPostLow; /* 0xC0 */
252 U32 RequestDescriptorPostHigh; /* 0xC4 */
253 U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */
254 U32 Reserved7[13]; /* 0xCC */
255 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
256 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
257
258 /*
259 * Defines for working with the Doorbell register.
260 */
261 #define MPI2_DOORBELL_OFFSET (0x00000000)
262
263 /* IOC --> System values */
264 #define MPI2_DOORBELL_USED (0x08000000)
265 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
266 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
267 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
268 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
269
270 /* System --> IOC values */
271 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
272 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
273 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
274 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
275
276
277 /*
278 * Defines for the WriteSequence register
279 */
280 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
281 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
282 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
283 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
284 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
285 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
286 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
287 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
288 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
289
290 /*
291 * Defines for the HostDiagnostic register
292 */
293 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
294
295 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
296
297 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
298 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
299 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
300
301 /* Defines for V7A/V7R HostDiagnostic Register */
302 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
303 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
304 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
305 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
306
307 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
308 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
309 #define MPI2_DIAG_HCB_MODE (0x00000100)
310 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
311 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
312 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
313 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
314 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
315 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
316
317 /*
318 * Offsets for DiagRWData and address
319 */
320 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
321 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
322 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
323
324 /*
325 * Defines for the HostInterruptStatus register
326 */
357 * Defines for the Reply Descriptor Post Queue
358 */
359 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
360 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
361 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
362 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
363 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
364
365
366 /*
367 * Defines for the HCBSize and address
368 */
369 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
370 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
371 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
372
373 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
374 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
375
376 /*
377 * Offsets for the Scratchpad registers
378 */
379 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
380 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
381 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
382 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
383
384 /*
385 * Offsets for the Request Descriptor Post Queue
386 */
387 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
388 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
389 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
390
391
392 /* Hard Reset delay timings */
393 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
394 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
395 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
396
397 /*****************************************************************************
398 *
399 * Message Descriptors
400 *
401 *****************************************************************************/
402
403 /* Request Descriptors */
404
405 /* Default Request Descriptor */
406 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
407 {
408 U8 RequestFlags; /* 0x00 */
409 U8 MSIxIndex; /* 0x01 */
410 U16 SMID; /* 0x02 */
411 U16 LMID; /* 0x04 */
412 U16 DescriptorTypeDependent; /* 0x06 */
413 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
414 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
415 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
416
417 /* defines for the RequestFlags field */
418 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
419 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */
420 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
421 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
422 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
423 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
424 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
425 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
426 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
427
428 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
429
430
431 /* High Priority Request Descriptor */
432 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
433 {
434 U8 RequestFlags; /* 0x00 */
435 U8 MSIxIndex; /* 0x01 */
436 U16 SMID; /* 0x02 */
437 U16 LMID; /* 0x04 */
438 U16 Reserved1; /* 0x06 */
439 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
440 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
441 Mpi2HighPriorityRequestDescriptor_t,
442 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
443
444
445 /* SCSI IO Request Descriptor */
446 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
474 {
475 U8 RequestFlags; /* 0x00 */
476 U8 MSIxIndex; /* 0x01 */
477 U16 SMID; /* 0x02 */
478 U16 LMID; /* 0x04 */
479 U16 Reserved; /* 0x06 */
480 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
481 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
482 Mpi2RAIDAcceleratorRequestDescriptor_t,
483 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
484
485
486 /* Fast Path SCSI IO Request Descriptor */
487 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
488 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
489 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
490 Mpi25FastPathSCSIIORequestDescriptor_t,
491 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t;
492
493
494 /* PCIe Encapsulated Request Descriptor */
495 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
496 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
497 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
498 Mpi26PCIeEncapsulatedRequestDescriptor_t,
499 MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t;
500
501
502 /* union of Request Descriptors */
503 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
504 {
505 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
506 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
507 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
508 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
509 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
510 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
511 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
512 U64 Words;
513 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
514 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
515
516
517 /* Atomic Request Descriptors */
518
519 /*
520 * All Atomic Request Descriptors have the same format, so the following
521 * structure is used for all Atomic Request Descriptors:
522 * Atomic Default Request Descriptor
523 * Atomic High Priority Request Descriptor
524 * Atomic SCSI IO Request Descriptor
525 * Atomic SCSI Target Request Descriptor
526 * Atomic RAID Accelerator Request Descriptor
527 * Atomic Fast Path SCSI IO Request Descriptor
528 * Atomic PCIe Encapsulated Request Descriptor
529 */
530
531 /* Atomic Request Descriptor */
532 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR
533 {
534 U8 RequestFlags; /* 0x00 */
535 U8 MSIxIndex; /* 0x01 */
536 U16 SMID; /* 0x02 */
537 } MPI26_ATOMIC_REQUEST_DESCRIPTOR,
538 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
539 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t;
540
541 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */
542
543
544 /* Reply Descriptors */
545
546 /* Default Reply Descriptor */
547 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
548 {
549 U8 ReplyFlags; /* 0x00 */
550 U8 MSIxIndex; /* 0x01 */
551 U16 DescriptorTypeDependent1; /* 0x02 */
552 U32 DescriptorTypeDependent2; /* 0x04 */
553 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
554 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
555
556 /* defines for the ReplyFlags field */
557 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
558 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
559 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
560 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
561 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
562 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
563 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
564 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
565 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
566
567 /* values for marking a reply descriptor as unused */
568 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
569 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
570
571 /* Address Reply Descriptor */
572 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
573 {
574 U8 ReplyFlags; /* 0x00 */
575 U8 MSIxIndex; /* 0x01 */
576 U16 SMID; /* 0x02 */
577 U32 ReplyFrameAddress; /* 0x04 */
578 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
579 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
580
581 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
582
583
584 /* SCSI IO Success Reply Descriptor */
632 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
633 {
634 U8 ReplyFlags; /* 0x00 */
635 U8 MSIxIndex; /* 0x01 */
636 U16 SMID; /* 0x02 */
637 U32 Reserved; /* 0x04 */
638 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
639 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
640 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
641 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
642
643
644 /* Fast Path SCSI IO Success Reply Descriptor */
645 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
646 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
647 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
648 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
649 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
650
651
652 /* PCIe Encapsulated Success Reply Descriptor */
653 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
654 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
655 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
656 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
657 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
658
659
660 /* union of Reply Descriptors */
661 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
662 {
663 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
664 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
665 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
666 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
667 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
668 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
669 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
670 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess;
671 U64 Words;
672 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
673 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
674
675
676
677 /*****************************************************************************
678 *
679 * Message Functions
680 *
681 *****************************************************************************/
682
683 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
684 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
685 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
686 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
687 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
688 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
689 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
690 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
691 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
692 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
693 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
694 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
695 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
696 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
697 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
698 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
699 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
700 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
701 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
702 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */
703 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */
704 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
705 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
706 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
707 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
708 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
709 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
710 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
711 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
712 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */
713 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */
714 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
715 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
716
717
718
719 /* Doorbell functions */
720 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
721 #define MPI2_FUNCTION_HANDSHAKE (0x42)
722
723
724 /*****************************************************************************
725 *
726 * IOC Status Values
727 *
728 *****************************************************************************/
729
730 /* mask for IOCStatus status value */
731 #define MPI2_IOCSTATUS_MASK (0x7FFF)
732
733 /****************************************************************************
734 * Common IOCStatus values for all replies
735 ****************************************************************************/
736
737 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
738 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
739 #define MPI2_IOCSTATUS_BUSY (0x0002)
740 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
741 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
742 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
743 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
744 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
745 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
746 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
747 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */
748
749 /****************************************************************************
750 * Config IOCStatus values
751 ****************************************************************************/
752
753 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
754 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
755 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
756 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
757 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
758 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
759
760 /****************************************************************************
761 * SCSI IO Reply
762 ****************************************************************************/
763
764 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
765 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
766 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
767 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
1205 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1206
1207
1208 /****************************************************************************
1209 * IEEE Chain Element structures
1210 ****************************************************************************/
1211
1212 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1213 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1214
1215 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1216 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1217
1218 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1219 {
1220 MPI2_IEEE_SGE_CHAIN32 Chain32;
1221 MPI2_IEEE_SGE_CHAIN64 Chain64;
1222 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1223 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1224
1225 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1226 typedef struct _MPI25_IEEE_SGE_CHAIN64
1227 {
1228 U64 Address;
1229 U32 Length;
1230 U16 Reserved1;
1231 U8 NextChainOffset;
1232 U8 Flags;
1233 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
1234 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
1235
1236
1237 /****************************************************************************
1238 * All IEEE SGE types union
1239 ****************************************************************************/
1240
1241 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1242 typedef struct _MPI2_IEEE_SGE_UNION
1243 {
1244 union
1245 {
1263
1264
1265 /****************************************************************************
1266 * IEEE SGE field definitions and masks
1267 ****************************************************************************/
1268
1269 /* Flags field bit definitions */
1270
1271 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1272 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1273
1274 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1275
1276 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1277
1278 /* Element Type */
1279
1280 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1281 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1282
1283 /* Next Segment Format */
1284
1285 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1286 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1287 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1288 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1289
1290 /* Data Location Address Space */
1291
1292 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1293 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */
1294 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */
1295 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1296 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */
1297 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */
1298 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1299
1300 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */
1301
1302 /****************************************************************************
1303 * IEEE SGE operation Macros
1304 ****************************************************************************/
1305
1306 /* SIMPLE FlagsLength manipulations... */
1307 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1308 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1309 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1310
1311 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1312
1313 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1314 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1315 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1316
1317 /* CAUTION - The following are READ-MODIFY-WRITE! */
1318 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1319 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1320
1321
1337 typedef union _MPI2_SGE_IO_UNION
1338 {
1339 MPI2_SGE_SIMPLE_UNION MpiSimple;
1340 MPI2_SGE_CHAIN_UNION MpiChain;
1341 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1342 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1343 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1344 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1345
1346
1347 /****************************************************************************
1348 *
1349 * Values for SGLFlags field, used in many request messages with an SGL
1350 *
1351 ****************************************************************************/
1352
1353 /* values for MPI SGL Data Location Address Space subfield */
1354 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1355 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1356 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1357 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */
1358 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */
1359 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */
1360 /* values for SGL Type subfield */
1361 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1362 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1363 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */
1364 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1365
1366
1367 #endif
1368
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