5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
25 */
26
27
28 #ifndef _AHCIVAR_H
29 #define _AHCIVAR_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 /*
36 * AHCI address qualifier flags (in qual field of ahci_addr struct).
37 */
38 #define AHCI_ADDR_NULL 0x00
39 #define AHCI_ADDR_PORT 0x01
40 #define AHCI_ADDR_PMPORT 0x02
41 #define AHCI_ADDR_PMULT 0x04
42 #define AHCI_ADDR_VALID (AHCI_ADDR_PORT | \
43 AHCI_ADDR_PMULT | \
44 AHCI_ADDR_PMPORT)
45
46 /*
47 * AHCI address structure.
48 */
49 struct ahci_addr {
50
51 /* HBA port number */
52 uint8_t aa_port;
53
54 /* Port multiplier port number */
347 else \
348 AHCIPORT_PMDEV_TYPE(portp, addrp) = type;
349
350 #define AHCIPORT_STATE(portp, addrp) \
351 (portp)->ahciport_port_state
352
353 #define AHCIPORT_PMSTATE(portp, addrp) \
354 (portp)->ahciport_pmult_info->ahcipmi_port_state \
355 [(addrp)->aa_pmport]
356
357 #define AHCIPORT_GET_STATE(portp, addrp) \
358 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \
359 AHCIPORT_STATE(portp, addrp) : AHCIPORT_PMSTATE(portp, addrp))
360
361 #define AHCIPORT_SET_STATE(portp, addrp, state) \
362 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \
363 AHCIPORT_STATE(portp, addrp) = state; \
364 else \
365 AHCIPORT_PMSTATE(portp, addrp) = state;
366
367 typedef struct ahci_ctl {
368 dev_info_t *ahcictl_dip;
369
370 ushort_t ahcictl_venid;
371 ushort_t ahcictl_devid;
372
373 /* To map port number to cport number */
374 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS];
375 /* To map cport number to port number */
376 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS];
377
378 /* Number of controller ports */
379 int ahcictl_num_ports;
380 /* Number of command slots */
381 int ahcictl_num_cmd_slots;
382 /* Number of implemented ports */
383 int ahcictl_num_implemented_ports;
384 /* Bit map to indicate which port is implemented */
385 uint32_t ahcictl_ports_implemented;
386 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS];
423 ddi_dma_attr_t ahcictl_cmd_list_dma_attr;
424 /* DMA attributes for command tables */
425 ddi_dma_attr_t ahcictl_cmd_table_dma_attr;
426
427 /* Used for watchdog handler */
428 timeout_id_t ahcictl_timeout_id;
429
430 /* Per controller mutex */
431 kmutex_t ahcictl_mutex;
432
433 /* Components for interrupt */
434 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */
435 int ahcictl_intr_type; /* What type of interrupt */
436 int ahcictl_intr_cnt; /* # of intrs returned */
437 size_t ahcictl_intr_size; /* Size of intr array */
438 uint_t ahcictl_intr_pri; /* Intr priority */
439 int ahcictl_intr_cap; /* Intr capabilities */
440
441 /* FMA capabilities */
442 int ahcictl_fm_cap;
443 } ahci_ctl_t;
444
445 /* Warlock annotation */
446 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports))
447 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port))
448 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport))
449
450 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
451 ahci_ctl_t::ahcictl_power_level))
452 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
453 ahci_ctl_t::ahcictl_flags))
454 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
455 ahci_ctl_t::ahcictl_timeout_id))
456
457 #define AHCI_SUCCESS (0) /* Successful return */
458 #define AHCI_TIMEOUT (1) /* Timed out */
459 #define AHCI_FAILURE (-1) /* Unsuccessful return */
460
461 /* Flags for ahcictl_flags */
462 #define AHCI_ATTACH 0x1
475 /* Native Command Queuing (NCQ) */
476 #define AHCI_CAP_NCQ 0x4
477 /* Power Management (PM) */
478 #define AHCI_CAP_PM 0x8
479 /* 32-bit DMA addressing for buffer block */
480 #define AHCI_CAP_BUF_32BIT_DMA 0x10
481 /* Supports Command List Override */
482 #define AHCI_CAP_SCLO 0x20
483 /* 32-bit DMA addressing for communication memory descriptors */
484 #define AHCI_CAP_COMMU_32BIT_DMA 0x40
485 /* Port reset is needed for initialization */
486 #define AHCI_CAP_INIT_PORT_RESET 0x80
487 /* Port Asychronous Notification */
488 #define AHCI_CAP_SNTF 0x100
489 /* Port Multiplier Command-Based Switching Support (PMULT_CBSS) */
490 #define AHCI_CAP_PMULT_CBSS 0x200
491 /* Port Multiplier FIS-Based Switching Support (PMULT_FBSS) */
492 #define AHCI_CAP_PMULT_FBSS 0x400
493 /* Software Reset FIS cannot set pmport with 0xf for direct access device */
494 #define AHCI_CAP_SRST_NO_HOSTPORT 0x800
495
496 /* Flags controlling the restart port behavior */
497 #define AHCI_PORT_RESET 0x0001 /* Reset the port */
498 #define AHCI_RESET_NO_EVENTS_UP 0x0002 /* Don't send reset events up */
499
500 #define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \
501 (ahci_portp->ahciport_flags & \
502 (AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT))
503
504 #define RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) \
505 (ahci_portp->ahciport_flags & \
506 AHCI_PORT_FLAG_RDWR_PMULT)
507
508 #define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \
509 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \
510 ahci_portp->ahciport_pending_tags != 0 && \
511 ahci_portp->ahciport_pending_ncq_tags == 0)
512
513 #define NCQ_CMD_IN_PROGRESS(ahci_portp) \
514 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \
515 ahci_portp->ahciport_pending_ncq_tags != 0)
516
517 /* Command type for ahci_claim_free_slot routine */
518 #define AHCI_NON_NCQ_CMD 0x0
519 #define AHCI_NCQ_CMD 0x1
520 #define AHCI_ERR_RETRI_CMD 0x2
521 #define AHCI_RDWR_PMULT_CMD 0x4
522
523 /* State values for ahci_attach */
524 #define AHCI_ATTACH_STATE_NONE (0x1 << 0)
525 #define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1)
526 #define AHCI_ATTACH_STATE_FMA (0x1 << 2)
527 #define AHCI_ATTACH_STATE_REG_MAP (0x1 << 3)
528 #define AHCI_ATTACH_STATE_PCICFG_SETUP (0x1 << 4)
529 #define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 5)
530 #define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 6)
531 #define AHCI_ATTACH_STATE_PORT_ALLOC (0x1 << 7)
532 #define AHCI_ATTACH_STATE_HW_INIT (0x1 << 8)
533 #define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 9)
534
535 /* Interval used for delay */
536 #define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 ms */
537 #define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 ms */
538 #define AHCI_100US_TICKS (drv_usectohz(100)) /* ticks in 100 us */
539 #define AHCI_10MS_USECS (10000) /* microsecs in 10 millisec */
540 #define AHCI_1MS_USECS (1000) /* microsecs in 1 millisec */
541 #define AHCI_100US_USECS (100)
542
543 /*
544 * The following values are the numbers of times to retry polled requests.
545 */
546 #define AHCI_POLLRATE_HBA_RESET 100
547 #define AHCI_POLLRATE_PORT_SSTATUS 10
548 #define AHCI_POLLRATE_PORT_TFD_ERROR 1100
549 #define AHCI_POLLRATE_PORT_IDLE 50
550 #define AHCI_POLLRATE_PORT_SOFTRESET 100
551 #define AHCI_POLLRATE_GET_SPKT 100
552 #define AHCI_POLLRATE_PORT_IDLE_FR 500
553
593 if (ahci_ctlp == NULL) \
594 sata_trace_debug(NULL, fmt, ## args); \
595 else \
596 sata_trace_debug(ahci_ctlp->ahcictl_dip,\
597 fmt, ## args); \
598 }
599
600 #else
601
602 #define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \
603 if (ahci_debug_flags & (flag)) { \
604 if (ahci_ctlp == NULL) \
605 sata_trace_debug(NULL, fmt, ## args); \
606 else \
607 sata_trace_debug(ahci_ctlp->ahcictl_dip,\
608 fmt, ## args); \
609 }
610
611 #endif /* DEBUG */
612
613
614 #ifdef __cplusplus
615 }
616 #endif
617
618 #endif /* _AHCIVAR_H */
|
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2018, Joyent, Inc.
26 */
27
28
29 #ifndef _AHCIVAR_H
30 #define _AHCIVAR_H
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 #include <sys/sata/adapters/ahci/ahciem.h>
37
38 /*
39 * AHCI address qualifier flags (in qual field of ahci_addr struct).
40 */
41 #define AHCI_ADDR_NULL 0x00
42 #define AHCI_ADDR_PORT 0x01
43 #define AHCI_ADDR_PMPORT 0x02
44 #define AHCI_ADDR_PMULT 0x04
45 #define AHCI_ADDR_VALID (AHCI_ADDR_PORT | \
46 AHCI_ADDR_PMULT | \
47 AHCI_ADDR_PMPORT)
48
49 /*
50 * AHCI address structure.
51 */
52 struct ahci_addr {
53
54 /* HBA port number */
55 uint8_t aa_port;
56
57 /* Port multiplier port number */
350 else \
351 AHCIPORT_PMDEV_TYPE(portp, addrp) = type;
352
353 #define AHCIPORT_STATE(portp, addrp) \
354 (portp)->ahciport_port_state
355
356 #define AHCIPORT_PMSTATE(portp, addrp) \
357 (portp)->ahciport_pmult_info->ahcipmi_port_state \
358 [(addrp)->aa_pmport]
359
360 #define AHCIPORT_GET_STATE(portp, addrp) \
361 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \
362 AHCIPORT_STATE(portp, addrp) : AHCIPORT_PMSTATE(portp, addrp))
363
364 #define AHCIPORT_SET_STATE(portp, addrp, state) \
365 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \
366 AHCIPORT_STATE(portp, addrp) = state; \
367 else \
368 AHCIPORT_PMSTATE(portp, addrp) = state;
369
370 typedef enum ahci_em_flags {
371 AHCI_EM_PRESENT = 1 << 0,
372 AHCI_EM_RESETTING = 1 << 1,
373 AHCI_EM_TIMEOUT = 1 << 2,
374 AHCI_EM_QUIESCE = 1 << 3,
375 AHCI_EM_READY = 1 << 4,
376 } ahci_em_flags_t;
377
378 #define AHCI_EM_USABLE (AHCI_EM_PRESENT | AHCI_EM_READY)
379
380 typedef struct ahci_ctl {
381 dev_info_t *ahcictl_dip;
382
383 ushort_t ahcictl_venid;
384 ushort_t ahcictl_devid;
385
386 /* To map port number to cport number */
387 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS];
388 /* To map cport number to port number */
389 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS];
390
391 /* Number of controller ports */
392 int ahcictl_num_ports;
393 /* Number of command slots */
394 int ahcictl_num_cmd_slots;
395 /* Number of implemented ports */
396 int ahcictl_num_implemented_ports;
397 /* Bit map to indicate which port is implemented */
398 uint32_t ahcictl_ports_implemented;
399 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS];
436 ddi_dma_attr_t ahcictl_cmd_list_dma_attr;
437 /* DMA attributes for command tables */
438 ddi_dma_attr_t ahcictl_cmd_table_dma_attr;
439
440 /* Used for watchdog handler */
441 timeout_id_t ahcictl_timeout_id;
442
443 /* Per controller mutex */
444 kmutex_t ahcictl_mutex;
445
446 /* Components for interrupt */
447 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */
448 int ahcictl_intr_type; /* What type of interrupt */
449 int ahcictl_intr_cnt; /* # of intrs returned */
450 size_t ahcictl_intr_size; /* Size of intr array */
451 uint_t ahcictl_intr_pri; /* Intr priority */
452 int ahcictl_intr_cap; /* Intr capabilities */
453
454 /* FMA capabilities */
455 int ahcictl_fm_cap;
456
457 /*
458 * Enclosure information
459 */
460 uint32_t ahcictl_em_loc;
461 uint32_t ahcictl_em_ctl;
462 uintptr_t ahcictl_em_tx_off;
463 ahci_em_flags_t ahcictl_em_flags;
464 ddi_taskq_t *ahcictl_em_taskq;
465 ahci_em_led_state_t ahcictl_em_state[AHCI_MAX_PORTS];
466 } ahci_ctl_t;
467
468 /* Warlock annotation */
469 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports))
470 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port))
471 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport))
472
473 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
474 ahci_ctl_t::ahcictl_power_level))
475 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
476 ahci_ctl_t::ahcictl_flags))
477 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
478 ahci_ctl_t::ahcictl_timeout_id))
479
480 #define AHCI_SUCCESS (0) /* Successful return */
481 #define AHCI_TIMEOUT (1) /* Timed out */
482 #define AHCI_FAILURE (-1) /* Unsuccessful return */
483
484 /* Flags for ahcictl_flags */
485 #define AHCI_ATTACH 0x1
498 /* Native Command Queuing (NCQ) */
499 #define AHCI_CAP_NCQ 0x4
500 /* Power Management (PM) */
501 #define AHCI_CAP_PM 0x8
502 /* 32-bit DMA addressing for buffer block */
503 #define AHCI_CAP_BUF_32BIT_DMA 0x10
504 /* Supports Command List Override */
505 #define AHCI_CAP_SCLO 0x20
506 /* 32-bit DMA addressing for communication memory descriptors */
507 #define AHCI_CAP_COMMU_32BIT_DMA 0x40
508 /* Port reset is needed for initialization */
509 #define AHCI_CAP_INIT_PORT_RESET 0x80
510 /* Port Asychronous Notification */
511 #define AHCI_CAP_SNTF 0x100
512 /* Port Multiplier Command-Based Switching Support (PMULT_CBSS) */
513 #define AHCI_CAP_PMULT_CBSS 0x200
514 /* Port Multiplier FIS-Based Switching Support (PMULT_FBSS) */
515 #define AHCI_CAP_PMULT_FBSS 0x400
516 /* Software Reset FIS cannot set pmport with 0xf for direct access device */
517 #define AHCI_CAP_SRST_NO_HOSTPORT 0x800
518 /* Enclosure Management Services available */
519 #define AHCI_CAP_EMS 0x1000
520
521 /* Flags controlling the restart port behavior */
522 #define AHCI_PORT_RESET 0x0001 /* Reset the port */
523 #define AHCI_RESET_NO_EVENTS_UP 0x0002 /* Don't send reset events up */
524
525 #define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \
526 (ahci_portp->ahciport_flags & \
527 (AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT))
528
529 #define RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) \
530 (ahci_portp->ahciport_flags & \
531 AHCI_PORT_FLAG_RDWR_PMULT)
532
533 #define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \
534 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \
535 ahci_portp->ahciport_pending_tags != 0 && \
536 ahci_portp->ahciport_pending_ncq_tags == 0)
537
538 #define NCQ_CMD_IN_PROGRESS(ahci_portp) \
539 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \
540 ahci_portp->ahciport_pending_ncq_tags != 0)
541
542 /* Command type for ahci_claim_free_slot routine */
543 #define AHCI_NON_NCQ_CMD 0x0
544 #define AHCI_NCQ_CMD 0x1
545 #define AHCI_ERR_RETRI_CMD 0x2
546 #define AHCI_RDWR_PMULT_CMD 0x4
547
548 /* State values for ahci_attach */
549 #define AHCI_ATTACH_STATE_NONE (0x1 << 0)
550 #define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1)
551 #define AHCI_ATTACH_STATE_FMA (0x1 << 2)
552 #define AHCI_ATTACH_STATE_REG_MAP (0x1 << 3)
553 #define AHCI_ATTACH_STATE_PCICFG_SETUP (0x1 << 4)
554 #define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 5)
555 #define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 6)
556 #define AHCI_ATTACH_STATE_PORT_ALLOC (0x1 << 7)
557 #define AHCI_ATTACH_STATE_HW_INIT (0x1 << 8)
558 #define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 9)
559 #define AHCI_ATTACH_STATE_ENCLOSURE (0x1 << 10)
560
561 /* Interval used for delay */
562 #define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 ms */
563 #define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 ms */
564 #define AHCI_100US_TICKS (drv_usectohz(100)) /* ticks in 100 us */
565 #define AHCI_10MS_USECS (10000) /* microsecs in 10 millisec */
566 #define AHCI_1MS_USECS (1000) /* microsecs in 1 millisec */
567 #define AHCI_100US_USECS (100)
568
569 /*
570 * The following values are the numbers of times to retry polled requests.
571 */
572 #define AHCI_POLLRATE_HBA_RESET 100
573 #define AHCI_POLLRATE_PORT_SSTATUS 10
574 #define AHCI_POLLRATE_PORT_TFD_ERROR 1100
575 #define AHCI_POLLRATE_PORT_IDLE 50
576 #define AHCI_POLLRATE_PORT_SOFTRESET 100
577 #define AHCI_POLLRATE_GET_SPKT 100
578 #define AHCI_POLLRATE_PORT_IDLE_FR 500
579
619 if (ahci_ctlp == NULL) \
620 sata_trace_debug(NULL, fmt, ## args); \
621 else \
622 sata_trace_debug(ahci_ctlp->ahcictl_dip,\
623 fmt, ## args); \
624 }
625
626 #else
627
628 #define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \
629 if (ahci_debug_flags & (flag)) { \
630 if (ahci_ctlp == NULL) \
631 sata_trace_debug(NULL, fmt, ## args); \
632 else \
633 sata_trace_debug(ahci_ctlp->ahcictl_dip,\
634 fmt, ## args); \
635 }
636
637 #endif /* DEBUG */
638
639 /*
640 * Minimum size required for the enclosure message buffer. This value is in
641 * 4-byte quantities. So we need to multiply it by two.
642 */
643 #define AHCI_EM_BUFFER_MIN 2
644
645 /*
646 * Enclosure Management LED message format values
647 */
648 #define AHCI_LED_OFF 0
649 #define AHCI_LED_ON 1
650
651 #define AHCI_LED_ACTIVITY_OFF 0
652 #define AHCI_LED_IDENT_OFF 3
653 #define AHCI_LED_FAULT_OFF 6
654
655 #define AHCI_LED_MASK 0x7
656
657 #define AHCI_EM_MSG_TYPE_LED 0
658 #define AHCI_EM_MSG_TYPE_SAFTE 1
659 #define AHCI_EM_MSG_TYPE_SES 2
660 #define AHCI_EM_MSG_TYPE_SGPIO 3
661
662 #pragma pack(1)
663 typedef struct ahci_em_led_msg {
664 uint8_t alm_hba;
665 uint8_t alm_pminfo;
666 uint16_t alm_value;
667 } ahci_em_led_msg_t;
668
669 typedef struct ahci_em_msg_hdr {
670 uint8_t aemh_rsvd;
671 uint8_t aemh_mlen;
672 uint8_t aemh_dlen;
673 uint8_t aemh_mtype;
674 } ahci_em_msg_hdr_t;
675 #pragma pack()
676
677 #ifdef __cplusplus
678 }
679 #endif
680
681 #endif /* _AHCIVAR_H */
|