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MFV: illumos-gate@48d370f1e98a10b1bdf160dd83a49e0f49f6c1b7
9809 nvme driver should attach to all NVMe 1.x devices
9810 Update parts of NVMe headers for newer specs
9811 nvmeadm(1M) should have ctf
Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Andy Fiddaman <omnios@citrus-it.co.uk>
Approved by: Dan McDonald <danmcd@joyent.com>
Author: Robert Mustacchi <rm@joyent.com>
NEX-8020 illumos nvme changes
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Gordon Ross <gordon.ross@nexenta.com>
NEX-5792 support NVMe namespace EUI64
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-6132 nvmeadm(1M) get-feature command could use some cleanup
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-6130 basic NVMe 1.1 support
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-4431 want NVMe management utility
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
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--- old/usr/src/uts/common/sys/nvme.h
+++ new/usr/src/uts/common/sys/nvme.h
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
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4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2016 Nexenta Systems, Inc.
14 + * Copyright (c) 2018, Joyent, Inc.
14 15 */
15 16
16 17 #ifndef _SYS_NVME_H
17 18 #define _SYS_NVME_H
18 19
19 20 #include <sys/types.h>
20 21
21 22 #ifdef _KERNEL
22 23 #include <sys/types32.h>
23 24 #else
24 25 #include <stdint.h>
25 26 #endif
26 27
27 28 /*
28 29 * Declarations used for communication between nvmeadm(1M) and nvme(7D)
29 30 */
30 31
31 32 #ifdef __cplusplus
32 33 extern "C" {
33 34 #endif
34 35
35 36 /*
36 37 * NVMe ioctl definitions
37 38 */
38 39
39 40 #define NVME_IOC (('N' << 24) | ('V' << 16) | ('M' << 8))
40 41 #define NVME_IOC_IDENTIFY_CTRL (NVME_IOC | 1)
41 42 #define NVME_IOC_IDENTIFY_NSID (NVME_IOC | 2)
42 43 #define NVME_IOC_CAPABILITIES (NVME_IOC | 3)
43 44 #define NVME_IOC_GET_LOGPAGE (NVME_IOC | 4)
44 45 #define NVME_IOC_GET_FEATURES (NVME_IOC | 5)
45 46 #define NVME_IOC_INTR_CNT (NVME_IOC | 6)
46 47 #define NVME_IOC_VERSION (NVME_IOC | 7)
47 48 #define NVME_IOC_FORMAT (NVME_IOC | 8)
48 49 #define NVME_IOC_DETACH (NVME_IOC | 9)
49 50 #define NVME_IOC_ATTACH (NVME_IOC | 10)
50 51 #define NVME_IOC_MAX NVME_IOC_ATTACH
51 52
52 53 #define IS_NVME_IOC(x) ((x) > NVME_IOC && (x) <= NVME_IOC_MAX)
53 54 #define NVME_IOC_CMD(x) ((x) & 0xff)
54 55
55 56 typedef struct {
56 57 size_t n_len;
57 58 uintptr_t n_buf;
58 59 uint64_t n_arg;
59 60 } nvme_ioctl_t;
60 61
61 62 #ifdef _KERNEL
62 63 typedef struct {
63 64 size32_t n_len;
64 65 uintptr32_t n_buf;
65 66 uint64_t n_arg;
66 67 } nvme_ioctl32_t;
67 68 #endif
68 69
69 70 /*
70 71 * NVMe capabilities
71 72 */
72 73 typedef struct {
73 74 uint32_t mpsmax; /* Memory Page Size Maximum */
74 75 uint32_t mpsmin; /* Memory Page Size Minimum */
75 76 } nvme_capabilities_t;
76 77
77 78 /*
78 79 * NVMe version
79 80 */
80 81 typedef struct {
81 82 uint16_t v_minor;
82 83 uint16_t v_major;
83 84 } nvme_version_t;
84 85
85 86 #define NVME_VERSION_ATLEAST(v, maj, min) \
86 87 (((v)->v_major) > (maj) || \
87 88 ((v)->v_major == (maj) && (v)->v_minor >= (min)))
88 89
89 90 #define NVME_VERSION_HIGHER(v, maj, min) \
90 91 (((v)->v_major) > (maj) || \
91 92 ((v)->v_major == (maj) && (v)->v_minor > (min)))
92 93
93 94
94 95 #pragma pack(1)
95 96
96 97 /*
97 98 * NVMe Identify data structures
98 99 */
99 100
100 101 #define NVME_IDENTIFY_BUFSIZE 4096 /* buffer size for Identify */
101 102
102 103 /* NVMe Queue Entry Size bitfield */
103 104 typedef struct {
104 105 uint8_t qes_min:4; /* minimum entry size */
105 106 uint8_t qes_max:4; /* maximum entry size */
106 107 } nvme_idctl_qes_t;
107 108
108 109 /* NVMe Power State Descriptor */
109 110 typedef struct {
110 111 uint16_t psd_mp; /* Maximum Power */
111 112 uint8_t psd_rsvd1;
112 113 uint8_t psd_mps:1; /* Max Power Scale (1.1) */
113 114 uint8_t psd_nops:1; /* Non-Operational State (1.1) */
114 115 uint8_t psd_rsvd2:6;
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115 116 uint32_t psd_enlat; /* Entry Latency */
116 117 uint32_t psd_exlat; /* Exit Latency */
117 118 uint8_t psd_rrt:5; /* Relative Read Throughput */
118 119 uint8_t psd_rsvd3:3;
119 120 uint8_t psd_rrl:5; /* Relative Read Latency */
120 121 uint8_t psd_rsvd4:3;
121 122 uint8_t psd_rwt:5; /* Relative Write Throughput */
122 123 uint8_t psd_rsvd5:3;
123 124 uint8_t psd_rwl:5; /* Relative Write Latency */
124 125 uint8_t psd_rsvd6:3;
125 - uint8_t psd_rsvd7[16];
126 + uint16_t psd_idlp; /* Idle Power (1.2) */
127 + uint8_t psd_rsvd7:6;
128 + uint8_t psd_ips:2; /* Idle Power Scale (1.2) */
129 + uint8_t psd_rsvd8;
130 + uint16_t psd_actp; /* Active Power (1.2) */
131 + uint8_t psd_apw:3; /* Active Power Workload (1.2) */
132 + uint8_t psd_rsvd9:3;
133 + uint8_t psd_aps:2; /* Active Power Scale */
134 + uint8_t psd_rsvd10[9];
126 135 } nvme_idctl_psd_t;
127 136
128 137 /* NVMe Identify Controller Data Structure */
129 138 typedef struct {
130 139 /* Controller Capabilities & Features */
131 140 uint16_t id_vid; /* PCI vendor ID */
132 - uint16_t id_ssvid; /* PCI subsystem vendor ID */
141 + uint16_t id_ssvid; /* PCI subsystem vendor ID */
133 142 char id_serial[20]; /* Serial Number */
134 143 char id_model[40]; /* Model Number */
135 144 char id_fwrev[8]; /* Firmware Revision */
136 145 uint8_t id_rab; /* Recommended Arbitration Burst */
137 146 uint8_t id_oui[3]; /* vendor IEEE OUI */
138 147 struct { /* Multi-Interface Capabilities */
139 148 uint8_t m_multi_pci:1; /* HW has multiple PCIe interfaces */
140 149 uint8_t m_multi_ctrl:1; /* HW has multiple controllers (1.1) */
141 150 uint8_t m_sr_iov:1; /* controller is SR-IOV virt fn (1.1) */
142 151 uint8_t m_rsvd:5;
143 152 } id_mic;
144 153 uint8_t id_mdts; /* Maximum Data Transfer Size */
145 154 uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */
146 - uint8_t id_rsvd_cc[256 - 80];
155 + /* Added in NVMe 1.2 */
156 + uint32_t id_ver; /* Version */
157 + uint32_t id_rtd3r; /* RTD3 Resume Latency */
158 + uint32_t id_rtd3e; /* RTD3 Entry Latency */
159 + uint32_t id_oaes; /* Optional Asynchronous Events */
160 + /* Added in NVMe 1.3 */
161 + uint32_t id_ctratt; /* Controller Attributes */
162 + uint8_t id_rsvd_cc[12];
163 + uint8_t id_frguid[16]; /* FRU GUID */
164 + uint8_t id_rsvd2_cc[240 - 128];
165 + uint8_t id_rsvd_nvmemi[255 - 240];
166 + uint8_t id_mec; /* Management Endpiont Capabilities */
147 167
148 168 /* Admin Command Set Attributes */
149 169 struct { /* Optional Admin Command Support */
150 170 uint16_t oa_security:1; /* Security Send & Receive */
151 171 uint16_t oa_format:1; /* Format NVM */
152 172 uint16_t oa_firmware:1; /* Firmware Activate & Download */
153 173 uint16_t oa_rsvd:13;
154 174 } id_oacs;
155 175 uint8_t id_acl; /* Abort Command Limit */
156 176 uint8_t id_aerl; /* Asynchronous Event Request Limit */
157 177 struct { /* Firmware Updates */
158 178 uint8_t fw_readonly:1; /* Slot 1 is Read-Only */
159 179 uint8_t fw_nslot:3; /* number of firmware slots */
160 180 uint8_t fw_rsvd:4;
161 181 } id_frmw;
162 182 struct { /* Log Page Attributes */
163 183 uint8_t lp_smart:1; /* SMART/Health information per NS */
164 184 uint8_t lp_rsvd:7;
165 185 } id_lpa;
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166 186 uint8_t id_elpe; /* Error Log Page Entries */
167 187 uint8_t id_npss; /* Number of Power States */
168 188 struct { /* Admin Vendor Specific Command Conf */
169 189 uint8_t av_spec:1; /* use format from spec */
170 190 uint8_t av_rsvd:7;
171 191 } id_avscc;
172 192 struct { /* Autonomous Power State Trans (1.1) */
173 193 uint8_t ap_sup:1; /* APST supported (1.1) */
174 194 uint8_t ap_rsvd:7;
175 195 } id_apsta;
176 - uint8_t id_rsvd_ac[256 - 10];
196 + /* Added in NVMe 1.2 */
197 + uint16_t ap_wctemp; /* Warning Composite Temperature */
198 + uint16_t ap_cctemp; /* Critical Composite Temperature */
199 + uint16_t ap_mtfa; /* Maximum Firmware Activation Time */
200 + uint32_t ap_hmpre; /* Host Memory Buffer Preferred Size */
201 + uint32_t ap_hmmin; /* Host Memory Buffer Min Size */
202 + uint8_t ap_tnvmcap[16]; /* Total NVM Capacity in Bytes */
203 + uint8_t ap_unvmcap[16]; /* Unallocated NVM Capacity */
204 + uint32_t ap_rpmbs; /* Replay Protected Memory Block */
205 + /* Added in NVMe 1.3 */
206 + uint16_t ap_edstt; /* Extended Device Self-test time */
207 + uint8_t ap_dsto; /* Device Self-test Options */
208 + uint8_t ap_fwug; /* Firmware Update Granularity */
209 + uint16_t ap_kas; /* Keep Alive Support */
210 + uint16_t ap_hctma; /* Host Thermal Management */
211 + uint16_t ap_mntmt; /* Minimum Thermal Temperature */
212 + uint16_t ap_mxtmt; /* Maximum Thermal Temperature */
213 + uint32_t ap_sanitize; /* Sanitize Caps */
214 + uint8_t id_rsvd_ac[512 - 332];
177 215
178 216 /* NVM Command Set Attributes */
179 217 nvme_idctl_qes_t id_sqes; /* Submission Queue Entry Size */
180 218 nvme_idctl_qes_t id_cqes; /* Completion Queue Entry Size */
181 - uint16_t id_rsvd_nc_1;
219 + uint16_t id_maxcmd; /* Max Outstanding Commands (1.3) */
182 220 uint32_t id_nn; /* Number of Namespaces */
183 221 struct { /* Optional NVM Command Support */
184 222 uint16_t on_compare:1; /* Compare */
185 223 uint16_t on_wr_unc:1; /* Write Uncorrectable */
186 224 uint16_t on_dset_mgmt:1; /* Dataset Management */
187 225 uint16_t on_wr_zero:1; /* Write Zeros (1.1) */
188 226 uint16_t on_save:1; /* Save/Select in Get/Set Feat (1.1) */
189 227 uint16_t on_reserve:1; /* Reservations (1.1) */
190 228 uint16_t on_rsvd:10;
191 229 } id_oncs;
192 230 struct { /* Fused Operation Support */
193 231 uint16_t f_cmp_wr:1; /* Compare and Write */
194 232 uint16_t f_rsvd:15;
195 233 } id_fuses;
196 234 struct { /* Format NVM Attributes */
197 235 uint8_t fn_format:1; /* Format applies to all NS */
198 236 uint8_t fn_sec_erase:1; /* Secure Erase applies to all NS */
199 237 uint8_t fn_crypt_erase:1; /* Cryptographic Erase supported */
200 238 uint8_t fn_rsvd:5;
201 239 } id_fna;
202 240 struct { /* Volatile Write Cache */
203 241 uint8_t vwc_present:1; /* Volatile Write Cache present */
204 242 uint8_t rsvd:7;
205 243 } id_vwc;
206 244 uint16_t id_awun; /* Atomic Write Unit Normal */
207 245 uint16_t id_awupf; /* Atomic Write Unit Power Fail */
208 246 struct { /* NVM Vendor Specific Command Conf */
209 247 uint8_t nv_spec:1; /* use format from spec */
210 248 uint8_t nv_rsvd:7;
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211 249 } id_nvscc;
212 250 uint8_t id_rsvd_nc_2;
213 251 uint16_t id_acwu; /* Atomic Compare & Write Unit (1.1) */
214 252 uint16_t id_rsvd_nc_3;
215 253 struct { /* SGL Support (1.1) */
216 254 uint16_t sgl_sup:1; /* SGL Supported in NVM cmds (1.1) */
217 255 uint16_t sgl_rsvd1:15;
218 256 uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */
219 257 uint16_t sgl_rsvd2:15;
220 258 } id_sgls;
221 - uint8_t id_rsvd_nc_4[192 - 28];
259 + uint8_t id_rsvd_nc_4[768 - 540];
222 260
223 261 /* I/O Command Set Attributes */
224 - uint8_t id_rsvd_ioc[1344];
262 + uint8_t id_subnqn[1024 - 768]; /* Subsystem Qualified Name (1.2.1+) */
263 + uint8_t id_rsvd_ioc[1792 - 1024];
264 + uint8_t id_nvmof[2048 - 1792]; /* NVMe over Fabrics */
225 265
226 266 /* Power State Descriptors */
227 267 nvme_idctl_psd_t id_psd[32];
228 268
229 269 /* Vendor Specific */
230 270 uint8_t id_vs[1024];
231 271 } nvme_identify_ctrl_t;
232 272
233 273 /* NVMe Identify Namespace LBA Format */
234 274 typedef struct {
235 275 uint16_t lbaf_ms; /* Metadata Size */
236 276 uint8_t lbaf_lbads; /* LBA Data Size */
237 277 uint8_t lbaf_rp:2; /* Relative Performance */
238 278 uint8_t lbaf_rsvd1:6;
239 279 } nvme_idns_lbaf_t;
240 280
241 281 /* NVMe Identify Namespace Data Structure */
242 282 typedef struct {
243 283 uint64_t id_nsize; /* Namespace Size */
244 284 uint64_t id_ncap; /* Namespace Capacity */
245 285 uint64_t id_nuse; /* Namespace Utilization */
246 286 struct { /* Namespace Features */
247 287 uint8_t f_thin:1; /* Thin Provisioning */
248 288 uint8_t f_rsvd:7;
249 289 } id_nsfeat;
250 290 uint8_t id_nlbaf; /* Number of LBA formats */
251 291 struct { /* Formatted LBA size */
252 292 uint8_t lba_format:4; /* LBA format */
253 293 uint8_t lba_extlba:1; /* extended LBA (includes metadata) */
254 294 uint8_t lba_rsvd:3;
255 295 } id_flbas;
256 296 struct { /* Metadata Capabilities */
257 297 uint8_t mc_extlba:1; /* extended LBA transfers */
258 298 uint8_t mc_separate:1; /* separate metadata transfers */
259 299 uint8_t mc_rsvd:6;
260 300 } id_mc;
261 301 struct { /* Data Protection Capabilities */
262 302 uint8_t dp_type1:1; /* Protection Information Type 1 */
263 303 uint8_t dp_type2:1; /* Protection Information Type 2 */
264 304 uint8_t dp_type3:1; /* Protection Information Type 3 */
265 305 uint8_t dp_first:1; /* first 8 bytes of metadata */
266 306 uint8_t dp_last:1; /* last 8 bytes of metadata */
267 307 uint8_t dp_rsvd:3;
268 308 } id_dpc;
269 309 struct { /* Data Protection Settings */
270 310 uint8_t dp_pinfo:3; /* Protection Information enabled */
271 311 uint8_t dp_first:1; /* first 8 bytes of metadata */
272 312 uint8_t dp_rsvd:4;
273 313 } id_dps;
274 314 struct { /* NS Multi-Path/Sharing Cap (1.1) */
275 315 uint8_t nm_shared:1; /* NS is shared (1.1) */
276 316 uint8_t nm_rsvd:7;
277 317 } id_nmic;
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278 318 struct { /* Reservation Capabilities (1.1) */
279 319 uint8_t rc_persist:1; /* Persist Through Power Loss (1.1) */
280 320 uint8_t rc_wr_excl:1; /* Write Exclusive (1.1) */
281 321 uint8_t rc_excl:1; /* Exclusive Access (1.1) */
282 322 uint8_t rc_wr_excl_r:1; /* Wr Excl - Registrants Only (1.1) */
283 323 uint8_t rc_excl_r:1; /* Excl Acc - Registrants Only (1.1) */
284 324 uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */
285 325 uint8_t rc_excl_a:1; /* Excl Acc - All Registrants (1.1) */
286 326 uint8_t rc_rsvd:1;
287 327 } id_rescap;
288 - uint8_t id_rsvd1[120 - 32];
328 + uint8_t id_fpi; /* Format Progress Indicator (1.2) */
329 + uint8_t id_dfleat; /* Deallocate Log. Block (1.3) */
330 + uint16_t id_nawun; /* Atomic Write Unit Normal (1.2) */
331 + uint16_t id_nawupf; /* Atomic Write Unit Power Fail (1.2) */
332 + uint16_t id_nacwu; /* Atomic Compare & Write Unit (1.2) */
333 + uint16_t id_nabsn; /* Atomic Boundary Size Normal (1.2) */
334 + uint16_t id_nbao; /* Atomic Boundary Offset (1.2) */
335 + uint16_t id_nabspf; /* Atomic Boundary Size Fail (1.2) */
336 + uint16_t id_noiob; /* Optimal I/O Bondary (1.3) */
337 + uint8_t id_nvmcap[16]; /* NVM Capacity */
338 + uint8_t id_rsvd1[104 - 64];
339 + uint8_t id_nguid[16]; /* Namespace GUID (1.2) */
289 340 uint8_t id_eui64[8]; /* IEEE Extended Unique Id (1.1) */
290 341 nvme_idns_lbaf_t id_lbaf[16]; /* LBA Formats */
291 342
292 - uint8_t id_rsvd2[192];
343 + uint8_t id_rsvd2[384 - 192];
293 344
294 - uint8_t id_vs[3712]; /* Vendor Specific */
345 + uint8_t id_vs[4096 - 384]; /* Vendor Specific */
295 346 } nvme_identify_nsid_t;
296 347
348 +/* NVMe Identify Primary Controller Capabilities */
349 +typedef struct {
350 + uint16_t nipc_cntlid; /* Controller ID */
351 + uint16_t nipc_portid; /* Port Identifier */
352 + uint8_t nipc_crt; /* Controller Resource Types */
353 + uint8_t nipc_rsvd0[32 - 5];
354 + uint32_t nipc_vqfrt; /* VQ Resources Flexible Total */
355 + uint32_t nipc_vqrfa; /* VQ Resources Flexible Assigned */
356 + uint16_t nipc_vqrfap; /* VQ Resources to Primary */
357 + uint16_t nipc_vqprt; /* VQ Resources Private Total */
358 + uint16_t nipc_vqfrsm; /* VQ Resources Secondary Max */
359 + uint16_t nipc_vqgran; /* VQ Flexible Resource Gran */
360 + uint8_t nipc_rvsd1[64 - 48];
361 + uint32_t nipc_vifrt; /* VI Flexible total */
362 + uint32_t nipc_virfa; /* VI Flexible Assigned */
363 + uint16_t nipc_virfap; /* VI Flexible Allocatd to Primary */
364 + uint16_t nipc_viprt; /* VI Resources Private Total */
365 + uint16_t nipc_vifrsm; /* VI Resources Secondary Max */
366 + uint16_t nipc_vigran; /* VI Flexible Granularity */
367 + uint8_t nipc_rsvd2[4096 - 80];
368 +} nvme_identify_primary_caps_t;
297 369
298 370 /*
299 371 * NVMe completion queue entry status field
300 372 */
301 373 typedef struct {
302 374 uint16_t sf_p:1; /* Phase Tag */
303 375 uint16_t sf_sc:8; /* Status Code */
304 376 uint16_t sf_sct:3; /* Status Code Type */
305 377 uint16_t sf_rsvd2:2;
306 378 uint16_t sf_m:1; /* More */
307 379 uint16_t sf_dnr:1; /* Do Not Retry */
308 380 } nvme_cqe_sf_t;
309 381
310 382
311 383 /*
312 384 * NVMe Get Log Page
313 385 */
314 386 #define NVME_LOGPAGE_ERROR 0x1 /* Error Information */
315 387 #define NVME_LOGPAGE_HEALTH 0x2 /* SMART/Health Information */
316 388 #define NVME_LOGPAGE_FWSLOT 0x3 /* Firmware Slot Information */
317 389
318 390 typedef struct {
319 391 uint64_t el_count; /* Error Count */
320 392 uint16_t el_sqid; /* Submission Queue ID */
321 393 uint16_t el_cid; /* Command ID */
322 394 nvme_cqe_sf_t el_sf; /* Status Field */
323 395 uint8_t el_byte; /* Parameter Error Location byte */
324 396 uint8_t el_bit:3; /* Parameter Error Location bit */
325 397 uint8_t el_rsvd1:5;
326 398 uint64_t el_lba; /* Logical Block Address */
327 399 uint32_t el_nsid; /* Namespace ID */
328 400 uint8_t el_vendor; /* Vendor Specific Information avail */
329 401 uint8_t el_rsvd2[64 - 29];
330 402 } nvme_error_log_entry_t;
331 403
332 404 typedef struct {
333 405 uint64_t lo;
334 406 uint64_t hi;
335 407 } nvme_uint128_t;
336 408
337 409 typedef struct {
338 410 struct { /* Critical Warning */
339 411 uint8_t cw_avail:1; /* available space too low */
340 412 uint8_t cw_temp:1; /* temperature too high */
341 413 uint8_t cw_reliab:1; /* degraded reliability */
342 414 uint8_t cw_readonly:1; /* media is read-only */
343 415 uint8_t cw_volatile:1; /* volatile memory backup failed */
344 416 uint8_t cw_rsvd:3;
345 417 } hl_crit_warn;
346 418 uint16_t hl_temp; /* Temperature */
347 419 uint8_t hl_avail_spare; /* Available Spare */
348 420 uint8_t hl_avail_spare_thr; /* Available Spare Threshold */
349 421 uint8_t hl_used; /* Percentage Used */
350 422 uint8_t hl_rsvd1[32 - 6];
351 423 nvme_uint128_t hl_data_read; /* Data Units Read */
352 424 nvme_uint128_t hl_data_write; /* Data Units Written */
353 425 nvme_uint128_t hl_host_read; /* Host Read Commands */
354 426 nvme_uint128_t hl_host_write; /* Host Write Commands */
355 427 nvme_uint128_t hl_ctrl_busy; /* Controller Busy Time */
356 428 nvme_uint128_t hl_power_cycles; /* Power Cycles */
357 429 nvme_uint128_t hl_power_on_hours; /* Power On Hours */
358 430 nvme_uint128_t hl_unsafe_shutdn; /* Unsafe Shutdowns */
359 431 nvme_uint128_t hl_media_errors; /* Media Errors */
360 432 nvme_uint128_t hl_errors_logged; /* Number of errors logged */
361 433 uint8_t hl_rsvd2[512 - 192];
362 434 } nvme_health_log_t;
363 435
364 436 typedef struct {
365 437 uint8_t fw_afi:3; /* Active Firmware Slot */
366 438 uint8_t fw_rsvd1:5;
367 439 uint8_t fw_rsvd2[7];
368 440 char fw_frs[7][8]; /* Firmware Revision / Slot */
369 441 uint8_t fw_rsvd3[512 - 64];
370 442 } nvme_fwslot_log_t;
371 443
372 444
373 445 /*
374 446 * NVMe Format NVM
375 447 */
376 448 #define NVME_FRMT_SES_NONE 0
377 449 #define NVME_FRMT_SES_USER 1
378 450 #define NVME_FRMT_SES_CRYPTO 2
379 451 #define NVME_FRMT_MAX_SES 2
380 452
381 453 #define NVME_FRMT_MAX_LBAF 15
382 454
383 455 typedef union {
384 456 struct {
385 457 uint32_t fm_lbaf:4; /* LBA Format */
386 458 uint32_t fm_ms:1; /* Metadata Settings */
387 459 uint32_t fm_pi:3; /* Protection Information */
388 460 uint32_t fm_pil:1; /* Prot. Information Location */
389 461 uint32_t fm_ses:3; /* Secure Erase Settings */
390 462 uint32_t fm_resvd:20;
391 463 } b;
392 464 uint32_t r;
393 465 } nvme_format_nvm_t;
394 466
395 467
396 468 /*
397 469 * NVMe Get / Set Features
398 470 */
399 471 #define NVME_FEAT_ARBITRATION 0x1 /* Command Arbitration */
400 472 #define NVME_FEAT_POWER_MGMT 0x2 /* Power Management */
401 473 #define NVME_FEAT_LBA_RANGE 0x3 /* LBA Range Type */
402 474 #define NVME_FEAT_TEMPERATURE 0x4 /* Temperature Threshold */
403 475 #define NVME_FEAT_ERROR 0x5 /* Error Recovery */
404 476 #define NVME_FEAT_WRITE_CACHE 0x6 /* Volatile Write Cache */
405 477 #define NVME_FEAT_NQUEUES 0x7 /* Number of Queues */
406 478 #define NVME_FEAT_INTR_COAL 0x8 /* Interrupt Coalescing */
407 479 #define NVME_FEAT_INTR_VECT 0x9 /* Interrupt Vector Configuration */
408 480 #define NVME_FEAT_WRITE_ATOM 0xa /* Write Atomicity */
409 481 #define NVME_FEAT_ASYNC_EVENT 0xb /* Asynchronous Event Configuration */
410 482 #define NVME_FEAT_AUTO_PST 0xc /* Autonomous Power State Transition */
411 483 /* (1.1) */
412 484
413 485 #define NVME_FEAT_PROGRESS 0x80 /* Software Progress Marker */
414 486
415 487 /* Arbitration Feature */
416 488 typedef union {
417 489 struct {
418 490 uint8_t arb_ab:3; /* Arbitration Burst */
419 491 uint8_t arb_rsvd:5;
420 492 uint8_t arb_lpw; /* Low Priority Weight */
421 493 uint8_t arb_mpw; /* Medium Priority Weight */
422 494 uint8_t arb_hpw; /* High Priority Weight */
423 495 } b;
424 496 uint32_t r;
425 497 } nvme_arbitration_t;
426 498
427 499 /* Power Management Feature */
428 500 typedef union {
429 501 struct {
430 502 uint32_t pm_ps:5; /* Power State */
431 503 uint32_t pm_rsvd:27;
432 504 } b;
433 505 uint32_t r;
434 506 } nvme_power_mgmt_t;
435 507
436 508 /* LBA Range Type Feature */
437 509 typedef union {
438 510 struct {
439 511 uint32_t lr_num:6; /* Number of LBA ranges */
440 512 uint32_t lr_rsvd:26;
441 513 } b;
442 514 uint32_t r;
443 515 } nvme_lba_range_type_t;
444 516
445 517 typedef struct {
446 518 uint8_t lr_type; /* Type */
447 519 struct { /* Attributes */
448 520 uint8_t lr_write:1; /* may be overwritten */
449 521 uint8_t lr_hidden:1; /* hidden from OS/EFI/BIOS */
450 522 uint8_t lr_rsvd1:6;
451 523 } lr_attr;
452 524 uint8_t lr_rsvd2[14];
453 525 uint64_t lr_slba; /* Starting LBA */
454 526 uint64_t lr_nlb; /* Number of Logical Blocks */
455 527 uint8_t lr_guid[16]; /* Unique Identifier */
456 528 uint8_t lr_rsvd3[16];
457 529 } nvme_lba_range_t;
458 530
459 531 #define NVME_LBA_RANGE_BUFSIZE 4096
460 532
461 533 /* Temperature Threshold Feature */
462 534 typedef union {
463 535 struct {
464 536 uint16_t tt_tmpth; /* Temperature Threshold */
465 537 uint16_t tt_rsvd;
466 538 } b;
467 539 uint32_t r;
468 540 } nvme_temp_threshold_t;
469 541
470 542 /* Error Recovery Feature */
471 543 typedef union {
472 544 struct {
473 545 uint16_t er_tler; /* Time-Limited Error Recovery */
474 546 uint16_t er_rsvd;
475 547 } b;
476 548 uint32_t r;
477 549 } nvme_error_recovery_t;
478 550
479 551 /* Volatile Write Cache Feature */
480 552 typedef union {
481 553 struct {
482 554 uint32_t wc_wce:1; /* Volatile Write Cache Enable */
483 555 uint32_t wc_rsvd:31;
484 556 } b;
485 557 uint32_t r;
486 558 } nvme_write_cache_t;
487 559
488 560 /* Number of Queues Feature */
489 561 typedef union {
490 562 struct {
491 563 uint16_t nq_nsq; /* Number of Submission Queues */
492 564 uint16_t nq_ncq; /* Number of Completion Queues */
493 565 } b;
494 566 uint32_t r;
495 567 } nvme_nqueues_t;
496 568
497 569 /* Interrupt Coalescing Feature */
498 570 typedef union {
499 571 struct {
500 572 uint8_t ic_thr; /* Aggregation Threshold */
501 573 uint8_t ic_time; /* Aggregation Time */
502 574 uint16_t ic_rsvd;
503 575 } b;
504 576 uint32_t r;
505 577 } nvme_intr_coal_t;
506 578
507 579 /* Interrupt Configuration Features */
508 580 typedef union {
509 581 struct {
510 582 uint16_t iv_iv; /* Interrupt Vector */
511 583 uint16_t iv_cd:1; /* Coalescing Disable */
512 584 uint16_t iv_rsvd:15;
513 585 } b;
514 586 uint32_t r;
515 587 } nvme_intr_vect_t;
516 588
517 589 /* Write Atomicity Feature */
518 590 typedef union {
519 591 struct {
520 592 uint32_t wa_dn:1; /* Disable Normal */
521 593 uint32_t wa_rsvd:31;
522 594 } b;
523 595 uint32_t r;
524 596 } nvme_write_atomicity_t;
525 597
526 598 /* Asynchronous Event Configuration Feature */
527 599 typedef union {
528 600 struct {
529 601 uint8_t aec_avail:1; /* available space too low */
530 602 uint8_t aec_temp:1; /* temperature too high */
531 603 uint8_t aec_reliab:1; /* degraded reliability */
532 604 uint8_t aec_readonly:1; /* media is read-only */
533 605 uint8_t aec_volatile:1; /* volatile memory backup failed */
534 606 uint8_t aec_rsvd1:3;
535 607 uint8_t aec_rsvd2[3];
536 608 } b;
537 609 uint32_t r;
538 610 } nvme_async_event_conf_t;
539 611
540 612 /* Autonomous Power State Transition Feature (1.1) */
541 613 typedef union {
542 614 struct {
543 615 uint8_t apst_apste:1; /* APST enabled */
544 616 uint8_t apst_rsvd:7;
545 617 } b;
546 618 uint8_t r;
547 619 } nvme_auto_power_state_trans_t;
548 620
549 621 typedef struct {
550 622 uint32_t apst_rsvd1:3;
551 623 uint32_t apst_itps:5; /* Idle Transition Power State */
552 624 uint32_t apst_itpt:24; /* Idle Time Prior to Transition */
553 625 uint32_t apst_rsvd2;
554 626 } nvme_auto_power_state_t;
555 627
556 628 #define NVME_AUTO_PST_BUFSIZE 256
557 629
558 630 /* Software Progress Marker Feature */
559 631 typedef union {
560 632 struct {
561 633 uint8_t spm_pbslc; /* Pre-Boot Software Load Count */
562 634 uint8_t spm_rsvd[3];
563 635 } b;
564 636 uint32_t r;
565 637 } nvme_software_progress_marker_t;
566 638
567 639 #pragma pack() /* pack(1) */
568 640
569 641
570 642 #ifdef __cplusplus
571 643 }
572 644 #endif
573 645
574 646 #endif /* _SYS_NVME_H */
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