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MFV: illumos-gate@48d370f1e98a10b1bdf160dd83a49e0f49f6c1b7
9809 nvme driver should attach to all NVMe 1.x devices
9810 Update parts of NVMe headers for newer specs
9811 nvmeadm(1M) should have ctf
Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Andy Fiddaman <omnios@citrus-it.co.uk>
Approved by: Dan McDonald <danmcd@joyent.com>
Author: Robert Mustacchi <rm@joyent.com>
NEX-8020 illumos nvme changes
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Gordon Ross <gordon.ross@nexenta.com>
NEX-5792 support NVMe namespace EUI64
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-6132 nvmeadm(1M) get-feature command could use some cleanup
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-6130 basic NVMe 1.1 support
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-4431 want NVMe management utility
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
@@ -9,10 +9,11 @@
* http://www.illumos.org/license/CDDL.
*/
/*
* Copyright 2016 Nexenta Systems, Inc.
+ * Copyright (c) 2018, Joyent, Inc.
*/
#ifndef _SYS_NVME_H
#define _SYS_NVME_H
@@ -120,11 +121,19 @@
uint8_t psd_rsvd4:3;
uint8_t psd_rwt:5; /* Relative Write Throughput */
uint8_t psd_rsvd5:3;
uint8_t psd_rwl:5; /* Relative Write Latency */
uint8_t psd_rsvd6:3;
- uint8_t psd_rsvd7[16];
+ uint16_t psd_idlp; /* Idle Power (1.2) */
+ uint8_t psd_rsvd7:6;
+ uint8_t psd_ips:2; /* Idle Power Scale (1.2) */
+ uint8_t psd_rsvd8;
+ uint16_t psd_actp; /* Active Power (1.2) */
+ uint8_t psd_apw:3; /* Active Power Workload (1.2) */
+ uint8_t psd_rsvd9:3;
+ uint8_t psd_aps:2; /* Active Power Scale */
+ uint8_t psd_rsvd10[9];
} nvme_idctl_psd_t;
/* NVMe Identify Controller Data Structure */
typedef struct {
/* Controller Capabilities & Features */
@@ -141,11 +150,22 @@
uint8_t m_sr_iov:1; /* controller is SR-IOV virt fn (1.1) */
uint8_t m_rsvd:5;
} id_mic;
uint8_t id_mdts; /* Maximum Data Transfer Size */
uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */
- uint8_t id_rsvd_cc[256 - 80];
+ /* Added in NVMe 1.2 */
+ uint32_t id_ver; /* Version */
+ uint32_t id_rtd3r; /* RTD3 Resume Latency */
+ uint32_t id_rtd3e; /* RTD3 Entry Latency */
+ uint32_t id_oaes; /* Optional Asynchronous Events */
+ /* Added in NVMe 1.3 */
+ uint32_t id_ctratt; /* Controller Attributes */
+ uint8_t id_rsvd_cc[12];
+ uint8_t id_frguid[16]; /* FRU GUID */
+ uint8_t id_rsvd2_cc[240 - 128];
+ uint8_t id_rsvd_nvmemi[255 - 240];
+ uint8_t id_mec; /* Management Endpiont Capabilities */
/* Admin Command Set Attributes */
struct { /* Optional Admin Command Support */
uint16_t oa_security:1; /* Security Send & Receive */
uint16_t oa_format:1; /* Format NVM */
@@ -171,16 +191,34 @@
} id_avscc;
struct { /* Autonomous Power State Trans (1.1) */
uint8_t ap_sup:1; /* APST supported (1.1) */
uint8_t ap_rsvd:7;
} id_apsta;
- uint8_t id_rsvd_ac[256 - 10];
+ /* Added in NVMe 1.2 */
+ uint16_t ap_wctemp; /* Warning Composite Temperature */
+ uint16_t ap_cctemp; /* Critical Composite Temperature */
+ uint16_t ap_mtfa; /* Maximum Firmware Activation Time */
+ uint32_t ap_hmpre; /* Host Memory Buffer Preferred Size */
+ uint32_t ap_hmmin; /* Host Memory Buffer Min Size */
+ uint8_t ap_tnvmcap[16]; /* Total NVM Capacity in Bytes */
+ uint8_t ap_unvmcap[16]; /* Unallocated NVM Capacity */
+ uint32_t ap_rpmbs; /* Replay Protected Memory Block */
+ /* Added in NVMe 1.3 */
+ uint16_t ap_edstt; /* Extended Device Self-test time */
+ uint8_t ap_dsto; /* Device Self-test Options */
+ uint8_t ap_fwug; /* Firmware Update Granularity */
+ uint16_t ap_kas; /* Keep Alive Support */
+ uint16_t ap_hctma; /* Host Thermal Management */
+ uint16_t ap_mntmt; /* Minimum Thermal Temperature */
+ uint16_t ap_mxtmt; /* Maximum Thermal Temperature */
+ uint32_t ap_sanitize; /* Sanitize Caps */
+ uint8_t id_rsvd_ac[512 - 332];
/* NVM Command Set Attributes */
nvme_idctl_qes_t id_sqes; /* Submission Queue Entry Size */
nvme_idctl_qes_t id_cqes; /* Completion Queue Entry Size */
- uint16_t id_rsvd_nc_1;
+ uint16_t id_maxcmd; /* Max Outstanding Commands (1.3) */
uint32_t id_nn; /* Number of Namespaces */
struct { /* Optional NVM Command Support */
uint16_t on_compare:1; /* Compare */
uint16_t on_wr_unc:1; /* Write Uncorrectable */
uint16_t on_dset_mgmt:1; /* Dataset Management */
@@ -216,14 +254,16 @@
uint16_t sgl_sup:1; /* SGL Supported in NVM cmds (1.1) */
uint16_t sgl_rsvd1:15;
uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */
uint16_t sgl_rsvd2:15;
} id_sgls;
- uint8_t id_rsvd_nc_4[192 - 28];
+ uint8_t id_rsvd_nc_4[768 - 540];
/* I/O Command Set Attributes */
- uint8_t id_rsvd_ioc[1344];
+ uint8_t id_subnqn[1024 - 768]; /* Subsystem Qualified Name (1.2.1+) */
+ uint8_t id_rsvd_ioc[1792 - 1024];
+ uint8_t id_nvmof[2048 - 1792]; /* NVMe over Fabrics */
/* Power State Descriptors */
nvme_idctl_psd_t id_psd[32];
/* Vendor Specific */
@@ -283,19 +323,51 @@
uint8_t rc_excl_r:1; /* Excl Acc - Registrants Only (1.1) */
uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */
uint8_t rc_excl_a:1; /* Excl Acc - All Registrants (1.1) */
uint8_t rc_rsvd:1;
} id_rescap;
- uint8_t id_rsvd1[120 - 32];
+ uint8_t id_fpi; /* Format Progress Indicator (1.2) */
+ uint8_t id_dfleat; /* Deallocate Log. Block (1.3) */
+ uint16_t id_nawun; /* Atomic Write Unit Normal (1.2) */
+ uint16_t id_nawupf; /* Atomic Write Unit Power Fail (1.2) */
+ uint16_t id_nacwu; /* Atomic Compare & Write Unit (1.2) */
+ uint16_t id_nabsn; /* Atomic Boundary Size Normal (1.2) */
+ uint16_t id_nbao; /* Atomic Boundary Offset (1.2) */
+ uint16_t id_nabspf; /* Atomic Boundary Size Fail (1.2) */
+ uint16_t id_noiob; /* Optimal I/O Bondary (1.3) */
+ uint8_t id_nvmcap[16]; /* NVM Capacity */
+ uint8_t id_rsvd1[104 - 64];
+ uint8_t id_nguid[16]; /* Namespace GUID (1.2) */
uint8_t id_eui64[8]; /* IEEE Extended Unique Id (1.1) */
nvme_idns_lbaf_t id_lbaf[16]; /* LBA Formats */
- uint8_t id_rsvd2[192];
+ uint8_t id_rsvd2[384 - 192];
- uint8_t id_vs[3712]; /* Vendor Specific */
+ uint8_t id_vs[4096 - 384]; /* Vendor Specific */
} nvme_identify_nsid_t;
+/* NVMe Identify Primary Controller Capabilities */
+typedef struct {
+ uint16_t nipc_cntlid; /* Controller ID */
+ uint16_t nipc_portid; /* Port Identifier */
+ uint8_t nipc_crt; /* Controller Resource Types */
+ uint8_t nipc_rsvd0[32 - 5];
+ uint32_t nipc_vqfrt; /* VQ Resources Flexible Total */
+ uint32_t nipc_vqrfa; /* VQ Resources Flexible Assigned */
+ uint16_t nipc_vqrfap; /* VQ Resources to Primary */
+ uint16_t nipc_vqprt; /* VQ Resources Private Total */
+ uint16_t nipc_vqfrsm; /* VQ Resources Secondary Max */
+ uint16_t nipc_vqgran; /* VQ Flexible Resource Gran */
+ uint8_t nipc_rvsd1[64 - 48];
+ uint32_t nipc_vifrt; /* VI Flexible total */
+ uint32_t nipc_virfa; /* VI Flexible Assigned */
+ uint16_t nipc_virfap; /* VI Flexible Allocatd to Primary */
+ uint16_t nipc_viprt; /* VI Resources Private Total */
+ uint16_t nipc_vifrsm; /* VI Resources Secondary Max */
+ uint16_t nipc_vigran; /* VI Flexible Granularity */
+ uint8_t nipc_rsvd2[4096 - 80];
+} nvme_identify_primary_caps_t;
/*
* NVMe completion queue entry status field
*/
typedef struct {