1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2016 Nexenta Systems, Inc.
14 */
15
16 #ifndef _SYS_NVME_H
17 #define _SYS_NVME_H
18
19 #include <sys/types.h>
20
21 #ifdef _KERNEL
22 #include <sys/types32.h>
23 #else
24 #include <stdint.h>
25 #endif
26
27 /*
28 * Declarations used for communication between nvmeadm(1M) and nvme(7D)
29 */
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
105 uint8_t qes_max:4; /* maximum entry size */
106 } nvme_idctl_qes_t;
107
108 /* NVMe Power State Descriptor */
109 typedef struct {
110 uint16_t psd_mp; /* Maximum Power */
111 uint8_t psd_rsvd1;
112 uint8_t psd_mps:1; /* Max Power Scale (1.1) */
113 uint8_t psd_nops:1; /* Non-Operational State (1.1) */
114 uint8_t psd_rsvd2:6;
115 uint32_t psd_enlat; /* Entry Latency */
116 uint32_t psd_exlat; /* Exit Latency */
117 uint8_t psd_rrt:5; /* Relative Read Throughput */
118 uint8_t psd_rsvd3:3;
119 uint8_t psd_rrl:5; /* Relative Read Latency */
120 uint8_t psd_rsvd4:3;
121 uint8_t psd_rwt:5; /* Relative Write Throughput */
122 uint8_t psd_rsvd5:3;
123 uint8_t psd_rwl:5; /* Relative Write Latency */
124 uint8_t psd_rsvd6:3;
125 uint8_t psd_rsvd7[16];
126 } nvme_idctl_psd_t;
127
128 /* NVMe Identify Controller Data Structure */
129 typedef struct {
130 /* Controller Capabilities & Features */
131 uint16_t id_vid; /* PCI vendor ID */
132 uint16_t id_ssvid; /* PCI subsystem vendor ID */
133 char id_serial[20]; /* Serial Number */
134 char id_model[40]; /* Model Number */
135 char id_fwrev[8]; /* Firmware Revision */
136 uint8_t id_rab; /* Recommended Arbitration Burst */
137 uint8_t id_oui[3]; /* vendor IEEE OUI */
138 struct { /* Multi-Interface Capabilities */
139 uint8_t m_multi_pci:1; /* HW has multiple PCIe interfaces */
140 uint8_t m_multi_ctrl:1; /* HW has multiple controllers (1.1) */
141 uint8_t m_sr_iov:1; /* controller is SR-IOV virt fn (1.1) */
142 uint8_t m_rsvd:5;
143 } id_mic;
144 uint8_t id_mdts; /* Maximum Data Transfer Size */
145 uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */
146 uint8_t id_rsvd_cc[256 - 80];
147
148 /* Admin Command Set Attributes */
149 struct { /* Optional Admin Command Support */
150 uint16_t oa_security:1; /* Security Send & Receive */
151 uint16_t oa_format:1; /* Format NVM */
152 uint16_t oa_firmware:1; /* Firmware Activate & Download */
153 uint16_t oa_rsvd:13;
154 } id_oacs;
155 uint8_t id_acl; /* Abort Command Limit */
156 uint8_t id_aerl; /* Asynchronous Event Request Limit */
157 struct { /* Firmware Updates */
158 uint8_t fw_readonly:1; /* Slot 1 is Read-Only */
159 uint8_t fw_nslot:3; /* number of firmware slots */
160 uint8_t fw_rsvd:4;
161 } id_frmw;
162 struct { /* Log Page Attributes */
163 uint8_t lp_smart:1; /* SMART/Health information per NS */
164 uint8_t lp_rsvd:7;
165 } id_lpa;
166 uint8_t id_elpe; /* Error Log Page Entries */
167 uint8_t id_npss; /* Number of Power States */
168 struct { /* Admin Vendor Specific Command Conf */
169 uint8_t av_spec:1; /* use format from spec */
170 uint8_t av_rsvd:7;
171 } id_avscc;
172 struct { /* Autonomous Power State Trans (1.1) */
173 uint8_t ap_sup:1; /* APST supported (1.1) */
174 uint8_t ap_rsvd:7;
175 } id_apsta;
176 uint8_t id_rsvd_ac[256 - 10];
177
178 /* NVM Command Set Attributes */
179 nvme_idctl_qes_t id_sqes; /* Submission Queue Entry Size */
180 nvme_idctl_qes_t id_cqes; /* Completion Queue Entry Size */
181 uint16_t id_rsvd_nc_1;
182 uint32_t id_nn; /* Number of Namespaces */
183 struct { /* Optional NVM Command Support */
184 uint16_t on_compare:1; /* Compare */
185 uint16_t on_wr_unc:1; /* Write Uncorrectable */
186 uint16_t on_dset_mgmt:1; /* Dataset Management */
187 uint16_t on_wr_zero:1; /* Write Zeros (1.1) */
188 uint16_t on_save:1; /* Save/Select in Get/Set Feat (1.1) */
189 uint16_t on_reserve:1; /* Reservations (1.1) */
190 uint16_t on_rsvd:10;
191 } id_oncs;
192 struct { /* Fused Operation Support */
193 uint16_t f_cmp_wr:1; /* Compare and Write */
194 uint16_t f_rsvd:15;
195 } id_fuses;
196 struct { /* Format NVM Attributes */
197 uint8_t fn_format:1; /* Format applies to all NS */
198 uint8_t fn_sec_erase:1; /* Secure Erase applies to all NS */
199 uint8_t fn_crypt_erase:1; /* Cryptographic Erase supported */
200 uint8_t fn_rsvd:5;
201 } id_fna;
202 struct { /* Volatile Write Cache */
203 uint8_t vwc_present:1; /* Volatile Write Cache present */
204 uint8_t rsvd:7;
205 } id_vwc;
206 uint16_t id_awun; /* Atomic Write Unit Normal */
207 uint16_t id_awupf; /* Atomic Write Unit Power Fail */
208 struct { /* NVM Vendor Specific Command Conf */
209 uint8_t nv_spec:1; /* use format from spec */
210 uint8_t nv_rsvd:7;
211 } id_nvscc;
212 uint8_t id_rsvd_nc_2;
213 uint16_t id_acwu; /* Atomic Compare & Write Unit (1.1) */
214 uint16_t id_rsvd_nc_3;
215 struct { /* SGL Support (1.1) */
216 uint16_t sgl_sup:1; /* SGL Supported in NVM cmds (1.1) */
217 uint16_t sgl_rsvd1:15;
218 uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */
219 uint16_t sgl_rsvd2:15;
220 } id_sgls;
221 uint8_t id_rsvd_nc_4[192 - 28];
222
223 /* I/O Command Set Attributes */
224 uint8_t id_rsvd_ioc[1344];
225
226 /* Power State Descriptors */
227 nvme_idctl_psd_t id_psd[32];
228
229 /* Vendor Specific */
230 uint8_t id_vs[1024];
231 } nvme_identify_ctrl_t;
232
233 /* NVMe Identify Namespace LBA Format */
234 typedef struct {
235 uint16_t lbaf_ms; /* Metadata Size */
236 uint8_t lbaf_lbads; /* LBA Data Size */
237 uint8_t lbaf_rp:2; /* Relative Performance */
238 uint8_t lbaf_rsvd1:6;
239 } nvme_idns_lbaf_t;
240
241 /* NVMe Identify Namespace Data Structure */
242 typedef struct {
243 uint64_t id_nsize; /* Namespace Size */
244 uint64_t id_ncap; /* Namespace Capacity */
268 } id_dpc;
269 struct { /* Data Protection Settings */
270 uint8_t dp_pinfo:3; /* Protection Information enabled */
271 uint8_t dp_first:1; /* first 8 bytes of metadata */
272 uint8_t dp_rsvd:4;
273 } id_dps;
274 struct { /* NS Multi-Path/Sharing Cap (1.1) */
275 uint8_t nm_shared:1; /* NS is shared (1.1) */
276 uint8_t nm_rsvd:7;
277 } id_nmic;
278 struct { /* Reservation Capabilities (1.1) */
279 uint8_t rc_persist:1; /* Persist Through Power Loss (1.1) */
280 uint8_t rc_wr_excl:1; /* Write Exclusive (1.1) */
281 uint8_t rc_excl:1; /* Exclusive Access (1.1) */
282 uint8_t rc_wr_excl_r:1; /* Wr Excl - Registrants Only (1.1) */
283 uint8_t rc_excl_r:1; /* Excl Acc - Registrants Only (1.1) */
284 uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */
285 uint8_t rc_excl_a:1; /* Excl Acc - All Registrants (1.1) */
286 uint8_t rc_rsvd:1;
287 } id_rescap;
288 uint8_t id_rsvd1[120 - 32];
289 uint8_t id_eui64[8]; /* IEEE Extended Unique Id (1.1) */
290 nvme_idns_lbaf_t id_lbaf[16]; /* LBA Formats */
291
292 uint8_t id_rsvd2[192];
293
294 uint8_t id_vs[3712]; /* Vendor Specific */
295 } nvme_identify_nsid_t;
296
297
298 /*
299 * NVMe completion queue entry status field
300 */
301 typedef struct {
302 uint16_t sf_p:1; /* Phase Tag */
303 uint16_t sf_sc:8; /* Status Code */
304 uint16_t sf_sct:3; /* Status Code Type */
305 uint16_t sf_rsvd2:2;
306 uint16_t sf_m:1; /* More */
307 uint16_t sf_dnr:1; /* Do Not Retry */
308 } nvme_cqe_sf_t;
309
310
311 /*
312 * NVMe Get Log Page
313 */
314 #define NVME_LOGPAGE_ERROR 0x1 /* Error Information */
315 #define NVME_LOGPAGE_HEALTH 0x2 /* SMART/Health Information */
316 #define NVME_LOGPAGE_FWSLOT 0x3 /* Firmware Slot Information */
|
1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2016 Nexenta Systems, Inc.
14 * Copyright (c) 2018, Joyent, Inc.
15 */
16
17 #ifndef _SYS_NVME_H
18 #define _SYS_NVME_H
19
20 #include <sys/types.h>
21
22 #ifdef _KERNEL
23 #include <sys/types32.h>
24 #else
25 #include <stdint.h>
26 #endif
27
28 /*
29 * Declarations used for communication between nvmeadm(1M) and nvme(7D)
30 */
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
106 uint8_t qes_max:4; /* maximum entry size */
107 } nvme_idctl_qes_t;
108
109 /* NVMe Power State Descriptor */
110 typedef struct {
111 uint16_t psd_mp; /* Maximum Power */
112 uint8_t psd_rsvd1;
113 uint8_t psd_mps:1; /* Max Power Scale (1.1) */
114 uint8_t psd_nops:1; /* Non-Operational State (1.1) */
115 uint8_t psd_rsvd2:6;
116 uint32_t psd_enlat; /* Entry Latency */
117 uint32_t psd_exlat; /* Exit Latency */
118 uint8_t psd_rrt:5; /* Relative Read Throughput */
119 uint8_t psd_rsvd3:3;
120 uint8_t psd_rrl:5; /* Relative Read Latency */
121 uint8_t psd_rsvd4:3;
122 uint8_t psd_rwt:5; /* Relative Write Throughput */
123 uint8_t psd_rsvd5:3;
124 uint8_t psd_rwl:5; /* Relative Write Latency */
125 uint8_t psd_rsvd6:3;
126 uint16_t psd_idlp; /* Idle Power (1.2) */
127 uint8_t psd_rsvd7:6;
128 uint8_t psd_ips:2; /* Idle Power Scale (1.2) */
129 uint8_t psd_rsvd8;
130 uint16_t psd_actp; /* Active Power (1.2) */
131 uint8_t psd_apw:3; /* Active Power Workload (1.2) */
132 uint8_t psd_rsvd9:3;
133 uint8_t psd_aps:2; /* Active Power Scale */
134 uint8_t psd_rsvd10[9];
135 } nvme_idctl_psd_t;
136
137 /* NVMe Identify Controller Data Structure */
138 typedef struct {
139 /* Controller Capabilities & Features */
140 uint16_t id_vid; /* PCI vendor ID */
141 uint16_t id_ssvid; /* PCI subsystem vendor ID */
142 char id_serial[20]; /* Serial Number */
143 char id_model[40]; /* Model Number */
144 char id_fwrev[8]; /* Firmware Revision */
145 uint8_t id_rab; /* Recommended Arbitration Burst */
146 uint8_t id_oui[3]; /* vendor IEEE OUI */
147 struct { /* Multi-Interface Capabilities */
148 uint8_t m_multi_pci:1; /* HW has multiple PCIe interfaces */
149 uint8_t m_multi_ctrl:1; /* HW has multiple controllers (1.1) */
150 uint8_t m_sr_iov:1; /* controller is SR-IOV virt fn (1.1) */
151 uint8_t m_rsvd:5;
152 } id_mic;
153 uint8_t id_mdts; /* Maximum Data Transfer Size */
154 uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */
155 /* Added in NVMe 1.2 */
156 uint32_t id_ver; /* Version */
157 uint32_t id_rtd3r; /* RTD3 Resume Latency */
158 uint32_t id_rtd3e; /* RTD3 Entry Latency */
159 uint32_t id_oaes; /* Optional Asynchronous Events */
160 /* Added in NVMe 1.3 */
161 uint32_t id_ctratt; /* Controller Attributes */
162 uint8_t id_rsvd_cc[12];
163 uint8_t id_frguid[16]; /* FRU GUID */
164 uint8_t id_rsvd2_cc[240 - 128];
165 uint8_t id_rsvd_nvmemi[255 - 240];
166 uint8_t id_mec; /* Management Endpiont Capabilities */
167
168 /* Admin Command Set Attributes */
169 struct { /* Optional Admin Command Support */
170 uint16_t oa_security:1; /* Security Send & Receive */
171 uint16_t oa_format:1; /* Format NVM */
172 uint16_t oa_firmware:1; /* Firmware Activate & Download */
173 uint16_t oa_rsvd:13;
174 } id_oacs;
175 uint8_t id_acl; /* Abort Command Limit */
176 uint8_t id_aerl; /* Asynchronous Event Request Limit */
177 struct { /* Firmware Updates */
178 uint8_t fw_readonly:1; /* Slot 1 is Read-Only */
179 uint8_t fw_nslot:3; /* number of firmware slots */
180 uint8_t fw_rsvd:4;
181 } id_frmw;
182 struct { /* Log Page Attributes */
183 uint8_t lp_smart:1; /* SMART/Health information per NS */
184 uint8_t lp_rsvd:7;
185 } id_lpa;
186 uint8_t id_elpe; /* Error Log Page Entries */
187 uint8_t id_npss; /* Number of Power States */
188 struct { /* Admin Vendor Specific Command Conf */
189 uint8_t av_spec:1; /* use format from spec */
190 uint8_t av_rsvd:7;
191 } id_avscc;
192 struct { /* Autonomous Power State Trans (1.1) */
193 uint8_t ap_sup:1; /* APST supported (1.1) */
194 uint8_t ap_rsvd:7;
195 } id_apsta;
196 /* Added in NVMe 1.2 */
197 uint16_t ap_wctemp; /* Warning Composite Temperature */
198 uint16_t ap_cctemp; /* Critical Composite Temperature */
199 uint16_t ap_mtfa; /* Maximum Firmware Activation Time */
200 uint32_t ap_hmpre; /* Host Memory Buffer Preferred Size */
201 uint32_t ap_hmmin; /* Host Memory Buffer Min Size */
202 uint8_t ap_tnvmcap[16]; /* Total NVM Capacity in Bytes */
203 uint8_t ap_unvmcap[16]; /* Unallocated NVM Capacity */
204 uint32_t ap_rpmbs; /* Replay Protected Memory Block */
205 /* Added in NVMe 1.3 */
206 uint16_t ap_edstt; /* Extended Device Self-test time */
207 uint8_t ap_dsto; /* Device Self-test Options */
208 uint8_t ap_fwug; /* Firmware Update Granularity */
209 uint16_t ap_kas; /* Keep Alive Support */
210 uint16_t ap_hctma; /* Host Thermal Management */
211 uint16_t ap_mntmt; /* Minimum Thermal Temperature */
212 uint16_t ap_mxtmt; /* Maximum Thermal Temperature */
213 uint32_t ap_sanitize; /* Sanitize Caps */
214 uint8_t id_rsvd_ac[512 - 332];
215
216 /* NVM Command Set Attributes */
217 nvme_idctl_qes_t id_sqes; /* Submission Queue Entry Size */
218 nvme_idctl_qes_t id_cqes; /* Completion Queue Entry Size */
219 uint16_t id_maxcmd; /* Max Outstanding Commands (1.3) */
220 uint32_t id_nn; /* Number of Namespaces */
221 struct { /* Optional NVM Command Support */
222 uint16_t on_compare:1; /* Compare */
223 uint16_t on_wr_unc:1; /* Write Uncorrectable */
224 uint16_t on_dset_mgmt:1; /* Dataset Management */
225 uint16_t on_wr_zero:1; /* Write Zeros (1.1) */
226 uint16_t on_save:1; /* Save/Select in Get/Set Feat (1.1) */
227 uint16_t on_reserve:1; /* Reservations (1.1) */
228 uint16_t on_rsvd:10;
229 } id_oncs;
230 struct { /* Fused Operation Support */
231 uint16_t f_cmp_wr:1; /* Compare and Write */
232 uint16_t f_rsvd:15;
233 } id_fuses;
234 struct { /* Format NVM Attributes */
235 uint8_t fn_format:1; /* Format applies to all NS */
236 uint8_t fn_sec_erase:1; /* Secure Erase applies to all NS */
237 uint8_t fn_crypt_erase:1; /* Cryptographic Erase supported */
238 uint8_t fn_rsvd:5;
239 } id_fna;
240 struct { /* Volatile Write Cache */
241 uint8_t vwc_present:1; /* Volatile Write Cache present */
242 uint8_t rsvd:7;
243 } id_vwc;
244 uint16_t id_awun; /* Atomic Write Unit Normal */
245 uint16_t id_awupf; /* Atomic Write Unit Power Fail */
246 struct { /* NVM Vendor Specific Command Conf */
247 uint8_t nv_spec:1; /* use format from spec */
248 uint8_t nv_rsvd:7;
249 } id_nvscc;
250 uint8_t id_rsvd_nc_2;
251 uint16_t id_acwu; /* Atomic Compare & Write Unit (1.1) */
252 uint16_t id_rsvd_nc_3;
253 struct { /* SGL Support (1.1) */
254 uint16_t sgl_sup:1; /* SGL Supported in NVM cmds (1.1) */
255 uint16_t sgl_rsvd1:15;
256 uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */
257 uint16_t sgl_rsvd2:15;
258 } id_sgls;
259 uint8_t id_rsvd_nc_4[768 - 540];
260
261 /* I/O Command Set Attributes */
262 uint8_t id_subnqn[1024 - 768]; /* Subsystem Qualified Name (1.2.1+) */
263 uint8_t id_rsvd_ioc[1792 - 1024];
264 uint8_t id_nvmof[2048 - 1792]; /* NVMe over Fabrics */
265
266 /* Power State Descriptors */
267 nvme_idctl_psd_t id_psd[32];
268
269 /* Vendor Specific */
270 uint8_t id_vs[1024];
271 } nvme_identify_ctrl_t;
272
273 /* NVMe Identify Namespace LBA Format */
274 typedef struct {
275 uint16_t lbaf_ms; /* Metadata Size */
276 uint8_t lbaf_lbads; /* LBA Data Size */
277 uint8_t lbaf_rp:2; /* Relative Performance */
278 uint8_t lbaf_rsvd1:6;
279 } nvme_idns_lbaf_t;
280
281 /* NVMe Identify Namespace Data Structure */
282 typedef struct {
283 uint64_t id_nsize; /* Namespace Size */
284 uint64_t id_ncap; /* Namespace Capacity */
308 } id_dpc;
309 struct { /* Data Protection Settings */
310 uint8_t dp_pinfo:3; /* Protection Information enabled */
311 uint8_t dp_first:1; /* first 8 bytes of metadata */
312 uint8_t dp_rsvd:4;
313 } id_dps;
314 struct { /* NS Multi-Path/Sharing Cap (1.1) */
315 uint8_t nm_shared:1; /* NS is shared (1.1) */
316 uint8_t nm_rsvd:7;
317 } id_nmic;
318 struct { /* Reservation Capabilities (1.1) */
319 uint8_t rc_persist:1; /* Persist Through Power Loss (1.1) */
320 uint8_t rc_wr_excl:1; /* Write Exclusive (1.1) */
321 uint8_t rc_excl:1; /* Exclusive Access (1.1) */
322 uint8_t rc_wr_excl_r:1; /* Wr Excl - Registrants Only (1.1) */
323 uint8_t rc_excl_r:1; /* Excl Acc - Registrants Only (1.1) */
324 uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */
325 uint8_t rc_excl_a:1; /* Excl Acc - All Registrants (1.1) */
326 uint8_t rc_rsvd:1;
327 } id_rescap;
328 uint8_t id_fpi; /* Format Progress Indicator (1.2) */
329 uint8_t id_dfleat; /* Deallocate Log. Block (1.3) */
330 uint16_t id_nawun; /* Atomic Write Unit Normal (1.2) */
331 uint16_t id_nawupf; /* Atomic Write Unit Power Fail (1.2) */
332 uint16_t id_nacwu; /* Atomic Compare & Write Unit (1.2) */
333 uint16_t id_nabsn; /* Atomic Boundary Size Normal (1.2) */
334 uint16_t id_nbao; /* Atomic Boundary Offset (1.2) */
335 uint16_t id_nabspf; /* Atomic Boundary Size Fail (1.2) */
336 uint16_t id_noiob; /* Optimal I/O Bondary (1.3) */
337 uint8_t id_nvmcap[16]; /* NVM Capacity */
338 uint8_t id_rsvd1[104 - 64];
339 uint8_t id_nguid[16]; /* Namespace GUID (1.2) */
340 uint8_t id_eui64[8]; /* IEEE Extended Unique Id (1.1) */
341 nvme_idns_lbaf_t id_lbaf[16]; /* LBA Formats */
342
343 uint8_t id_rsvd2[384 - 192];
344
345 uint8_t id_vs[4096 - 384]; /* Vendor Specific */
346 } nvme_identify_nsid_t;
347
348 /* NVMe Identify Primary Controller Capabilities */
349 typedef struct {
350 uint16_t nipc_cntlid; /* Controller ID */
351 uint16_t nipc_portid; /* Port Identifier */
352 uint8_t nipc_crt; /* Controller Resource Types */
353 uint8_t nipc_rsvd0[32 - 5];
354 uint32_t nipc_vqfrt; /* VQ Resources Flexible Total */
355 uint32_t nipc_vqrfa; /* VQ Resources Flexible Assigned */
356 uint16_t nipc_vqrfap; /* VQ Resources to Primary */
357 uint16_t nipc_vqprt; /* VQ Resources Private Total */
358 uint16_t nipc_vqfrsm; /* VQ Resources Secondary Max */
359 uint16_t nipc_vqgran; /* VQ Flexible Resource Gran */
360 uint8_t nipc_rvsd1[64 - 48];
361 uint32_t nipc_vifrt; /* VI Flexible total */
362 uint32_t nipc_virfa; /* VI Flexible Assigned */
363 uint16_t nipc_virfap; /* VI Flexible Allocatd to Primary */
364 uint16_t nipc_viprt; /* VI Resources Private Total */
365 uint16_t nipc_vifrsm; /* VI Resources Secondary Max */
366 uint16_t nipc_vigran; /* VI Flexible Granularity */
367 uint8_t nipc_rsvd2[4096 - 80];
368 } nvme_identify_primary_caps_t;
369
370 /*
371 * NVMe completion queue entry status field
372 */
373 typedef struct {
374 uint16_t sf_p:1; /* Phase Tag */
375 uint16_t sf_sc:8; /* Status Code */
376 uint16_t sf_sct:3; /* Status Code Type */
377 uint16_t sf_rsvd2:2;
378 uint16_t sf_m:1; /* More */
379 uint16_t sf_dnr:1; /* Do Not Retry */
380 } nvme_cqe_sf_t;
381
382
383 /*
384 * NVMe Get Log Page
385 */
386 #define NVME_LOGPAGE_ERROR 0x1 /* Error Information */
387 #define NVME_LOGPAGE_HEALTH 0x2 /* SMART/Health Information */
388 #define NVME_LOGPAGE_FWSLOT 0x3 /* Firmware Slot Information */
|