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NEX-5717 import QLogic 16G FC drivers
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
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--- old/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_xioctl.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_xioctl.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 -/* Copyright 2010 QLogic Corporation */
22 +/* Copyright 2015 QLogic Corporation */
23 23
24 24 /*
25 25 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
26 26 */
27 27
28 28 #ifndef _QL_XIOCTL_H
29 29 #define _QL_XIOCTL_H
30 30
31 31 /*
32 32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
33 33 *
34 34 * ***********************************************************************
35 35 * * **
36 36 * * NOTICE **
37 - * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
37 + * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
38 38 * * ALL RIGHTS RESERVED **
39 39 * * **
40 40 * ***********************************************************************
41 41 *
42 42 */
43 43
44 44 #ifdef __cplusplus
45 45 extern "C" {
46 46 #endif
47 47
48 48 #include <exioct.h>
49 49
50 50 /* 0xFFFFFA Mgmt Server */
51 51 #define MANAGEMENT_SERVER_LOOP_ID 0xfe
52 52 #define MANAGEMENT_SERVER_24XX_LOOP_ID 0x7ef
53 53
54 54 /* Returned Mailbox registers. */
55 55 typedef struct ql_mbx_ret {
56 56 uint16_t mb[MAX_MBOX_COUNT];
57 57 } ql_mbx_ret_t;
58 58
59 59 /*
60 60 * Name type defines for use with ql_scsi_passthru() and
61 61 * elsewhere when searching for name matches.
62 62 * NOTE that these defines are used both as flags and values.
63 63 */
64 64 #define QLNT_NODE 0x01
65 65 #define QLNT_PORT 0x02
66 66 #define QLNT_BOTH (QLNT_NODE | QLNT_PORT)
67 67 #define QLNT_PID 0x04
68 68 #define QLNT_LOOP_ID 0x08
69 69 #define QLNT_MASK 0x0F
70 70
71 71 /*
72 72 * CT information unit basic preamble.
73 73 */
74 74 typedef struct ql_ct_iu_preamble {
75 75 uint8_t revision;
76 76 uint8_t in_id[3];
77 77 uint8_t gs_type;
78 78 uint8_t gs_subtype;
79 79 uint8_t options;
80 80 uint8_t reserved;
81 81 uint16_t command_response_code;
82 82 uint16_t max_residual_size;
83 83 uint8_t fragment_id;
84 84 uint8_t reason_code;
85 85 uint8_t reason_code_explanation;
86 86 uint8_t vendor_specific;
87 87 } ql_ct_iu_preamble_t;
88 88
89 89 #define GS_TYPE_DIR_SERVER 0xFC
90 90
91 91 /*
92 92 * Link Status Counts structure
93 93 *
94 94 * Counts are BIG ENDIAN
95 95 */
96 96 typedef struct ql_link_stats {
97 97 uint32_t link_fail_cnt;
98 98 uint32_t sync_loss_cnt;
99 99 uint32_t signal_loss_cnt;
100 100 uint32_t prot_err_cnt; /* Primitive seq protocol errors */
101 101 uint32_t inv_xmit_cnt; /* Invalid transmission word count */
102 102 uint32_t inv_crc_cnt; /* Invalid CRC count */
103 103 } ql_link_stats_t;
104 104
105 105 /*
106 106 * Report LUN definitions.
107 107 */
108 108 typedef struct ql_rpt_hdr {
109 109 uint32_t len;
110 110 uint32_t rsrv;
111 111 } ql_rpt_hdr_t;
112 112
113 113 typedef struct ql_rpt_lun {
114 114 struct {
115 115 uint8_t b : 6;
116 116 uint8_t address_method : 2;
117 117 } msb;
118 118 uint8_t lsb;
119 119 uint8_t unused[6];
120 120 } ql_rpt_lun_t;
121 121
122 122 typedef struct ql_rpt_lun_lst {
123 123 ql_rpt_hdr_t hdr;
124 124 ql_rpt_lun_t lst[MAX_LUNS];
125 125 } ql_rpt_lun_lst_t;
126 126
127 127 #define INQ_DATA_SIZE 8
128 128
129 129 /*
130 130 * Flash definitions.
131 131 */
132 132 typedef struct ql_flash_info {
133 133 uint32_t type; /* flash type */
134 134 uint32_t size; /* length in bytes of flash */
135 135 uint32_t sec_mask; /* sector number mask */
136 136 uint8_t man_id; /* flash chip manufacturer id */
137 137 uint8_t id; /* flash chip id */
138 138 uint8_t cap; /* flash chip capacity */
139 139 } ql_flash_info_t;
140 140
141 141 /*
142 142 * Flash Description Table
143 143 */
144 144 #define FLASH_DESC_VERSION 1
145 145 #define FLASH_DESC_VAILD 0x44494C51 /* "QLID" */
146 146 typedef struct flash_desc {
147 147 uint32_t flash_valid;
148 148 uint16_t flash_version;
149 149 uint16_t flash_len;
150 150 uint16_t flash_checksum;
151 151 uint16_t flash_unused;
152 152 uint8_t flash_model[16];
153 153 uint16_t flash_manuf;
154 154 uint16_t flash_id;
155 155 uint8_t flash_flag;
156 156 uint8_t erase_cmd;
157 157 uint8_t alt_erase_cmd;
158 158 uint8_t write_enable_cmd;
159 159 uint8_t write_enable_bits;
160 160 uint8_t write_statusreg_cmd;
161 161 uint8_t unprotect_sector_cmd;
162 162 uint8_t read_manuf_cmd;
163 163 uint32_t block_size;
164 164 uint32_t alt_block_size;
165 165 uint32_t flash_size;
166 166 uint32_t write_enable_data;
167 167 uint8_t readid_address_len;
168 168 uint8_t write_disable_bits;
169 169 uint8_t read_device_id_len;
170 170 uint8_t chip_erase_cmd;
171 171 uint16_t read_timeout;
172 172 uint8_t protect_sector_cmd;
173 173 uint8_t exp_reserved[65];
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174 174 } flash_desc_t;
175 175
176 176 /* flash manufacturer id's */
177 177 #define AMD_FLASH 0x01 /* AMD / Spansion */
178 178 #define ST_FLASH 0x20 /* ST Electronics */
179 179 #define SST_FLASH 0xbf /* SST Electronics */
180 180 #define MXIC_FLASH 0xc2 /* Macronix (MXIC) */
181 181 #define ATMEL_FLASH 0x1f /* Atmel (AT26DF081A) */
182 182 #define WINBOND_FLASH 0xef /* Winbond (W25X16) */
183 183 #define INTEL_FLASH 0x89 /* Intel (QB25F016S33B8) */
184 +#define EON_FLASH 0x1c /* EON Silicon Solutions */
184 185
185 186 /* flash id defines */
186 187 #define AMD_FLASHID_128K 0x6e /* 128k AMD flash chip */
187 188 #define AMD_FLASHID_512K 0x4f /* 512k AMD flash chip */
188 189 #define AMD_FLASHID_512Kt 0xb9 /* 512k AMD flash chip - top boot blk */
189 190 #define AMD_FLASHID_512Kb 0xba /* 512k AMD flash chip - btm boot blk */
190 191 #define AMD_FLASHID_1024K 0x38 /* 1 MB AMD flash chip */
191 192 #define ST_FLASHID_128K 0x23 /* 128k ST flash chip */
192 193 #define ST_FLASHID_512K 0xe3 /* 512k ST flash chip */
193 194 #define ST_FLASHID_M25PXX 0x20 /* M25Pxx ST flash chip */
195 +#define ST_FLASHID_N25QXXX 0xBA /* M25Qxx ST flash chip */
194 196 #define SST_FLASHID_128K 0xd5 /* 128k SST flash chip */
195 197 #define SST_FLASHID_1024K 0xd8 /* 1 MB SST flash chip */
196 198 #define SST_FLASHID_1024K_A 0x80 /* 1 MB SST 25LF080A flash chip */
197 199 #define SST_FLASHID_1024K_B 0x8e /* 1 MB SST 25VF080B flash chip */
198 200 #define SST_FLASHID_2048K 0x25 /* 2 MB SST 25VF016B flash chip */
199 201 #define MXIC_FLASHID_512K 0x4f /* 512k MXIC flash chip */
200 202 #define MXIC_FLASHID_1024K 0x38 /* 1 MB MXIC flash chip */
201 203 #define MXIC_FLASHID_25LXX 0x20 /* 25Lxx MXIC flash chip */
202 204 #define ATMEL_FLASHID_1024K 0x45 /* 1 MB ATMEL flash chip */
203 205 #define SPAN_FLASHID_2048K 0x02 /* 2 MB Spansion flash chip */
206 +#define SPAN_FLASHID_16384K 0x20 /* 16 MB Spansion flash chip */
204 207 #define WINBOND_FLASHID 0x30 /* Winbond W25Xxx flash chip */
208 +#define WINBOND_FLASHID_Q 0x40 /* Winbond W25Qxxx flash chip */
205 209 #define INTEL_FLASHID 0x89 /* Intel QB25F016S33B8 flash chip */
210 +#define EON_FLASHID_EN25QXXX 0x30 /* EON EN25Qxxx flash chip */
206 211
207 212 /* flash type defines */
208 213 #define FLASH128 BIT_0
209 214 #define FLASH512 BIT_1
210 215 #define FLASH512S BIT_2
211 216 #define FLASH1024 BIT_3
212 217 #define FLASH2048 BIT_4
213 218 #define FLASH4096 BIT_5
214 219 #define FLASH8192 BIT_6
215 220 #define FLASH_PAGE BIT_31
216 221 #define FLASH_LEGACY (FLASH128 | FLASH512S)
217 222
218 -typedef struct ql_ledstate {
219 - uint32_t BeaconState;
220 - uint32_t LEDflags;
221 - uint32_t flags;
222 -} ql_ledstate_t;
223 -
224 223 /*
225 224 * ledstate flags definitions
226 225 */
227 226 #define LED_ACTIVE BIT_0
228 227
229 228 /*
230 229 * ledstate BeaconState definitions
231 230 */
232 231 #define BEACON_OFF 0
233 232 #define BEACON_ON BIT_0
234 233
235 234 /*
236 235 * ledstate LEDflags definitions
237 236 */
238 237 #define LED_ALL_OFF 0
239 238 #define LED_RED BIT_0
240 239 #define LED_GREEN BIT_6
241 240 #define LED_AMBER BIT_7
242 241 #define LED_MASK (LED_AMBER | LED_GREEN | LED_RED)
243 242
244 243 /*
245 244 * 24xx ledstate LEDflags definitions
246 245 */
247 246 #define LED_MASK_UPDATE_24 (BIT_20 | BIT_19 | BIT_18)
248 247 #define LED_YELLOW_24 BIT_2
249 248 #define LED_GREEN_24 BIT_3
250 249 #define LED_AMBER_24 BIT_4
251 250 #define LED_MASK_COLORS_24 (LED_AMBER_24 | LED_GREEN_24 | LED_YELLOW_24)
252 251
253 252 typedef struct {
254 253 uint8_t signature[2];
255 254 uint8_t reserved[0x16];
256 255 uint8_t dataoffset[2];
257 256 uint8_t pad[6];
258 257 } pci_header_t;
259 258
260 259 typedef struct {
261 260 uint8_t signature[4];
262 261 uint8_t vid[2];
263 262 uint8_t did[2];
264 263 uint8_t reserved0[2];
265 264 uint8_t pcidatalen[2];
266 265 uint8_t pcidatarev;
267 266 uint8_t classcode[3];
268 267 uint8_t imagelength[2]; /* In sectors */
269 268 uint8_t revisionlevel[2];
270 269 uint8_t codetype;
271 270 uint8_t indicator;
272 271 uint8_t reserved1[2];
273 272 uint8_t pad[8];
274 273 } pci_data_t;
275 274
276 275 #define PCI_HEADER0 0x55
277 276 #define PCI_HEADER1 0xAA
278 277 #define PCI_DATASIG "PCIR"
279 278 #define PCI_SECTOR_SIZE 0x200
280 279 #define PCI_CODE_X86PC 0
281 280 #define PCI_CODE_FCODE 1
282 281 #define PCI_CODE_HPPA 2
283 282 #define PCI_CODE_EFI 3
284 283 #define PCI_CODE_FW 0xfe
285 284 #define PCI_IND_LAST_IMAGE 0x80
286 285 #define SBUS_CODE_FCODE 0xf1
287 286
288 287 typedef struct ql_fcache {
289 288 struct ql_fcache *next;
290 289 uint32_t type;
291 290 int8_t verstr[FCHBA_OPTION_ROM_VERSION_LEN];
292 291 uint32_t buflen;
293 292 uint8_t *buf;
294 293 } ql_fcache_t;
295 294
296 295 /* fcache types */
297 296 #define FTYPE_UNKNOWN 0
298 297 #define FTYPE_FCODE BIT_0
299 298 #define FTYPE_BIOS BIT_1
300 299 #define FTYPE_EFI BIT_2
301 300 #define FTYPE_FW BIT_3
302 301 #define FTYPE_HPPA BIT_4
303 302
304 303 #define FBUFSIZE 100
305 304
306 305 /*
307 306 * Flash Layout Table definitions.
308 307 */
309 308 typedef struct ql_flash_layout_pointer {
310 309 uint8_t sig[4];
311 310 uint8_t addr[4];
312 311 uint8_t version;
313 312 uint8_t reserved[5];
314 313 uint8_t checksum[2];
315 314 } ql_flt_ptr_t;
316 315
317 316 typedef struct ql_flash_layout_header {
318 317 uint8_t version[2];
319 318 uint8_t len[2];
320 319 uint8_t checksum[2];
321 320 uint8_t reserved[2];
322 321 } ql_flt_hdr_t;
323 322
324 323 typedef struct ql_flash_layout_region {
325 324 uint8_t region;
326 325 uint8_t reserved;
327 326 uint8_t attribute;
328 327 uint8_t reserved_1;
329 328 uint8_t size[4];
330 329 uint8_t beg_addr[4];
331 330 uint8_t end_addr[4];
332 331 } ql_flt_region_t;
333 332
334 333 typedef struct ql_fp_cfg_hdr {
335 334 uint8_t version[2];
336 335 uint8_t len[2];
337 336 uint8_t checksum[2];
338 337 uint8_t NumberEntries[2];
339 338 uint8_t SizeEntry[2];
340 339 uint8_t unused[2];
341 340 uint8_t Signature[4];
342 341 } ql_fp_cfg_hdr_t;
343 342
344 343 typedef struct ql_fp_cfg {
345 344 uint8_t FunctionNumber[2];
346 345 uint8_t FunctionType;
347 346 uint8_t PortConfigIndex;
348 347 uint8_t ConfigRegion;
349 348 uint8_t VpdRegion;
350 349 uint8_t DCBXRegion;
351 350 uint8_t Reserved;
352 351 } ql_fp_cfg_t;
353 352
354 353 #define FT_NIC 0
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355 354 #define FT_FC 1
356 355 #define FT_ISCSI 2
357 356 #define FT_VNIC 3
358 357
359 358 typedef struct ql_fp_cfg_map {
360 359 ql_fp_cfg_hdr_t hdr;
361 360 ql_fp_cfg_t cfg[6];
362 361 } ql_fp_cfg_map_t;
363 362
364 363 #define FLASH_FW_REGION 0x01
364 +#define FLASH_BOOT_CODE_REGION 0x07
365 365 #define FLASH_VPD_0_REGION 0x14
366 366 #define FLASH_NVRAM_0_REGION 0x15
367 367 #define FLASH_VPD_1_REGION 0x16
368 368 #define FLASH_NVRAM_1_REGION 0x17
369 369 #define FLASH_DESC_TABLE_REGION 0x1A
370 370 #define FLASH_ERROR_LOG_0_REGION 0x1D
371 371 #define FLASH_ERROR_LOG_1_REGION 0x1F
372 372 #define FLASH_GOLDEN_FW_REGION 0x2F
373 +#define FLASH_BOOTLOADER_REGION 0x72
373 374
374 375 #define FLASH_8021_FW_REGION 0x74
375 376 #define FLASH_8021_GOLDEN_FW_REGION 0x75
376 377 #define FLASH_8021_BOOTLOADER_REGION 0x72
377 378 #define FLASH_8021_VPD_REGION 0x81
378 379
379 380 #define FLASH_LAYOUT_TABLE_SIZE 4096
380 381
381 382 /*
382 383 * Per instance XIOCTL context defintions.
383 384 */
384 385 typedef struct ql_xioctl {
385 386 /* Driver context */
386 387 flash_desc_t fdesc;
387 388
388 389 /* Adapter I/O statistics */
389 390 uint32_t ControllerErrorCount;
390 391 uint32_t DeviceErrorCount;
391 392 uint32_t TotalLipResets;
392 393 uint32_t TotalInterrupts;
393 394
394 395 uint64_t BytesRequested;
395 396 uint64_t IosRequested;
396 397
397 398 /* SNIA stat counters */
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398 399 int64_t IOInputRequests;
399 400 int64_t IOOutputRequests;
400 401 int64_t IOControlRequests;
401 402 int64_t IOOutputMByteCnt; /* # of mb's */
402 403 int64_t IOInputMByteCnt; /* # of mb's */
403 404
404 405 /* SNIA intermediate (less than 1mb) counters */
405 406 int64_t IOOutputByteCnt;
406 407 int64_t IOInputByteCnt;
407 408
408 - /* Adapter LED state */
409 - ql_ledstate_t ledstate;
410 -
411 409 /* Async event context */
412 410 void *aen_tracking_queue;
413 411 uint8_t aen_q_head;
414 412 uint8_t aen_q_tail;
415 413
416 414 uint32_t flags;
417 415 } ql_xioctl_t;
418 416
419 417 /*
420 418 * ql adapter flag defintions.
421 419 */
422 420 #define QL_AEN_TRACKING_ENABLE BIT_0
423 421 #define QL_MGMT_SERVER_LOGIN BIT_1
424 422
425 423 /*
426 424 * Global Data in ql_xioctl.c source file.
427 425 */
428 426
429 427 /*
430 428 * Global Function Prototypes in ql_xioctl.c source file.
431 429 */
432 430 int ql_alloc_xioctl_resource(ql_adapter_state_t *);
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433 431 void ql_free_xioctl_resource(ql_adapter_state_t *);
434 432 int ql_xioctl(ql_adapter_state_t *, int, intptr_t, int, cred_t *, int *);
435 433 void ql_enqueue_aen(ql_adapter_state_t *, uint16_t, void *);
436 434 int ql_setup_fcache(ql_adapter_state_t *);
437 435 void ql_blink_led(ql_adapter_state_t *);
438 436 void ql_fcache_rel(ql_fcache_t *);
439 437 ql_fcache_t *ql_get_fbuf(ql_fcache_t *, uint32_t);
440 438 int ql_dump_fcode(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t);
441 439 int ql_pci_dump(ql_adapter_state_t *, uint32_t *, uint32_t, int);
442 440 int ql_load_fcode(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t);
441 +int ql_set_loop_point(ql_adapter_state_t *, uint16_t);
443 442
444 443 #ifdef __cplusplus
445 444 }
446 445 #endif
447 446
448 447 #endif /* _QL_XIOCTL_H */
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