1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright 2015 QLogic Corporation */
23
24 /*
25 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
26 */
27
28 #ifndef _QL_XIOCTL_H
29 #define _QL_XIOCTL_H
30
31 /*
32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
33 *
34 * ***********************************************************************
35 * * **
36 * * NOTICE **
37 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
38 * * ALL RIGHTS RESERVED **
39 * * **
40 * ***********************************************************************
41 *
42 */
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 #include <exioct.h>
49
50 /* 0xFFFFFA Mgmt Server */
51 #define MANAGEMENT_SERVER_LOOP_ID 0xfe
52 #define MANAGEMENT_SERVER_24XX_LOOP_ID 0x7ef
53
54 /* Returned Mailbox registers. */
55 typedef struct ql_mbx_ret {
56 uint16_t mb[MAX_MBOX_COUNT];
57 } ql_mbx_ret_t;
58
59 /*
60 * Name type defines for use with ql_scsi_passthru() and
61 * elsewhere when searching for name matches.
62 * NOTE that these defines are used both as flags and values.
63 */
64 #define QLNT_NODE 0x01
65 #define QLNT_PORT 0x02
66 #define QLNT_BOTH (QLNT_NODE | QLNT_PORT)
67 #define QLNT_PID 0x04
68 #define QLNT_LOOP_ID 0x08
69 #define QLNT_MASK 0x0F
70
71 /*
72 * CT information unit basic preamble.
73 */
74 typedef struct ql_ct_iu_preamble {
75 uint8_t revision;
76 uint8_t in_id[3];
77 uint8_t gs_type;
78 uint8_t gs_subtype;
79 uint8_t options;
80 uint8_t reserved;
81 uint16_t command_response_code;
82 uint16_t max_residual_size;
83 uint8_t fragment_id;
84 uint8_t reason_code;
85 uint8_t reason_code_explanation;
86 uint8_t vendor_specific;
87 } ql_ct_iu_preamble_t;
88
89 #define GS_TYPE_DIR_SERVER 0xFC
90
91 /*
92 * Link Status Counts structure
93 *
94 * Counts are BIG ENDIAN
95 */
96 typedef struct ql_link_stats {
97 uint32_t link_fail_cnt;
98 uint32_t sync_loss_cnt;
99 uint32_t signal_loss_cnt;
100 uint32_t prot_err_cnt; /* Primitive seq protocol errors */
101 uint32_t inv_xmit_cnt; /* Invalid transmission word count */
102 uint32_t inv_crc_cnt; /* Invalid CRC count */
103 } ql_link_stats_t;
104
105 /*
106 * Report LUN definitions.
107 */
108 typedef struct ql_rpt_hdr {
109 uint32_t len;
110 uint32_t rsrv;
111 } ql_rpt_hdr_t;
112
113 typedef struct ql_rpt_lun {
114 struct {
115 uint8_t b : 6;
116 uint8_t address_method : 2;
117 } msb;
118 uint8_t lsb;
119 uint8_t unused[6];
120 } ql_rpt_lun_t;
121
122 typedef struct ql_rpt_lun_lst {
123 ql_rpt_hdr_t hdr;
124 ql_rpt_lun_t lst[MAX_LUNS];
125 } ql_rpt_lun_lst_t;
126
127 #define INQ_DATA_SIZE 8
128
129 /*
130 * Flash definitions.
131 */
132 typedef struct ql_flash_info {
133 uint32_t type; /* flash type */
134 uint32_t size; /* length in bytes of flash */
135 uint32_t sec_mask; /* sector number mask */
136 uint8_t man_id; /* flash chip manufacturer id */
137 uint8_t id; /* flash chip id */
138 uint8_t cap; /* flash chip capacity */
139 } ql_flash_info_t;
140
141 /*
142 * Flash Description Table
143 */
144 #define FLASH_DESC_VERSION 1
145 #define FLASH_DESC_VAILD 0x44494C51 /* "QLID" */
146 typedef struct flash_desc {
147 uint32_t flash_valid;
148 uint16_t flash_version;
149 uint16_t flash_len;
150 uint16_t flash_checksum;
151 uint16_t flash_unused;
152 uint8_t flash_model[16];
153 uint16_t flash_manuf;
154 uint16_t flash_id;
155 uint8_t flash_flag;
156 uint8_t erase_cmd;
157 uint8_t alt_erase_cmd;
158 uint8_t write_enable_cmd;
159 uint8_t write_enable_bits;
160 uint8_t write_statusreg_cmd;
161 uint8_t unprotect_sector_cmd;
162 uint8_t read_manuf_cmd;
163 uint32_t block_size;
164 uint32_t alt_block_size;
165 uint32_t flash_size;
166 uint32_t write_enable_data;
167 uint8_t readid_address_len;
168 uint8_t write_disable_bits;
169 uint8_t read_device_id_len;
170 uint8_t chip_erase_cmd;
171 uint16_t read_timeout;
172 uint8_t protect_sector_cmd;
173 uint8_t exp_reserved[65];
174 } flash_desc_t;
175
176 /* flash manufacturer id's */
177 #define AMD_FLASH 0x01 /* AMD / Spansion */
178 #define ST_FLASH 0x20 /* ST Electronics */
179 #define SST_FLASH 0xbf /* SST Electronics */
180 #define MXIC_FLASH 0xc2 /* Macronix (MXIC) */
181 #define ATMEL_FLASH 0x1f /* Atmel (AT26DF081A) */
182 #define WINBOND_FLASH 0xef /* Winbond (W25X16) */
183 #define INTEL_FLASH 0x89 /* Intel (QB25F016S33B8) */
184 #define EON_FLASH 0x1c /* EON Silicon Solutions */
185
186 /* flash id defines */
187 #define AMD_FLASHID_128K 0x6e /* 128k AMD flash chip */
188 #define AMD_FLASHID_512K 0x4f /* 512k AMD flash chip */
189 #define AMD_FLASHID_512Kt 0xb9 /* 512k AMD flash chip - top boot blk */
190 #define AMD_FLASHID_512Kb 0xba /* 512k AMD flash chip - btm boot blk */
191 #define AMD_FLASHID_1024K 0x38 /* 1 MB AMD flash chip */
192 #define ST_FLASHID_128K 0x23 /* 128k ST flash chip */
193 #define ST_FLASHID_512K 0xe3 /* 512k ST flash chip */
194 #define ST_FLASHID_M25PXX 0x20 /* M25Pxx ST flash chip */
195 #define ST_FLASHID_N25QXXX 0xBA /* M25Qxx ST flash chip */
196 #define SST_FLASHID_128K 0xd5 /* 128k SST flash chip */
197 #define SST_FLASHID_1024K 0xd8 /* 1 MB SST flash chip */
198 #define SST_FLASHID_1024K_A 0x80 /* 1 MB SST 25LF080A flash chip */
199 #define SST_FLASHID_1024K_B 0x8e /* 1 MB SST 25VF080B flash chip */
200 #define SST_FLASHID_2048K 0x25 /* 2 MB SST 25VF016B flash chip */
201 #define MXIC_FLASHID_512K 0x4f /* 512k MXIC flash chip */
202 #define MXIC_FLASHID_1024K 0x38 /* 1 MB MXIC flash chip */
203 #define MXIC_FLASHID_25LXX 0x20 /* 25Lxx MXIC flash chip */
204 #define ATMEL_FLASHID_1024K 0x45 /* 1 MB ATMEL flash chip */
205 #define SPAN_FLASHID_2048K 0x02 /* 2 MB Spansion flash chip */
206 #define SPAN_FLASHID_16384K 0x20 /* 16 MB Spansion flash chip */
207 #define WINBOND_FLASHID 0x30 /* Winbond W25Xxx flash chip */
208 #define WINBOND_FLASHID_Q 0x40 /* Winbond W25Qxxx flash chip */
209 #define INTEL_FLASHID 0x89 /* Intel QB25F016S33B8 flash chip */
210 #define EON_FLASHID_EN25QXXX 0x30 /* EON EN25Qxxx flash chip */
211
212 /* flash type defines */
213 #define FLASH128 BIT_0
214 #define FLASH512 BIT_1
215 #define FLASH512S BIT_2
216 #define FLASH1024 BIT_3
217 #define FLASH2048 BIT_4
218 #define FLASH4096 BIT_5
219 #define FLASH8192 BIT_6
220 #define FLASH_PAGE BIT_31
221 #define FLASH_LEGACY (FLASH128 | FLASH512S)
222
223 /*
224 * ledstate flags definitions
225 */
226 #define LED_ACTIVE BIT_0
227
228 /*
229 * ledstate BeaconState definitions
230 */
231 #define BEACON_OFF 0
232 #define BEACON_ON BIT_0
233
234 /*
235 * ledstate LEDflags definitions
236 */
237 #define LED_ALL_OFF 0
238 #define LED_RED BIT_0
239 #define LED_GREEN BIT_6
240 #define LED_AMBER BIT_7
241 #define LED_MASK (LED_AMBER | LED_GREEN | LED_RED)
242
243 /*
244 * 24xx ledstate LEDflags definitions
245 */
246 #define LED_MASK_UPDATE_24 (BIT_20 | BIT_19 | BIT_18)
247 #define LED_YELLOW_24 BIT_2
248 #define LED_GREEN_24 BIT_3
249 #define LED_AMBER_24 BIT_4
250 #define LED_MASK_COLORS_24 (LED_AMBER_24 | LED_GREEN_24 | LED_YELLOW_24)
251
252 typedef struct {
253 uint8_t signature[2];
254 uint8_t reserved[0x16];
255 uint8_t dataoffset[2];
256 uint8_t pad[6];
257 } pci_header_t;
258
259 typedef struct {
260 uint8_t signature[4];
261 uint8_t vid[2];
262 uint8_t did[2];
263 uint8_t reserved0[2];
264 uint8_t pcidatalen[2];
265 uint8_t pcidatarev;
266 uint8_t classcode[3];
267 uint8_t imagelength[2]; /* In sectors */
268 uint8_t revisionlevel[2];
269 uint8_t codetype;
270 uint8_t indicator;
271 uint8_t reserved1[2];
272 uint8_t pad[8];
273 } pci_data_t;
274
275 #define PCI_HEADER0 0x55
276 #define PCI_HEADER1 0xAA
277 #define PCI_DATASIG "PCIR"
278 #define PCI_SECTOR_SIZE 0x200
279 #define PCI_CODE_X86PC 0
280 #define PCI_CODE_FCODE 1
281 #define PCI_CODE_HPPA 2
282 #define PCI_CODE_EFI 3
283 #define PCI_CODE_FW 0xfe
284 #define PCI_IND_LAST_IMAGE 0x80
285 #define SBUS_CODE_FCODE 0xf1
286
287 typedef struct ql_fcache {
288 struct ql_fcache *next;
289 uint32_t type;
290 int8_t verstr[FCHBA_OPTION_ROM_VERSION_LEN];
291 uint32_t buflen;
292 uint8_t *buf;
293 } ql_fcache_t;
294
295 /* fcache types */
296 #define FTYPE_UNKNOWN 0
297 #define FTYPE_FCODE BIT_0
298 #define FTYPE_BIOS BIT_1
299 #define FTYPE_EFI BIT_2
300 #define FTYPE_FW BIT_3
301 #define FTYPE_HPPA BIT_4
302
303 #define FBUFSIZE 100
304
305 /*
306 * Flash Layout Table definitions.
307 */
308 typedef struct ql_flash_layout_pointer {
309 uint8_t sig[4];
310 uint8_t addr[4];
311 uint8_t version;
312 uint8_t reserved[5];
313 uint8_t checksum[2];
314 } ql_flt_ptr_t;
315
316 typedef struct ql_flash_layout_header {
317 uint8_t version[2];
318 uint8_t len[2];
319 uint8_t checksum[2];
320 uint8_t reserved[2];
321 } ql_flt_hdr_t;
322
323 typedef struct ql_flash_layout_region {
324 uint8_t region;
325 uint8_t reserved;
326 uint8_t attribute;
327 uint8_t reserved_1;
328 uint8_t size[4];
329 uint8_t beg_addr[4];
330 uint8_t end_addr[4];
331 } ql_flt_region_t;
332
333 typedef struct ql_fp_cfg_hdr {
334 uint8_t version[2];
335 uint8_t len[2];
336 uint8_t checksum[2];
337 uint8_t NumberEntries[2];
338 uint8_t SizeEntry[2];
339 uint8_t unused[2];
340 uint8_t Signature[4];
341 } ql_fp_cfg_hdr_t;
342
343 typedef struct ql_fp_cfg {
344 uint8_t FunctionNumber[2];
345 uint8_t FunctionType;
346 uint8_t PortConfigIndex;
347 uint8_t ConfigRegion;
348 uint8_t VpdRegion;
349 uint8_t DCBXRegion;
350 uint8_t Reserved;
351 } ql_fp_cfg_t;
352
353 #define FT_NIC 0
354 #define FT_FC 1
355 #define FT_ISCSI 2
356 #define FT_VNIC 3
357
358 typedef struct ql_fp_cfg_map {
359 ql_fp_cfg_hdr_t hdr;
360 ql_fp_cfg_t cfg[6];
361 } ql_fp_cfg_map_t;
362
363 #define FLASH_FW_REGION 0x01
364 #define FLASH_BOOT_CODE_REGION 0x07
365 #define FLASH_VPD_0_REGION 0x14
366 #define FLASH_NVRAM_0_REGION 0x15
367 #define FLASH_VPD_1_REGION 0x16
368 #define FLASH_NVRAM_1_REGION 0x17
369 #define FLASH_DESC_TABLE_REGION 0x1A
370 #define FLASH_ERROR_LOG_0_REGION 0x1D
371 #define FLASH_ERROR_LOG_1_REGION 0x1F
372 #define FLASH_GOLDEN_FW_REGION 0x2F
373 #define FLASH_BOOTLOADER_REGION 0x72
374
375 #define FLASH_8021_FW_REGION 0x74
376 #define FLASH_8021_GOLDEN_FW_REGION 0x75
377 #define FLASH_8021_BOOTLOADER_REGION 0x72
378 #define FLASH_8021_VPD_REGION 0x81
379
380 #define FLASH_LAYOUT_TABLE_SIZE 4096
381
382 /*
383 * Per instance XIOCTL context defintions.
384 */
385 typedef struct ql_xioctl {
386 /* Driver context */
387 flash_desc_t fdesc;
388
389 /* Adapter I/O statistics */
390 uint32_t ControllerErrorCount;
391 uint32_t DeviceErrorCount;
392 uint32_t TotalLipResets;
393 uint32_t TotalInterrupts;
394
395 uint64_t BytesRequested;
396 uint64_t IosRequested;
397
398 /* SNIA stat counters */
399 int64_t IOInputRequests;
400 int64_t IOOutputRequests;
401 int64_t IOControlRequests;
402 int64_t IOOutputMByteCnt; /* # of mb's */
403 int64_t IOInputMByteCnt; /* # of mb's */
404
405 /* SNIA intermediate (less than 1mb) counters */
406 int64_t IOOutputByteCnt;
407 int64_t IOInputByteCnt;
408
409 /* Async event context */
410 void *aen_tracking_queue;
411 uint8_t aen_q_head;
412 uint8_t aen_q_tail;
413
414 uint32_t flags;
415 } ql_xioctl_t;
416
417 /*
418 * ql adapter flag defintions.
419 */
420 #define QL_AEN_TRACKING_ENABLE BIT_0
421 #define QL_MGMT_SERVER_LOGIN BIT_1
422
423 /*
424 * Global Data in ql_xioctl.c source file.
425 */
426
427 /*
428 * Global Function Prototypes in ql_xioctl.c source file.
429 */
430 int ql_alloc_xioctl_resource(ql_adapter_state_t *);
431 void ql_free_xioctl_resource(ql_adapter_state_t *);
432 int ql_xioctl(ql_adapter_state_t *, int, intptr_t, int, cred_t *, int *);
433 void ql_enqueue_aen(ql_adapter_state_t *, uint16_t, void *);
434 int ql_setup_fcache(ql_adapter_state_t *);
435 void ql_blink_led(ql_adapter_state_t *);
436 void ql_fcache_rel(ql_fcache_t *);
437 ql_fcache_t *ql_get_fbuf(ql_fcache_t *, uint32_t);
438 int ql_dump_fcode(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t);
439 int ql_pci_dump(ql_adapter_state_t *, uint32_t *, uint32_t, int);
440 int ql_load_fcode(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t);
441 int ql_set_loop_point(ql_adapter_state_t *, uint16_t);
442
443 #ifdef __cplusplus
444 }
445 #endif
446
447 #endif /* _QL_XIOCTL_H */