Print this page 
NEX-5717 import QLogic 16G FC drivers
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Split Close
Expand all
Collapse all
          --- old/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h
          +++ new/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_nx.h
↓ open down ↓ 12 lines elided ↑ open up ↑ 
  13   13   * When distributing Covered Code, include this CDDL HEADER in each
  14   14   * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15   15   * If applicable, add the following below this CDDL HEADER, with the
  16   16   * fields enclosed by brackets "[]" replaced with your own identifying
  17   17   * information: Portions Copyright [yyyy] [name of copyright owner]
  18   18   *
  19   19   * CDDL HEADER END
  20   20   */
  21   21  
  22   22  /*
  23      - * Copyright 2010 QLogic Corporation.  All rights reserved.
  24      - * Use is subject to license terms.
       23 + * Copyright (c) 2015 QLogic Corporation.  All rights reserved.
  25   24   */
  26   25  
  27   26  #ifndef _QL_NX_H
  28   27  #define _QL_NX_H
  29   28  
  30   29  /*
  31   30   * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
  32   31   *
  33   32   * ***********************************************************************
  34   33   * *                                                                    **
  35   34   * *                            NOTICE                                  **
  36      - * *            COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION              **
       35 + * *            COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION              **
  37   36   * *                    ALL RIGHTS RESERVED                             **
  38   37   * *                                                                    **
  39   38   * ***********************************************************************
  40   39   *
  41   40   */
  42   41  
  43   42  #ifdef  __cplusplus
  44   43  extern "C" {
  45   44  #endif
  46   45  
  47   46  #define NX_P3_A0        0x30
  48   47  #define NX_P3_A2        0x32
  49   48  #define NX_P3_B0        0x40
  50   49  #define NX_P3_B1        0x41
  51   50  #define NX_P3_B2        0x42
  52   51  #define NX_P3P_A0       0x50
  53   52  #define NX_P3P_B0       0x54
  54   53  
  55      -#define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
  56      -#define NX_IS_REVISION_P3PLUS(REVISION) (REVISION >= NX_P3P_A0)
       54 +#define NX_IS_REVISION_P3(REVISION)             (REVISION >= NX_P3_A0)
       55 +#define NX_IS_REVISION_P3PLUS(REVISION)         (REVISION >= NX_P3P_A0)
       56 +#define NX_IS_REVISION_P3PLUS_B0(REVISION)      (REVISION >= NX_P3P_B0)
  57   57  
  58   58  /*
  59   59   * Following are the states of the Phantom. Phantom will set them and
  60   60   * Host will read to check if the fields are correct.
  61   61   */
  62   62  #define PHAN_INITIALIZE_START           0xff00
  63   63  #define PHAN_INITIALIZE_FAILED          0xffff
  64   64  #define PHAN_INITIALIZE_COMPLETE        0xff01
  65   65  
  66   66  /* Host writes the following to notify that it has done the init-handshake */
↓ open down ↓ 8 lines elided ↑ open up ↑ 
  75   75  #define UNM_NIC_REG_2(X)        (NIC_CRB_BASE_2 + (X))
  76   76  
  77   77  #define CRB_CUT_THRU_PAGE_SIZE  (UNM_CAM_RAM(0x170))
  78   78  
  79   79  #define CRB_DEV_PARTITION_INFO  (UNM_CAM_RAM(0x14c))
  80   80  #define CRB_DEV_STATE           (UNM_CAM_RAM(0x140))
  81   81  #define CRB_DRV_IDC_VERSION     (UNM_CAM_RAM(0x174))
  82   82  #define CRB_DRV_ACTIVE          (UNM_CAM_RAM(0x138))
  83   83  #define CRB_DRV_STATE           (UNM_CAM_RAM(0x144))
  84   84  #define CRB_DRV_SCRATCH         (UNM_CAM_RAM(0x148))
  85      -#define CRB_FCOE_PORT_0_REQIN   (UNM_CAM_RAM(0x1b8))
  86      -#define CRB_FCOE_PORT_1_REQIN   (UNM_CAM_RAM(0x1bc))
       85 +#define CRB_PORT_0_REQIN        (UNM_CAM_RAM(0x1b8))
       86 +#define CRB_PORT_1_REQIN        (UNM_CAM_RAM(0x1bc))
  87   87  
  88   88  /* Every driver should use these Device State */
       89 +#define NX_DEV_POLL             0
  89   90  #define NX_DEV_COLD             1
  90      -#define NX_DEV_INITIALIZING     2
       91 +#define NX_DEV_INITIALIZING     2
  91   92  #define NX_DEV_READY            3
  92   93  #define NX_DEV_NEED_RESET       4
  93      -#define NX_DEV_NEED_QUIESCENT   5
       94 +#define NX_DEV_NEED_QUIESCENT   5
  94   95  #define NX_DEV_FAILED           6
  95   96  #define NX_DEV_QUIESCENT        7
       97 +#define NX_DEV_BADOBADO         0xbad0bad0
  96   98  
  97   99  #define NX_IDC_VERSION          0x1
  98  100  
  99  101  #define CRB_CMD_PRODUCER_OFFSET (UNM_NIC_REG(0x08))
 100  102  #define CRB_CMD_CONSUMER_OFFSET (UNM_NIC_REG(0x0c))
 101  103  #define CRB_PAUSE_ADDR_LO       (UNM_NIC_REG(0x10)) /* C0 EPG BUG  */
 102  104  #define CRB_PAUSE_ADDR_HI       (UNM_NIC_REG(0x14))
 103  105  #define NX_CDRP_CRB_OFFSET      (UNM_NIC_REG(0x18))
 104  106  #define NX_ARG1_CRB_OFFSET      (UNM_NIC_REG(0x1c))
 105  107  #define NX_ARG2_CRB_OFFSET      (UNM_NIC_REG(0x20))
↓ open down ↓ 657 lines elided ↑ open up ↑ 
 763  765  #define UNM_NIU_MAX_GBE_PORTS   4
 764  766  #define UNM_NIU_MAX_XG_PORTS    2
 765  767  #define MIN_CORE_CLK_SPEED      200
 766  768  #define MAX_CORE_CLK_SPEED      400
 767  769  #define ACCEPTABLE_CORE_CLK_RANGE(speed) ((speed >= MIN_CORE_CLK_SPEED) && \
 768  770          (speed <= MAX_CORE_CLK_SPEED))
 769  771  
 770  772  #define P2_TICKS_PER_SEC        2048
 771  773  #define P2_MIN_TICKS_PER_SEC    (P2_TICKS_PER_SEC - 10)
 772  774  #define P2_MAX_TICKS_PER_SEC    (P2_TICKS_PER_SEC + 10)
 773      -#define CHECK_TICKS_PER_SEC(ticks)      ((ticks >= P2_MIN_TICKS_PER_SEC) &&  \
      775 +#define CHECK_TICKS_PER_SEC(ticks)      ((ticks >= P2_MIN_TICKS_PER_SEC) && \
 774  776          (ticks <= P2_MAX_TICKS_PER_SEC))
 775  777  
 776  778  /* CAM RAM */
 777  779  #define UNM_CAM_RAM_BASE         (UNM_CRB_CAM + 0x02000)
 778  780  #define UNM_CAM_RAM(reg)         (UNM_CAM_RAM_BASE + (reg))
 779  781  
 780  782  #define UNM_PORT_MODE_NONE              0
 781  783  #define UNM_PORT_MODE_XG                1
 782  784  #define UNM_PORT_MODE_GB                2
 783  785  #define UNM_PORT_MODE_802_3_AP          3
 784  786  #define UNM_PORT_MODE_AUTO_NEG          4
 785  787  #define UNM_PORT_MODE_AUTO_NEG_1G       5
 786  788  #define UNM_PORT_MODE_AUTO_NEG_XG       6
 787  789  #define UNM_PORT_MODE_ADDR              (UNM_CAM_RAM(0x24))
 788  790  #define UNM_FW_PORT_MODE_ADDR           (UNM_CAM_RAM(0x28))
 789  791  #define UNM_WOL_PORT_MODE               (UNM_CAM_RAM(0x198))
 790  792  #define UNM_RAM_COLD_BOOT               (UNM_CAM_RAM(0x1fc))
 791  793  #define UNM_BUS_DEV_NO                  (UNM_CAM_RAM(0x114))
 792  794  
 793  795  #define NX_PEG_TUNE_MN_SPD_ZEROED       0x80000000
 794      -#define NX_BOOT_LOADER_MN_OTHER         0x100   /* other problem with DIMM */
      796 +#define NX_BOOT_LOADER_MN_OTHER         0x100   /* other problem with DIMM */
 795  797  #define NX_BOOT_LOADER_MN_NOT_DDR2      0x80    /* not a DDR2 DIMM */
 796  798  #define NX_BOOT_LOADER_MN_NO_ECC        0x40    /* ECC not supported */
 797  799  #define NX_BOOT_LOADER_MN_WRONG_CAS     0x20    /* CL 5 not supported */
 798  800  #define NX_BOOT_LOADER_MN_NOT_REG       0x10    /* not a registered DIMM */
 799  801  #define NX_BOOT_LOADER_MN_ISSUE         0xff00ffff
 800  802  #define NX_PEG_TUNE_MN_PRESENT          0x1
 801  803  #define NX_PEG_TUNE_CAPABILITY          (UNM_CAM_RAM(0x02c))
 802  804  
 803  805  #define UNM_ROM_LOCK_ID                 (UNM_CAM_RAM(0x100))
 804  806  #define UNM_I2C_ROM_LOCK_ID             (UNM_CAM_RAM(0x104))
↓ open down ↓ 145 lines elided ↑ open up ↑ 
 950  952  
 951  953  /*
 952  954   * The PCI VendorID and DeviceID for our board.
 953  955   */
 954  956  #define PCI_VENDOR_ID_NX8021            0x4040
 955  957  #define PCI_DEVICE_ID_NX8021_FC         0x0101
 956  958  
 957  959  /* ISP 3031 related declarations  */
 958  960  
 959  961  #define NX_MSIX_MEM_REGION_THRESHOLD    0x2000000
 960      -#define UNM_MSIX_TBL_SPACE              8192
      962 +#define UNM_MSIX_TBL_SPACE              8192
 961  963  #define UNM_PCI_REG_MSIX_TBL            0x44
 962  964  #define NX_PCI_MSIX_CONTROL             0x40
 963  965  
 964  966  typedef struct {
 965  967          uint32_t        valid;
 966  968          uint32_t        start_128M;
 967  969          uint32_t        end_128M;
 968  970          uint32_t        start_2M;
 969  971  } crb_128M_2M_sub_block_map_t;
 970  972
↓ open down ↓ 94 lines elided ↑ open up ↑ 
1065 1067   */
1066 1068  #define PCIX_INT_VECTOR_BIT_F0  0x0080
1067 1069  #define PCIX_INT_VECTOR_BIT_F1  0x0100
1068 1070  #define PCIX_INT_VECTOR_BIT_F2  0x0200
1069 1071  #define PCIX_INT_VECTOR_BIT_F3  0x0400
1070 1072  #define PCIX_INT_VECTOR_BIT_F4  0x0800
1071 1073  #define PCIX_INT_VECTOR_BIT_F5  0x1000
1072 1074  #define PCIX_INT_VECTOR_BIT_F6  0x2000
1073 1075  #define PCIX_INT_VECTOR_BIT_F7  0x4000
1074 1076  
1075      -#define NX_LEGACY_INTR_CONFIG                                   \
1076      -{                                                               \
1077      -        {                                                       \
1078      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F0,       \
1079      -                .tgt_status_reg = ISR_INT_TARGET_STATUS,        \
1080      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK,          \
1081      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(0) },     \
     1077 +#define NX_LEGACY_INTR_CONFIG                                   \
     1078 +{                                                               \
     1079 +        {                                                       \
     1080 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F0,       \
     1081 +                .tgt_status_reg = ISR_INT_TARGET_STATUS,        \
     1082 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK,          \
     1083 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(0) },     \
1082 1084                                                                  \
1083      -        {                                                       \
1084      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F1,       \
1085      -                .tgt_status_reg = ISR_INT_TARGET_STATUS_F1,     \
1086      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F1,       \
1087      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(1) },     \
     1085 +        {                                                       \
     1086 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F1,       \
     1087 +                .tgt_status_reg = ISR_INT_TARGET_STATUS_F1,     \
     1088 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F1,       \
     1089 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(1) },     \
1088 1090                                                                  \
1089      -        {                                                       \
1090      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F2,       \
1091      -                .tgt_status_reg = ISR_INT_TARGET_STATUS_F2,     \
1092      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F2,       \
1093      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(2) },     \
     1091 +        {                                                       \
     1092 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F2,       \
     1093 +                .tgt_status_reg = ISR_INT_TARGET_STATUS_F2,     \
     1094 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F2,       \
     1095 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(2) },     \
1094 1096                                                                  \
1095      -        {                                                       \
1096      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F3,       \
1097      -                .tgt_status_reg = ISR_INT_TARGET_STATUS_F3,     \
1098      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F3,       \
1099      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(3) },     \
1100      -                                                                \
1101      -        {                                                       \
1102      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F4,       \
1103      -                .tgt_status_reg = ISR_INT_TARGET_STATUS_F4,     \
1104      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F4,       \
1105      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(4) },     \
     1097 +        {                                                       \
     1098 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F3,       \
     1099 +                .tgt_status_reg = ISR_INT_TARGET_STATUS_F3,     \
     1100 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F3,       \
     1101 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(3) },     \
1106 1102                                                                  \
1107      -        {                                                       \
1108      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F5,       \
1109      -                .tgt_status_reg = ISR_INT_TARGET_STATUS_F5,     \
1110      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F5,       \
1111      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(5) },     \
     1103 +        {                                                       \
     1104 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F4,       \
     1105 +                .tgt_status_reg = ISR_INT_TARGET_STATUS_F4,     \
     1106 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F4,       \
     1107 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(4) },     \
1112 1108                                                                  \
1113      -        {                                                       \
1114      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F6,       \
1115      -                .tgt_status_reg = ISR_INT_TARGET_STATUS_F6,     \
1116      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F6,       \
1117      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(6) },     \
     1109 +        {                                                       \
     1110 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F5,       \
     1111 +                .tgt_status_reg = ISR_INT_TARGET_STATUS_F5,     \
     1112 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F5,       \
     1113 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(5) },     \
1118 1114                                                                  \
1119      -        {                                                       \
1120      -                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F7,       \
1121      -                .tgt_status_reg = ISR_INT_TARGET_STATUS_F7,     \
1122      -                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F7,       \
1123      -                .pci_int_reg    = ISR_MSI_INT_TRIGGER(7) },     \
     1115 +        {                                                       \
     1116 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F6,       \
     1117 +                .tgt_status_reg = ISR_INT_TARGET_STATUS_F6,     \
     1118 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F6,       \
     1119 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(6) },     \
     1120 +                                                                \
     1121 +        {                                                       \
     1122 +                .int_vec_bit    = PCIX_INT_VECTOR_BIT_F7,       \
     1123 +                .tgt_status_reg = ISR_INT_TARGET_STATUS_F7,     \
     1124 +                .tgt_mask_reg   = ISR_INT_TARGET_MASK_F7,       \
     1125 +                .pci_int_reg    = ISR_MSI_INT_TRIGGER(7) },     \
1124 1126  }
1125 1127  
1126 1128  #define BOOTLD_START            0x10000
1127 1129  #define IMAGE_START             0x43000
1128 1130  
1129 1131  /* Magic number to let user know flash is programmed */
1130 1132  #define UNM_BDINFO_MAGIC        0x12345678
1131 1133  #define FW_SIZE_OFFSET          0x3e840c
1132 1134  
1133 1135  #define PCI_CAP_ID_GEN          0x10
↓ open down ↓ 29 lines elided ↑ open up ↑ 
1163 1165  #define CRB_WINDOW_2M           (0x130060)
1164 1166  #define UNM_PCI_CAMQM_2M_END    (0x04800800UL)
1165 1167  #define CRB_HI(off)             ((crb_hub_agt[CRB_BLK(off)] << 20) | \
1166 1168          ((off) & 0xf0000))
1167 1169  #define UNM_PCI_CAMQM_2M_BASE   (0x000ff800UL)
1168 1170  #define CRB_INDIRECT_2M         (0x1e0000UL)
1169 1171  /* #define      ADDR_ERROR ((unsigned long ) 0xffffffff) */
1170 1172  
1171 1173  /* PCI Windowing for DDR regions.  */
1172 1174  #define QL_8021_ADDR_IN_RANGE(addr, low, high)  \
1173      -        (((addr) <= (high)) && ((addr) >= (low)))
     1175 +        (((addr) <= (high)) && ((int64_t)(addr) >= (low)))
1174 1176  
1175 1177  #define CRB_WIN_LOCK_TIMEOUT    100000000
1176 1178  #define ROM_LOCK_TIMEOUT        100
1177 1179  #define ROM_MAX_TIMEOUT         100
1178 1180  #define IDC_LOCK_TIMEOUT        100000000
1179 1181  
1180 1182  /*
1181      - * IDC parameters are defined in “user area” in the flash
     1183 + * IDC parameters are defined in "user area" in the flash
1182 1184   */
1183 1185  #define ROM_DEV_INIT_TIMEOUT            0x3e885c
1184 1186  #define ROM_DRV_RESET_ACK_TIMEOUT       0x3e8860
1185 1187  
     1188 +/* ****************************************************************** */
     1189 +/* ******************* NetXen MiniDump Defines ********************** */
     1190 +/* ****************************************************************** */
     1191 +
1186 1192  /*
     1193 + * Get MBC_GET_DUMP_TEMPLATE Command Options
     1194 + */
     1195 +#define GTO_TEMPLATE_SIZE       0
     1196 +#define GTO_TEMPLATE            1
     1197 +
     1198 +/*
     1199 + * Entry Type Defines
     1200 + */
     1201 +#define RDNOP            0
     1202 +#define RDCRB            1
     1203 +#define RDMUX            2
     1204 +#define QUEUE            3
     1205 +#define BOARD            4
     1206 +#define RDSRE            5
     1207 +#define RDOCM            6
     1208 +#define PREGS            7
     1209 +#define L1DTG            8
     1210 +#define L1ITG            9
     1211 +#define CACHE           10
     1212 +#define L1DAT           11
     1213 +#define L1INS           12
     1214 +#define RDSTK           13
     1215 +#define RDCON           14
     1216 +#define L2DTG           21
     1217 +#define L2ITG           22
     1218 +#define L2DAT           23
     1219 +#define L2INS           24
     1220 +#define RDOC3           25
     1221 +#define MEMBK           32
     1222 +#define RDROM           71
     1223 +#define RDMEM           72
     1224 +#define INFOR           81
     1225 +#define CNTRL           98
     1226 +#define TLHDR           99
     1227 +#define RDEND           255
     1228 +#define PRIMQ           103
     1229 +#define SQG2Q           104
     1230 +#define SQG3Q           105
     1231 +#define ISCSI_EVENT_LOG 201
     1232 +
     1233 +/*
     1234 + * Minidump Template Header
     1235 + * Parts of the template header can be modified by the driver.
     1236 + * These include the saved_state_array, capture_debug_level, driver_timestamp
     1237 + * The driver_info_wordX is used to add info about the drivers environment.
     1238 + * It is important that drivers add identication and system info in these
     1239 + * fields.
     1240 + */
     1241 +
     1242 +#define QL_DBG_STATE_ARRAY_LEN          16
     1243 +#define QL_DBG_CAP_SIZE_ARRAY_LEN       8
     1244 +#define QL_DBG_RSVD_ARRAY_LEN           8
     1245 +
     1246 +typedef struct md_template_hdr {
     1247 +        uint32_t        entry_type;
     1248 +        uint32_t        first_entry_offset;
     1249 +        uint32_t        size_of_template;
     1250 +        uint32_t        capture_debug_level;
     1251 +        uint32_t        num_of_entries;
     1252 +        uint32_t        version;
     1253 +        uint32_t        driver_timestamp;
     1254 +        uint32_t        checksum;
     1255 +        uint32_t        driver_capture_mask;
     1256 +        uint32_t        driver_info_word1;
     1257 +        uint32_t        driver_info_word2;
     1258 +        uint32_t        driver_info_word3;
     1259 +        uint32_t        saved_state_array[QL_DBG_STATE_ARRAY_LEN];
     1260 +        uint32_t        capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN];
     1261 +
     1262 +        /* markers_array used to capture some special locations on board */
     1263 +        uint32_t        markers_array[QL_DBG_RSVD_ARRAY_LEN];
     1264 +        uint32_t        num_of_free_entries;    /* For internal use */
     1265 +        uint32_t        free_entry_offset;      /* For internal use */
     1266 +        uint32_t        total_table_size;       /* For internal use */
     1267 +        uint32_t        bkup_table_offset;      /* For internal use */
     1268 +} md_template_hdr_t;
     1269 +
     1270 +/*
     1271 + * Driver Flags
     1272 + */
     1273 +#define QL_DBG_SKIPPED_FLAG     0x80    /* driver skipped this entry  */
     1274 +#define QL_DBG_SIZE_ERR_FLAG    0x40    /* entry siz vs capture siz mismatch */
     1275 +
     1276 +/*
     1277 + * Minidump Entry Header
     1278 + */
     1279 +typedef struct md_entry_hdr {
     1280 +        uint32_t        entry_type;
     1281 +        uint32_t        entry_size;
     1282 +        uint32_t        entry_capture_size;
     1283 +        union {
     1284 +                struct {
     1285 +#ifdef _BIG_ENDIAN
     1286 +                        uint8_t driver_flags;
     1287 +                        uint8_t driver_code;
     1288 +                        uint8_t entry_code;
     1289 +                        uint8_t entry_capture_mask;
     1290 +#else
     1291 +                        uint8_t entry_capture_mask;
     1292 +                        uint8_t entry_code;
     1293 +                        uint8_t driver_code;
     1294 +                        uint8_t driver_flags;
     1295 +#endif
     1296 +                } ecw;
     1297 +                uint32_t        entry_ctrl_word;
     1298 +        } a;
     1299 +} md_entry_hdr_t;
     1300 +
     1301 +/*
     1302 + * Minidump Entry Including Header
     1303 + */
     1304 +typedef struct md_entry {
     1305 +        md_entry_hdr_t  h;
     1306 +        uint32_t        entry_data00;
     1307 +        uint32_t        entry_data01;
     1308 +        uint32_t        entry_data02;
     1309 +        uint32_t        entry_data03;
     1310 +        uint32_t        entry_data04;
     1311 +        uint32_t        entry_data05;
     1312 +        uint32_t        entry_data06;
     1313 +        uint32_t        entry_data07;
     1314 +} md_entry_t;
     1315 +
     1316 +/*
     1317 + *  Minidump Read CRB Entry Header
     1318 + */
     1319 +typedef struct md_entry_rdcrb {
     1320 +        md_entry_hdr_t  h;
     1321 +        uint32_t        addr;
     1322 +        union {
     1323 +                struct {
     1324 +#ifdef _BIG_ENDIAN
     1325 +                        uint8_t rsvd_1[2];
     1326 +                        uint8_t rsvd_0;
     1327 +                        uint8_t addr_stride;
     1328 +#else
     1329 +                        uint8_t addr_stride;
     1330 +                        uint8_t rsvd_0;
     1331 +                        uint8_t rsvd_1[2];
     1332 +#endif
     1333 +                } ac;
     1334 +                uint32_t        addr_cntrl;
     1335 +        } a;
     1336 +        uint32_t        data_size;
     1337 +        uint32_t        op_count;
     1338 +        uint32_t        rsvd_2;
     1339 +        uint32_t        rsvd_3;
     1340 +        uint32_t        rsvd_4;
     1341 +        uint32_t        rsvd_5;
     1342 +} md_entry_rdcrb_t;
     1343 +
     1344 +/*
     1345 + * Minidump Cache Entry Header
     1346 + */
     1347 +typedef struct ql_md_entry_cache {
     1348 +        md_entry_hdr_t  h;
     1349 +        uint32_t        tag_reg_addr;
     1350 +        union {
     1351 +                struct {
     1352 +#ifdef _BIG_ENDIAN
     1353 +                        uint8_t init_tag_value[2];
     1354 +                        uint8_t tag_value_stride[2];
     1355 +#else
     1356 +                        uint8_t tag_value_stride[2];
     1357 +                        uint8_t init_tag_value[2];
     1358 +#endif
     1359 +                } sac;
     1360 +                uint32_t        select_addr_cntrl;
     1361 +        } a;
     1362 +        uint32_t        data_size;
     1363 +        uint32_t        op_count;
     1364 +        uint32_t        control_addr;
     1365 +        union {
     1366 +                struct {
     1367 +#ifdef _BIG_ENDIAN
     1368 +                        uint8_t poll_wait;
     1369 +                        uint8_t poll_mask;
     1370 +                        uint8_t write_value[2];
     1371 +#else
     1372 +                        uint8_t write_value[2];
     1373 +                        uint8_t poll_mask;
     1374 +                        uint8_t poll_wait;
     1375 +#endif
     1376 +                } cv;
     1377 +                uint32_t        control_value;
     1378 +        } b;
     1379 +        uint32_t        read_addr;
     1380 +        union {
     1381 +                struct {
     1382 +#ifdef _BIG_ENDIAN
     1383 +                        uint8_t rsvd_1[2];
     1384 +                        uint8_t read_addr_cnt;
     1385 +                        uint8_t read_addr_stride;
     1386 +#else
     1387 +                        uint8_t read_addr_stride;
     1388 +                        uint8_t read_addr_cnt;
     1389 +                        uint8_t rsvd_1[2];
     1390 +#endif
     1391 +                } rac;
     1392 +                uint32_t        read_addr_cntrl;
     1393 +        } c;
     1394 +} md_entry_cache_t;
     1395 +
     1396 +/*
     1397 + * Minidump Read OCM Entry Header
     1398 + */
     1399 +typedef struct md_entry_rdocm {
     1400 +        md_entry_hdr_t  h;
     1401 +        uint32_t        rsvd_0;
     1402 +        uint32_t        rsvd_1;
     1403 +        uint32_t        data_size;
     1404 +        uint32_t        op_count;
     1405 +        uint32_t        rsvd_2;
     1406 +        uint32_t        rsvd_3;
     1407 +        uint32_t        read_addr;
     1408 +        uint32_t        read_addr_stride;
     1409 +} md_entry_rdocm_t;
     1410 +
     1411 +/*
     1412 + * Minidump Read MEM Entry Header
     1413 + */
     1414 +typedef struct md_entry_rdmem {
     1415 +        md_entry_hdr_t  h;
     1416 +        uint32_t        rsvd_0[6];
     1417 +        uint32_t        read_addr;
     1418 +        uint32_t        read_data_size;
     1419 +} md_entry_rdmem_t;
     1420 +/*
     1421 + * Minidump MIU AGENT ADDRESSES.
     1422 + */
     1423 +#define MD_TA_CTL_ENABLE                0x2
     1424 +#define MD_TA_CTL_START                 0x1
     1425 +#define MD_TA_CTL_BUSY                  0x8
     1426 +#define MD_TA_CTL_CHECK                 1000
     1427 +#define MD_MIU_TEST_AGT_CTRL            0x41000090
     1428 +#define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
     1429 +#define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
     1430 +#define MD_MIU_TEST_AGT_RDDATA_0_31     0x410000A8
     1431 +#define MD_MIU_TEST_AGT_RDDATA_32_63    0x410000AC
     1432 +#define MD_MIU_TEST_AGT_RDDATA_64_95    0x410000B8
     1433 +#define MD_MIU_TEST_AGT_RDDATA_96_127   0x410000BC
     1434 +#define MD_MIU_TEST_AGT_WRDATA_0_31     0x410000A0
     1435 +#define MD_MIU_TEST_AGT_WRDATA_32_63    0x410000A4
     1436 +#define MD_MIU_TEST_AGT_WRDATA_64_95    0x410000B0
     1437 +#define MD_MIU_TEST_AGT_WRDATA_96_127   0x410000B4
     1438 +
     1439 +/*
     1440 + * Minidump Read ROM Entry Header
     1441 + */
     1442 +typedef struct md_entry_rdrom {
     1443 +        md_entry_hdr_t  h;
     1444 +        uint32_t        rsvd_0[6];
     1445 +        uint32_t        read_addr;
     1446 +        uint32_t        read_data_size;
     1447 +} md_entry_rdrom_t;
     1448 +/*
     1449 + *  Minidump ROM Read Address
     1450 + */
     1451 +#define MD_DIRECT_ROM_WINDOW    0x42110030
     1452 +#define MD_DIRECT_ROM_READ_BASE 0x42150000
     1453 +
     1454 +/*
     1455 + * Minidump Read MUX Entry Header
     1456 + */
     1457 +typedef struct md_entry_mux {
     1458 +        md_entry_hdr_t  h;
     1459 +        uint32_t        select_addr;
     1460 +        union {
     1461 +                struct {
     1462 +                        uint32_t        rsvd_0;
     1463 +                } sac;
     1464 +                uint32_t        select_addr_cntrl;
     1465 +        } a;
     1466 +        uint32_t        data_size;
     1467 +        uint32_t        op_count;
     1468 +        uint32_t        select_value;
     1469 +        uint32_t        select_value_stride;
     1470 +        uint32_t        read_addr;
     1471 +        uint32_t        rsvd_1;
     1472 +} md_entry_mux_t;
     1473 +
     1474 +/*
     1475 + * Minidump Read QUEUE Entry Header
     1476 + */
     1477 +typedef struct md_entry_queue {
     1478 +        md_entry_hdr_t  h;
     1479 +        uint32_t        select_addr;
     1480 +        union {
     1481 +                struct {
     1482 +#ifdef _BIG_ENDIAN
     1483 +                        uint8_t rsvd_0[2];
     1484 +                        uint8_t queue_id_stride[2];
     1485 +#else
     1486 +                        uint8_t queue_id_stride[2];
     1487 +                        uint8_t rsvd_0[2];
     1488 +#endif
     1489 +                } sac;
     1490 +                uint32_t        select_addr_cntrl;
     1491 +        } a;
     1492 +        uint32_t        data_size;
     1493 +        uint32_t        op_count;
     1494 +        uint32_t        rsvd_1;
     1495 +        uint32_t        rsvd_2;
     1496 +        uint32_t        read_addr;
     1497 +        union {
     1498 +                struct {
     1499 +#ifdef _BIG_ENDIAN
     1500 +                        uint8_t rsvd_3[2];
     1501 +                        uint8_t read_addr_cnt;
     1502 +                        uint8_t read_addr_stride;
     1503 +#else
     1504 +                        uint8_t read_addr_stride;
     1505 +                        uint8_t read_addr_cnt;
     1506 +                        uint8_t rsvd_3[2];
     1507 +#endif
     1508 +                } rac;
     1509 +                uint32_t        read_addr_cntrl;
     1510 +        } b;
     1511 +} md_entry_queue_t;
     1512 +
     1513 +/*
     1514 + * Minidump Control Entry Header
     1515 + */
     1516 +typedef struct md_entry_cntrl {
     1517 +        md_entry_hdr_t  h;
     1518 +        uint32_t        addr;
     1519 +        union {
     1520 +                struct {
     1521 +#ifdef _BIG_ENDIAN
     1522 +                        uint8_t poll_timeout[2];
     1523 +                        uint8_t state_index_a;
     1524 +                        uint8_t addr_stride;
     1525 +#else
     1526 +                        uint8_t addr_stride;
     1527 +                        uint8_t state_index_a;
     1528 +                        uint8_t poll_timeout[2];
     1529 +#endif
     1530 +                } ac;
     1531 +                uint32_t        addr_cntrl;
     1532 +        } a;
     1533 +        uint32_t        data_size;
     1534 +        uint32_t        op_count;
     1535 +        union {
     1536 +                struct {
     1537 +#ifdef _BIG_ENDIAN
     1538 +                        uint8_t shr;
     1539 +                        uint8_t shl;
     1540 +                        uint8_t state_index_v;
     1541 +                        uint8_t opcode;
     1542 +#else
     1543 +                        uint8_t opcode;
     1544 +                        uint8_t state_index_v;
     1545 +                        uint8_t shl;
     1546 +                        uint8_t shr;
     1547 +#endif
     1548 +                } cv;
     1549 +                uint32_t        control_value;
     1550 +        } b;
     1551 +        uint32_t        value_1;
     1552 +        uint32_t        value_2;
     1553 +        uint32_t        value_3;
     1554 +} md_entry_cntrl_t;
     1555 +
     1556 +/*
     1557 + * Opcodes for Control Entries.
     1558 + * These Flags are bit fields.
     1559 + */
     1560 +#define QL_DBG_OPCODE_WR        0x01
     1561 +#define QL_DBG_OPCODE_RW        0x02
     1562 +#define QL_DBG_OPCODE_AND       0x04
     1563 +#define QL_DBG_OPCODE_OR        0x08
     1564 +#define QL_DBG_OPCODE_POLL      0x10
     1565 +#define QL_DBG_OPCODE_RDSTATE   0x20
     1566 +#define QL_DBG_OPCODE_WRSTATE   0x40
     1567 +#define QL_DBG_OPCODE_MDSTATE   0x80
     1568 +
     1569 +/*
1187 1570   * Global Data in ql_nx.c source file.
1188 1571   */
1189 1572  
1190 1573  /*
1191 1574   * Global Function Prototypes in ql_nx.c source file.
1192 1575   */
     1576 +void ql_8021_wr_32(ql_adapter_state_t *, uint64_t, uint32_t);
     1577 +void ql_8021_rd_32(ql_adapter_state_t *, uint64_t, uint32_t *);
1193 1578  void ql_8021_reset_chip(ql_adapter_state_t *);
1194      -int ql_8021_load_risc(ql_adapter_state_t *);
     1579 +int ql_8021_fw_reload(ql_adapter_state_t *);
1195 1580  void ql_8021_clr_hw_intr(ql_adapter_state_t *);
1196 1581  void ql_8021_clr_fw_intr(ql_adapter_state_t *);
1197 1582  void ql_8021_enable_intrs(ql_adapter_state_t *);
1198 1583  void ql_8021_disable_intrs(ql_adapter_state_t *);
1199 1584  void ql_8021_update_crb_int_ptr(ql_adapter_state_t *);
1200 1585  int ql_8021_rom_read(ql_adapter_state_t *, uint32_t, uint32_t *);
1201 1586  int ql_8021_rom_write(ql_adapter_state_t *, uint32_t, uint32_t);
1202 1587  int ql_8021_rom_erase(ql_adapter_state_t *, uint32_t);
1203 1588  int ql_8021_rom_wrsr(ql_adapter_state_t *, uint32_t);
1204 1589  void ql_8021_set_drv_active(ql_adapter_state_t *);
1205 1590  void ql_8021_clr_drv_active(ql_adapter_state_t *);
1206      -uint32_t ql_8021_idc_handler(ql_adapter_state_t *);
     1591 +int ql_8021_idc_handler(ql_adapter_state_t *, uint32_t);
     1592 +void ql_8021_wr_req_in(ql_adapter_state_t *, uint32_t);
     1593 +void ql_8021_idc_poll(ql_adapter_state_t *);
     1594 +int ql_8021_reset_fw(ql_adapter_state_t *);
     1595 +int ql_8021_fw_chk(ql_adapter_state_t *);
     1596 +int ql_8021_get_md_template(ql_adapter_state_t *);
1207 1597  
1208 1598  #ifdef __cplusplus
1209 1599  }
1210 1600  #endif
1211 1601  
1212 1602  #endif /* _QL_NX_H */
    
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX