3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2010 QLogic Corporation. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _QL_NX_H
28 #define _QL_NX_H
29
30 /*
31 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
32 *
33 * ***********************************************************************
34 * * **
35 * * NOTICE **
36 * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
37 * * ALL RIGHTS RESERVED **
38 * * **
39 * ***********************************************************************
40 *
41 */
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 #define NX_P3_A0 0x30
48 #define NX_P3_A2 0x32
49 #define NX_P3_B0 0x40
50 #define NX_P3_B1 0x41
51 #define NX_P3_B2 0x42
52 #define NX_P3P_A0 0x50
53 #define NX_P3P_B0 0x54
54
55 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
56 #define NX_IS_REVISION_P3PLUS(REVISION) (REVISION >= NX_P3P_A0)
57
58 /*
59 * Following are the states of the Phantom. Phantom will set them and
60 * Host will read to check if the fields are correct.
61 */
62 #define PHAN_INITIALIZE_START 0xff00
63 #define PHAN_INITIALIZE_FAILED 0xffff
64 #define PHAN_INITIALIZE_COMPLETE 0xff01
65
66 /* Host writes the following to notify that it has done the init-handshake */
67 #define PHAN_INITIALIZE_ACK 0xf00f
68 #define PHAN_PEG_RCV_INITIALIZED 0xff01
69 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
70
71 /* CRB_RELATED */
72 #define NIC_CRB_BASE (UNM_CAM_RAM(0x200))
73 #define NIC_CRB_BASE_2 (UNM_CAM_RAM(0x700))
74 #define UNM_NIC_REG(X) (NIC_CRB_BASE + (X))
75 #define UNM_NIC_REG_2(X) (NIC_CRB_BASE_2 + (X))
76
77 #define CRB_CUT_THRU_PAGE_SIZE (UNM_CAM_RAM(0x170))
78
79 #define CRB_DEV_PARTITION_INFO (UNM_CAM_RAM(0x14c))
80 #define CRB_DEV_STATE (UNM_CAM_RAM(0x140))
81 #define CRB_DRV_IDC_VERSION (UNM_CAM_RAM(0x174))
82 #define CRB_DRV_ACTIVE (UNM_CAM_RAM(0x138))
83 #define CRB_DRV_STATE (UNM_CAM_RAM(0x144))
84 #define CRB_DRV_SCRATCH (UNM_CAM_RAM(0x148))
85 #define CRB_FCOE_PORT_0_REQIN (UNM_CAM_RAM(0x1b8))
86 #define CRB_FCOE_PORT_1_REQIN (UNM_CAM_RAM(0x1bc))
87
88 /* Every driver should use these Device State */
89 #define NX_DEV_COLD 1
90 #define NX_DEV_INITIALIZING 2
91 #define NX_DEV_READY 3
92 #define NX_DEV_NEED_RESET 4
93 #define NX_DEV_NEED_QUIESCENT 5
94 #define NX_DEV_FAILED 6
95 #define NX_DEV_QUIESCENT 7
96
97 #define NX_IDC_VERSION 0x1
98
99 #define CRB_CMD_PRODUCER_OFFSET (UNM_NIC_REG(0x08))
100 #define CRB_CMD_CONSUMER_OFFSET (UNM_NIC_REG(0x0c))
101 #define CRB_PAUSE_ADDR_LO (UNM_NIC_REG(0x10)) /* C0 EPG BUG */
102 #define CRB_PAUSE_ADDR_HI (UNM_NIC_REG(0x14))
103 #define NX_CDRP_CRB_OFFSET (UNM_NIC_REG(0x18))
104 #define NX_ARG1_CRB_OFFSET (UNM_NIC_REG(0x1c))
105 #define NX_ARG2_CRB_OFFSET (UNM_NIC_REG(0x20))
106 #define NX_ARG3_CRB_OFFSET (UNM_NIC_REG(0x24))
107 #define NX_SIGN_CRB_OFFSET (UNM_NIC_REG(0x28))
108 #define CRB_CMDPEG_CMDRING (UNM_NIC_REG(0x38))
109 #define CRB_HOST_DUMMY_BUF_ADDR_HI (UNM_NIC_REG(0x3c))
110 #define CRB_HOST_DUMMY_BUF_ADDR_LO (UNM_NIC_REG(0x40))
111 #define CRB_CMDPEG_STATE (UNM_NIC_REG(0x50))
112 #define BOOT_LOADER_DIMM_STATUS (UNM_NIC_REG(0x54))
113 #define CRB_GLOBAL_INT_COAL (UNM_NIC_REG(0x64)) /* intrt coalescing */
114 #define CRB_INT_COAL_MODE (UNM_NIC_REG(0x68))
115 #define CRB_MAX_RCV_BUFS (UNM_NIC_REG(0x6c))
1153 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
1154 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
1155
1156 #define UNM_BOARDTYPE 0x4008
1157 #define UNM_BOARDNUM 0x400c
1158 #define UNM_CHIPNUM 0x4010
1159
1160 /* CRB window related */
1161 #define CRB_BLK(off) ((off >> 20) & 0x3f)
1162 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
1163 #define CRB_WINDOW_2M (0x130060)
1164 #define UNM_PCI_CAMQM_2M_END (0x04800800UL)
1165 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | \
1166 ((off) & 0xf0000))
1167 #define UNM_PCI_CAMQM_2M_BASE (0x000ff800UL)
1168 #define CRB_INDIRECT_2M (0x1e0000UL)
1169 /* #define ADDR_ERROR ((unsigned long ) 0xffffffff) */
1170
1171 /* PCI Windowing for DDR regions. */
1172 #define QL_8021_ADDR_IN_RANGE(addr, low, high) \
1173 (((addr) <= (high)) && ((addr) >= (low)))
1174
1175 #define CRB_WIN_LOCK_TIMEOUT 100000000
1176 #define ROM_LOCK_TIMEOUT 100
1177 #define ROM_MAX_TIMEOUT 100
1178 #define IDC_LOCK_TIMEOUT 100000000
1179
1180 /*
1181 * IDC parameters are defined in “user area” in the flash
1182 */
1183 #define ROM_DEV_INIT_TIMEOUT 0x3e885c
1184 #define ROM_DRV_RESET_ACK_TIMEOUT 0x3e8860
1185
1186 /*
1187 * Global Data in ql_nx.c source file.
1188 */
1189
1190 /*
1191 * Global Function Prototypes in ql_nx.c source file.
1192 */
1193 void ql_8021_reset_chip(ql_adapter_state_t *);
1194 int ql_8021_load_risc(ql_adapter_state_t *);
1195 void ql_8021_clr_hw_intr(ql_adapter_state_t *);
1196 void ql_8021_clr_fw_intr(ql_adapter_state_t *);
1197 void ql_8021_enable_intrs(ql_adapter_state_t *);
1198 void ql_8021_disable_intrs(ql_adapter_state_t *);
1199 void ql_8021_update_crb_int_ptr(ql_adapter_state_t *);
1200 int ql_8021_rom_read(ql_adapter_state_t *, uint32_t, uint32_t *);
1201 int ql_8021_rom_write(ql_adapter_state_t *, uint32_t, uint32_t);
1202 int ql_8021_rom_erase(ql_adapter_state_t *, uint32_t);
1203 int ql_8021_rom_wrsr(ql_adapter_state_t *, uint32_t);
1204 void ql_8021_set_drv_active(ql_adapter_state_t *);
1205 void ql_8021_clr_drv_active(ql_adapter_state_t *);
1206 uint32_t ql_8021_idc_handler(ql_adapter_state_t *);
1207
1208 #ifdef __cplusplus
1209 }
1210 #endif
1211
1212 #endif /* _QL_NX_H */
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2015 QLogic Corporation. All rights reserved.
24 */
25
26 #ifndef _QL_NX_H
27 #define _QL_NX_H
28
29 /*
30 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
31 *
32 * ***********************************************************************
33 * * **
34 * * NOTICE **
35 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
36 * * ALL RIGHTS RESERVED **
37 * * **
38 * ***********************************************************************
39 *
40 */
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #define NX_P3_A0 0x30
47 #define NX_P3_A2 0x32
48 #define NX_P3_B0 0x40
49 #define NX_P3_B1 0x41
50 #define NX_P3_B2 0x42
51 #define NX_P3P_A0 0x50
52 #define NX_P3P_B0 0x54
53
54 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
55 #define NX_IS_REVISION_P3PLUS(REVISION) (REVISION >= NX_P3P_A0)
56 #define NX_IS_REVISION_P3PLUS_B0(REVISION) (REVISION >= NX_P3P_B0)
57
58 /*
59 * Following are the states of the Phantom. Phantom will set them and
60 * Host will read to check if the fields are correct.
61 */
62 #define PHAN_INITIALIZE_START 0xff00
63 #define PHAN_INITIALIZE_FAILED 0xffff
64 #define PHAN_INITIALIZE_COMPLETE 0xff01
65
66 /* Host writes the following to notify that it has done the init-handshake */
67 #define PHAN_INITIALIZE_ACK 0xf00f
68 #define PHAN_PEG_RCV_INITIALIZED 0xff01
69 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
70
71 /* CRB_RELATED */
72 #define NIC_CRB_BASE (UNM_CAM_RAM(0x200))
73 #define NIC_CRB_BASE_2 (UNM_CAM_RAM(0x700))
74 #define UNM_NIC_REG(X) (NIC_CRB_BASE + (X))
75 #define UNM_NIC_REG_2(X) (NIC_CRB_BASE_2 + (X))
76
77 #define CRB_CUT_THRU_PAGE_SIZE (UNM_CAM_RAM(0x170))
78
79 #define CRB_DEV_PARTITION_INFO (UNM_CAM_RAM(0x14c))
80 #define CRB_DEV_STATE (UNM_CAM_RAM(0x140))
81 #define CRB_DRV_IDC_VERSION (UNM_CAM_RAM(0x174))
82 #define CRB_DRV_ACTIVE (UNM_CAM_RAM(0x138))
83 #define CRB_DRV_STATE (UNM_CAM_RAM(0x144))
84 #define CRB_DRV_SCRATCH (UNM_CAM_RAM(0x148))
85 #define CRB_PORT_0_REQIN (UNM_CAM_RAM(0x1b8))
86 #define CRB_PORT_1_REQIN (UNM_CAM_RAM(0x1bc))
87
88 /* Every driver should use these Device State */
89 #define NX_DEV_POLL 0
90 #define NX_DEV_COLD 1
91 #define NX_DEV_INITIALIZING 2
92 #define NX_DEV_READY 3
93 #define NX_DEV_NEED_RESET 4
94 #define NX_DEV_NEED_QUIESCENT 5
95 #define NX_DEV_FAILED 6
96 #define NX_DEV_QUIESCENT 7
97 #define NX_DEV_BADOBADO 0xbad0bad0
98
99 #define NX_IDC_VERSION 0x1
100
101 #define CRB_CMD_PRODUCER_OFFSET (UNM_NIC_REG(0x08))
102 #define CRB_CMD_CONSUMER_OFFSET (UNM_NIC_REG(0x0c))
103 #define CRB_PAUSE_ADDR_LO (UNM_NIC_REG(0x10)) /* C0 EPG BUG */
104 #define CRB_PAUSE_ADDR_HI (UNM_NIC_REG(0x14))
105 #define NX_CDRP_CRB_OFFSET (UNM_NIC_REG(0x18))
106 #define NX_ARG1_CRB_OFFSET (UNM_NIC_REG(0x1c))
107 #define NX_ARG2_CRB_OFFSET (UNM_NIC_REG(0x20))
108 #define NX_ARG3_CRB_OFFSET (UNM_NIC_REG(0x24))
109 #define NX_SIGN_CRB_OFFSET (UNM_NIC_REG(0x28))
110 #define CRB_CMDPEG_CMDRING (UNM_NIC_REG(0x38))
111 #define CRB_HOST_DUMMY_BUF_ADDR_HI (UNM_NIC_REG(0x3c))
112 #define CRB_HOST_DUMMY_BUF_ADDR_LO (UNM_NIC_REG(0x40))
113 #define CRB_CMDPEG_STATE (UNM_NIC_REG(0x50))
114 #define BOOT_LOADER_DIMM_STATUS (UNM_NIC_REG(0x54))
115 #define CRB_GLOBAL_INT_COAL (UNM_NIC_REG(0x64)) /* intrt coalescing */
116 #define CRB_INT_COAL_MODE (UNM_NIC_REG(0x68))
117 #define CRB_MAX_RCV_BUFS (UNM_NIC_REG(0x6c))
1155 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
1156 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
1157
1158 #define UNM_BOARDTYPE 0x4008
1159 #define UNM_BOARDNUM 0x400c
1160 #define UNM_CHIPNUM 0x4010
1161
1162 /* CRB window related */
1163 #define CRB_BLK(off) ((off >> 20) & 0x3f)
1164 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
1165 #define CRB_WINDOW_2M (0x130060)
1166 #define UNM_PCI_CAMQM_2M_END (0x04800800UL)
1167 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | \
1168 ((off) & 0xf0000))
1169 #define UNM_PCI_CAMQM_2M_BASE (0x000ff800UL)
1170 #define CRB_INDIRECT_2M (0x1e0000UL)
1171 /* #define ADDR_ERROR ((unsigned long ) 0xffffffff) */
1172
1173 /* PCI Windowing for DDR regions. */
1174 #define QL_8021_ADDR_IN_RANGE(addr, low, high) \
1175 (((addr) <= (high)) && ((int64_t)(addr) >= (low)))
1176
1177 #define CRB_WIN_LOCK_TIMEOUT 100000000
1178 #define ROM_LOCK_TIMEOUT 100
1179 #define ROM_MAX_TIMEOUT 100
1180 #define IDC_LOCK_TIMEOUT 100000000
1181
1182 /*
1183 * IDC parameters are defined in "user area" in the flash
1184 */
1185 #define ROM_DEV_INIT_TIMEOUT 0x3e885c
1186 #define ROM_DRV_RESET_ACK_TIMEOUT 0x3e8860
1187
1188 /* ****************************************************************** */
1189 /* ******************* NetXen MiniDump Defines ********************** */
1190 /* ****************************************************************** */
1191
1192 /*
1193 * Get MBC_GET_DUMP_TEMPLATE Command Options
1194 */
1195 #define GTO_TEMPLATE_SIZE 0
1196 #define GTO_TEMPLATE 1
1197
1198 /*
1199 * Entry Type Defines
1200 */
1201 #define RDNOP 0
1202 #define RDCRB 1
1203 #define RDMUX 2
1204 #define QUEUE 3
1205 #define BOARD 4
1206 #define RDSRE 5
1207 #define RDOCM 6
1208 #define PREGS 7
1209 #define L1DTG 8
1210 #define L1ITG 9
1211 #define CACHE 10
1212 #define L1DAT 11
1213 #define L1INS 12
1214 #define RDSTK 13
1215 #define RDCON 14
1216 #define L2DTG 21
1217 #define L2ITG 22
1218 #define L2DAT 23
1219 #define L2INS 24
1220 #define RDOC3 25
1221 #define MEMBK 32
1222 #define RDROM 71
1223 #define RDMEM 72
1224 #define INFOR 81
1225 #define CNTRL 98
1226 #define TLHDR 99
1227 #define RDEND 255
1228 #define PRIMQ 103
1229 #define SQG2Q 104
1230 #define SQG3Q 105
1231 #define ISCSI_EVENT_LOG 201
1232
1233 /*
1234 * Minidump Template Header
1235 * Parts of the template header can be modified by the driver.
1236 * These include the saved_state_array, capture_debug_level, driver_timestamp
1237 * The driver_info_wordX is used to add info about the drivers environment.
1238 * It is important that drivers add identication and system info in these
1239 * fields.
1240 */
1241
1242 #define QL_DBG_STATE_ARRAY_LEN 16
1243 #define QL_DBG_CAP_SIZE_ARRAY_LEN 8
1244 #define QL_DBG_RSVD_ARRAY_LEN 8
1245
1246 typedef struct md_template_hdr {
1247 uint32_t entry_type;
1248 uint32_t first_entry_offset;
1249 uint32_t size_of_template;
1250 uint32_t capture_debug_level;
1251 uint32_t num_of_entries;
1252 uint32_t version;
1253 uint32_t driver_timestamp;
1254 uint32_t checksum;
1255 uint32_t driver_capture_mask;
1256 uint32_t driver_info_word1;
1257 uint32_t driver_info_word2;
1258 uint32_t driver_info_word3;
1259 uint32_t saved_state_array[QL_DBG_STATE_ARRAY_LEN];
1260 uint32_t capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN];
1261
1262 /* markers_array used to capture some special locations on board */
1263 uint32_t markers_array[QL_DBG_RSVD_ARRAY_LEN];
1264 uint32_t num_of_free_entries; /* For internal use */
1265 uint32_t free_entry_offset; /* For internal use */
1266 uint32_t total_table_size; /* For internal use */
1267 uint32_t bkup_table_offset; /* For internal use */
1268 } md_template_hdr_t;
1269
1270 /*
1271 * Driver Flags
1272 */
1273 #define QL_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
1274 #define QL_DBG_SIZE_ERR_FLAG 0x40 /* entry siz vs capture siz mismatch */
1275
1276 /*
1277 * Minidump Entry Header
1278 */
1279 typedef struct md_entry_hdr {
1280 uint32_t entry_type;
1281 uint32_t entry_size;
1282 uint32_t entry_capture_size;
1283 union {
1284 struct {
1285 #ifdef _BIG_ENDIAN
1286 uint8_t driver_flags;
1287 uint8_t driver_code;
1288 uint8_t entry_code;
1289 uint8_t entry_capture_mask;
1290 #else
1291 uint8_t entry_capture_mask;
1292 uint8_t entry_code;
1293 uint8_t driver_code;
1294 uint8_t driver_flags;
1295 #endif
1296 } ecw;
1297 uint32_t entry_ctrl_word;
1298 } a;
1299 } md_entry_hdr_t;
1300
1301 /*
1302 * Minidump Entry Including Header
1303 */
1304 typedef struct md_entry {
1305 md_entry_hdr_t h;
1306 uint32_t entry_data00;
1307 uint32_t entry_data01;
1308 uint32_t entry_data02;
1309 uint32_t entry_data03;
1310 uint32_t entry_data04;
1311 uint32_t entry_data05;
1312 uint32_t entry_data06;
1313 uint32_t entry_data07;
1314 } md_entry_t;
1315
1316 /*
1317 * Minidump Read CRB Entry Header
1318 */
1319 typedef struct md_entry_rdcrb {
1320 md_entry_hdr_t h;
1321 uint32_t addr;
1322 union {
1323 struct {
1324 #ifdef _BIG_ENDIAN
1325 uint8_t rsvd_1[2];
1326 uint8_t rsvd_0;
1327 uint8_t addr_stride;
1328 #else
1329 uint8_t addr_stride;
1330 uint8_t rsvd_0;
1331 uint8_t rsvd_1[2];
1332 #endif
1333 } ac;
1334 uint32_t addr_cntrl;
1335 } a;
1336 uint32_t data_size;
1337 uint32_t op_count;
1338 uint32_t rsvd_2;
1339 uint32_t rsvd_3;
1340 uint32_t rsvd_4;
1341 uint32_t rsvd_5;
1342 } md_entry_rdcrb_t;
1343
1344 /*
1345 * Minidump Cache Entry Header
1346 */
1347 typedef struct ql_md_entry_cache {
1348 md_entry_hdr_t h;
1349 uint32_t tag_reg_addr;
1350 union {
1351 struct {
1352 #ifdef _BIG_ENDIAN
1353 uint8_t init_tag_value[2];
1354 uint8_t tag_value_stride[2];
1355 #else
1356 uint8_t tag_value_stride[2];
1357 uint8_t init_tag_value[2];
1358 #endif
1359 } sac;
1360 uint32_t select_addr_cntrl;
1361 } a;
1362 uint32_t data_size;
1363 uint32_t op_count;
1364 uint32_t control_addr;
1365 union {
1366 struct {
1367 #ifdef _BIG_ENDIAN
1368 uint8_t poll_wait;
1369 uint8_t poll_mask;
1370 uint8_t write_value[2];
1371 #else
1372 uint8_t write_value[2];
1373 uint8_t poll_mask;
1374 uint8_t poll_wait;
1375 #endif
1376 } cv;
1377 uint32_t control_value;
1378 } b;
1379 uint32_t read_addr;
1380 union {
1381 struct {
1382 #ifdef _BIG_ENDIAN
1383 uint8_t rsvd_1[2];
1384 uint8_t read_addr_cnt;
1385 uint8_t read_addr_stride;
1386 #else
1387 uint8_t read_addr_stride;
1388 uint8_t read_addr_cnt;
1389 uint8_t rsvd_1[2];
1390 #endif
1391 } rac;
1392 uint32_t read_addr_cntrl;
1393 } c;
1394 } md_entry_cache_t;
1395
1396 /*
1397 * Minidump Read OCM Entry Header
1398 */
1399 typedef struct md_entry_rdocm {
1400 md_entry_hdr_t h;
1401 uint32_t rsvd_0;
1402 uint32_t rsvd_1;
1403 uint32_t data_size;
1404 uint32_t op_count;
1405 uint32_t rsvd_2;
1406 uint32_t rsvd_3;
1407 uint32_t read_addr;
1408 uint32_t read_addr_stride;
1409 } md_entry_rdocm_t;
1410
1411 /*
1412 * Minidump Read MEM Entry Header
1413 */
1414 typedef struct md_entry_rdmem {
1415 md_entry_hdr_t h;
1416 uint32_t rsvd_0[6];
1417 uint32_t read_addr;
1418 uint32_t read_data_size;
1419 } md_entry_rdmem_t;
1420 /*
1421 * Minidump MIU AGENT ADDRESSES.
1422 */
1423 #define MD_TA_CTL_ENABLE 0x2
1424 #define MD_TA_CTL_START 0x1
1425 #define MD_TA_CTL_BUSY 0x8
1426 #define MD_TA_CTL_CHECK 1000
1427 #define MD_MIU_TEST_AGT_CTRL 0x41000090
1428 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1429 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1430 #define MD_MIU_TEST_AGT_RDDATA_0_31 0x410000A8
1431 #define MD_MIU_TEST_AGT_RDDATA_32_63 0x410000AC
1432 #define MD_MIU_TEST_AGT_RDDATA_64_95 0x410000B8
1433 #define MD_MIU_TEST_AGT_RDDATA_96_127 0x410000BC
1434 #define MD_MIU_TEST_AGT_WRDATA_0_31 0x410000A0
1435 #define MD_MIU_TEST_AGT_WRDATA_32_63 0x410000A4
1436 #define MD_MIU_TEST_AGT_WRDATA_64_95 0x410000B0
1437 #define MD_MIU_TEST_AGT_WRDATA_96_127 0x410000B4
1438
1439 /*
1440 * Minidump Read ROM Entry Header
1441 */
1442 typedef struct md_entry_rdrom {
1443 md_entry_hdr_t h;
1444 uint32_t rsvd_0[6];
1445 uint32_t read_addr;
1446 uint32_t read_data_size;
1447 } md_entry_rdrom_t;
1448 /*
1449 * Minidump ROM Read Address
1450 */
1451 #define MD_DIRECT_ROM_WINDOW 0x42110030
1452 #define MD_DIRECT_ROM_READ_BASE 0x42150000
1453
1454 /*
1455 * Minidump Read MUX Entry Header
1456 */
1457 typedef struct md_entry_mux {
1458 md_entry_hdr_t h;
1459 uint32_t select_addr;
1460 union {
1461 struct {
1462 uint32_t rsvd_0;
1463 } sac;
1464 uint32_t select_addr_cntrl;
1465 } a;
1466 uint32_t data_size;
1467 uint32_t op_count;
1468 uint32_t select_value;
1469 uint32_t select_value_stride;
1470 uint32_t read_addr;
1471 uint32_t rsvd_1;
1472 } md_entry_mux_t;
1473
1474 /*
1475 * Minidump Read QUEUE Entry Header
1476 */
1477 typedef struct md_entry_queue {
1478 md_entry_hdr_t h;
1479 uint32_t select_addr;
1480 union {
1481 struct {
1482 #ifdef _BIG_ENDIAN
1483 uint8_t rsvd_0[2];
1484 uint8_t queue_id_stride[2];
1485 #else
1486 uint8_t queue_id_stride[2];
1487 uint8_t rsvd_0[2];
1488 #endif
1489 } sac;
1490 uint32_t select_addr_cntrl;
1491 } a;
1492 uint32_t data_size;
1493 uint32_t op_count;
1494 uint32_t rsvd_1;
1495 uint32_t rsvd_2;
1496 uint32_t read_addr;
1497 union {
1498 struct {
1499 #ifdef _BIG_ENDIAN
1500 uint8_t rsvd_3[2];
1501 uint8_t read_addr_cnt;
1502 uint8_t read_addr_stride;
1503 #else
1504 uint8_t read_addr_stride;
1505 uint8_t read_addr_cnt;
1506 uint8_t rsvd_3[2];
1507 #endif
1508 } rac;
1509 uint32_t read_addr_cntrl;
1510 } b;
1511 } md_entry_queue_t;
1512
1513 /*
1514 * Minidump Control Entry Header
1515 */
1516 typedef struct md_entry_cntrl {
1517 md_entry_hdr_t h;
1518 uint32_t addr;
1519 union {
1520 struct {
1521 #ifdef _BIG_ENDIAN
1522 uint8_t poll_timeout[2];
1523 uint8_t state_index_a;
1524 uint8_t addr_stride;
1525 #else
1526 uint8_t addr_stride;
1527 uint8_t state_index_a;
1528 uint8_t poll_timeout[2];
1529 #endif
1530 } ac;
1531 uint32_t addr_cntrl;
1532 } a;
1533 uint32_t data_size;
1534 uint32_t op_count;
1535 union {
1536 struct {
1537 #ifdef _BIG_ENDIAN
1538 uint8_t shr;
1539 uint8_t shl;
1540 uint8_t state_index_v;
1541 uint8_t opcode;
1542 #else
1543 uint8_t opcode;
1544 uint8_t state_index_v;
1545 uint8_t shl;
1546 uint8_t shr;
1547 #endif
1548 } cv;
1549 uint32_t control_value;
1550 } b;
1551 uint32_t value_1;
1552 uint32_t value_2;
1553 uint32_t value_3;
1554 } md_entry_cntrl_t;
1555
1556 /*
1557 * Opcodes for Control Entries.
1558 * These Flags are bit fields.
1559 */
1560 #define QL_DBG_OPCODE_WR 0x01
1561 #define QL_DBG_OPCODE_RW 0x02
1562 #define QL_DBG_OPCODE_AND 0x04
1563 #define QL_DBG_OPCODE_OR 0x08
1564 #define QL_DBG_OPCODE_POLL 0x10
1565 #define QL_DBG_OPCODE_RDSTATE 0x20
1566 #define QL_DBG_OPCODE_WRSTATE 0x40
1567 #define QL_DBG_OPCODE_MDSTATE 0x80
1568
1569 /*
1570 * Global Data in ql_nx.c source file.
1571 */
1572
1573 /*
1574 * Global Function Prototypes in ql_nx.c source file.
1575 */
1576 void ql_8021_wr_32(ql_adapter_state_t *, uint64_t, uint32_t);
1577 void ql_8021_rd_32(ql_adapter_state_t *, uint64_t, uint32_t *);
1578 void ql_8021_reset_chip(ql_adapter_state_t *);
1579 int ql_8021_fw_reload(ql_adapter_state_t *);
1580 void ql_8021_clr_hw_intr(ql_adapter_state_t *);
1581 void ql_8021_clr_fw_intr(ql_adapter_state_t *);
1582 void ql_8021_enable_intrs(ql_adapter_state_t *);
1583 void ql_8021_disable_intrs(ql_adapter_state_t *);
1584 void ql_8021_update_crb_int_ptr(ql_adapter_state_t *);
1585 int ql_8021_rom_read(ql_adapter_state_t *, uint32_t, uint32_t *);
1586 int ql_8021_rom_write(ql_adapter_state_t *, uint32_t, uint32_t);
1587 int ql_8021_rom_erase(ql_adapter_state_t *, uint32_t);
1588 int ql_8021_rom_wrsr(ql_adapter_state_t *, uint32_t);
1589 void ql_8021_set_drv_active(ql_adapter_state_t *);
1590 void ql_8021_clr_drv_active(ql_adapter_state_t *);
1591 int ql_8021_idc_handler(ql_adapter_state_t *, uint32_t);
1592 void ql_8021_wr_req_in(ql_adapter_state_t *, uint32_t);
1593 void ql_8021_idc_poll(ql_adapter_state_t *);
1594 int ql_8021_reset_fw(ql_adapter_state_t *);
1595 int ql_8021_fw_chk(ql_adapter_state_t *);
1596 int ql_8021_get_md_template(ql_adapter_state_t *);
1597
1598 #ifdef __cplusplus
1599 }
1600 #endif
1601
1602 #endif /* _QL_NX_H */
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