1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2015 QLogic Corporation. All rights reserved.
24 */
25
26 #ifndef _QL_NX_H
27 #define _QL_NX_H
28
29 /*
30 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
31 *
32 * ***********************************************************************
33 * * **
34 * * NOTICE **
35 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
36 * * ALL RIGHTS RESERVED **
37 * * **
38 * ***********************************************************************
39 *
40 */
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #define NX_P3_A0 0x30
47 #define NX_P3_A2 0x32
48 #define NX_P3_B0 0x40
49 #define NX_P3_B1 0x41
50 #define NX_P3_B2 0x42
51 #define NX_P3P_A0 0x50
52 #define NX_P3P_B0 0x54
53
54 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
55 #define NX_IS_REVISION_P3PLUS(REVISION) (REVISION >= NX_P3P_A0)
56 #define NX_IS_REVISION_P3PLUS_B0(REVISION) (REVISION >= NX_P3P_B0)
57
58 /*
59 * Following are the states of the Phantom. Phantom will set them and
60 * Host will read to check if the fields are correct.
61 */
62 #define PHAN_INITIALIZE_START 0xff00
63 #define PHAN_INITIALIZE_FAILED 0xffff
64 #define PHAN_INITIALIZE_COMPLETE 0xff01
65
66 /* Host writes the following to notify that it has done the init-handshake */
67 #define PHAN_INITIALIZE_ACK 0xf00f
68 #define PHAN_PEG_RCV_INITIALIZED 0xff01
69 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
70
71 /* CRB_RELATED */
72 #define NIC_CRB_BASE (UNM_CAM_RAM(0x200))
73 #define NIC_CRB_BASE_2 (UNM_CAM_RAM(0x700))
74 #define UNM_NIC_REG(X) (NIC_CRB_BASE + (X))
75 #define UNM_NIC_REG_2(X) (NIC_CRB_BASE_2 + (X))
76
77 #define CRB_CUT_THRU_PAGE_SIZE (UNM_CAM_RAM(0x170))
78
79 #define CRB_DEV_PARTITION_INFO (UNM_CAM_RAM(0x14c))
80 #define CRB_DEV_STATE (UNM_CAM_RAM(0x140))
81 #define CRB_DRV_IDC_VERSION (UNM_CAM_RAM(0x174))
82 #define CRB_DRV_ACTIVE (UNM_CAM_RAM(0x138))
83 #define CRB_DRV_STATE (UNM_CAM_RAM(0x144))
84 #define CRB_DRV_SCRATCH (UNM_CAM_RAM(0x148))
85 #define CRB_PORT_0_REQIN (UNM_CAM_RAM(0x1b8))
86 #define CRB_PORT_1_REQIN (UNM_CAM_RAM(0x1bc))
87
88 /* Every driver should use these Device State */
89 #define NX_DEV_POLL 0
90 #define NX_DEV_COLD 1
91 #define NX_DEV_INITIALIZING 2
92 #define NX_DEV_READY 3
93 #define NX_DEV_NEED_RESET 4
94 #define NX_DEV_NEED_QUIESCENT 5
95 #define NX_DEV_FAILED 6
96 #define NX_DEV_QUIESCENT 7
97 #define NX_DEV_BADOBADO 0xbad0bad0
98
99 #define NX_IDC_VERSION 0x1
100
101 #define CRB_CMD_PRODUCER_OFFSET (UNM_NIC_REG(0x08))
102 #define CRB_CMD_CONSUMER_OFFSET (UNM_NIC_REG(0x0c))
103 #define CRB_PAUSE_ADDR_LO (UNM_NIC_REG(0x10)) /* C0 EPG BUG */
104 #define CRB_PAUSE_ADDR_HI (UNM_NIC_REG(0x14))
105 #define NX_CDRP_CRB_OFFSET (UNM_NIC_REG(0x18))
106 #define NX_ARG1_CRB_OFFSET (UNM_NIC_REG(0x1c))
107 #define NX_ARG2_CRB_OFFSET (UNM_NIC_REG(0x20))
108 #define NX_ARG3_CRB_OFFSET (UNM_NIC_REG(0x24))
109 #define NX_SIGN_CRB_OFFSET (UNM_NIC_REG(0x28))
110 #define CRB_CMDPEG_CMDRING (UNM_NIC_REG(0x38))
111 #define CRB_HOST_DUMMY_BUF_ADDR_HI (UNM_NIC_REG(0x3c))
112 #define CRB_HOST_DUMMY_BUF_ADDR_LO (UNM_NIC_REG(0x40))
113 #define CRB_CMDPEG_STATE (UNM_NIC_REG(0x50))
114 #define BOOT_LOADER_DIMM_STATUS (UNM_NIC_REG(0x54))
115 #define CRB_GLOBAL_INT_COAL (UNM_NIC_REG(0x64)) /* intrt coalescing */
116 #define CRB_INT_COAL_MODE (UNM_NIC_REG(0x68))
117 #define CRB_MAX_RCV_BUFS (UNM_NIC_REG(0x6c))
118 #define CRB_TX_INT_THRESHOLD (UNM_NIC_REG(0x70))
119 #define CRB_RX_PKT_TIMER (UNM_NIC_REG(0x74))
120 #define CRB_TX_PKT_TIMER (UNM_NIC_REG(0x78))
121 #define CRB_RX_PKT_CNT (UNM_NIC_REG(0x7c))
122 #define CRB_RX_TMR_CNT (UNM_NIC_REG(0x80))
123 #define CRB_RCV_INTR_COUNT (UNM_NIC_REG(0x84))
124 #define CRB_XG_STATE (UNM_NIC_REG(0x94)) /* XG Link status */
125 #define CRB_XG_STATE_P3 (UNM_NIC_REG(0x98)) /* XG PF Link status */
126 #define CRB_TX_STATE (UNM_NIC_REG(0xac)) /* Debug -performance */
127 #define CRB_TX_COUNT (UNM_NIC_REG(0xb0))
128 #define CRB_RX_STATE (UNM_NIC_REG(0xb4))
129 #define CRB_RX_PERF_DEBUG_1 (UNM_NIC_REG(0xb8))
130 #define CRB_RX_LRO_CONTROL (UNM_NIC_REG(0xbc)) /* LRO On/OFF */
131 #define CRB_MPORT_MODE (UNM_NIC_REG(0xc4)) /* Multiport Mode */
132 #define CRB_DMA_SHIFT (UNM_NIC_REG(0xcc)) /* DMA mask extension */
133 #define CRB_INT_VECTOR (UNM_NIC_REG(0xd4))
134 #define CRB_PF_LINK_SPEED_1 (UNM_NIC_REG(0xe8))
135 #define CRB_PF_LINK_SPEED_2 (UNM_NIC_REG(0xec))
136 #define CRB_PF_MAX_LINK_SPEED_1 (UNM_NIC_REG(0xf0))
137 #define CRB_PF_MAX_LINK_SPEED_2 (UNM_NIC_REG(0xf4))
138 #define CRB_HOST_DUMMY_BUF (UNM_NIC_REG(0xfc))
139
140 /* used for ethtool tests */
141 #define CRB_SCRATCHPAD_TEST (UNM_NIC_REG(0x280))
142
143 #define CRB_RCVPEG_STATE (UNM_NIC_REG(0x13c))
144
145 #define UNM_PEG_HALT_STATUS1 (UNM_CAM_RAM(0xa8))
146 #define UNM_PEG_HALT_STATUS2 (UNM_CAM_RAM(0xac))
147 #define UNM_PEG_ALIVE_COUNTER (UNM_CAM_RAM(0x0b0))
148 #define UNM_FW_CAPABILITIES_1 (UNM_CAM_RAM(0x128))
149
150 /* 12 registers to store MAC addresses for 8 PCI functions */
151 #define CRB_MAC_BLOCK_START (UNM_CAM_RAM(0x1c0))
152
153 #define CRB_CMD_PRODUCER_OFFSET_1 (UNM_NIC_REG(0x1ac))
154 #define CRB_CMD_CONSUMER_OFFSET_1 (UNM_NIC_REG(0x1b0))
155 #define CRB_TEMP_STATE (UNM_NIC_REG(0x1b4))
156 #define CRB_CMD_PRODUCER_OFFSET_2 (UNM_NIC_REG(0x1b8))
157 #define CRB_CMD_CONSUMER_OFFSET_2 (UNM_NIC_REG(0x1bc))
158
159 #define CRB_CMD_PRODUCER_OFFSET_3 (UNM_NIC_REG(0x1d0))
160 #define CRB_CMD_CONSUMER_OFFSET_3 (UNM_NIC_REG(0x1d4))
161 /* sw int status/mask registers */
162 #define CRB_SW_INT_MASK_OFFSET_0 0x1d8
163 #define CRB_SW_INT_MASK_OFFSET_1 0x1e0
164 #define CRB_SW_INT_MASK_OFFSET_2 0x1e4
165 #define CRB_SW_INT_MASK_OFFSET_3 0x1e8
166 #define CRB_SW_INT_MASK_OFFSET_4 0x450
167 #define CRB_SW_INT_MASK_OFFSET_5 0x454
168 #define CRB_SW_INT_MASK_OFFSET_6 0x458
169 #define CRB_SW_INT_MASK_OFFSET_7 0x45c
170 #define CRB_SW_INT_MASK_0 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0))
171 #define CRB_SW_INT_MASK_1 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1))
172 #define CRB_SW_INT_MASK_2 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2))
173 #define CRB_SW_INT_MASK_3 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3))
174 #define CRB_SW_INT_MASK_4 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4))
175 #define CRB_SW_INT_MASK_5 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5))
176 #define CRB_SW_INT_MASK_6 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6))
177 #define CRB_SW_INT_MASK_7 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7))
178
179 #define CRB_NIC_DEBUG_STRUCT_BASE (UNM_NIC_REG(0x288))
180
181 #define CRB_NIC_CAPABILITIES_HOST (UNM_NIC_REG(0x1a8))
182 #define CRB_NIC_CAPABILITIES_FW (UNM_NIC_REG(0x1dc))
183 #define CRB_NIC_MSI_MODE_HOST (UNM_NIC_REG(0x270))
184 #define CRB_NIC_MSI_MODE_FW (UNM_NIC_REG(0x274))
185
186 #define INTR_SCHEME_PERPORT 0x1
187 #define MSI_MODE_MULTIFUNC 0x1
188
189 #define CRB_EPG_QUEUE_BUSY_COUNT (UNM_NIC_REG(0x200))
190
191 #define CRB_V2P_0 (UNM_NIC_REG(0x290))
192 #define CRB_V2P_1 (UNM_NIC_REG(0x294))
193 #define CRB_V2P_2 (UNM_NIC_REG(0x298))
194 #define CRB_V2P_3 (UNM_NIC_REG(0x29c))
195 #define CRB_V2P(port) (CRB_V2P_0 + ((port) * 4))
196 #define CRB_DRIVER_VERSION (UNM_NIC_REG(0x2a0))
197
198 #define CRB_CNT_DBG1 (UNM_NIC_REG(0x2a4))
199 #define CRB_CNT_DBG2 (UNM_NIC_REG(0x2a8))
200 #define CRB_CNT_DBG3 (UNM_NIC_REG(0x2ac))
201
202 /* ends here */
203 #define UNM_HW_H0_CH_HUB_ADR 0x05
204 #define UNM_HW_H1_CH_HUB_ADR 0x0E
205 #define UNM_HW_H2_CH_HUB_ADR 0x03
206 #define UNM_HW_H3_CH_HUB_ADR 0x01
207 #define UNM_HW_H4_CH_HUB_ADR 0x06
208 #define UNM_HW_H5_CH_HUB_ADR 0x07
209 #define UNM_HW_H6_CH_HUB_ADR 0x08
210 /*
211 * WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an
212 * ILLEGAL hub!!!!!
213 */
214
215 /* Hub 0 */
216 #define UNM_HW_MN_CRB_AGT_ADR 0x15
217 #define UNM_HW_MS_CRB_AGT_ADR 0x25
218
219 /* Hub 1 */
220 #define UNM_HW_PS_CRB_AGT_ADR 0x73
221 #define UNM_HW_SS_CRB_AGT_ADR 0x20
222 #define UNM_HW_RPMX3_CRB_AGT_ADR 0x0b
223 #define UNM_HW_QMS_CRB_AGT_ADR 0x00
224 #define UNM_HW_SQGS0_CRB_AGT_ADR 0x01
225 #define UNM_HW_SQGS1_CRB_AGT_ADR 0x02
226 #define UNM_HW_SQGS2_CRB_AGT_ADR 0x03
227 #define UNM_HW_SQGS3_CRB_AGT_ADR 0x04
228 #define UNM_HW_C2C0_CRB_AGT_ADR 0x58
229 #define UNM_HW_C2C1_CRB_AGT_ADR 0x59
230 #define UNM_HW_C2C2_CRB_AGT_ADR 0x5a
231 #define UNM_HW_RPMX2_CRB_AGT_ADR 0x0a
232 #define UNM_HW_RPMX4_CRB_AGT_ADR 0x0c
233 #define UNM_HW_RPMX7_CRB_AGT_ADR 0x0f
234 #define UNM_HW_RPMX9_CRB_AGT_ADR 0x12
235 #define UNM_HW_SMB_CRB_AGT_ADR 0x18
236
237 /* Hub 2 */
238 #define UNM_HW_NIU_CRB_AGT_ADR 0x31
239 #define UNM_HW_I2C0_CRB_AGT_ADR 0x19
240 #define UNM_HW_I2C1_CRB_AGT_ADR 0x29
241
242 #define UNM_HW_SN_CRB_AGT_ADR 0x10
243 #define UNM_HW_I2Q_CRB_AGT_ADR 0x20
244 #define UNM_HW_LPC_CRB_AGT_ADR 0x22
245 #define UNM_HW_ROMUSB_CRB_AGT_ADR 0x21
246 #define UNM_HW_QM_CRB_AGT_ADR 0x66
247 #define UNM_HW_SQG0_CRB_AGT_ADR 0x60
248 #define UNM_HW_SQG1_CRB_AGT_ADR 0x61
249 #define UNM_HW_SQG2_CRB_AGT_ADR 0x62
250 #define UNM_HW_SQG3_CRB_AGT_ADR 0x63
251 #define UNM_HW_RPMX1_CRB_AGT_ADR 0x09
252 #define UNM_HW_RPMX5_CRB_AGT_ADR 0x0d
253 #define UNM_HW_RPMX6_CRB_AGT_ADR 0x0e
254 #define UNM_HW_RPMX8_CRB_AGT_ADR 0x11
255
256 /* Hub 3 */
257 #define UNM_HW_PH_CRB_AGT_ADR 0x1A
258 #define UNM_HW_SRE_CRB_AGT_ADR 0x50
259 #define UNM_HW_EG_CRB_AGT_ADR 0x51
260 #define UNM_HW_RPMX0_CRB_AGT_ADR 0x08
261
262 /* Hub 4 */
263 #define UNM_HW_PEGN0_CRB_AGT_ADR 0x40
264 #define UNM_HW_PEGN1_CRB_AGT_ADR 0x41
265 #define UNM_HW_PEGN2_CRB_AGT_ADR 0x42
266 #define UNM_HW_PEGN3_CRB_AGT_ADR 0x43
267 #define UNM_HW_PEGNI_CRB_AGT_ADR 0x44
268 #define UNM_HW_PEGND_CRB_AGT_ADR 0x45
269 #define UNM_HW_PEGNC_CRB_AGT_ADR 0x46
270 #define UNM_HW_PEGR0_CRB_AGT_ADR 0x47
271 #define UNM_HW_PEGR1_CRB_AGT_ADR 0x48
272 #define UNM_HW_PEGR2_CRB_AGT_ADR 0x49
273 #define UNM_HW_PEGR3_CRB_AGT_ADR 0x4a
274 #define UNM_HW_PEGN4_CRB_AGT_ADR 0x4b
275
276 /* Hub 5 */
277 #define UNM_HW_PEGS0_CRB_AGT_ADR 0x40
278 #define UNM_HW_PEGS1_CRB_AGT_ADR 0x41
279 #define UNM_HW_PEGS2_CRB_AGT_ADR 0x42
280 #define UNM_HW_PEGS3_CRB_AGT_ADR 0x43
281 #define UNM_HW_PEGSI_CRB_AGT_ADR 0x44
282 #define UNM_HW_PEGSD_CRB_AGT_ADR 0x45
283 #define UNM_HW_PEGSC_CRB_AGT_ADR 0x46
284
285 /* Hub 6 */
286 #define UNM_HW_CAS0_CRB_AGT_ADR 0x46
287 #define UNM_HW_CAS1_CRB_AGT_ADR 0x47
288 #define UNM_HW_CAS2_CRB_AGT_ADR 0x48
289 #define UNM_HW_CAS3_CRB_AGT_ADR 0x49
290 #define UNM_HW_NCM_CRB_AGT_ADR 0x16
291 #define UNM_HW_TMR_CRB_AGT_ADR 0x17
292 #define UNM_HW_XDMA_CRB_AGT_ADR 0x05
293 #define UNM_HW_OCM0_CRB_AGT_ADR 0x06
294 #define UNM_HW_OCM1_CRB_AGT_ADR 0x07
295
296 /* This field defines PCI/X adr [25:20] of agents on the CRB */
297
298 #define UNM_HW_PX_MAP_CRB_PH 0
299 #define UNM_HW_PX_MAP_CRB_PS 1
300 #define UNM_HW_PX_MAP_CRB_MN 2
301 #define UNM_HW_PX_MAP_CRB_MS 3
302 #define UNM_HW_PX_MAP_CRB_SRE 5
303 #define UNM_HW_PX_MAP_CRB_NIU 6
304 #define UNM_HW_PX_MAP_CRB_QMN 7
305 #define UNM_HW_PX_MAP_CRB_SQN0 8
306 #define UNM_HW_PX_MAP_CRB_SQN1 9
307 #define UNM_HW_PX_MAP_CRB_SQN2 10
308 #define UNM_HW_PX_MAP_CRB_SQN3 11
309 #define UNM_HW_PX_MAP_CRB_QMS 12
310 #define UNM_HW_PX_MAP_CRB_SQS0 13
311 #define UNM_HW_PX_MAP_CRB_SQS1 14
312 #define UNM_HW_PX_MAP_CRB_SQS2 15
313 #define UNM_HW_PX_MAP_CRB_SQS3 16
314 #define UNM_HW_PX_MAP_CRB_PGN0 17
315 #define UNM_HW_PX_MAP_CRB_PGN1 18
316 #define UNM_HW_PX_MAP_CRB_PGN2 19
317 #define UNM_HW_PX_MAP_CRB_PGN3 20
318 #define UNM_HW_PX_MAP_CRB_PGN4 (UNM_HW_PX_MAP_CRB_SQS2)
319 #define UNM_HW_PX_MAP_CRB_PGND 21
320 #define UNM_HW_PX_MAP_CRB_PGNI 22
321 #define UNM_HW_PX_MAP_CRB_PGS0 23
322 #define UNM_HW_PX_MAP_CRB_PGS1 24
323 #define UNM_HW_PX_MAP_CRB_PGS2 25
324 #define UNM_HW_PX_MAP_CRB_PGS3 26
325 #define UNM_HW_PX_MAP_CRB_PGSD 27
326 #define UNM_HW_PX_MAP_CRB_PGSI 28
327 #define UNM_HW_PX_MAP_CRB_SN 29
328 #define UNM_HW_PX_MAP_CRB_EG 31
329 #define UNM_HW_PX_MAP_CRB_PH2 32
330 #define UNM_HW_PX_MAP_CRB_PS2 33
331 #define UNM_HW_PX_MAP_CRB_CAM 34
332 #define UNM_HW_PX_MAP_CRB_CAS0 35
333 #define UNM_HW_PX_MAP_CRB_CAS1 36
334 #define UNM_HW_PX_MAP_CRB_CAS2 37
335 #define UNM_HW_PX_MAP_CRB_C2C0 38
336 #define UNM_HW_PX_MAP_CRB_C2C1 39
337 #define UNM_HW_PX_MAP_CRB_TIMR 40
338 /*
339 * #define PX_MAP_CRB_SS 41
340 */
341 #define UNM_HW_PX_MAP_CRB_RPMX1 42
342 #define UNM_HW_PX_MAP_CRB_RPMX2 43
343 #define UNM_HW_PX_MAP_CRB_RPMX3 44
344 #define UNM_HW_PX_MAP_CRB_RPMX4 45
345 #define UNM_HW_PX_MAP_CRB_RPMX5 46
346 #define UNM_HW_PX_MAP_CRB_RPMX6 47
347 #define UNM_HW_PX_MAP_CRB_RPMX7 48
348 #define UNM_HW_PX_MAP_CRB_XDMA 49
349 #define UNM_HW_PX_MAP_CRB_I2Q 50
350 #define UNM_HW_PX_MAP_CRB_ROMUSB 51
351 #define UNM_HW_PX_MAP_CRB_CAS3 52
352 #define UNM_HW_PX_MAP_CRB_RPMX0 53
353 #define UNM_HW_PX_MAP_CRB_RPMX8 54
354 #define UNM_HW_PX_MAP_CRB_RPMX9 55
355 #define UNM_HW_PX_MAP_CRB_OCM0 56
356 #define UNM_HW_PX_MAP_CRB_OCM1 57
357 #define UNM_HW_PX_MAP_CRB_SMB 58
358 #define UNM_HW_PX_MAP_CRB_I2C0 59
359 #define UNM_HW_PX_MAP_CRB_I2C1 60
360 #define UNM_HW_PX_MAP_CRB_LPC 61
361 #define UNM_HW_PX_MAP_CRB_PGNC 62
362 #define UNM_HW_PX_MAP_CRB_PGR0 63
363 #define UNM_HW_PX_MAP_CRB_PGR1 4
364 #define UNM_HW_PX_MAP_CRB_PGR2 30
365 #define UNM_HW_PX_MAP_CRB_PGR3 41
366
367 /* This field defines CRB adr [31:20] of the agents */
368
369 #define UNM_HW_CRB_HUB_AGT_ADR_MN ((UNM_HW_H0_CH_HUB_ADR << 7) | \
370 UNM_HW_MN_CRB_AGT_ADR)
371 #define UNM_HW_CRB_HUB_AGT_ADR_PH ((UNM_HW_H0_CH_HUB_ADR << 7) | \
372 UNM_HW_PH_CRB_AGT_ADR)
373 #define UNM_HW_CRB_HUB_AGT_ADR_MS ((UNM_HW_H0_CH_HUB_ADR << 7) | \
374 UNM_HW_MS_CRB_AGT_ADR)
375
376 #define UNM_HW_CRB_HUB_AGT_ADR_PS ((UNM_HW_H1_CH_HUB_ADR << 7) | \
377 UNM_HW_PS_CRB_AGT_ADR)
378 #define UNM_HW_CRB_HUB_AGT_ADR_SS ((UNM_HW_H1_CH_HUB_ADR << 7) | \
379 UNM_HW_SS_CRB_AGT_ADR)
380 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX3 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
381 UNM_HW_RPMX3_CRB_AGT_ADR)
382 #define UNM_HW_CRB_HUB_AGT_ADR_QMS ((UNM_HW_H1_CH_HUB_ADR << 7) | \
383 UNM_HW_QMS_CRB_AGT_ADR)
384 #define UNM_HW_CRB_HUB_AGT_ADR_SQS0 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
385 UNM_HW_SQGS0_CRB_AGT_ADR)
386 #define UNM_HW_CRB_HUB_AGT_ADR_SQS1 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
387 UNM_HW_SQGS1_CRB_AGT_ADR)
388 #define UNM_HW_CRB_HUB_AGT_ADR_SQS2 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
389 UNM_HW_SQGS2_CRB_AGT_ADR)
390 #define UNM_HW_CRB_HUB_AGT_ADR_SQS3 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
391 UNM_HW_SQGS3_CRB_AGT_ADR)
392 #define UNM_HW_CRB_HUB_AGT_ADR_C2C0 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
393 UNM_HW_C2C0_CRB_AGT_ADR)
394 #define UNM_HW_CRB_HUB_AGT_ADR_C2C1 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
395 UNM_HW_C2C1_CRB_AGT_ADR)
396 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX2 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
397 UNM_HW_RPMX2_CRB_AGT_ADR)
398 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX4 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
399 UNM_HW_RPMX4_CRB_AGT_ADR)
400 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX7 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
401 UNM_HW_RPMX7_CRB_AGT_ADR)
402 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX9 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
403 UNM_HW_RPMX9_CRB_AGT_ADR)
404 #define UNM_HW_CRB_HUB_AGT_ADR_SMB ((UNM_HW_H1_CH_HUB_ADR << 7) | \
405 UNM_HW_SMB_CRB_AGT_ADR)
406
407 #define UNM_HW_CRB_HUB_AGT_ADR_NIU ((UNM_HW_H2_CH_HUB_ADR << 7) | \
408 UNM_HW_NIU_CRB_AGT_ADR)
409 #define UNM_HW_CRB_HUB_AGT_ADR_I2C0 ((UNM_HW_H2_CH_HUB_ADR << 7) | \
410 UNM_HW_I2C0_CRB_AGT_ADR)
411 #define UNM_HW_CRB_HUB_AGT_ADR_I2C1 ((UNM_HW_H2_CH_HUB_ADR << 7) | \
412 UNM_HW_I2C1_CRB_AGT_ADR)
413
414 #define UNM_HW_CRB_HUB_AGT_ADR_SRE ((UNM_HW_H3_CH_HUB_ADR << 7) | \
415 UNM_HW_SRE_CRB_AGT_ADR)
416 #define UNM_HW_CRB_HUB_AGT_ADR_EG ((UNM_HW_H3_CH_HUB_ADR << 7) | \
417 UNM_HW_EG_CRB_AGT_ADR)
418 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX0 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
419 UNM_HW_RPMX0_CRB_AGT_ADR)
420 #define UNM_HW_CRB_HUB_AGT_ADR_QMN ((UNM_HW_H3_CH_HUB_ADR << 7) | \
421 UNM_HW_QM_CRB_AGT_ADR)
422 #define UNM_HW_CRB_HUB_AGT_ADR_SQN0 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
423 UNM_HW_SQG0_CRB_AGT_ADR)
424 #define UNM_HW_CRB_HUB_AGT_ADR_SQN1 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
425 UNM_HW_SQG1_CRB_AGT_ADR)
426 #define UNM_HW_CRB_HUB_AGT_ADR_SQN2 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
427 UNM_HW_SQG2_CRB_AGT_ADR)
428 #define UNM_HW_CRB_HUB_AGT_ADR_SQN3 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
429 UNM_HW_SQG3_CRB_AGT_ADR)
430 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX1 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
431 UNM_HW_RPMX1_CRB_AGT_ADR)
432 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX5 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
433 UNM_HW_RPMX5_CRB_AGT_ADR)
434 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX6 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
435 UNM_HW_RPMX6_CRB_AGT_ADR)
436 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX8 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
437 UNM_HW_RPMX8_CRB_AGT_ADR)
438 #define UNM_HW_CRB_HUB_AGT_ADR_CAS0 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
439 UNM_HW_CAS0_CRB_AGT_ADR)
440 #define UNM_HW_CRB_HUB_AGT_ADR_CAS1 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
441 UNM_HW_CAS1_CRB_AGT_ADR)
442 #define UNM_HW_CRB_HUB_AGT_ADR_CAS2 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
443 UNM_HW_CAS2_CRB_AGT_ADR)
444 #define UNM_HW_CRB_HUB_AGT_ADR_CAS3 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
445 UNM_HW_CAS3_CRB_AGT_ADR)
446
447 #define UNM_HW_CRB_HUB_AGT_ADR_PGNI ((UNM_HW_H4_CH_HUB_ADR << 7) | \
448 UNM_HW_PEGNI_CRB_AGT_ADR)
449 #define UNM_HW_CRB_HUB_AGT_ADR_PGND ((UNM_HW_H4_CH_HUB_ADR << 7) | \
450 UNM_HW_PEGND_CRB_AGT_ADR)
451 #define UNM_HW_CRB_HUB_AGT_ADR_PGN0 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
452 UNM_HW_PEGN0_CRB_AGT_ADR)
453 #define UNM_HW_CRB_HUB_AGT_ADR_PGN1 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
454 UNM_HW_PEGN1_CRB_AGT_ADR)
455 #define UNM_HW_CRB_HUB_AGT_ADR_PGN2 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
456 UNM_HW_PEGN2_CRB_AGT_ADR)
457 #define UNM_HW_CRB_HUB_AGT_ADR_PGN3 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
458 UNM_HW_PEGN3_CRB_AGT_ADR)
459 #define UNM_HW_CRB_HUB_AGT_ADR_PGN4 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
460 UNM_HW_PEGN4_CRB_AGT_ADR)
461
462 #define UNM_HW_CRB_HUB_AGT_ADR_PGNC ((UNM_HW_H4_CH_HUB_ADR << 7) | \
463 UNM_HW_PEGNC_CRB_AGT_ADR)
464 #define UNM_HW_CRB_HUB_AGT_ADR_PGR0 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
465 UNM_HW_PEGR0_CRB_AGT_ADR)
466 #define UNM_HW_CRB_HUB_AGT_ADR_PGR1 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
467 UNM_HW_PEGR1_CRB_AGT_ADR)
468 #define UNM_HW_CRB_HUB_AGT_ADR_PGR2 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
469 UNM_HW_PEGR2_CRB_AGT_ADR)
470 #define UNM_HW_CRB_HUB_AGT_ADR_PGR3 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
471 UNM_HW_PEGR3_CRB_AGT_ADR)
472
473 #define UNM_HW_CRB_HUB_AGT_ADR_PGSI ((UNM_HW_H5_CH_HUB_ADR << 7) | \
474 UNM_HW_PEGSI_CRB_AGT_ADR)
475 #define UNM_HW_CRB_HUB_AGT_ADR_PGSD ((UNM_HW_H5_CH_HUB_ADR << 7) | \
476 UNM_HW_PEGSD_CRB_AGT_ADR)
477 #define UNM_HW_CRB_HUB_AGT_ADR_PGS0 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
478 UNM_HW_PEGS0_CRB_AGT_ADR)
479 #define UNM_HW_CRB_HUB_AGT_ADR_PGS1 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
480 UNM_HW_PEGS1_CRB_AGT_ADR)
481 #define UNM_HW_CRB_HUB_AGT_ADR_PGS2 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
482 UNM_HW_PEGS2_CRB_AGT_ADR)
483 #define UNM_HW_CRB_HUB_AGT_ADR_PGS3 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
484 UNM_HW_PEGS3_CRB_AGT_ADR)
485 #define UNM_HW_CRB_HUB_AGT_ADR_PGSC ((UNM_HW_H5_CH_HUB_ADR << 7) | \
486 UNM_HW_PEGSC_CRB_AGT_ADR)
487
488 #define UNM_HW_CRB_HUB_AGT_ADR_CAM ((UNM_HW_H6_CH_HUB_ADR << 7) | \
489 UNM_HW_NCM_CRB_AGT_ADR)
490 #define UNM_HW_CRB_HUB_AGT_ADR_TIMR ((UNM_HW_H6_CH_HUB_ADR << 7) | \
491 UNM_HW_TMR_CRB_AGT_ADR)
492 #define UNM_HW_CRB_HUB_AGT_ADR_XDMA ((UNM_HW_H6_CH_HUB_ADR << 7) | \
493 UNM_HW_XDMA_CRB_AGT_ADR)
494 #define UNM_HW_CRB_HUB_AGT_ADR_SN ((UNM_HW_H6_CH_HUB_ADR << 7) | \
495 UNM_HW_SN_CRB_AGT_ADR)
496 #define UNM_HW_CRB_HUB_AGT_ADR_I2Q ((UNM_HW_H6_CH_HUB_ADR << 7) | \
497 UNM_HW_I2Q_CRB_AGT_ADR)
498 #define UNM_HW_CRB_HUB_AGT_ADR_ROMUSB ((UNM_HW_H6_CH_HUB_ADR << 7) | \
499 UNM_HW_ROMUSB_CRB_AGT_ADR)
500 #define UNM_HW_CRB_HUB_AGT_ADR_OCM0 ((UNM_HW_H6_CH_HUB_ADR << 7) | \
501 UNM_HW_OCM0_CRB_AGT_ADR)
502 #define UNM_HW_CRB_HUB_AGT_ADR_OCM1 ((UNM_HW_H6_CH_HUB_ADR << 7) | \
503 UNM_HW_OCM1_CRB_AGT_ADR)
504 #define UNM_HW_CRB_HUB_AGT_ADR_LPC ((UNM_HW_H6_CH_HUB_ADR << 7) | \
505 UNM_HW_LPC_CRB_AGT_ADR)
506
507 /*
508 * ROM USB CRB space is divided into 4 regions depending on decode of
509 * address bits [19:16]
510 */
511 #define ROMUSB_GLB (UNM_CRB_ROMUSB + 0x00000)
512 #define ROMUSB_ROM (UNM_CRB_ROMUSB + 0x10000)
513 #define ROMUSB_USB (UNM_CRB_ROMUSB + 0x20000)
514 #define ROMUSB_DIRECT_ROM (UNM_CRB_ROMUSB + 0x30000)
515 #define ROMUSB_TAP (UNM_CRB_ROMUSB + 0x40000)
516
517 /* ROMUSB GLB register definitions */
518 #define UNM_ROMUSB_GLB_CONTROL (ROMUSB_GLB + 0x0000)
519 #define UNM_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
520 #define UNM_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
521 #define UNM_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
522 #define UNM_ROMUSB_GLB_RNG_PLL_CTL (ROMUSB_GLB + 0x0010)
523 #define UNM_ROMUSB_GLB_TEST_MUX_O (ROMUSB_GLB + 0x0014)
524 #define UNM_ROMUSB_GLB_PLL0_CTRL (ROMUSB_GLB + 0x0018)
525 #define UNM_ROMUSB_GLB_PLL1_CTRL (ROMUSB_GLB + 0x001c)
526 #define UNM_ROMUSB_GLB_PLL2_CTRL (ROMUSB_GLB + 0x0020)
527 #define UNM_ROMUSB_GLB_PLL3_CTRL (ROMUSB_GLB + 0x0024)
528 #define UNM_ROMUSB_GLB_PLL_LOCK (ROMUSB_GLB + 0x0028)
529 #define UNM_ROMUSB_GLB_EXTERN_INT (ROMUSB_GLB + 0x002c)
530 #define UNM_ROMUSB_GLB_PH_RST (ROMUSB_GLB + 0x0030)
531 #define UNM_ROMUSB_GLB_PS_RST (ROMUSB_GLB + 0x0034)
532 #define UNM_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
533 #define UNM_ROMUSB_GLB_MIU_RST (ROMUSB_GLB + 0x003c)
534 #define UNM_ROMUSB_GLB_CRB_RST (ROMUSB_GLB + 0x0040)
535 #define UNM_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
536 #define UNM_ROMUSB_GLB_MN_COM_A2T (ROMUSB_GLB + 0x0050)
537 #define UNM_ROMUSB_GLB_MN_COM_A2T (ROMUSB_GLB + 0x0050)
538 #define UNM_ROMUSB_GLB_REV_ID (ROMUSB_GLB + 0x0054)
539 #define UNM_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
540 #define UNM_ROMUSB_GLB_VENDOR_DEV_ID (ROMUSB_GLB + 0x0058)
541 #define UNM_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00a8)
542
543 #define UNM_ROMUSB_GPIO(n) ((n) <= 15 ? (ROMUSB_GLB + 0x60 + (4 * (n))): \
544 ((n) <= 18) ? (ROMUSB_GLB + 0x70 + (4 * (n))) : \
545 (ROMUSB_GLB + 0x70 + (4 * (19))))
546
547 #define UNM_ROMUSB_ROM_CONTROL (ROMUSB_ROM + 0x0000)
548 #define UNM_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
549 #define UNM_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
550 #define UNM_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
551 #define UNM_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
552 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
553 #define UNM_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
554 #define UNM_ROMUSB_ROM_AGT_TAG (ROMUSB_ROM + 0x001c)
555 #define UNM_ROMUSB_ROM_TIME_PARM (ROMUSB_ROM + 0x0020)
556 #define UNM_ROMUSB_ROM_CLK_DIV (ROMUSB_ROM + 0x0024)
557 #define UNM_ROMUSB_ROM_MISS_INSTR (ROMUSB_ROM + 0x0028)
558
559 #define UNM_ROMUSB_ROM_WRSR_INSTR 0x01
560 #define UNM_ROMUSB_ROM_PP_INSTR 0x02
561 #define UNM_ROMUSB_ROM_READ_INSTR 0x03
562 #define UNM_ROMUSB_ROM_WRDI_INSTR 0x04
563 #define UNM_ROMUSB_ROM_RDSR_INSTR 0x05
564 #define UNM_ROMUSB_ROM_WREN_INSTR 0x06
565 #define UNM_ROMUSB_ROM_FAST_RD_INSTR 0x0B
566 #define UNM_ROMUSB_ROM_RES_INSTR 0xAB
567 #define UNM_ROMUSB_ROM_BE_INSTR 0xC7
568 #define UNM_ROMUSB_ROM_DP_INSTR 0xC9
569 #define UNM_ROMUSB_ROM_SE_INSTR 0xD8
570
571 /* Lock IDs for ROM lock */
572 #define ROM_LOCK_DRIVER 0x0d417340
573
574 /* Lock IDs for PHY lock */
575 #define PHY_LOCK_DRIVER 0x44524956
576
577 #define UNM_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
578 #define UNM_PCI_CRB_WINDOW(A) (UNM_PCI_CRBSPACE + (A)*UNM_PCI_CRB_WINDOWSIZE)
579 #define UNM_CRB_C2C_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C0))
580 #define UNM_CRB_C2C_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C1))
581 #define UNM_CRB_C2C_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C2))
582 #define UNM_CRB_CAM (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAM))
583 #define UNM_CRB_CASPER (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS))
584 #define UNM_CRB_CASPER_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS0))
585 #define UNM_CRB_CASPER_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS1))
586 #define UNM_CRB_CASPER_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS2))
587 #define UNM_CRB_DDR_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MS))
588 #define UNM_CRB_DDR_NET (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MN))
589 #define UNM_CRB_EPG (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_EG))
590 #define UNM_CRB_I2Q (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2Q))
591 #define UNM_CRB_NIU (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_NIU))
592 /* HACK upon HACK upon HACK (for PCIE builds) */
593 #define UNM_CRB_PCIX_HOST (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH))
594 #define UNM_CRB_PCIX_HOST2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH2))
595 #define UNM_CRB_PCIX_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS))
596 #define UNM_CRB_PCIE (UNM_CRB_PCIX_MD)
597 /* window 1 pcie slot */
598 #define UNM_CRB_PCIE2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS2))
599
600 #define UNM_CRB_PEG_MD_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS0))
601 #define UNM_CRB_PEG_MD_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS1))
602 #define UNM_CRB_PEG_MD_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS2))
603 #define UNM_CRB_PEG_MD_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS3))
604 #define UNM_CRB_PEG_MD_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS3))
605 #define UNM_CRB_PEG_MD_D (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSD))
606 #define UNM_CRB_PEG_MD_I (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSI))
607 #define UNM_CRB_PEG_NET_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN0))
608 #define UNM_CRB_PEG_NET_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN1))
609 #define UNM_CRB_PEG_NET_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN2))
610 #define UNM_CRB_PEG_NET_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN3))
611 #define UNM_CRB_PEG_NET_4 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN4))
612 #define UNM_CRB_PEG_NET_D (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGND))
613 #define UNM_CRB_PEG_NET_I (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGNI))
614 #define UNM_CRB_PQM_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMS))
615 #define UNM_CRB_PQM_NET (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMN))
616 #define UNM_CRB_QDR_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SS))
617 #define UNM_CRB_QDR_NET (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SN))
618 #define UNM_CRB_ROMUSB (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_ROMUSB))
619 #define UNM_CRB_RPMX_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX0))
620 #define UNM_CRB_RPMX_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX1))
621 #define UNM_CRB_RPMX_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX2))
622 #define UNM_CRB_RPMX_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX3))
623 #define UNM_CRB_RPMX_4 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX4))
624 #define UNM_CRB_RPMX_5 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX5))
625 #define UNM_CRB_RPMX_6 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX6))
626 #define UNM_CRB_RPMX_7 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX7))
627 #define UNM_CRB_SQM_MD_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS0))
628 #define UNM_CRB_SQM_MD_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS1))
629 #define UNM_CRB_SQM_MD_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS2))
630 #define UNM_CRB_SQM_MD_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS3))
631 #define UNM_CRB_SQM_NET_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN0))
632 #define UNM_CRB_SQM_NET_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN1))
633 #define UNM_CRB_SQM_NET_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN2))
634 #define UNM_CRB_SQM_NET_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN3))
635 #define UNM_CRB_SRE (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SRE))
636 #define UNM_CRB_TIMER (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_TIMR))
637 #define UNM_CRB_XDMA (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_XDMA))
638 #define UNM_CRB_I2C0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C0))
639 #define UNM_CRB_I2C1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C1))
640 #define UNM_CRB_OCM0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_OCM0))
641 #define UNM_CRB_SMB (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SMB))
642
643 #define UNM_CRB_MAX (UNM_PCI_CRB_WINDOW(64))
644
645 /*
646 * ====================== BASE ADDRESSES ON-CHIP ======================
647 * Base addresses of major components on-chip.
648 * ====================== BASE ADDRESSES ON-CHIP ======================
649 */
650 #define UNM_ADDR_DDR_NET 0x0000000000000000
651 #define UNM_ADDR_DDR_NET_MAX 0x000000000fffffff
652
653 /*
654 * Imbus address bit used to indicate a host address. This bit is
655 * eliminated by the pcie bar and bar select before presentation
656 * over pcie.
657 */
658 /* host memory via IMBUS */
659 #define NX_P2_ADDR_PCIE 0x0000000800000000
660 #define NX_P3_ADDR_PCIE 0x0000008000000000
661 #define UNM_ADDR_PCIE_MAX 0x0000000FFFFFFFFF
662 #define UNM_ADDR_OCM0 0x0000000200000000
663 #define UNM_ADDR_OCM0_MAX 0x00000002000fffff
664 #define UNM_ADDR_OCM1 0x0000000200400000
665 #define UNM_ADDR_OCM1_MAX 0x00000002004fffff
666 #define UNM_ADDR_QDR_NET 0x0000000300000000
667
668 #define NX_P2_ADDR_QDR_NET_MAX 0x00000003001fffff
669 #define NX_P3_ADDR_QDR_NET_MAX 0x0000000303ffffff
670 /*
671 * The ifdef at the bottom should go. All drivers should start using the above
672 * 2 defines.
673 */
674 #ifdef P3
675 #define UNM_ADDR_QDR_NET_MAX (NX_P3_ADDR_QDR_NET_MAX)
676 #else
677 #define UNM_ADDR_QDR_NET_MAX (NX_P2_ADDR_QDR_NET_MAX)
678 #endif
679
680 #define D3_CRB_REG_FUN0 (UNM_PCIX_PS_REG(0x0084))
681 #define D3_CRB_REG_FUN1 (UNM_PCIX_PS_REG(0x1084))
682 #define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084))
683 #define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084))
684
685
686 #define ISR_I2Q_CLR_PCI_LO (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_LO))
687 #define ISR_I2Q_CLR_PCI_HI (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_HI))
688 #define UNM_PCI_ARCH_CRB_BASE (UNM_PCI_DIRECT_CRB)
689
690 #define UNM_PCI_MAPSIZE 128 /* we're mapping 128MB of mem on PCI bus */
691 #define UNM_PCI_DDR_NET 0x00000000
692 #define UNM_PCI_DDR_NET_MAX 0x01ffffff
693 #define UNM_PCI_DDR_MD 0x02000000
694 #define UNM_PCI_DDR_MD_MAX 0x03ffffff
695 #define UNM_PCI_QDR_NET 0x04000000
696 #define UNM_PCI_QDR_NET_MAX 0x043fffff
697 #define UNM_PCI_DIRECT_CRB 0x04400000
698 #define UNM_PCI_DIRECT_CRB_MAX 0x047fffff
699 #define UNM_PCI_CAMQM 0x04800000
700 #define UNM_PCI_CAMQM_MAX 0x04ffffff
701 #define UNM_PCI_OCM0 0x05000000
702 #define UNM_PCI_OCM0_MAX 0x050fffff
703 #define UNM_PCI_OCM1 0x05100000
704 #define UNM_PCI_OCM1_MAX 0x051fffff
705 #define UNM_PCI_CRBSPACE 0x06000000
706 #define UNM_PCI_CRBSPACE_MAX 0x07ffffff
707 #define UNM_PCI_128MB_SIZE 0x08000000
708 #define UNM_PCI_32MB_SIZE 0x02000000
709 #define UNM_PCI_2MB_SIZE 0x00200000
710
711 /*
712 * Definitions relating to access/control of the Network Interface Unit
713 * h/w block.
714 */
715 /*
716 * Configuration registers.
717 */
718 #define UNM_NIU_MODE (UNM_CRB_NIU + 0x00000)
719
720 /*
721 * Register offsets for MN
722 */
723 #define MIU_CONTROL (0x000)
724 #define MIU_TAG (0x004)
725 #define MIU_TEST_AGT_CTRL (0x090)
726 #define MIU_TEST_AGT_ADDR_LO (0x094)
727 #define MIU_TEST_AGT_ADDR_HI (0x098)
728 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
729 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
730 #define MIU_TEST_AGT_WRDATA(i) (0x0a0 + (4 * (i)))
731 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
732 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
733 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
734 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
735 #define MIU_TEST_AGT_RDDATA_UPPER_LO (0x0b8)
736 #define MIU_TEST_AGT_RDDATA_UPPER_HI (0x0bc)
737 #define MIU_TEST_AGT_RDDATA(i) (0x0a8 + (4 * (i)))
738 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
739 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
740
741 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
742 #define MIU_TA_CTL_START 1
743 #define MIU_TA_CTL_ENABLE 2
744 #define MIU_TA_CTL_WRITE 4
745 #define MIU_TA_CTL_BUSY 8
746
747 #define SIU_TEST_AGT_CTRL (0x060)
748 #define SIU_TEST_AGT_ADDR_LO (0x064)
749 #define SIU_TEST_AGT_ADDR_HI (0x078)
750 #define SIU_TEST_AGT_WRDATA_LO (0x068)
751 #define SIU_TEST_AGT_WRDATA_HI (0x06c)
752 #define SIU_TEST_AGT_WRDATA(i) (0x068 + (4 * (i)))
753 #define SIU_TEST_AGT_RDDATA_LO (0x070)
754 #define SIU_TEST_AGT_RDDATA_HI (0x074)
755 #define SIU_TEST_AGT_RDDATA(i) (0x070 + (4 * (i)))
756
757 #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
758 #define SIU_TEST_AGT_UPPER_ADDR(off) ((off) >> 22)
759 #define XG_LINK_UP 0x10
760
761
762 /* ====================== Configuration Constants ======================== */
763 #define UNM_NIU_PHY_WAITLEN 200000 /* 200ms delay in each loop */
764 #define UNM_NIU_PHY_WAITMAX 50 /* 10 seconds before we give up */
765 #define UNM_NIU_MAX_GBE_PORTS 4
766 #define UNM_NIU_MAX_XG_PORTS 2
767 #define MIN_CORE_CLK_SPEED 200
768 #define MAX_CORE_CLK_SPEED 400
769 #define ACCEPTABLE_CORE_CLK_RANGE(speed) ((speed >= MIN_CORE_CLK_SPEED) && \
770 (speed <= MAX_CORE_CLK_SPEED))
771
772 #define P2_TICKS_PER_SEC 2048
773 #define P2_MIN_TICKS_PER_SEC (P2_TICKS_PER_SEC - 10)
774 #define P2_MAX_TICKS_PER_SEC (P2_TICKS_PER_SEC + 10)
775 #define CHECK_TICKS_PER_SEC(ticks) ((ticks >= P2_MIN_TICKS_PER_SEC) && \
776 (ticks <= P2_MAX_TICKS_PER_SEC))
777
778 /* CAM RAM */
779 #define UNM_CAM_RAM_BASE (UNM_CRB_CAM + 0x02000)
780 #define UNM_CAM_RAM(reg) (UNM_CAM_RAM_BASE + (reg))
781
782 #define UNM_PORT_MODE_NONE 0
783 #define UNM_PORT_MODE_XG 1
784 #define UNM_PORT_MODE_GB 2
785 #define UNM_PORT_MODE_802_3_AP 3
786 #define UNM_PORT_MODE_AUTO_NEG 4
787 #define UNM_PORT_MODE_AUTO_NEG_1G 5
788 #define UNM_PORT_MODE_AUTO_NEG_XG 6
789 #define UNM_PORT_MODE_ADDR (UNM_CAM_RAM(0x24))
790 #define UNM_FW_PORT_MODE_ADDR (UNM_CAM_RAM(0x28))
791 #define UNM_WOL_PORT_MODE (UNM_CAM_RAM(0x198))
792 #define UNM_RAM_COLD_BOOT (UNM_CAM_RAM(0x1fc))
793 #define UNM_BUS_DEV_NO (UNM_CAM_RAM(0x114))
794
795 #define NX_PEG_TUNE_MN_SPD_ZEROED 0x80000000
796 #define NX_BOOT_LOADER_MN_OTHER 0x100 /* other problem with DIMM */
797 #define NX_BOOT_LOADER_MN_NOT_DDR2 0x80 /* not a DDR2 DIMM */
798 #define NX_BOOT_LOADER_MN_NO_ECC 0x40 /* ECC not supported */
799 #define NX_BOOT_LOADER_MN_WRONG_CAS 0x20 /* CL 5 not supported */
800 #define NX_BOOT_LOADER_MN_NOT_REG 0x10 /* not a registered DIMM */
801 #define NX_BOOT_LOADER_MN_ISSUE 0xff00ffff
802 #define NX_PEG_TUNE_MN_PRESENT 0x1
803 #define NX_PEG_TUNE_CAPABILITY (UNM_CAM_RAM(0x02c))
804
805 #define UNM_ROM_LOCK_ID (UNM_CAM_RAM(0x100))
806 #define UNM_I2C_ROM_LOCK_ID (UNM_CAM_RAM(0x104))
807 #define UNM_PHY_LOCK_ID (UNM_CAM_RAM(0x120))
808 #define UNM_CRB_WIN_LOCK_ID (UNM_CAM_RAM(0x124))
809 #define CAM_RAM_DMA_WATCHDOG_CTRL 0x14 /* See dma_watchdog_ctrl_t */
810 #define UNM_EFUSE_CHIP_ID_HIGH (UNM_CAM_RAM(0x18))
811 #define UNM_EFUSE_CHIP_ID_LOW (UNM_CAM_RAM(0x1c))
812
813 #define UNM_FW_VERSION_MAJOR (UNM_CAM_RAM(0x150))
814 #define UNM_FW_VERSION_MINOR (UNM_CAM_RAM(0x154))
815 #define UNM_FW_VERSION_SUB (UNM_CAM_RAM(0x158))
816 #define UNM_TCP_FW_VERSION_MAJOR_ADDR (UNM_CAM_RAM(0x15c))
817 #define UNM_TCP_FW_VERSION_MINOR_ADDR (UNM_CAM_RAM(0x160))
818 #define UNM_TCP_FW_VERSION_SUB_ADDR (UNM_CAM_RAM(0x164))
819 #define UNM_FW_VERSION_BUILD (UNM_CAM_RAM(0x168))
820 #define UNM_PCIE_REG(reg) (UNM_CRB_PCIE + (reg))
821
822 #define PCIE_DCR (0x00d8)
823 #define PCIE_DB_DATA2 (0x10070)
824 #define PCIE_DB_CTRL (0x100a0)
825 #define PCIE_DB_ADDR (0x100a4)
826 #define PCIE_DB_DATA (0x100a8)
827 #define PCIE_IMBUS_CONTROL (0x101b8)
828 #define PCIE_SETUP_FUNCTION (0x12040)
829 #define PCIE_SETUP_FUNCTION2 (0x12048)
830 #define PCIE_TGT_SPLIT_CHICKEN (0x12080)
831 #define PCIE_CHICKEN3 (0x120c8)
832 #define PCIE_MAX_MASTER_SPLIT (0x14048)
833 #define PCIE_MAX_DMA_XFER_SIZE (0x1404c)
834 #define UNM_WOL_WAKE (UNM_CAM_RAM(0x180))
835 #define UNM_WOL_CONFIG_NV (UNM_CAM_RAM(0x184))
836 #define UNM_WOL_CONFIG (UNM_CAM_RAM(0x188))
837 #define UNM_PRE_WOL_RX_ENABLE (UNM_CAM_RAM(0x18c))
838 #define UNM_FW_RESET (UNM_CAM_RAM(0x138))
839 /*
840 * Following define address space withing PCIX CRB space to talk with
841 * devices on the storage side PCI bus.
842 */
843 #define PCIX_PS_MEM_SPACE (0x90000)
844
845 #define UNM_PCIX_PH_REG(reg) (UNM_CRB_PCIE + (reg))
846
847 /*
848 * Configuration registers. These are the same offsets on both host and
849 * storage side PCI blocks.
850 */
851 #define PCIX_PS_OP_ADDR_LO (0x10000) /* Used for PS PCI Memory access */
852 #define PCIX_PS_OP_ADDR_HI (0x10004) /* via CRB (PS side only) */
853
854 #define PCIX_MS_WINDOW (0x10204) /* UNUSED */
855
856 #define PCIX_CRB_WINDOW (0x10210)
857 #define PCIX_CRB_WINDOW_F0 (0x10210)
858 #define PCIX_CRB_WINDOW_F1 (0x10230)
859 #define PCIX_CRB_WINDOW_F2 (0x10250)
860 #define PCIX_CRB_WINDOW_F3 (0x10270)
861 #define PCIX_CRB_WINDOW_F4 (0x102ac)
862 #define PCIX_CRB_WINDOW_F5 (0x102bc)
863 #define PCIX_CRB_WINDOW_F6 (0x102cc)
864 #define PCIX_CRB_WINDOW_F7 (0x102dc)
865 #define PCIE_CRB_WINDOW_REG(func) (((func) < 4) ? \
866 (PCIX_CRB_WINDOW_F0 + (0x20 * (func))) : \
867 (PCIX_CRB_WINDOW_F4 + (0x10 * ((func) - 4))))
868
869 #define PCIX_MN_WINDOW (0x10200)
870 #define PCIX_MN_WINDOW_F0 (0x10200)
871 #define PCIX_MN_WINDOW_F1 (0x10220)
872 #define PCIX_MN_WINDOW_F2 (0x10240)
873 #define PCIX_MN_WINDOW_F3 (0x10260)
874 #define PCIX_MN_WINDOW_F4 (0x102a0)
875 #define PCIX_MN_WINDOW_F5 (0x102b0)
876 #define PCIX_MN_WINDOW_F6 (0x102c0)
877 #define PCIX_MN_WINDOW_F7 (0x102d0)
878 #define PCIE_MN_WINDOW_REG(func) (((func) < 4) ? \
879 (PCIX_MN_WINDOW_F0 + (0x20 * (func))) : \
880 (PCIX_MN_WINDOW_F4 + (0x10 * ((func) - 4))))
881
882 #define PCIX_SN_WINDOW (0x10208)
883 #define PCIX_SN_WINDOW_F0 (0x10208)
884 #define PCIX_SN_WINDOW_F1 (0x10228)
885 #define PCIX_SN_WINDOW_F2 (0x10248)
886 #define PCIX_SN_WINDOW_F3 (0x10268)
887 #define PCIX_SN_WINDOW_F4 (0x102a8)
888 #define PCIX_SN_WINDOW_F5 (0x102b8)
889 #define PCIX_SN_WINDOW_F6 (0x102c8)
890 #define PCIX_SN_WINDOW_F7 (0x102d8)
891 #define PCIE_SN_WINDOW_REG(func) (((func) < 4) ? \
892 (PCIX_SN_WINDOW_F0 + (0x20 * (func))) : \
893 (PCIX_SN_WINDOW_F4 + (0x10 * ((func) - 4))))
894
895 #define UNM_PCIX_PS_REG(reg) (UNM_CRB_PCIX_MD + (reg))
896 #define UNM_PCIX_PS2_REG(reg) (UNM_CRB_PCIE2 + (reg))
897 #define MANAGEMENT_COMMAND_REG (UNM_CRB_PCIE + (4))
898
899 #define UNM_PH_INT_MASK (UNM_CRB_PCIE + PCIX_INT_MASK)
900
901 /*
902 * Definitions relating to access/control of the I2Q h/w block.
903 */
904 /*
905 * Configuration registers.
906 */
907 #define UNM_I2Q_CONFIG (UNM_CRB_I2Q + 0x00000)
908 #define UNM_I2Q_ENA_PCI_LO (UNM_CRB_I2Q + 0x00010)
909 #define UNM_I2Q_ENA_PCI_HI (UNM_CRB_I2Q + 0x00014)
910 #define UNM_I2Q_ENA_CASPER_LO (UNM_CRB_I2Q + 0x00018)
911 #define UNM_I2Q_ENA_CASPER_HI (UNM_CRB_I2Q + 0x0001c)
912 #define UNM_I2Q_ENA_QM_LO (UNM_CRB_I2Q + 0x00020)
913 #define UNM_I2Q_ENA_QM_HI (UNM_CRB_I2Q + 0x00024)
914 #define UNM_I2Q_CLR_PCI_LO (UNM_CRB_I2Q + 0x00030)
915 #define UNM_I2Q_CLR_PCI_HI (UNM_CRB_I2Q + 0x00034)
916 #define UNM_I2Q_CLR_CASPER_LO (UNM_CRB_I2Q + 0x00038)
917 #define UNM_I2Q_CLR_CASPER_HI (UNM_CRB_I2Q + 0x0003c)
918 #define UNM_I2Q_MSG_HDR_LO(I) (UNM_CRB_I2Q + 0x00100 + (I) * 0x8)
919 #define UNM_I2Q_MSG_HDR_HI(I) (UNM_CRB_I2Q + 0x00104 + (I) * 0x8)
920
921 #ifdef PCIX
922 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_HOST + 0x20000 + ((U) << 16))
923 #else
924 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_MD + 0x20000 + ((U) << 6))
925 #endif
926 #define UNM_DMA_COMMAND(U) (UNM_DMA_BASE(U) + 0x00008)
927
928 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
929 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
930 #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */
931 #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */
932 #define PCIE_SEM4_LOCK (0x1c020) /* I2C lock */
933 #define PCIE_SEM4_UNLOCK (0x1c024) /* I2C unlock */
934 #define PCIE_SEM5_LOCK (0x1c028) /* API lock */
935 #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */
936 #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */
937 #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */
938 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
939 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock */
940
941 #define PCIE_PS_STRAP_RESET (0x18000)
942
943 #define M25P_INSTR_WREN 0x06
944 #define M25P_INSTR_RDSR 0x05
945 #define M25P_INSTR_PP 0x02
946 #define M25P_INSTR_SE 0xd8
947 #define CAM_RAM_P2I_ENABLE 0xc
948 #define CAM_RAM_P2D_ENABLE 0x8
949 #define PCIX_IMBTAG (0x18004)
950
951 #define CAM_RAM_PEG_ENABLES 0x4
952
953 /*
954 * The PCI VendorID and DeviceID for our board.
955 */
956 #define PCI_VENDOR_ID_NX8021 0x4040
957 #define PCI_DEVICE_ID_NX8021_FC 0x0101
958
959 /* ISP 3031 related declarations */
960
961 #define NX_MSIX_MEM_REGION_THRESHOLD 0x2000000
962 #define UNM_MSIX_TBL_SPACE 8192
963 #define UNM_PCI_REG_MSIX_TBL 0x44
964 #define NX_PCI_MSIX_CONTROL 0x40
965
966 typedef struct {
967 uint32_t valid;
968 uint32_t start_128M;
969 uint32_t end_128M;
970 uint32_t start_2M;
971 } crb_128M_2M_sub_block_map_t;
972
973 typedef struct {
974 crb_128M_2M_sub_block_map_t sub_block[16];
975 } crb_128M_2M_block_map_t;
976
977 struct crb_addr_pair {
978 uint32_t addr;
979 uint32_t data;
980 };
981
982 #define ADDR_ERROR ((unsigned long) 0xffffffff)
983 #define MAX_CTL_CHECK 1000
984
985 /*
986 * ************************************************************************
987 * PCI related defines.
988 * ************************************************************************
989 */
990
991 /*
992 * Interrupt related defines.
993 */
994 #define PCIX_TARGET_STATUS (0x10118)
995 #define PCIX_TARGET_STATUS_F1 (0x10160)
996 #define PCIX_TARGET_STATUS_F2 (0x10164)
997 #define PCIX_TARGET_STATUS_F3 (0x10168)
998 #define PCIX_TARGET_STATUS_F4 (0x10360)
999 #define PCIX_TARGET_STATUS_F5 (0x10364)
1000 #define PCIX_TARGET_STATUS_F6 (0x10368)
1001 #define PCIX_TARGET_STATUS_F7 (0x1036c)
1002
1003 #define PCIX_TARGET_MASK (0x10128)
1004 #define PCIX_TARGET_MASK_F1 (0x10170)
1005 #define PCIX_TARGET_MASK_F2 (0x10174)
1006 #define PCIX_TARGET_MASK_F3 (0x10178)
1007 #define PCIX_TARGET_MASK_F4 (0x10370)
1008 #define PCIX_TARGET_MASK_F5 (0x10374)
1009 #define PCIX_TARGET_MASK_F6 (0x10378)
1010 #define PCIX_TARGET_MASK_F7 (0x1037c)
1011
1012 /*
1013 * Message Signaled Interrupts
1014 */
1015 #define PCIX_MSI_F0 (0x13000)
1016 #define PCIX_MSI_F1 (0x13004)
1017 #define PCIX_MSI_F2 (0x13008)
1018 #define PCIX_MSI_F3 (0x1300c)
1019 #define PCIX_MSI_F4 (0x13010)
1020 #define PCIX_MSI_F5 (0x13014)
1021 #define PCIX_MSI_F6 (0x13018)
1022 #define PCIX_MSI_F7 (0x1301c)
1023 #define PCIX_MSI_F(FUNC) (0x13000 +((FUNC) * 4))
1024
1025 /*
1026 *
1027 */
1028 #define PCIX_INT_VECTOR (0x10100)
1029 #define PCIX_INT_MASK (0x10104)
1030
1031 /*
1032 * Interrupt state machine and other bits.
1033 */
1034 #define PCIE_MISCCFG_RC (0x1206c)
1035
1036
1037 #define ISR_INT_TARGET_STATUS (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS))
1038 #define ISR_INT_TARGET_STATUS_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
1039 #define ISR_INT_TARGET_STATUS_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
1040 #define ISR_INT_TARGET_STATUS_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
1041 #define ISR_INT_TARGET_STATUS_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
1042 #define ISR_INT_TARGET_STATUS_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
1043 #define ISR_INT_TARGET_STATUS_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
1044 #define ISR_INT_TARGET_STATUS_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
1045
1046 #define ISR_INT_TARGET_MASK (UNM_PCIX_PS_REG(PCIX_TARGET_MASK))
1047 #define ISR_INT_TARGET_MASK_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
1048 #define ISR_INT_TARGET_MASK_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
1049 #define ISR_INT_TARGET_MASK_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
1050 #define ISR_INT_TARGET_MASK_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
1051 #define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
1052 #define ISR_INT_TARGET_MASK_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
1053 #define ISR_INT_TARGET_MASK_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
1054
1055 #define ISR_INT_VECTOR (UNM_PCIX_PS_REG(PCIX_INT_VECTOR))
1056 #define ISR_INT_MASK (UNM_PCIX_PS_REG(PCIX_INT_MASK))
1057 #define ISR_INT_STATE_REG (UNM_PCIX_PS_REG(PCIE_MISCCFG_RC))
1058
1059 #define ISR_MSI_INT_TRIGGER(FUNC) (UNM_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
1060
1061
1062 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
1063 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
1064
1065 /*
1066 * PCI Interrupt Vector Values.
1067 */
1068 #define PCIX_INT_VECTOR_BIT_F0 0x0080
1069 #define PCIX_INT_VECTOR_BIT_F1 0x0100
1070 #define PCIX_INT_VECTOR_BIT_F2 0x0200
1071 #define PCIX_INT_VECTOR_BIT_F3 0x0400
1072 #define PCIX_INT_VECTOR_BIT_F4 0x0800
1073 #define PCIX_INT_VECTOR_BIT_F5 0x1000
1074 #define PCIX_INT_VECTOR_BIT_F6 0x2000
1075 #define PCIX_INT_VECTOR_BIT_F7 0x4000
1076
1077 #define NX_LEGACY_INTR_CONFIG \
1078 { \
1079 { \
1080 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
1081 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
1082 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
1083 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
1084 \
1085 { \
1086 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
1087 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
1088 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
1089 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
1090 \
1091 { \
1092 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
1093 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
1094 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
1095 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
1096 \
1097 { \
1098 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
1099 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
1100 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
1101 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
1102 \
1103 { \
1104 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
1105 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
1106 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
1107 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
1108 \
1109 { \
1110 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
1111 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
1112 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
1113 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
1114 \
1115 { \
1116 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
1117 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
1118 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
1119 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
1120 \
1121 { \
1122 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
1123 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
1124 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
1125 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
1126 }
1127
1128 #define BOOTLD_START 0x10000
1129 #define IMAGE_START 0x43000
1130
1131 /* Magic number to let user know flash is programmed */
1132 #define UNM_BDINFO_MAGIC 0x12345678
1133 #define FW_SIZE_OFFSET 0x3e840c
1134
1135 #define PCI_CAP_ID_GEN 0x10
1136 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */
1137 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
1138 #define PCI_EXP_LNKSTA 18 /* Link Status */
1139 #define MAX_CRB_XFORM 60
1140 #define MTU_FUDGE_FACTOR 100
1141
1142 #define crb_addr_transform(name) \
1143 (crb_addr_xform[UNM_HW_PX_MAP_CRB_##name] = \
1144 UNM_HW_CRB_HUB_AGT_ADR_##name << 20)
1145
1146 #define MASK(n) ((1ULL << (n)) - 1)
1147 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
1148 /* 64K? */
1149 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
1150
1151 #define MS_WIN(addr) (addr & 0x0ffc0000)
1152 #define UNM_PCI_MN_2M (0)
1153 #define UNM_PCI_MS_2M (0x80000)
1154 #define UNM_PCI_OCM0_2M (0xc0000)
1155 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
1156 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
1157
1158 #define UNM_BOARDTYPE 0x4008
1159 #define UNM_BOARDNUM 0x400c
1160 #define UNM_CHIPNUM 0x4010
1161
1162 /* CRB window related */
1163 #define CRB_BLK(off) ((off >> 20) & 0x3f)
1164 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
1165 #define CRB_WINDOW_2M (0x130060)
1166 #define UNM_PCI_CAMQM_2M_END (0x04800800UL)
1167 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | \
1168 ((off) & 0xf0000))
1169 #define UNM_PCI_CAMQM_2M_BASE (0x000ff800UL)
1170 #define CRB_INDIRECT_2M (0x1e0000UL)
1171 /* #define ADDR_ERROR ((unsigned long ) 0xffffffff) */
1172
1173 /* PCI Windowing for DDR regions. */
1174 #define QL_8021_ADDR_IN_RANGE(addr, low, high) \
1175 (((addr) <= (high)) && ((int64_t)(addr) >= (low)))
1176
1177 #define CRB_WIN_LOCK_TIMEOUT 100000000
1178 #define ROM_LOCK_TIMEOUT 100
1179 #define ROM_MAX_TIMEOUT 100
1180 #define IDC_LOCK_TIMEOUT 100000000
1181
1182 /*
1183 * IDC parameters are defined in "user area" in the flash
1184 */
1185 #define ROM_DEV_INIT_TIMEOUT 0x3e885c
1186 #define ROM_DRV_RESET_ACK_TIMEOUT 0x3e8860
1187
1188 /* ****************************************************************** */
1189 /* ******************* NetXen MiniDump Defines ********************** */
1190 /* ****************************************************************** */
1191
1192 /*
1193 * Get MBC_GET_DUMP_TEMPLATE Command Options
1194 */
1195 #define GTO_TEMPLATE_SIZE 0
1196 #define GTO_TEMPLATE 1
1197
1198 /*
1199 * Entry Type Defines
1200 */
1201 #define RDNOP 0
1202 #define RDCRB 1
1203 #define RDMUX 2
1204 #define QUEUE 3
1205 #define BOARD 4
1206 #define RDSRE 5
1207 #define RDOCM 6
1208 #define PREGS 7
1209 #define L1DTG 8
1210 #define L1ITG 9
1211 #define CACHE 10
1212 #define L1DAT 11
1213 #define L1INS 12
1214 #define RDSTK 13
1215 #define RDCON 14
1216 #define L2DTG 21
1217 #define L2ITG 22
1218 #define L2DAT 23
1219 #define L2INS 24
1220 #define RDOC3 25
1221 #define MEMBK 32
1222 #define RDROM 71
1223 #define RDMEM 72
1224 #define INFOR 81
1225 #define CNTRL 98
1226 #define TLHDR 99
1227 #define RDEND 255
1228 #define PRIMQ 103
1229 #define SQG2Q 104
1230 #define SQG3Q 105
1231 #define ISCSI_EVENT_LOG 201
1232
1233 /*
1234 * Minidump Template Header
1235 * Parts of the template header can be modified by the driver.
1236 * These include the saved_state_array, capture_debug_level, driver_timestamp
1237 * The driver_info_wordX is used to add info about the drivers environment.
1238 * It is important that drivers add identication and system info in these
1239 * fields.
1240 */
1241
1242 #define QL_DBG_STATE_ARRAY_LEN 16
1243 #define QL_DBG_CAP_SIZE_ARRAY_LEN 8
1244 #define QL_DBG_RSVD_ARRAY_LEN 8
1245
1246 typedef struct md_template_hdr {
1247 uint32_t entry_type;
1248 uint32_t first_entry_offset;
1249 uint32_t size_of_template;
1250 uint32_t capture_debug_level;
1251 uint32_t num_of_entries;
1252 uint32_t version;
1253 uint32_t driver_timestamp;
1254 uint32_t checksum;
1255 uint32_t driver_capture_mask;
1256 uint32_t driver_info_word1;
1257 uint32_t driver_info_word2;
1258 uint32_t driver_info_word3;
1259 uint32_t saved_state_array[QL_DBG_STATE_ARRAY_LEN];
1260 uint32_t capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN];
1261
1262 /* markers_array used to capture some special locations on board */
1263 uint32_t markers_array[QL_DBG_RSVD_ARRAY_LEN];
1264 uint32_t num_of_free_entries; /* For internal use */
1265 uint32_t free_entry_offset; /* For internal use */
1266 uint32_t total_table_size; /* For internal use */
1267 uint32_t bkup_table_offset; /* For internal use */
1268 } md_template_hdr_t;
1269
1270 /*
1271 * Driver Flags
1272 */
1273 #define QL_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
1274 #define QL_DBG_SIZE_ERR_FLAG 0x40 /* entry siz vs capture siz mismatch */
1275
1276 /*
1277 * Minidump Entry Header
1278 */
1279 typedef struct md_entry_hdr {
1280 uint32_t entry_type;
1281 uint32_t entry_size;
1282 uint32_t entry_capture_size;
1283 union {
1284 struct {
1285 #ifdef _BIG_ENDIAN
1286 uint8_t driver_flags;
1287 uint8_t driver_code;
1288 uint8_t entry_code;
1289 uint8_t entry_capture_mask;
1290 #else
1291 uint8_t entry_capture_mask;
1292 uint8_t entry_code;
1293 uint8_t driver_code;
1294 uint8_t driver_flags;
1295 #endif
1296 } ecw;
1297 uint32_t entry_ctrl_word;
1298 } a;
1299 } md_entry_hdr_t;
1300
1301 /*
1302 * Minidump Entry Including Header
1303 */
1304 typedef struct md_entry {
1305 md_entry_hdr_t h;
1306 uint32_t entry_data00;
1307 uint32_t entry_data01;
1308 uint32_t entry_data02;
1309 uint32_t entry_data03;
1310 uint32_t entry_data04;
1311 uint32_t entry_data05;
1312 uint32_t entry_data06;
1313 uint32_t entry_data07;
1314 } md_entry_t;
1315
1316 /*
1317 * Minidump Read CRB Entry Header
1318 */
1319 typedef struct md_entry_rdcrb {
1320 md_entry_hdr_t h;
1321 uint32_t addr;
1322 union {
1323 struct {
1324 #ifdef _BIG_ENDIAN
1325 uint8_t rsvd_1[2];
1326 uint8_t rsvd_0;
1327 uint8_t addr_stride;
1328 #else
1329 uint8_t addr_stride;
1330 uint8_t rsvd_0;
1331 uint8_t rsvd_1[2];
1332 #endif
1333 } ac;
1334 uint32_t addr_cntrl;
1335 } a;
1336 uint32_t data_size;
1337 uint32_t op_count;
1338 uint32_t rsvd_2;
1339 uint32_t rsvd_3;
1340 uint32_t rsvd_4;
1341 uint32_t rsvd_5;
1342 } md_entry_rdcrb_t;
1343
1344 /*
1345 * Minidump Cache Entry Header
1346 */
1347 typedef struct ql_md_entry_cache {
1348 md_entry_hdr_t h;
1349 uint32_t tag_reg_addr;
1350 union {
1351 struct {
1352 #ifdef _BIG_ENDIAN
1353 uint8_t init_tag_value[2];
1354 uint8_t tag_value_stride[2];
1355 #else
1356 uint8_t tag_value_stride[2];
1357 uint8_t init_tag_value[2];
1358 #endif
1359 } sac;
1360 uint32_t select_addr_cntrl;
1361 } a;
1362 uint32_t data_size;
1363 uint32_t op_count;
1364 uint32_t control_addr;
1365 union {
1366 struct {
1367 #ifdef _BIG_ENDIAN
1368 uint8_t poll_wait;
1369 uint8_t poll_mask;
1370 uint8_t write_value[2];
1371 #else
1372 uint8_t write_value[2];
1373 uint8_t poll_mask;
1374 uint8_t poll_wait;
1375 #endif
1376 } cv;
1377 uint32_t control_value;
1378 } b;
1379 uint32_t read_addr;
1380 union {
1381 struct {
1382 #ifdef _BIG_ENDIAN
1383 uint8_t rsvd_1[2];
1384 uint8_t read_addr_cnt;
1385 uint8_t read_addr_stride;
1386 #else
1387 uint8_t read_addr_stride;
1388 uint8_t read_addr_cnt;
1389 uint8_t rsvd_1[2];
1390 #endif
1391 } rac;
1392 uint32_t read_addr_cntrl;
1393 } c;
1394 } md_entry_cache_t;
1395
1396 /*
1397 * Minidump Read OCM Entry Header
1398 */
1399 typedef struct md_entry_rdocm {
1400 md_entry_hdr_t h;
1401 uint32_t rsvd_0;
1402 uint32_t rsvd_1;
1403 uint32_t data_size;
1404 uint32_t op_count;
1405 uint32_t rsvd_2;
1406 uint32_t rsvd_3;
1407 uint32_t read_addr;
1408 uint32_t read_addr_stride;
1409 } md_entry_rdocm_t;
1410
1411 /*
1412 * Minidump Read MEM Entry Header
1413 */
1414 typedef struct md_entry_rdmem {
1415 md_entry_hdr_t h;
1416 uint32_t rsvd_0[6];
1417 uint32_t read_addr;
1418 uint32_t read_data_size;
1419 } md_entry_rdmem_t;
1420 /*
1421 * Minidump MIU AGENT ADDRESSES.
1422 */
1423 #define MD_TA_CTL_ENABLE 0x2
1424 #define MD_TA_CTL_START 0x1
1425 #define MD_TA_CTL_BUSY 0x8
1426 #define MD_TA_CTL_CHECK 1000
1427 #define MD_MIU_TEST_AGT_CTRL 0x41000090
1428 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1429 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1430 #define MD_MIU_TEST_AGT_RDDATA_0_31 0x410000A8
1431 #define MD_MIU_TEST_AGT_RDDATA_32_63 0x410000AC
1432 #define MD_MIU_TEST_AGT_RDDATA_64_95 0x410000B8
1433 #define MD_MIU_TEST_AGT_RDDATA_96_127 0x410000BC
1434 #define MD_MIU_TEST_AGT_WRDATA_0_31 0x410000A0
1435 #define MD_MIU_TEST_AGT_WRDATA_32_63 0x410000A4
1436 #define MD_MIU_TEST_AGT_WRDATA_64_95 0x410000B0
1437 #define MD_MIU_TEST_AGT_WRDATA_96_127 0x410000B4
1438
1439 /*
1440 * Minidump Read ROM Entry Header
1441 */
1442 typedef struct md_entry_rdrom {
1443 md_entry_hdr_t h;
1444 uint32_t rsvd_0[6];
1445 uint32_t read_addr;
1446 uint32_t read_data_size;
1447 } md_entry_rdrom_t;
1448 /*
1449 * Minidump ROM Read Address
1450 */
1451 #define MD_DIRECT_ROM_WINDOW 0x42110030
1452 #define MD_DIRECT_ROM_READ_BASE 0x42150000
1453
1454 /*
1455 * Minidump Read MUX Entry Header
1456 */
1457 typedef struct md_entry_mux {
1458 md_entry_hdr_t h;
1459 uint32_t select_addr;
1460 union {
1461 struct {
1462 uint32_t rsvd_0;
1463 } sac;
1464 uint32_t select_addr_cntrl;
1465 } a;
1466 uint32_t data_size;
1467 uint32_t op_count;
1468 uint32_t select_value;
1469 uint32_t select_value_stride;
1470 uint32_t read_addr;
1471 uint32_t rsvd_1;
1472 } md_entry_mux_t;
1473
1474 /*
1475 * Minidump Read QUEUE Entry Header
1476 */
1477 typedef struct md_entry_queue {
1478 md_entry_hdr_t h;
1479 uint32_t select_addr;
1480 union {
1481 struct {
1482 #ifdef _BIG_ENDIAN
1483 uint8_t rsvd_0[2];
1484 uint8_t queue_id_stride[2];
1485 #else
1486 uint8_t queue_id_stride[2];
1487 uint8_t rsvd_0[2];
1488 #endif
1489 } sac;
1490 uint32_t select_addr_cntrl;
1491 } a;
1492 uint32_t data_size;
1493 uint32_t op_count;
1494 uint32_t rsvd_1;
1495 uint32_t rsvd_2;
1496 uint32_t read_addr;
1497 union {
1498 struct {
1499 #ifdef _BIG_ENDIAN
1500 uint8_t rsvd_3[2];
1501 uint8_t read_addr_cnt;
1502 uint8_t read_addr_stride;
1503 #else
1504 uint8_t read_addr_stride;
1505 uint8_t read_addr_cnt;
1506 uint8_t rsvd_3[2];
1507 #endif
1508 } rac;
1509 uint32_t read_addr_cntrl;
1510 } b;
1511 } md_entry_queue_t;
1512
1513 /*
1514 * Minidump Control Entry Header
1515 */
1516 typedef struct md_entry_cntrl {
1517 md_entry_hdr_t h;
1518 uint32_t addr;
1519 union {
1520 struct {
1521 #ifdef _BIG_ENDIAN
1522 uint8_t poll_timeout[2];
1523 uint8_t state_index_a;
1524 uint8_t addr_stride;
1525 #else
1526 uint8_t addr_stride;
1527 uint8_t state_index_a;
1528 uint8_t poll_timeout[2];
1529 #endif
1530 } ac;
1531 uint32_t addr_cntrl;
1532 } a;
1533 uint32_t data_size;
1534 uint32_t op_count;
1535 union {
1536 struct {
1537 #ifdef _BIG_ENDIAN
1538 uint8_t shr;
1539 uint8_t shl;
1540 uint8_t state_index_v;
1541 uint8_t opcode;
1542 #else
1543 uint8_t opcode;
1544 uint8_t state_index_v;
1545 uint8_t shl;
1546 uint8_t shr;
1547 #endif
1548 } cv;
1549 uint32_t control_value;
1550 } b;
1551 uint32_t value_1;
1552 uint32_t value_2;
1553 uint32_t value_3;
1554 } md_entry_cntrl_t;
1555
1556 /*
1557 * Opcodes for Control Entries.
1558 * These Flags are bit fields.
1559 */
1560 #define QL_DBG_OPCODE_WR 0x01
1561 #define QL_DBG_OPCODE_RW 0x02
1562 #define QL_DBG_OPCODE_AND 0x04
1563 #define QL_DBG_OPCODE_OR 0x08
1564 #define QL_DBG_OPCODE_POLL 0x10
1565 #define QL_DBG_OPCODE_RDSTATE 0x20
1566 #define QL_DBG_OPCODE_WRSTATE 0x40
1567 #define QL_DBG_OPCODE_MDSTATE 0x80
1568
1569 /*
1570 * Global Data in ql_nx.c source file.
1571 */
1572
1573 /*
1574 * Global Function Prototypes in ql_nx.c source file.
1575 */
1576 void ql_8021_wr_32(ql_adapter_state_t *, uint64_t, uint32_t);
1577 void ql_8021_rd_32(ql_adapter_state_t *, uint64_t, uint32_t *);
1578 void ql_8021_reset_chip(ql_adapter_state_t *);
1579 int ql_8021_fw_reload(ql_adapter_state_t *);
1580 void ql_8021_clr_hw_intr(ql_adapter_state_t *);
1581 void ql_8021_clr_fw_intr(ql_adapter_state_t *);
1582 void ql_8021_enable_intrs(ql_adapter_state_t *);
1583 void ql_8021_disable_intrs(ql_adapter_state_t *);
1584 void ql_8021_update_crb_int_ptr(ql_adapter_state_t *);
1585 int ql_8021_rom_read(ql_adapter_state_t *, uint32_t, uint32_t *);
1586 int ql_8021_rom_write(ql_adapter_state_t *, uint32_t, uint32_t);
1587 int ql_8021_rom_erase(ql_adapter_state_t *, uint32_t);
1588 int ql_8021_rom_wrsr(ql_adapter_state_t *, uint32_t);
1589 void ql_8021_set_drv_active(ql_adapter_state_t *);
1590 void ql_8021_clr_drv_active(ql_adapter_state_t *);
1591 int ql_8021_idc_handler(ql_adapter_state_t *, uint32_t);
1592 void ql_8021_wr_req_in(ql_adapter_state_t *, uint32_t);
1593 void ql_8021_idc_poll(ql_adapter_state_t *);
1594 int ql_8021_reset_fw(ql_adapter_state_t *);
1595 int ql_8021_fw_chk(ql_adapter_state_t *);
1596 int ql_8021_get_md_template(ql_adapter_state_t *);
1597
1598 #ifdef __cplusplus
1599 }
1600 #endif
1601
1602 #endif /* _QL_NX_H */