1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2010 QLogic Corporation. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _QL_NX_H
28 #define _QL_NX_H
29
30 /*
31 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
32 *
33 * ***********************************************************************
34 * * **
35 * * NOTICE **
36 * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
37 * * ALL RIGHTS RESERVED **
38 * * **
39 * ***********************************************************************
40 *
41 */
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 #define NX_P3_A0 0x30
48 #define NX_P3_A2 0x32
49 #define NX_P3_B0 0x40
50 #define NX_P3_B1 0x41
51 #define NX_P3_B2 0x42
52 #define NX_P3P_A0 0x50
53 #define NX_P3P_B0 0x54
54
55 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
56 #define NX_IS_REVISION_P3PLUS(REVISION) (REVISION >= NX_P3P_A0)
57
58 /*
59 * Following are the states of the Phantom. Phantom will set them and
60 * Host will read to check if the fields are correct.
61 */
62 #define PHAN_INITIALIZE_START 0xff00
63 #define PHAN_INITIALIZE_FAILED 0xffff
64 #define PHAN_INITIALIZE_COMPLETE 0xff01
65
66 /* Host writes the following to notify that it has done the init-handshake */
67 #define PHAN_INITIALIZE_ACK 0xf00f
68 #define PHAN_PEG_RCV_INITIALIZED 0xff01
69 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
70
71 /* CRB_RELATED */
72 #define NIC_CRB_BASE (UNM_CAM_RAM(0x200))
73 #define NIC_CRB_BASE_2 (UNM_CAM_RAM(0x700))
74 #define UNM_NIC_REG(X) (NIC_CRB_BASE + (X))
75 #define UNM_NIC_REG_2(X) (NIC_CRB_BASE_2 + (X))
76
77 #define CRB_CUT_THRU_PAGE_SIZE (UNM_CAM_RAM(0x170))
78
79 #define CRB_DEV_PARTITION_INFO (UNM_CAM_RAM(0x14c))
80 #define CRB_DEV_STATE (UNM_CAM_RAM(0x140))
81 #define CRB_DRV_IDC_VERSION (UNM_CAM_RAM(0x174))
82 #define CRB_DRV_ACTIVE (UNM_CAM_RAM(0x138))
83 #define CRB_DRV_STATE (UNM_CAM_RAM(0x144))
84 #define CRB_DRV_SCRATCH (UNM_CAM_RAM(0x148))
85 #define CRB_FCOE_PORT_0_REQIN (UNM_CAM_RAM(0x1b8))
86 #define CRB_FCOE_PORT_1_REQIN (UNM_CAM_RAM(0x1bc))
87
88 /* Every driver should use these Device State */
89 #define NX_DEV_COLD 1
90 #define NX_DEV_INITIALIZING 2
91 #define NX_DEV_READY 3
92 #define NX_DEV_NEED_RESET 4
93 #define NX_DEV_NEED_QUIESCENT 5
94 #define NX_DEV_FAILED 6
95 #define NX_DEV_QUIESCENT 7
96
97 #define NX_IDC_VERSION 0x1
98
99 #define CRB_CMD_PRODUCER_OFFSET (UNM_NIC_REG(0x08))
100 #define CRB_CMD_CONSUMER_OFFSET (UNM_NIC_REG(0x0c))
101 #define CRB_PAUSE_ADDR_LO (UNM_NIC_REG(0x10)) /* C0 EPG BUG */
102 #define CRB_PAUSE_ADDR_HI (UNM_NIC_REG(0x14))
103 #define NX_CDRP_CRB_OFFSET (UNM_NIC_REG(0x18))
104 #define NX_ARG1_CRB_OFFSET (UNM_NIC_REG(0x1c))
105 #define NX_ARG2_CRB_OFFSET (UNM_NIC_REG(0x20))
106 #define NX_ARG3_CRB_OFFSET (UNM_NIC_REG(0x24))
107 #define NX_SIGN_CRB_OFFSET (UNM_NIC_REG(0x28))
108 #define CRB_CMDPEG_CMDRING (UNM_NIC_REG(0x38))
109 #define CRB_HOST_DUMMY_BUF_ADDR_HI (UNM_NIC_REG(0x3c))
110 #define CRB_HOST_DUMMY_BUF_ADDR_LO (UNM_NIC_REG(0x40))
111 #define CRB_CMDPEG_STATE (UNM_NIC_REG(0x50))
112 #define BOOT_LOADER_DIMM_STATUS (UNM_NIC_REG(0x54))
113 #define CRB_GLOBAL_INT_COAL (UNM_NIC_REG(0x64)) /* intrt coalescing */
114 #define CRB_INT_COAL_MODE (UNM_NIC_REG(0x68))
115 #define CRB_MAX_RCV_BUFS (UNM_NIC_REG(0x6c))
116 #define CRB_TX_INT_THRESHOLD (UNM_NIC_REG(0x70))
117 #define CRB_RX_PKT_TIMER (UNM_NIC_REG(0x74))
118 #define CRB_TX_PKT_TIMER (UNM_NIC_REG(0x78))
119 #define CRB_RX_PKT_CNT (UNM_NIC_REG(0x7c))
120 #define CRB_RX_TMR_CNT (UNM_NIC_REG(0x80))
121 #define CRB_RCV_INTR_COUNT (UNM_NIC_REG(0x84))
122 #define CRB_XG_STATE (UNM_NIC_REG(0x94)) /* XG Link status */
123 #define CRB_XG_STATE_P3 (UNM_NIC_REG(0x98)) /* XG PF Link status */
124 #define CRB_TX_STATE (UNM_NIC_REG(0xac)) /* Debug -performance */
125 #define CRB_TX_COUNT (UNM_NIC_REG(0xb0))
126 #define CRB_RX_STATE (UNM_NIC_REG(0xb4))
127 #define CRB_RX_PERF_DEBUG_1 (UNM_NIC_REG(0xb8))
128 #define CRB_RX_LRO_CONTROL (UNM_NIC_REG(0xbc)) /* LRO On/OFF */
129 #define CRB_MPORT_MODE (UNM_NIC_REG(0xc4)) /* Multiport Mode */
130 #define CRB_DMA_SHIFT (UNM_NIC_REG(0xcc)) /* DMA mask extension */
131 #define CRB_INT_VECTOR (UNM_NIC_REG(0xd4))
132 #define CRB_PF_LINK_SPEED_1 (UNM_NIC_REG(0xe8))
133 #define CRB_PF_LINK_SPEED_2 (UNM_NIC_REG(0xec))
134 #define CRB_PF_MAX_LINK_SPEED_1 (UNM_NIC_REG(0xf0))
135 #define CRB_PF_MAX_LINK_SPEED_2 (UNM_NIC_REG(0xf4))
136 #define CRB_HOST_DUMMY_BUF (UNM_NIC_REG(0xfc))
137
138 /* used for ethtool tests */
139 #define CRB_SCRATCHPAD_TEST (UNM_NIC_REG(0x280))
140
141 #define CRB_RCVPEG_STATE (UNM_NIC_REG(0x13c))
142
143 #define UNM_PEG_HALT_STATUS1 (UNM_CAM_RAM(0xa8))
144 #define UNM_PEG_HALT_STATUS2 (UNM_CAM_RAM(0xac))
145 #define UNM_PEG_ALIVE_COUNTER (UNM_CAM_RAM(0x0b0))
146 #define UNM_FW_CAPABILITIES_1 (UNM_CAM_RAM(0x128))
147
148 /* 12 registers to store MAC addresses for 8 PCI functions */
149 #define CRB_MAC_BLOCK_START (UNM_CAM_RAM(0x1c0))
150
151 #define CRB_CMD_PRODUCER_OFFSET_1 (UNM_NIC_REG(0x1ac))
152 #define CRB_CMD_CONSUMER_OFFSET_1 (UNM_NIC_REG(0x1b0))
153 #define CRB_TEMP_STATE (UNM_NIC_REG(0x1b4))
154 #define CRB_CMD_PRODUCER_OFFSET_2 (UNM_NIC_REG(0x1b8))
155 #define CRB_CMD_CONSUMER_OFFSET_2 (UNM_NIC_REG(0x1bc))
156
157 #define CRB_CMD_PRODUCER_OFFSET_3 (UNM_NIC_REG(0x1d0))
158 #define CRB_CMD_CONSUMER_OFFSET_3 (UNM_NIC_REG(0x1d4))
159 /* sw int status/mask registers */
160 #define CRB_SW_INT_MASK_OFFSET_0 0x1d8
161 #define CRB_SW_INT_MASK_OFFSET_1 0x1e0
162 #define CRB_SW_INT_MASK_OFFSET_2 0x1e4
163 #define CRB_SW_INT_MASK_OFFSET_3 0x1e8
164 #define CRB_SW_INT_MASK_OFFSET_4 0x450
165 #define CRB_SW_INT_MASK_OFFSET_5 0x454
166 #define CRB_SW_INT_MASK_OFFSET_6 0x458
167 #define CRB_SW_INT_MASK_OFFSET_7 0x45c
168 #define CRB_SW_INT_MASK_0 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0))
169 #define CRB_SW_INT_MASK_1 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1))
170 #define CRB_SW_INT_MASK_2 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2))
171 #define CRB_SW_INT_MASK_3 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3))
172 #define CRB_SW_INT_MASK_4 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4))
173 #define CRB_SW_INT_MASK_5 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5))
174 #define CRB_SW_INT_MASK_6 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6))
175 #define CRB_SW_INT_MASK_7 (UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7))
176
177 #define CRB_NIC_DEBUG_STRUCT_BASE (UNM_NIC_REG(0x288))
178
179 #define CRB_NIC_CAPABILITIES_HOST (UNM_NIC_REG(0x1a8))
180 #define CRB_NIC_CAPABILITIES_FW (UNM_NIC_REG(0x1dc))
181 #define CRB_NIC_MSI_MODE_HOST (UNM_NIC_REG(0x270))
182 #define CRB_NIC_MSI_MODE_FW (UNM_NIC_REG(0x274))
183
184 #define INTR_SCHEME_PERPORT 0x1
185 #define MSI_MODE_MULTIFUNC 0x1
186
187 #define CRB_EPG_QUEUE_BUSY_COUNT (UNM_NIC_REG(0x200))
188
189 #define CRB_V2P_0 (UNM_NIC_REG(0x290))
190 #define CRB_V2P_1 (UNM_NIC_REG(0x294))
191 #define CRB_V2P_2 (UNM_NIC_REG(0x298))
192 #define CRB_V2P_3 (UNM_NIC_REG(0x29c))
193 #define CRB_V2P(port) (CRB_V2P_0 + ((port) * 4))
194 #define CRB_DRIVER_VERSION (UNM_NIC_REG(0x2a0))
195
196 #define CRB_CNT_DBG1 (UNM_NIC_REG(0x2a4))
197 #define CRB_CNT_DBG2 (UNM_NIC_REG(0x2a8))
198 #define CRB_CNT_DBG3 (UNM_NIC_REG(0x2ac))
199
200 /* ends here */
201 #define UNM_HW_H0_CH_HUB_ADR 0x05
202 #define UNM_HW_H1_CH_HUB_ADR 0x0E
203 #define UNM_HW_H2_CH_HUB_ADR 0x03
204 #define UNM_HW_H3_CH_HUB_ADR 0x01
205 #define UNM_HW_H4_CH_HUB_ADR 0x06
206 #define UNM_HW_H5_CH_HUB_ADR 0x07
207 #define UNM_HW_H6_CH_HUB_ADR 0x08
208 /*
209 * WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an
210 * ILLEGAL hub!!!!!
211 */
212
213 /* Hub 0 */
214 #define UNM_HW_MN_CRB_AGT_ADR 0x15
215 #define UNM_HW_MS_CRB_AGT_ADR 0x25
216
217 /* Hub 1 */
218 #define UNM_HW_PS_CRB_AGT_ADR 0x73
219 #define UNM_HW_SS_CRB_AGT_ADR 0x20
220 #define UNM_HW_RPMX3_CRB_AGT_ADR 0x0b
221 #define UNM_HW_QMS_CRB_AGT_ADR 0x00
222 #define UNM_HW_SQGS0_CRB_AGT_ADR 0x01
223 #define UNM_HW_SQGS1_CRB_AGT_ADR 0x02
224 #define UNM_HW_SQGS2_CRB_AGT_ADR 0x03
225 #define UNM_HW_SQGS3_CRB_AGT_ADR 0x04
226 #define UNM_HW_C2C0_CRB_AGT_ADR 0x58
227 #define UNM_HW_C2C1_CRB_AGT_ADR 0x59
228 #define UNM_HW_C2C2_CRB_AGT_ADR 0x5a
229 #define UNM_HW_RPMX2_CRB_AGT_ADR 0x0a
230 #define UNM_HW_RPMX4_CRB_AGT_ADR 0x0c
231 #define UNM_HW_RPMX7_CRB_AGT_ADR 0x0f
232 #define UNM_HW_RPMX9_CRB_AGT_ADR 0x12
233 #define UNM_HW_SMB_CRB_AGT_ADR 0x18
234
235 /* Hub 2 */
236 #define UNM_HW_NIU_CRB_AGT_ADR 0x31
237 #define UNM_HW_I2C0_CRB_AGT_ADR 0x19
238 #define UNM_HW_I2C1_CRB_AGT_ADR 0x29
239
240 #define UNM_HW_SN_CRB_AGT_ADR 0x10
241 #define UNM_HW_I2Q_CRB_AGT_ADR 0x20
242 #define UNM_HW_LPC_CRB_AGT_ADR 0x22
243 #define UNM_HW_ROMUSB_CRB_AGT_ADR 0x21
244 #define UNM_HW_QM_CRB_AGT_ADR 0x66
245 #define UNM_HW_SQG0_CRB_AGT_ADR 0x60
246 #define UNM_HW_SQG1_CRB_AGT_ADR 0x61
247 #define UNM_HW_SQG2_CRB_AGT_ADR 0x62
248 #define UNM_HW_SQG3_CRB_AGT_ADR 0x63
249 #define UNM_HW_RPMX1_CRB_AGT_ADR 0x09
250 #define UNM_HW_RPMX5_CRB_AGT_ADR 0x0d
251 #define UNM_HW_RPMX6_CRB_AGT_ADR 0x0e
252 #define UNM_HW_RPMX8_CRB_AGT_ADR 0x11
253
254 /* Hub 3 */
255 #define UNM_HW_PH_CRB_AGT_ADR 0x1A
256 #define UNM_HW_SRE_CRB_AGT_ADR 0x50
257 #define UNM_HW_EG_CRB_AGT_ADR 0x51
258 #define UNM_HW_RPMX0_CRB_AGT_ADR 0x08
259
260 /* Hub 4 */
261 #define UNM_HW_PEGN0_CRB_AGT_ADR 0x40
262 #define UNM_HW_PEGN1_CRB_AGT_ADR 0x41
263 #define UNM_HW_PEGN2_CRB_AGT_ADR 0x42
264 #define UNM_HW_PEGN3_CRB_AGT_ADR 0x43
265 #define UNM_HW_PEGNI_CRB_AGT_ADR 0x44
266 #define UNM_HW_PEGND_CRB_AGT_ADR 0x45
267 #define UNM_HW_PEGNC_CRB_AGT_ADR 0x46
268 #define UNM_HW_PEGR0_CRB_AGT_ADR 0x47
269 #define UNM_HW_PEGR1_CRB_AGT_ADR 0x48
270 #define UNM_HW_PEGR2_CRB_AGT_ADR 0x49
271 #define UNM_HW_PEGR3_CRB_AGT_ADR 0x4a
272 #define UNM_HW_PEGN4_CRB_AGT_ADR 0x4b
273
274 /* Hub 5 */
275 #define UNM_HW_PEGS0_CRB_AGT_ADR 0x40
276 #define UNM_HW_PEGS1_CRB_AGT_ADR 0x41
277 #define UNM_HW_PEGS2_CRB_AGT_ADR 0x42
278 #define UNM_HW_PEGS3_CRB_AGT_ADR 0x43
279 #define UNM_HW_PEGSI_CRB_AGT_ADR 0x44
280 #define UNM_HW_PEGSD_CRB_AGT_ADR 0x45
281 #define UNM_HW_PEGSC_CRB_AGT_ADR 0x46
282
283 /* Hub 6 */
284 #define UNM_HW_CAS0_CRB_AGT_ADR 0x46
285 #define UNM_HW_CAS1_CRB_AGT_ADR 0x47
286 #define UNM_HW_CAS2_CRB_AGT_ADR 0x48
287 #define UNM_HW_CAS3_CRB_AGT_ADR 0x49
288 #define UNM_HW_NCM_CRB_AGT_ADR 0x16
289 #define UNM_HW_TMR_CRB_AGT_ADR 0x17
290 #define UNM_HW_XDMA_CRB_AGT_ADR 0x05
291 #define UNM_HW_OCM0_CRB_AGT_ADR 0x06
292 #define UNM_HW_OCM1_CRB_AGT_ADR 0x07
293
294 /* This field defines PCI/X adr [25:20] of agents on the CRB */
295
296 #define UNM_HW_PX_MAP_CRB_PH 0
297 #define UNM_HW_PX_MAP_CRB_PS 1
298 #define UNM_HW_PX_MAP_CRB_MN 2
299 #define UNM_HW_PX_MAP_CRB_MS 3
300 #define UNM_HW_PX_MAP_CRB_SRE 5
301 #define UNM_HW_PX_MAP_CRB_NIU 6
302 #define UNM_HW_PX_MAP_CRB_QMN 7
303 #define UNM_HW_PX_MAP_CRB_SQN0 8
304 #define UNM_HW_PX_MAP_CRB_SQN1 9
305 #define UNM_HW_PX_MAP_CRB_SQN2 10
306 #define UNM_HW_PX_MAP_CRB_SQN3 11
307 #define UNM_HW_PX_MAP_CRB_QMS 12
308 #define UNM_HW_PX_MAP_CRB_SQS0 13
309 #define UNM_HW_PX_MAP_CRB_SQS1 14
310 #define UNM_HW_PX_MAP_CRB_SQS2 15
311 #define UNM_HW_PX_MAP_CRB_SQS3 16
312 #define UNM_HW_PX_MAP_CRB_PGN0 17
313 #define UNM_HW_PX_MAP_CRB_PGN1 18
314 #define UNM_HW_PX_MAP_CRB_PGN2 19
315 #define UNM_HW_PX_MAP_CRB_PGN3 20
316 #define UNM_HW_PX_MAP_CRB_PGN4 (UNM_HW_PX_MAP_CRB_SQS2)
317 #define UNM_HW_PX_MAP_CRB_PGND 21
318 #define UNM_HW_PX_MAP_CRB_PGNI 22
319 #define UNM_HW_PX_MAP_CRB_PGS0 23
320 #define UNM_HW_PX_MAP_CRB_PGS1 24
321 #define UNM_HW_PX_MAP_CRB_PGS2 25
322 #define UNM_HW_PX_MAP_CRB_PGS3 26
323 #define UNM_HW_PX_MAP_CRB_PGSD 27
324 #define UNM_HW_PX_MAP_CRB_PGSI 28
325 #define UNM_HW_PX_MAP_CRB_SN 29
326 #define UNM_HW_PX_MAP_CRB_EG 31
327 #define UNM_HW_PX_MAP_CRB_PH2 32
328 #define UNM_HW_PX_MAP_CRB_PS2 33
329 #define UNM_HW_PX_MAP_CRB_CAM 34
330 #define UNM_HW_PX_MAP_CRB_CAS0 35
331 #define UNM_HW_PX_MAP_CRB_CAS1 36
332 #define UNM_HW_PX_MAP_CRB_CAS2 37
333 #define UNM_HW_PX_MAP_CRB_C2C0 38
334 #define UNM_HW_PX_MAP_CRB_C2C1 39
335 #define UNM_HW_PX_MAP_CRB_TIMR 40
336 /*
337 * #define PX_MAP_CRB_SS 41
338 */
339 #define UNM_HW_PX_MAP_CRB_RPMX1 42
340 #define UNM_HW_PX_MAP_CRB_RPMX2 43
341 #define UNM_HW_PX_MAP_CRB_RPMX3 44
342 #define UNM_HW_PX_MAP_CRB_RPMX4 45
343 #define UNM_HW_PX_MAP_CRB_RPMX5 46
344 #define UNM_HW_PX_MAP_CRB_RPMX6 47
345 #define UNM_HW_PX_MAP_CRB_RPMX7 48
346 #define UNM_HW_PX_MAP_CRB_XDMA 49
347 #define UNM_HW_PX_MAP_CRB_I2Q 50
348 #define UNM_HW_PX_MAP_CRB_ROMUSB 51
349 #define UNM_HW_PX_MAP_CRB_CAS3 52
350 #define UNM_HW_PX_MAP_CRB_RPMX0 53
351 #define UNM_HW_PX_MAP_CRB_RPMX8 54
352 #define UNM_HW_PX_MAP_CRB_RPMX9 55
353 #define UNM_HW_PX_MAP_CRB_OCM0 56
354 #define UNM_HW_PX_MAP_CRB_OCM1 57
355 #define UNM_HW_PX_MAP_CRB_SMB 58
356 #define UNM_HW_PX_MAP_CRB_I2C0 59
357 #define UNM_HW_PX_MAP_CRB_I2C1 60
358 #define UNM_HW_PX_MAP_CRB_LPC 61
359 #define UNM_HW_PX_MAP_CRB_PGNC 62
360 #define UNM_HW_PX_MAP_CRB_PGR0 63
361 #define UNM_HW_PX_MAP_CRB_PGR1 4
362 #define UNM_HW_PX_MAP_CRB_PGR2 30
363 #define UNM_HW_PX_MAP_CRB_PGR3 41
364
365 /* This field defines CRB adr [31:20] of the agents */
366
367 #define UNM_HW_CRB_HUB_AGT_ADR_MN ((UNM_HW_H0_CH_HUB_ADR << 7) | \
368 UNM_HW_MN_CRB_AGT_ADR)
369 #define UNM_HW_CRB_HUB_AGT_ADR_PH ((UNM_HW_H0_CH_HUB_ADR << 7) | \
370 UNM_HW_PH_CRB_AGT_ADR)
371 #define UNM_HW_CRB_HUB_AGT_ADR_MS ((UNM_HW_H0_CH_HUB_ADR << 7) | \
372 UNM_HW_MS_CRB_AGT_ADR)
373
374 #define UNM_HW_CRB_HUB_AGT_ADR_PS ((UNM_HW_H1_CH_HUB_ADR << 7) | \
375 UNM_HW_PS_CRB_AGT_ADR)
376 #define UNM_HW_CRB_HUB_AGT_ADR_SS ((UNM_HW_H1_CH_HUB_ADR << 7) | \
377 UNM_HW_SS_CRB_AGT_ADR)
378 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX3 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
379 UNM_HW_RPMX3_CRB_AGT_ADR)
380 #define UNM_HW_CRB_HUB_AGT_ADR_QMS ((UNM_HW_H1_CH_HUB_ADR << 7) | \
381 UNM_HW_QMS_CRB_AGT_ADR)
382 #define UNM_HW_CRB_HUB_AGT_ADR_SQS0 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
383 UNM_HW_SQGS0_CRB_AGT_ADR)
384 #define UNM_HW_CRB_HUB_AGT_ADR_SQS1 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
385 UNM_HW_SQGS1_CRB_AGT_ADR)
386 #define UNM_HW_CRB_HUB_AGT_ADR_SQS2 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
387 UNM_HW_SQGS2_CRB_AGT_ADR)
388 #define UNM_HW_CRB_HUB_AGT_ADR_SQS3 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
389 UNM_HW_SQGS3_CRB_AGT_ADR)
390 #define UNM_HW_CRB_HUB_AGT_ADR_C2C0 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
391 UNM_HW_C2C0_CRB_AGT_ADR)
392 #define UNM_HW_CRB_HUB_AGT_ADR_C2C1 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
393 UNM_HW_C2C1_CRB_AGT_ADR)
394 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX2 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
395 UNM_HW_RPMX2_CRB_AGT_ADR)
396 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX4 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
397 UNM_HW_RPMX4_CRB_AGT_ADR)
398 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX7 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
399 UNM_HW_RPMX7_CRB_AGT_ADR)
400 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX9 ((UNM_HW_H1_CH_HUB_ADR << 7) | \
401 UNM_HW_RPMX9_CRB_AGT_ADR)
402 #define UNM_HW_CRB_HUB_AGT_ADR_SMB ((UNM_HW_H1_CH_HUB_ADR << 7) | \
403 UNM_HW_SMB_CRB_AGT_ADR)
404
405 #define UNM_HW_CRB_HUB_AGT_ADR_NIU ((UNM_HW_H2_CH_HUB_ADR << 7) | \
406 UNM_HW_NIU_CRB_AGT_ADR)
407 #define UNM_HW_CRB_HUB_AGT_ADR_I2C0 ((UNM_HW_H2_CH_HUB_ADR << 7) | \
408 UNM_HW_I2C0_CRB_AGT_ADR)
409 #define UNM_HW_CRB_HUB_AGT_ADR_I2C1 ((UNM_HW_H2_CH_HUB_ADR << 7) | \
410 UNM_HW_I2C1_CRB_AGT_ADR)
411
412 #define UNM_HW_CRB_HUB_AGT_ADR_SRE ((UNM_HW_H3_CH_HUB_ADR << 7) | \
413 UNM_HW_SRE_CRB_AGT_ADR)
414 #define UNM_HW_CRB_HUB_AGT_ADR_EG ((UNM_HW_H3_CH_HUB_ADR << 7) | \
415 UNM_HW_EG_CRB_AGT_ADR)
416 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX0 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
417 UNM_HW_RPMX0_CRB_AGT_ADR)
418 #define UNM_HW_CRB_HUB_AGT_ADR_QMN ((UNM_HW_H3_CH_HUB_ADR << 7) | \
419 UNM_HW_QM_CRB_AGT_ADR)
420 #define UNM_HW_CRB_HUB_AGT_ADR_SQN0 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
421 UNM_HW_SQG0_CRB_AGT_ADR)
422 #define UNM_HW_CRB_HUB_AGT_ADR_SQN1 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
423 UNM_HW_SQG1_CRB_AGT_ADR)
424 #define UNM_HW_CRB_HUB_AGT_ADR_SQN2 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
425 UNM_HW_SQG2_CRB_AGT_ADR)
426 #define UNM_HW_CRB_HUB_AGT_ADR_SQN3 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
427 UNM_HW_SQG3_CRB_AGT_ADR)
428 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX1 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
429 UNM_HW_RPMX1_CRB_AGT_ADR)
430 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX5 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
431 UNM_HW_RPMX5_CRB_AGT_ADR)
432 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX6 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
433 UNM_HW_RPMX6_CRB_AGT_ADR)
434 #define UNM_HW_CRB_HUB_AGT_ADR_RPMX8 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
435 UNM_HW_RPMX8_CRB_AGT_ADR)
436 #define UNM_HW_CRB_HUB_AGT_ADR_CAS0 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
437 UNM_HW_CAS0_CRB_AGT_ADR)
438 #define UNM_HW_CRB_HUB_AGT_ADR_CAS1 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
439 UNM_HW_CAS1_CRB_AGT_ADR)
440 #define UNM_HW_CRB_HUB_AGT_ADR_CAS2 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
441 UNM_HW_CAS2_CRB_AGT_ADR)
442 #define UNM_HW_CRB_HUB_AGT_ADR_CAS3 ((UNM_HW_H3_CH_HUB_ADR << 7) | \
443 UNM_HW_CAS3_CRB_AGT_ADR)
444
445 #define UNM_HW_CRB_HUB_AGT_ADR_PGNI ((UNM_HW_H4_CH_HUB_ADR << 7) | \
446 UNM_HW_PEGNI_CRB_AGT_ADR)
447 #define UNM_HW_CRB_HUB_AGT_ADR_PGND ((UNM_HW_H4_CH_HUB_ADR << 7) | \
448 UNM_HW_PEGND_CRB_AGT_ADR)
449 #define UNM_HW_CRB_HUB_AGT_ADR_PGN0 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
450 UNM_HW_PEGN0_CRB_AGT_ADR)
451 #define UNM_HW_CRB_HUB_AGT_ADR_PGN1 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
452 UNM_HW_PEGN1_CRB_AGT_ADR)
453 #define UNM_HW_CRB_HUB_AGT_ADR_PGN2 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
454 UNM_HW_PEGN2_CRB_AGT_ADR)
455 #define UNM_HW_CRB_HUB_AGT_ADR_PGN3 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
456 UNM_HW_PEGN3_CRB_AGT_ADR)
457 #define UNM_HW_CRB_HUB_AGT_ADR_PGN4 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
458 UNM_HW_PEGN4_CRB_AGT_ADR)
459
460 #define UNM_HW_CRB_HUB_AGT_ADR_PGNC ((UNM_HW_H4_CH_HUB_ADR << 7) | \
461 UNM_HW_PEGNC_CRB_AGT_ADR)
462 #define UNM_HW_CRB_HUB_AGT_ADR_PGR0 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
463 UNM_HW_PEGR0_CRB_AGT_ADR)
464 #define UNM_HW_CRB_HUB_AGT_ADR_PGR1 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
465 UNM_HW_PEGR1_CRB_AGT_ADR)
466 #define UNM_HW_CRB_HUB_AGT_ADR_PGR2 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
467 UNM_HW_PEGR2_CRB_AGT_ADR)
468 #define UNM_HW_CRB_HUB_AGT_ADR_PGR3 ((UNM_HW_H4_CH_HUB_ADR << 7) | \
469 UNM_HW_PEGR3_CRB_AGT_ADR)
470
471 #define UNM_HW_CRB_HUB_AGT_ADR_PGSI ((UNM_HW_H5_CH_HUB_ADR << 7) | \
472 UNM_HW_PEGSI_CRB_AGT_ADR)
473 #define UNM_HW_CRB_HUB_AGT_ADR_PGSD ((UNM_HW_H5_CH_HUB_ADR << 7) | \
474 UNM_HW_PEGSD_CRB_AGT_ADR)
475 #define UNM_HW_CRB_HUB_AGT_ADR_PGS0 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
476 UNM_HW_PEGS0_CRB_AGT_ADR)
477 #define UNM_HW_CRB_HUB_AGT_ADR_PGS1 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
478 UNM_HW_PEGS1_CRB_AGT_ADR)
479 #define UNM_HW_CRB_HUB_AGT_ADR_PGS2 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
480 UNM_HW_PEGS2_CRB_AGT_ADR)
481 #define UNM_HW_CRB_HUB_AGT_ADR_PGS3 ((UNM_HW_H5_CH_HUB_ADR << 7) | \
482 UNM_HW_PEGS3_CRB_AGT_ADR)
483 #define UNM_HW_CRB_HUB_AGT_ADR_PGSC ((UNM_HW_H5_CH_HUB_ADR << 7) | \
484 UNM_HW_PEGSC_CRB_AGT_ADR)
485
486 #define UNM_HW_CRB_HUB_AGT_ADR_CAM ((UNM_HW_H6_CH_HUB_ADR << 7) | \
487 UNM_HW_NCM_CRB_AGT_ADR)
488 #define UNM_HW_CRB_HUB_AGT_ADR_TIMR ((UNM_HW_H6_CH_HUB_ADR << 7) | \
489 UNM_HW_TMR_CRB_AGT_ADR)
490 #define UNM_HW_CRB_HUB_AGT_ADR_XDMA ((UNM_HW_H6_CH_HUB_ADR << 7) | \
491 UNM_HW_XDMA_CRB_AGT_ADR)
492 #define UNM_HW_CRB_HUB_AGT_ADR_SN ((UNM_HW_H6_CH_HUB_ADR << 7) | \
493 UNM_HW_SN_CRB_AGT_ADR)
494 #define UNM_HW_CRB_HUB_AGT_ADR_I2Q ((UNM_HW_H6_CH_HUB_ADR << 7) | \
495 UNM_HW_I2Q_CRB_AGT_ADR)
496 #define UNM_HW_CRB_HUB_AGT_ADR_ROMUSB ((UNM_HW_H6_CH_HUB_ADR << 7) | \
497 UNM_HW_ROMUSB_CRB_AGT_ADR)
498 #define UNM_HW_CRB_HUB_AGT_ADR_OCM0 ((UNM_HW_H6_CH_HUB_ADR << 7) | \
499 UNM_HW_OCM0_CRB_AGT_ADR)
500 #define UNM_HW_CRB_HUB_AGT_ADR_OCM1 ((UNM_HW_H6_CH_HUB_ADR << 7) | \
501 UNM_HW_OCM1_CRB_AGT_ADR)
502 #define UNM_HW_CRB_HUB_AGT_ADR_LPC ((UNM_HW_H6_CH_HUB_ADR << 7) | \
503 UNM_HW_LPC_CRB_AGT_ADR)
504
505 /*
506 * ROM USB CRB space is divided into 4 regions depending on decode of
507 * address bits [19:16]
508 */
509 #define ROMUSB_GLB (UNM_CRB_ROMUSB + 0x00000)
510 #define ROMUSB_ROM (UNM_CRB_ROMUSB + 0x10000)
511 #define ROMUSB_USB (UNM_CRB_ROMUSB + 0x20000)
512 #define ROMUSB_DIRECT_ROM (UNM_CRB_ROMUSB + 0x30000)
513 #define ROMUSB_TAP (UNM_CRB_ROMUSB + 0x40000)
514
515 /* ROMUSB GLB register definitions */
516 #define UNM_ROMUSB_GLB_CONTROL (ROMUSB_GLB + 0x0000)
517 #define UNM_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
518 #define UNM_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
519 #define UNM_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
520 #define UNM_ROMUSB_GLB_RNG_PLL_CTL (ROMUSB_GLB + 0x0010)
521 #define UNM_ROMUSB_GLB_TEST_MUX_O (ROMUSB_GLB + 0x0014)
522 #define UNM_ROMUSB_GLB_PLL0_CTRL (ROMUSB_GLB + 0x0018)
523 #define UNM_ROMUSB_GLB_PLL1_CTRL (ROMUSB_GLB + 0x001c)
524 #define UNM_ROMUSB_GLB_PLL2_CTRL (ROMUSB_GLB + 0x0020)
525 #define UNM_ROMUSB_GLB_PLL3_CTRL (ROMUSB_GLB + 0x0024)
526 #define UNM_ROMUSB_GLB_PLL_LOCK (ROMUSB_GLB + 0x0028)
527 #define UNM_ROMUSB_GLB_EXTERN_INT (ROMUSB_GLB + 0x002c)
528 #define UNM_ROMUSB_GLB_PH_RST (ROMUSB_GLB + 0x0030)
529 #define UNM_ROMUSB_GLB_PS_RST (ROMUSB_GLB + 0x0034)
530 #define UNM_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
531 #define UNM_ROMUSB_GLB_MIU_RST (ROMUSB_GLB + 0x003c)
532 #define UNM_ROMUSB_GLB_CRB_RST (ROMUSB_GLB + 0x0040)
533 #define UNM_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
534 #define UNM_ROMUSB_GLB_MN_COM_A2T (ROMUSB_GLB + 0x0050)
535 #define UNM_ROMUSB_GLB_MN_COM_A2T (ROMUSB_GLB + 0x0050)
536 #define UNM_ROMUSB_GLB_REV_ID (ROMUSB_GLB + 0x0054)
537 #define UNM_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
538 #define UNM_ROMUSB_GLB_VENDOR_DEV_ID (ROMUSB_GLB + 0x0058)
539 #define UNM_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00a8)
540
541 #define UNM_ROMUSB_GPIO(n) ((n) <= 15 ? (ROMUSB_GLB + 0x60 + (4 * (n))): \
542 ((n) <= 18) ? (ROMUSB_GLB + 0x70 + (4 * (n))) : \
543 (ROMUSB_GLB + 0x70 + (4 * (19))))
544
545 #define UNM_ROMUSB_ROM_CONTROL (ROMUSB_ROM + 0x0000)
546 #define UNM_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
547 #define UNM_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
548 #define UNM_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
549 #define UNM_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
550 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
551 #define UNM_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
552 #define UNM_ROMUSB_ROM_AGT_TAG (ROMUSB_ROM + 0x001c)
553 #define UNM_ROMUSB_ROM_TIME_PARM (ROMUSB_ROM + 0x0020)
554 #define UNM_ROMUSB_ROM_CLK_DIV (ROMUSB_ROM + 0x0024)
555 #define UNM_ROMUSB_ROM_MISS_INSTR (ROMUSB_ROM + 0x0028)
556
557 #define UNM_ROMUSB_ROM_WRSR_INSTR 0x01
558 #define UNM_ROMUSB_ROM_PP_INSTR 0x02
559 #define UNM_ROMUSB_ROM_READ_INSTR 0x03
560 #define UNM_ROMUSB_ROM_WRDI_INSTR 0x04
561 #define UNM_ROMUSB_ROM_RDSR_INSTR 0x05
562 #define UNM_ROMUSB_ROM_WREN_INSTR 0x06
563 #define UNM_ROMUSB_ROM_FAST_RD_INSTR 0x0B
564 #define UNM_ROMUSB_ROM_RES_INSTR 0xAB
565 #define UNM_ROMUSB_ROM_BE_INSTR 0xC7
566 #define UNM_ROMUSB_ROM_DP_INSTR 0xC9
567 #define UNM_ROMUSB_ROM_SE_INSTR 0xD8
568
569 /* Lock IDs for ROM lock */
570 #define ROM_LOCK_DRIVER 0x0d417340
571
572 /* Lock IDs for PHY lock */
573 #define PHY_LOCK_DRIVER 0x44524956
574
575 #define UNM_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
576 #define UNM_PCI_CRB_WINDOW(A) (UNM_PCI_CRBSPACE + (A)*UNM_PCI_CRB_WINDOWSIZE)
577 #define UNM_CRB_C2C_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C0))
578 #define UNM_CRB_C2C_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C1))
579 #define UNM_CRB_C2C_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_C2C2))
580 #define UNM_CRB_CAM (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAM))
581 #define UNM_CRB_CASPER (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS))
582 #define UNM_CRB_CASPER_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS0))
583 #define UNM_CRB_CASPER_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS1))
584 #define UNM_CRB_CASPER_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_CAS2))
585 #define UNM_CRB_DDR_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MS))
586 #define UNM_CRB_DDR_NET (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_MN))
587 #define UNM_CRB_EPG (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_EG))
588 #define UNM_CRB_I2Q (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2Q))
589 #define UNM_CRB_NIU (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_NIU))
590 /* HACK upon HACK upon HACK (for PCIE builds) */
591 #define UNM_CRB_PCIX_HOST (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH))
592 #define UNM_CRB_PCIX_HOST2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PH2))
593 #define UNM_CRB_PCIX_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS))
594 #define UNM_CRB_PCIE (UNM_CRB_PCIX_MD)
595 /* window 1 pcie slot */
596 #define UNM_CRB_PCIE2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PS2))
597
598 #define UNM_CRB_PEG_MD_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS0))
599 #define UNM_CRB_PEG_MD_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS1))
600 #define UNM_CRB_PEG_MD_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS2))
601 #define UNM_CRB_PEG_MD_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS3))
602 #define UNM_CRB_PEG_MD_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGS3))
603 #define UNM_CRB_PEG_MD_D (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSD))
604 #define UNM_CRB_PEG_MD_I (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGSI))
605 #define UNM_CRB_PEG_NET_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN0))
606 #define UNM_CRB_PEG_NET_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN1))
607 #define UNM_CRB_PEG_NET_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN2))
608 #define UNM_CRB_PEG_NET_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN3))
609 #define UNM_CRB_PEG_NET_4 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGN4))
610 #define UNM_CRB_PEG_NET_D (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGND))
611 #define UNM_CRB_PEG_NET_I (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_PGNI))
612 #define UNM_CRB_PQM_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMS))
613 #define UNM_CRB_PQM_NET (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_QMN))
614 #define UNM_CRB_QDR_MD (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SS))
615 #define UNM_CRB_QDR_NET (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SN))
616 #define UNM_CRB_ROMUSB (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_ROMUSB))
617 #define UNM_CRB_RPMX_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX0))
618 #define UNM_CRB_RPMX_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX1))
619 #define UNM_CRB_RPMX_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX2))
620 #define UNM_CRB_RPMX_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX3))
621 #define UNM_CRB_RPMX_4 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX4))
622 #define UNM_CRB_RPMX_5 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX5))
623 #define UNM_CRB_RPMX_6 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX6))
624 #define UNM_CRB_RPMX_7 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_RPMX7))
625 #define UNM_CRB_SQM_MD_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS0))
626 #define UNM_CRB_SQM_MD_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS1))
627 #define UNM_CRB_SQM_MD_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS2))
628 #define UNM_CRB_SQM_MD_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQS3))
629 #define UNM_CRB_SQM_NET_0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN0))
630 #define UNM_CRB_SQM_NET_1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN1))
631 #define UNM_CRB_SQM_NET_2 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN2))
632 #define UNM_CRB_SQM_NET_3 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SQN3))
633 #define UNM_CRB_SRE (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SRE))
634 #define UNM_CRB_TIMER (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_TIMR))
635 #define UNM_CRB_XDMA (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_XDMA))
636 #define UNM_CRB_I2C0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C0))
637 #define UNM_CRB_I2C1 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_I2C1))
638 #define UNM_CRB_OCM0 (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_OCM0))
639 #define UNM_CRB_SMB (UNM_PCI_CRB_WINDOW(UNM_HW_PX_MAP_CRB_SMB))
640
641 #define UNM_CRB_MAX (UNM_PCI_CRB_WINDOW(64))
642
643 /*
644 * ====================== BASE ADDRESSES ON-CHIP ======================
645 * Base addresses of major components on-chip.
646 * ====================== BASE ADDRESSES ON-CHIP ======================
647 */
648 #define UNM_ADDR_DDR_NET 0x0000000000000000
649 #define UNM_ADDR_DDR_NET_MAX 0x000000000fffffff
650
651 /*
652 * Imbus address bit used to indicate a host address. This bit is
653 * eliminated by the pcie bar and bar select before presentation
654 * over pcie.
655 */
656 /* host memory via IMBUS */
657 #define NX_P2_ADDR_PCIE 0x0000000800000000
658 #define NX_P3_ADDR_PCIE 0x0000008000000000
659 #define UNM_ADDR_PCIE_MAX 0x0000000FFFFFFFFF
660 #define UNM_ADDR_OCM0 0x0000000200000000
661 #define UNM_ADDR_OCM0_MAX 0x00000002000fffff
662 #define UNM_ADDR_OCM1 0x0000000200400000
663 #define UNM_ADDR_OCM1_MAX 0x00000002004fffff
664 #define UNM_ADDR_QDR_NET 0x0000000300000000
665
666 #define NX_P2_ADDR_QDR_NET_MAX 0x00000003001fffff
667 #define NX_P3_ADDR_QDR_NET_MAX 0x0000000303ffffff
668 /*
669 * The ifdef at the bottom should go. All drivers should start using the above
670 * 2 defines.
671 */
672 #ifdef P3
673 #define UNM_ADDR_QDR_NET_MAX (NX_P3_ADDR_QDR_NET_MAX)
674 #else
675 #define UNM_ADDR_QDR_NET_MAX (NX_P2_ADDR_QDR_NET_MAX)
676 #endif
677
678 #define D3_CRB_REG_FUN0 (UNM_PCIX_PS_REG(0x0084))
679 #define D3_CRB_REG_FUN1 (UNM_PCIX_PS_REG(0x1084))
680 #define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084))
681 #define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084))
682
683
684 #define ISR_I2Q_CLR_PCI_LO (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_LO))
685 #define ISR_I2Q_CLR_PCI_HI (UNM_PCIX_PS_REG(UNM_I2Q_CLR_PCI_HI))
686 #define UNM_PCI_ARCH_CRB_BASE (UNM_PCI_DIRECT_CRB)
687
688 #define UNM_PCI_MAPSIZE 128 /* we're mapping 128MB of mem on PCI bus */
689 #define UNM_PCI_DDR_NET 0x00000000
690 #define UNM_PCI_DDR_NET_MAX 0x01ffffff
691 #define UNM_PCI_DDR_MD 0x02000000
692 #define UNM_PCI_DDR_MD_MAX 0x03ffffff
693 #define UNM_PCI_QDR_NET 0x04000000
694 #define UNM_PCI_QDR_NET_MAX 0x043fffff
695 #define UNM_PCI_DIRECT_CRB 0x04400000
696 #define UNM_PCI_DIRECT_CRB_MAX 0x047fffff
697 #define UNM_PCI_CAMQM 0x04800000
698 #define UNM_PCI_CAMQM_MAX 0x04ffffff
699 #define UNM_PCI_OCM0 0x05000000
700 #define UNM_PCI_OCM0_MAX 0x050fffff
701 #define UNM_PCI_OCM1 0x05100000
702 #define UNM_PCI_OCM1_MAX 0x051fffff
703 #define UNM_PCI_CRBSPACE 0x06000000
704 #define UNM_PCI_CRBSPACE_MAX 0x07ffffff
705 #define UNM_PCI_128MB_SIZE 0x08000000
706 #define UNM_PCI_32MB_SIZE 0x02000000
707 #define UNM_PCI_2MB_SIZE 0x00200000
708
709 /*
710 * Definitions relating to access/control of the Network Interface Unit
711 * h/w block.
712 */
713 /*
714 * Configuration registers.
715 */
716 #define UNM_NIU_MODE (UNM_CRB_NIU + 0x00000)
717
718 /*
719 * Register offsets for MN
720 */
721 #define MIU_CONTROL (0x000)
722 #define MIU_TAG (0x004)
723 #define MIU_TEST_AGT_CTRL (0x090)
724 #define MIU_TEST_AGT_ADDR_LO (0x094)
725 #define MIU_TEST_AGT_ADDR_HI (0x098)
726 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
727 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
728 #define MIU_TEST_AGT_WRDATA(i) (0x0a0 + (4 * (i)))
729 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
730 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
731 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
732 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
733 #define MIU_TEST_AGT_RDDATA_UPPER_LO (0x0b8)
734 #define MIU_TEST_AGT_RDDATA_UPPER_HI (0x0bc)
735 #define MIU_TEST_AGT_RDDATA(i) (0x0a8 + (4 * (i)))
736 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
737 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
738
739 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
740 #define MIU_TA_CTL_START 1
741 #define MIU_TA_CTL_ENABLE 2
742 #define MIU_TA_CTL_WRITE 4
743 #define MIU_TA_CTL_BUSY 8
744
745 #define SIU_TEST_AGT_CTRL (0x060)
746 #define SIU_TEST_AGT_ADDR_LO (0x064)
747 #define SIU_TEST_AGT_ADDR_HI (0x078)
748 #define SIU_TEST_AGT_WRDATA_LO (0x068)
749 #define SIU_TEST_AGT_WRDATA_HI (0x06c)
750 #define SIU_TEST_AGT_WRDATA(i) (0x068 + (4 * (i)))
751 #define SIU_TEST_AGT_RDDATA_LO (0x070)
752 #define SIU_TEST_AGT_RDDATA_HI (0x074)
753 #define SIU_TEST_AGT_RDDATA(i) (0x070 + (4 * (i)))
754
755 #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
756 #define SIU_TEST_AGT_UPPER_ADDR(off) ((off) >> 22)
757 #define XG_LINK_UP 0x10
758
759
760 /* ====================== Configuration Constants ======================== */
761 #define UNM_NIU_PHY_WAITLEN 200000 /* 200ms delay in each loop */
762 #define UNM_NIU_PHY_WAITMAX 50 /* 10 seconds before we give up */
763 #define UNM_NIU_MAX_GBE_PORTS 4
764 #define UNM_NIU_MAX_XG_PORTS 2
765 #define MIN_CORE_CLK_SPEED 200
766 #define MAX_CORE_CLK_SPEED 400
767 #define ACCEPTABLE_CORE_CLK_RANGE(speed) ((speed >= MIN_CORE_CLK_SPEED) && \
768 (speed <= MAX_CORE_CLK_SPEED))
769
770 #define P2_TICKS_PER_SEC 2048
771 #define P2_MIN_TICKS_PER_SEC (P2_TICKS_PER_SEC - 10)
772 #define P2_MAX_TICKS_PER_SEC (P2_TICKS_PER_SEC + 10)
773 #define CHECK_TICKS_PER_SEC(ticks) ((ticks >= P2_MIN_TICKS_PER_SEC) && \
774 (ticks <= P2_MAX_TICKS_PER_SEC))
775
776 /* CAM RAM */
777 #define UNM_CAM_RAM_BASE (UNM_CRB_CAM + 0x02000)
778 #define UNM_CAM_RAM(reg) (UNM_CAM_RAM_BASE + (reg))
779
780 #define UNM_PORT_MODE_NONE 0
781 #define UNM_PORT_MODE_XG 1
782 #define UNM_PORT_MODE_GB 2
783 #define UNM_PORT_MODE_802_3_AP 3
784 #define UNM_PORT_MODE_AUTO_NEG 4
785 #define UNM_PORT_MODE_AUTO_NEG_1G 5
786 #define UNM_PORT_MODE_AUTO_NEG_XG 6
787 #define UNM_PORT_MODE_ADDR (UNM_CAM_RAM(0x24))
788 #define UNM_FW_PORT_MODE_ADDR (UNM_CAM_RAM(0x28))
789 #define UNM_WOL_PORT_MODE (UNM_CAM_RAM(0x198))
790 #define UNM_RAM_COLD_BOOT (UNM_CAM_RAM(0x1fc))
791 #define UNM_BUS_DEV_NO (UNM_CAM_RAM(0x114))
792
793 #define NX_PEG_TUNE_MN_SPD_ZEROED 0x80000000
794 #define NX_BOOT_LOADER_MN_OTHER 0x100 /* other problem with DIMM */
795 #define NX_BOOT_LOADER_MN_NOT_DDR2 0x80 /* not a DDR2 DIMM */
796 #define NX_BOOT_LOADER_MN_NO_ECC 0x40 /* ECC not supported */
797 #define NX_BOOT_LOADER_MN_WRONG_CAS 0x20 /* CL 5 not supported */
798 #define NX_BOOT_LOADER_MN_NOT_REG 0x10 /* not a registered DIMM */
799 #define NX_BOOT_LOADER_MN_ISSUE 0xff00ffff
800 #define NX_PEG_TUNE_MN_PRESENT 0x1
801 #define NX_PEG_TUNE_CAPABILITY (UNM_CAM_RAM(0x02c))
802
803 #define UNM_ROM_LOCK_ID (UNM_CAM_RAM(0x100))
804 #define UNM_I2C_ROM_LOCK_ID (UNM_CAM_RAM(0x104))
805 #define UNM_PHY_LOCK_ID (UNM_CAM_RAM(0x120))
806 #define UNM_CRB_WIN_LOCK_ID (UNM_CAM_RAM(0x124))
807 #define CAM_RAM_DMA_WATCHDOG_CTRL 0x14 /* See dma_watchdog_ctrl_t */
808 #define UNM_EFUSE_CHIP_ID_HIGH (UNM_CAM_RAM(0x18))
809 #define UNM_EFUSE_CHIP_ID_LOW (UNM_CAM_RAM(0x1c))
810
811 #define UNM_FW_VERSION_MAJOR (UNM_CAM_RAM(0x150))
812 #define UNM_FW_VERSION_MINOR (UNM_CAM_RAM(0x154))
813 #define UNM_FW_VERSION_SUB (UNM_CAM_RAM(0x158))
814 #define UNM_TCP_FW_VERSION_MAJOR_ADDR (UNM_CAM_RAM(0x15c))
815 #define UNM_TCP_FW_VERSION_MINOR_ADDR (UNM_CAM_RAM(0x160))
816 #define UNM_TCP_FW_VERSION_SUB_ADDR (UNM_CAM_RAM(0x164))
817 #define UNM_FW_VERSION_BUILD (UNM_CAM_RAM(0x168))
818 #define UNM_PCIE_REG(reg) (UNM_CRB_PCIE + (reg))
819
820 #define PCIE_DCR (0x00d8)
821 #define PCIE_DB_DATA2 (0x10070)
822 #define PCIE_DB_CTRL (0x100a0)
823 #define PCIE_DB_ADDR (0x100a4)
824 #define PCIE_DB_DATA (0x100a8)
825 #define PCIE_IMBUS_CONTROL (0x101b8)
826 #define PCIE_SETUP_FUNCTION (0x12040)
827 #define PCIE_SETUP_FUNCTION2 (0x12048)
828 #define PCIE_TGT_SPLIT_CHICKEN (0x12080)
829 #define PCIE_CHICKEN3 (0x120c8)
830 #define PCIE_MAX_MASTER_SPLIT (0x14048)
831 #define PCIE_MAX_DMA_XFER_SIZE (0x1404c)
832 #define UNM_WOL_WAKE (UNM_CAM_RAM(0x180))
833 #define UNM_WOL_CONFIG_NV (UNM_CAM_RAM(0x184))
834 #define UNM_WOL_CONFIG (UNM_CAM_RAM(0x188))
835 #define UNM_PRE_WOL_RX_ENABLE (UNM_CAM_RAM(0x18c))
836 #define UNM_FW_RESET (UNM_CAM_RAM(0x138))
837 /*
838 * Following define address space withing PCIX CRB space to talk with
839 * devices on the storage side PCI bus.
840 */
841 #define PCIX_PS_MEM_SPACE (0x90000)
842
843 #define UNM_PCIX_PH_REG(reg) (UNM_CRB_PCIE + (reg))
844
845 /*
846 * Configuration registers. These are the same offsets on both host and
847 * storage side PCI blocks.
848 */
849 #define PCIX_PS_OP_ADDR_LO (0x10000) /* Used for PS PCI Memory access */
850 #define PCIX_PS_OP_ADDR_HI (0x10004) /* via CRB (PS side only) */
851
852 #define PCIX_MS_WINDOW (0x10204) /* UNUSED */
853
854 #define PCIX_CRB_WINDOW (0x10210)
855 #define PCIX_CRB_WINDOW_F0 (0x10210)
856 #define PCIX_CRB_WINDOW_F1 (0x10230)
857 #define PCIX_CRB_WINDOW_F2 (0x10250)
858 #define PCIX_CRB_WINDOW_F3 (0x10270)
859 #define PCIX_CRB_WINDOW_F4 (0x102ac)
860 #define PCIX_CRB_WINDOW_F5 (0x102bc)
861 #define PCIX_CRB_WINDOW_F6 (0x102cc)
862 #define PCIX_CRB_WINDOW_F7 (0x102dc)
863 #define PCIE_CRB_WINDOW_REG(func) (((func) < 4) ? \
864 (PCIX_CRB_WINDOW_F0 + (0x20 * (func))) : \
865 (PCIX_CRB_WINDOW_F4 + (0x10 * ((func) - 4))))
866
867 #define PCIX_MN_WINDOW (0x10200)
868 #define PCIX_MN_WINDOW_F0 (0x10200)
869 #define PCIX_MN_WINDOW_F1 (0x10220)
870 #define PCIX_MN_WINDOW_F2 (0x10240)
871 #define PCIX_MN_WINDOW_F3 (0x10260)
872 #define PCIX_MN_WINDOW_F4 (0x102a0)
873 #define PCIX_MN_WINDOW_F5 (0x102b0)
874 #define PCIX_MN_WINDOW_F6 (0x102c0)
875 #define PCIX_MN_WINDOW_F7 (0x102d0)
876 #define PCIE_MN_WINDOW_REG(func) (((func) < 4) ? \
877 (PCIX_MN_WINDOW_F0 + (0x20 * (func))) : \
878 (PCIX_MN_WINDOW_F4 + (0x10 * ((func) - 4))))
879
880 #define PCIX_SN_WINDOW (0x10208)
881 #define PCIX_SN_WINDOW_F0 (0x10208)
882 #define PCIX_SN_WINDOW_F1 (0x10228)
883 #define PCIX_SN_WINDOW_F2 (0x10248)
884 #define PCIX_SN_WINDOW_F3 (0x10268)
885 #define PCIX_SN_WINDOW_F4 (0x102a8)
886 #define PCIX_SN_WINDOW_F5 (0x102b8)
887 #define PCIX_SN_WINDOW_F6 (0x102c8)
888 #define PCIX_SN_WINDOW_F7 (0x102d8)
889 #define PCIE_SN_WINDOW_REG(func) (((func) < 4) ? \
890 (PCIX_SN_WINDOW_F0 + (0x20 * (func))) : \
891 (PCIX_SN_WINDOW_F4 + (0x10 * ((func) - 4))))
892
893 #define UNM_PCIX_PS_REG(reg) (UNM_CRB_PCIX_MD + (reg))
894 #define UNM_PCIX_PS2_REG(reg) (UNM_CRB_PCIE2 + (reg))
895 #define MANAGEMENT_COMMAND_REG (UNM_CRB_PCIE + (4))
896
897 #define UNM_PH_INT_MASK (UNM_CRB_PCIE + PCIX_INT_MASK)
898
899 /*
900 * Definitions relating to access/control of the I2Q h/w block.
901 */
902 /*
903 * Configuration registers.
904 */
905 #define UNM_I2Q_CONFIG (UNM_CRB_I2Q + 0x00000)
906 #define UNM_I2Q_ENA_PCI_LO (UNM_CRB_I2Q + 0x00010)
907 #define UNM_I2Q_ENA_PCI_HI (UNM_CRB_I2Q + 0x00014)
908 #define UNM_I2Q_ENA_CASPER_LO (UNM_CRB_I2Q + 0x00018)
909 #define UNM_I2Q_ENA_CASPER_HI (UNM_CRB_I2Q + 0x0001c)
910 #define UNM_I2Q_ENA_QM_LO (UNM_CRB_I2Q + 0x00020)
911 #define UNM_I2Q_ENA_QM_HI (UNM_CRB_I2Q + 0x00024)
912 #define UNM_I2Q_CLR_PCI_LO (UNM_CRB_I2Q + 0x00030)
913 #define UNM_I2Q_CLR_PCI_HI (UNM_CRB_I2Q + 0x00034)
914 #define UNM_I2Q_CLR_CASPER_LO (UNM_CRB_I2Q + 0x00038)
915 #define UNM_I2Q_CLR_CASPER_HI (UNM_CRB_I2Q + 0x0003c)
916 #define UNM_I2Q_MSG_HDR_LO(I) (UNM_CRB_I2Q + 0x00100 + (I) * 0x8)
917 #define UNM_I2Q_MSG_HDR_HI(I) (UNM_CRB_I2Q + 0x00104 + (I) * 0x8)
918
919 #ifdef PCIX
920 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_HOST + 0x20000 + ((U) << 16))
921 #else
922 #define UNM_DMA_BASE(U) (UNM_CRB_PCIX_MD + 0x20000 + ((U) << 6))
923 #endif
924 #define UNM_DMA_COMMAND(U) (UNM_DMA_BASE(U) + 0x00008)
925
926 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
927 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
928 #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */
929 #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */
930 #define PCIE_SEM4_LOCK (0x1c020) /* I2C lock */
931 #define PCIE_SEM4_UNLOCK (0x1c024) /* I2C unlock */
932 #define PCIE_SEM5_LOCK (0x1c028) /* API lock */
933 #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */
934 #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */
935 #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */
936 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
937 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock */
938
939 #define PCIE_PS_STRAP_RESET (0x18000)
940
941 #define M25P_INSTR_WREN 0x06
942 #define M25P_INSTR_RDSR 0x05
943 #define M25P_INSTR_PP 0x02
944 #define M25P_INSTR_SE 0xd8
945 #define CAM_RAM_P2I_ENABLE 0xc
946 #define CAM_RAM_P2D_ENABLE 0x8
947 #define PCIX_IMBTAG (0x18004)
948
949 #define CAM_RAM_PEG_ENABLES 0x4
950
951 /*
952 * The PCI VendorID and DeviceID for our board.
953 */
954 #define PCI_VENDOR_ID_NX8021 0x4040
955 #define PCI_DEVICE_ID_NX8021_FC 0x0101
956
957 /* ISP 3031 related declarations */
958
959 #define NX_MSIX_MEM_REGION_THRESHOLD 0x2000000
960 #define UNM_MSIX_TBL_SPACE 8192
961 #define UNM_PCI_REG_MSIX_TBL 0x44
962 #define NX_PCI_MSIX_CONTROL 0x40
963
964 typedef struct {
965 uint32_t valid;
966 uint32_t start_128M;
967 uint32_t end_128M;
968 uint32_t start_2M;
969 } crb_128M_2M_sub_block_map_t;
970
971 typedef struct {
972 crb_128M_2M_sub_block_map_t sub_block[16];
973 } crb_128M_2M_block_map_t;
974
975 struct crb_addr_pair {
976 uint32_t addr;
977 uint32_t data;
978 };
979
980 #define ADDR_ERROR ((unsigned long) 0xffffffff)
981 #define MAX_CTL_CHECK 1000
982
983 /*
984 * ************************************************************************
985 * PCI related defines.
986 * ************************************************************************
987 */
988
989 /*
990 * Interrupt related defines.
991 */
992 #define PCIX_TARGET_STATUS (0x10118)
993 #define PCIX_TARGET_STATUS_F1 (0x10160)
994 #define PCIX_TARGET_STATUS_F2 (0x10164)
995 #define PCIX_TARGET_STATUS_F3 (0x10168)
996 #define PCIX_TARGET_STATUS_F4 (0x10360)
997 #define PCIX_TARGET_STATUS_F5 (0x10364)
998 #define PCIX_TARGET_STATUS_F6 (0x10368)
999 #define PCIX_TARGET_STATUS_F7 (0x1036c)
1000
1001 #define PCIX_TARGET_MASK (0x10128)
1002 #define PCIX_TARGET_MASK_F1 (0x10170)
1003 #define PCIX_TARGET_MASK_F2 (0x10174)
1004 #define PCIX_TARGET_MASK_F3 (0x10178)
1005 #define PCIX_TARGET_MASK_F4 (0x10370)
1006 #define PCIX_TARGET_MASK_F5 (0x10374)
1007 #define PCIX_TARGET_MASK_F6 (0x10378)
1008 #define PCIX_TARGET_MASK_F7 (0x1037c)
1009
1010 /*
1011 * Message Signaled Interrupts
1012 */
1013 #define PCIX_MSI_F0 (0x13000)
1014 #define PCIX_MSI_F1 (0x13004)
1015 #define PCIX_MSI_F2 (0x13008)
1016 #define PCIX_MSI_F3 (0x1300c)
1017 #define PCIX_MSI_F4 (0x13010)
1018 #define PCIX_MSI_F5 (0x13014)
1019 #define PCIX_MSI_F6 (0x13018)
1020 #define PCIX_MSI_F7 (0x1301c)
1021 #define PCIX_MSI_F(FUNC) (0x13000 +((FUNC) * 4))
1022
1023 /*
1024 *
1025 */
1026 #define PCIX_INT_VECTOR (0x10100)
1027 #define PCIX_INT_MASK (0x10104)
1028
1029 /*
1030 * Interrupt state machine and other bits.
1031 */
1032 #define PCIE_MISCCFG_RC (0x1206c)
1033
1034
1035 #define ISR_INT_TARGET_STATUS (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS))
1036 #define ISR_INT_TARGET_STATUS_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
1037 #define ISR_INT_TARGET_STATUS_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
1038 #define ISR_INT_TARGET_STATUS_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
1039 #define ISR_INT_TARGET_STATUS_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
1040 #define ISR_INT_TARGET_STATUS_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
1041 #define ISR_INT_TARGET_STATUS_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
1042 #define ISR_INT_TARGET_STATUS_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
1043
1044 #define ISR_INT_TARGET_MASK (UNM_PCIX_PS_REG(PCIX_TARGET_MASK))
1045 #define ISR_INT_TARGET_MASK_F1 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
1046 #define ISR_INT_TARGET_MASK_F2 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
1047 #define ISR_INT_TARGET_MASK_F3 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
1048 #define ISR_INT_TARGET_MASK_F4 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
1049 #define ISR_INT_TARGET_MASK_F5 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
1050 #define ISR_INT_TARGET_MASK_F6 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
1051 #define ISR_INT_TARGET_MASK_F7 (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
1052
1053 #define ISR_INT_VECTOR (UNM_PCIX_PS_REG(PCIX_INT_VECTOR))
1054 #define ISR_INT_MASK (UNM_PCIX_PS_REG(PCIX_INT_MASK))
1055 #define ISR_INT_STATE_REG (UNM_PCIX_PS_REG(PCIE_MISCCFG_RC))
1056
1057 #define ISR_MSI_INT_TRIGGER(FUNC) (UNM_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
1058
1059
1060 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
1061 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
1062
1063 /*
1064 * PCI Interrupt Vector Values.
1065 */
1066 #define PCIX_INT_VECTOR_BIT_F0 0x0080
1067 #define PCIX_INT_VECTOR_BIT_F1 0x0100
1068 #define PCIX_INT_VECTOR_BIT_F2 0x0200
1069 #define PCIX_INT_VECTOR_BIT_F3 0x0400
1070 #define PCIX_INT_VECTOR_BIT_F4 0x0800
1071 #define PCIX_INT_VECTOR_BIT_F5 0x1000
1072 #define PCIX_INT_VECTOR_BIT_F6 0x2000
1073 #define PCIX_INT_VECTOR_BIT_F7 0x4000
1074
1075 #define NX_LEGACY_INTR_CONFIG \
1076 { \
1077 { \
1078 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
1079 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
1080 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
1081 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
1082 \
1083 { \
1084 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
1085 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
1086 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
1087 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
1088 \
1089 { \
1090 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
1091 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
1092 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
1093 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
1094 \
1095 { \
1096 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
1097 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
1098 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
1099 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
1100 \
1101 { \
1102 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
1103 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
1104 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
1105 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
1106 \
1107 { \
1108 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
1109 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
1110 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
1111 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
1112 \
1113 { \
1114 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
1115 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
1116 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
1117 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
1118 \
1119 { \
1120 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
1121 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
1122 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
1123 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
1124 }
1125
1126 #define BOOTLD_START 0x10000
1127 #define IMAGE_START 0x43000
1128
1129 /* Magic number to let user know flash is programmed */
1130 #define UNM_BDINFO_MAGIC 0x12345678
1131 #define FW_SIZE_OFFSET 0x3e840c
1132
1133 #define PCI_CAP_ID_GEN 0x10
1134 #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */
1135 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
1136 #define PCI_EXP_LNKSTA 18 /* Link Status */
1137 #define MAX_CRB_XFORM 60
1138 #define MTU_FUDGE_FACTOR 100
1139
1140 #define crb_addr_transform(name) \
1141 (crb_addr_xform[UNM_HW_PX_MAP_CRB_##name] = \
1142 UNM_HW_CRB_HUB_AGT_ADR_##name << 20)
1143
1144 #define MASK(n) ((1ULL << (n)) - 1)
1145 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
1146 /* 64K? */
1147 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
1148
1149 #define MS_WIN(addr) (addr & 0x0ffc0000)
1150 #define UNM_PCI_MN_2M (0)
1151 #define UNM_PCI_MS_2M (0x80000)
1152 #define UNM_PCI_OCM0_2M (0xc0000)
1153 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
1154 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
1155
1156 #define UNM_BOARDTYPE 0x4008
1157 #define UNM_BOARDNUM 0x400c
1158 #define UNM_CHIPNUM 0x4010
1159
1160 /* CRB window related */
1161 #define CRB_BLK(off) ((off >> 20) & 0x3f)
1162 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
1163 #define CRB_WINDOW_2M (0x130060)
1164 #define UNM_PCI_CAMQM_2M_END (0x04800800UL)
1165 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | \
1166 ((off) & 0xf0000))
1167 #define UNM_PCI_CAMQM_2M_BASE (0x000ff800UL)
1168 #define CRB_INDIRECT_2M (0x1e0000UL)
1169 /* #define ADDR_ERROR ((unsigned long ) 0xffffffff) */
1170
1171 /* PCI Windowing for DDR regions. */
1172 #define QL_8021_ADDR_IN_RANGE(addr, low, high) \
1173 (((addr) <= (high)) && ((addr) >= (low)))
1174
1175 #define CRB_WIN_LOCK_TIMEOUT 100000000
1176 #define ROM_LOCK_TIMEOUT 100
1177 #define ROM_MAX_TIMEOUT 100
1178 #define IDC_LOCK_TIMEOUT 100000000
1179
1180 /*
1181 * IDC parameters are defined in “user area” in the flash
1182 */
1183 #define ROM_DEV_INIT_TIMEOUT 0x3e885c
1184 #define ROM_DRV_RESET_ACK_TIMEOUT 0x3e8860
1185
1186 /*
1187 * Global Data in ql_nx.c source file.
1188 */
1189
1190 /*
1191 * Global Function Prototypes in ql_nx.c source file.
1192 */
1193 void ql_8021_reset_chip(ql_adapter_state_t *);
1194 int ql_8021_load_risc(ql_adapter_state_t *);
1195 void ql_8021_clr_hw_intr(ql_adapter_state_t *);
1196 void ql_8021_clr_fw_intr(ql_adapter_state_t *);
1197 void ql_8021_enable_intrs(ql_adapter_state_t *);
1198 void ql_8021_disable_intrs(ql_adapter_state_t *);
1199 void ql_8021_update_crb_int_ptr(ql_adapter_state_t *);
1200 int ql_8021_rom_read(ql_adapter_state_t *, uint32_t, uint32_t *);
1201 int ql_8021_rom_write(ql_adapter_state_t *, uint32_t, uint32_t);
1202 int ql_8021_rom_erase(ql_adapter_state_t *, uint32_t);
1203 int ql_8021_rom_wrsr(ql_adapter_state_t *, uint32_t);
1204 void ql_8021_set_drv_active(ql_adapter_state_t *);
1205 void ql_8021_clr_drv_active(ql_adapter_state_t *);
1206 uint32_t ql_8021_idc_handler(ql_adapter_state_t *);
1207
1208 #ifdef __cplusplus
1209 }
1210 #endif
1211
1212 #endif /* _QL_NX_H */