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NEX-5717 import QLogic 16G FC drivers
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
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--- old/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_init.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_init.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 -/* Copyright 2009 QLogic Corporation */
22 +/* Copyright 2015 QLogic Corporation */
23 23
24 24 /*
25 - * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
26 - * Use is subject to license terms.
25 + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
27 26 */
28 27
29 28 #ifndef _QL_INIT_H
30 29 #define _QL_INIT_H
31 30
32 31 /*
33 32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
34 33 *
35 34 * ***********************************************************************
36 35 * * **
37 36 * * NOTICE **
38 - * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION **
37 + * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
39 38 * * ALL RIGHTS RESERVED **
40 39 * * **
41 40 * ***********************************************************************
42 41 *
43 42 */
44 43
45 44 #ifdef __cplusplus
46 45 extern "C" {
47 46 #endif
48 47
48 +extern uint32_t ql_task_cb_dly;
49 +
49 50 /*
50 51 * ISP2200 NVRAM structure definition.
51 52 * Little endian except where noted.
52 53 */
53 54 typedef struct nvram {
54 55 /*
55 56 * NVRAM header
56 57 */
57 58 uint8_t id[4];
58 59 uint8_t nvram_version;
59 60 uint8_t reserved_0;
60 61
61 62 /*
62 63 * NVRAM RISC parameter block
63 64 */
64 65 uint8_t parameter_block_version;
65 66 uint8_t reserved_1;
66 67
67 68 /*
68 69 * LSB BIT 0 = enable_hard_loop_id
69 70 * LSB BIT 1 = enable_fairness
70 71 * LSB BIT 2 = enable_full_duplex
71 72 * LSB BIT 3 = enable_fast_posting
72 73 * LSB BIT 4 = enable_target_mode
73 74 * LSB BIT 5 = disable_initiator_mode
74 75 * LSB BIT 6 = enable_adisc
75 76 * LSB BIT 7 = enable_target_inquiry_data
76 77 *
77 78 * MSB BIT 0 = enable_port_update_ae
78 79 * MSB BIT 1 = disable_initial_lip
79 80 * MSB BIT 2 = enable_decending_soft_assign
80 81 * MSB BIT 3 = previous_assigned_addressing
81 82 * MSB BIT 4 = enable_stop_q_on_full
82 83 * MSB BIT 5 = enable_full_login_on_lip
83 84 * MSB BIT 6 = enable_node_name
84 85 * MSB BIT 7 = extended_control_block
85 86 */
86 87 uint8_t firmware_options[2];
87 88
88 89 uint8_t max_frame_length[2];
89 90 uint8_t max_iocb_allocation[2];
90 91 uint8_t execution_throttle[2];
91 92 uint8_t login_retry_count;
92 93 uint8_t retry_delay; /* unused */
93 94 uint8_t port_name[8]; /* Big endian. */
94 95 uint8_t hard_address[2];
95 96 uint8_t inquiry;
96 97 uint8_t login_timeout;
97 98 uint8_t node_name[8]; /* Big endian. */
98 99
99 100 /*
100 101 * LSB BIT 0 = Timer operation mode bit 0
101 102 * LSB BIT 1 = Timer operation mode bit 1
102 103 * LSB BIT 2 = Timer operation mode bit 2
103 104 * LSB BIT 3 = Timer operation mode bit 3
104 105 * LSB BIT 4 = P2P Connection option bit 0
105 106 * LSB BIT 5 = P2P Connection option bit 1
106 107 * LSB BIT 6 = P2P Connection option bit 2
107 108 * LSB BIT 7 = Enable Non part on LIHA failure
108 109 *
109 110 * MSB BIT 0 = Enable class 2
110 111 * MSB BIT 1 = Enable ACK0
111 112 * MSB BIT 2 =
112 113 * MSB BIT 3 =
113 114 * MSB BIT 4 = FC Tape Enable
114 115 * MSB BIT 5 = Enable FC Confirm
115 116 * MSB BIT 6 = Enable command queuing in target mode
116 117 * MSB BIT 7 = No Logo On Link Down
117 118 */
118 119 uint8_t add_fw_opt[2];
119 120 uint8_t response_accumulation_timer;
120 121 uint8_t interrupt_delay_timer;
121 122
122 123 /*
123 124 * LSB BIT 0 = Enable Read xfr_rdy
124 125 * LSB BIT 1 = Soft ID only
125 126 * LSB BIT 2 =
126 127 * LSB BIT 3 =
127 128 * LSB BIT 4 = FCP RSP Payload [0]
128 129 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
129 130 * LSB BIT 6 =
130 131 * LSB BIT 7 =
131 132 *
132 133 * MSB BIT 0 = Sbus enable - 2300
133 134 * MSB BIT 1 =
134 135 * MSB BIT 2 =
135 136 * MSB BIT 3 =
136 137 * MSB BIT 4 =
137 138 * MSB BIT 5 = Enable 50 ohm termination
138 139 * MSB BIT 6 = Data Rate (2300 only)
139 140 * MSB BIT 7 = Data Rate (2300 only)
140 141 */
141 142 uint8_t special_options[2];
142 143
143 144 /* Reserved for expanded RISC parameter block */
144 145 uint8_t reserved_4[26];
145 146
146 147 /*
147 148 * NVRAM host parameter block
148 149 *
149 150 * LSB BIT 0 = unused
150 151 * LSB BIT 1 = disable_bios
151 152 * LSB BIT 2 = disable_luns
152 153 * LSB BIT 3 = enable_selectable_boot
153 154 * LSB BIT 4 = disable_risc_code_load
154 155 * LSB BIT 5 = set_cache_line_size_1
155 156 * LSB BIT 6 = pci_parity_disable
156 157 * LSB BIT 7 = enable_extended_logging
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157 158 *
158 159 * MSB BIT 0 = enable_64bit_addressing
159 160 * MSB BIT 1 = enable_lip_reset
160 161 * MSB BIT 2 = enable_lip_full_login
161 162 * MSB BIT 3 = enable_target_reset
162 163 * MSB BIT 4 = enable_database_storage
163 164 * MSB BIT 5 = unused
164 165 * MSB BIT 6 = unused
165 166 * MSB BIT 7 = unused
166 167 */
167 - uint8_t host_p[2];
168 + uint8_t host_p[2];
168 169
169 - uint8_t boot_node_name[8];
170 - uint8_t boot_lun_number;
171 - uint8_t reset_delay;
172 - uint8_t port_down_retry_count;
173 - uint8_t reserved_5;
170 + uint8_t boot_node_name[8];
171 + uint8_t boot_lun_number;
172 + uint8_t reset_delay;
173 + uint8_t port_down_retry_count;
174 + uint8_t reserved_5;
174 175
175 - uint8_t maximum_luns_per_target[2];
176 + uint8_t maximum_luns_per_target[2];
176 177
177 178 uint8_t reserved_6[14];
178 179
179 180 /* Offset 100 */
180 181 uint8_t reverved_7[12];
181 182
182 183 /* offset 112 */
183 184 uint8_t adapInfo[16]; /* Sun OEM HBA's 23xx only */
184 185
185 186 uint8_t reserved_8[22];
186 187
187 188 /* Offset 150 */
188 189 uint8_t reserved_9[50];
189 190
190 191 /* Offset 200 */
191 192 uint8_t reserved_10[32];
192 193
193 194 /*
194 195 * NVRAM Adapter Features offset 232-239
195 196 *
196 197 * LSB BIT 0 = External GBIC
197 198 * LSB BIT 1 = Risc RAM parity
198 199 * LSB BIT 2 = Buffer Plus Module
199 200 * LSB BIT 3 = Multi Chip Adapter
200 201 * LSB BIT 4 =
201 202 * LSB BIT 5 =
202 203 * LSB BIT 6 =
203 204 * LSB BIT 7 =
204 205 *
205 206 * MSB BIT 0 =
206 207 * MSB BIT 1 =
207 208 * MSB BIT 2 =
208 209 * MSB BIT 3 =
209 210 * MSB BIT 4 =
210 211 * MSB BIT 5 =
211 212 * MSB BIT 6 =
212 213 * MSB BIT 7 =
213 214 */
214 215 uint8_t adapter_features[2];
215 216 uint8_t reserved_11[6];
216 217
217 218 /*
218 219 * Resrved for use with ISP2300 - offset 240
219 220 */
220 221 uint8_t reserved_12[4];
221 222
222 223 /* Subsystem ID must be at offset 244 */
223 224 uint8_t subsystem_vendor_id[2];
224 225
225 226 uint8_t reserved_13[2];
226 227
227 228 /* Subsystem device ID must be at offset 248 */
228 229 uint8_t subsystem_device_id[2];
229 230
230 231 /* Subsystem vendor ID for ISP2200 */
231 232 uint8_t subsystem_vendor_id_2200[2];
232 233
233 234 /* Subsystem device ID for ISP2200 */
234 235 uint8_t subsystem_device_id_2200[2];
235 236
236 237 uint8_t reserved_14;
237 238 uint8_t checksum;
238 239 } nvram_t;
239 240
240 241 /*
241 242 * NVRAM structure definition.
242 243 */
243 244 typedef struct nvram_24xx {
244 245 /* NVRAM header. */
245 246 uint8_t id[4];
246 247 uint8_t nvram_version[2];
247 248 uint8_t reserved_0[2];
248 249
249 250 /* Firmware Initialization Control Block. */
250 251 uint8_t version[2];
251 252 uint8_t reserved_1[2];
252 253 uint8_t max_frame_length[2];
253 254 uint8_t execution_throttle[2];
254 255 uint8_t exchange_count[2];
255 256 uint8_t hard_address[2];
256 257 uint8_t port_name[8];
257 258 uint8_t node_name[8];
258 259 uint8_t login_retry_count[2];
259 260 uint8_t link_down_on_nos[2];
260 261 uint8_t interrupt_delay_timer[2];
261 262 uint8_t login_timeout[2];
262 263
263 264 /*
264 265 * BIT 0 = Hard Assigned Loop ID
265 266 * BIT 1 = Enable Fairness
266 267 * BIT 2 = Enable Full-Duplex
267 268 * BIT 3 = Reserved
268 269 * BIT 4 = Target Mode Enable
269 270 * BIT 5 = Initiator Mode Disable
270 271 * BIT 6 = Reserved
271 272 * BIT 7 = Reserved
272 273 *
273 274 * BIT 8 = Reserved
274 275 * BIT 9 = Disable Initial LIP
275 276 * BIT 10 = Descending Loop ID Search
276 277 * BIT 11 = Previous Assigned Loop ID
277 278 * BIT 12 = Reserved
278 279 * BIT 13 = Full Login after LIP
279 280 * BIT 14 = Node Name Option
280 281 * BIT 15 = Reserved
281 282 *
282 283 * BIT 16-31 = Reserved
283 284 */
284 285 uint8_t firmware_options_1[4];
285 286
286 287 /*
287 288 * BIT 0 = Operation Mode bit 0
288 289 * BIT 1 = Operation Mode bit 1
289 290 * BIT 2 = Operation Mode bit 2
290 291 * BIT 3 = Operation Mode bit 3
291 292 * BIT 4 = Connection Options bit 0
292 293 * BIT 5 = Connection Options bit 1
293 294 * BIT 6 = Connection Options bit 2
294 295 * BIT 7 = Enable Non part on LIHA failure
295 296 *
296 297 * BIT 8 = Enable Class 2
297 298 * BIT 9 = Enable ACK0
298 299 * BIT 10 = Enable Virtual Fabric
299 300 * BIT 11 = Enable FC-SP Security
300 301 * BIT 12 = FC Tape Enable
301 302 * BIT 13 = Reserved
302 303 * BIT 14 = Target PRLI Control
303 304 * BIT 15 = Reserved
304 305 *
305 306 * BIT 16 = Enable Emulated MSIX
306 307 * BIT 17 = Reserved
307 308 * BIT 18 = Enable Alternate Device Number
308 309 * BIT 19 = Enable Alternate Bus Number
309 310 * BIT 20 = Enable Translated Address
310 311 * BIT 21 = Enable VM Security
311 312 * BIT 22 = Enable Interrupt Handshake
312 313 * BIT 23 = Enable Multiple Queue
313 314 *
314 315 * BIT 24 = IOCB Security
315 316 * BIT 25 = qos
316 317 * BIT 26-31 = Reserved
317 318 */
318 319 uint8_t firmware_options_2[4];
319 320
320 321 /*
321 322 * BIT 0 = Reserved
322 323 * BIT 1 = Soft ID only
323 324 * BIT 2 = Reserved
324 325 * BIT 3 = disable split completion timeout
325 326 * BIT 4 = FCP RSP Payload bit 0
326 327 * BIT 5 = FCP RSP Payload bit 1
327 328 * BIT 6 = Enable Rec Out-of-Order data frame handling
328 329 * BIT 7 = Disable Automatic PLOGI on Local Loop
329 330 *
330 331 * BIT 8 = Reserved
331 332 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
332 333 * offset handling
333 334 * BIT 10 = Reserved
334 335 * BIT 11 = Reserved
335 336 * BIT 12 = Reserved
336 337 * BIT 13 = Data Rate bit 0
337 338 * BIT 14 = Data Rate bit 1
338 339 * BIT 15 = Data Rate bit 2
339 340 *
340 341 * BIT 16 = 75-ohm Termination Select
341 342 * BIT 17 = Enable Multiple FCFs
342 343 * BIT 18 = MAC Addressing Mode
343 344 * BIT 19 = MAC Addressing Mode
344 345 * BIT 20 = MAC Addressing Mode
345 346 * BIT 21 = Ethernet Data Rate
346 347 * BIT 22 = Ethernet Data Rate
347 348 * BIT 23 = Ethernet Data Rate
348 349 *
349 350 * BIT 24 = Ethernet Data Rate
350 351 * BIT 25 = Ethernet Data Rate
351 352 * BIT 26 = Enable Ethernet Header ATIO Queue
352 353 * BIT 27 = Enable Ethernet Header Response Queue
353 354 * BIT 28 = SPMA Selection
354 355 * BIT 29 = SPMA Selection
355 356 * BIT 30 = Reserved
356 357 * BIT 31 = Reserved
357 358 */
358 359 uint8_t firmware_options_3[4];
359 360
360 361 union {
361 362 struct {
362 363 /*
363 364 * Offset 56 (38h)
364 365 * Serial Link Control
365 366 * BIT 0 = control enable
366 367 * BIT 1-15 = Reserved
367 368 */
368 369 uint8_t swing_opt[2];
369 370 /*
370 371 * Offset 58 (3Ah)
371 372 * Serial Link Control 1G
372 373 * BIT 0-7 = Reserved
373 374 *
374 375 * BIT 8-10 = output swing
375 376 * BIT 11-13 = output emphasis
376 377 * BIT 14-15 = Reserved
377 378 */
378 379 uint8_t swing_1g[2];
379 380 /*
380 381 * Offset 60 (3Ch)
381 382 * Serial Link Control 2G
382 383 * BIT 0-7 = Reserved
383 384 *
384 385 * BIT 8-10 = output swing
385 386 * BIT 11-13 = output emphasis
386 387 * BIT 14-15 = Reserved
387 388 */
388 389 uint8_t swing_2g[2];
389 390 /*
390 391 * Offset 62 (3Eh)
391 392 * Serial Link Control 4G
392 393 * BIT 0-7 = Reserved
393 394 *
394 395 * BIT 8-10 = output swing
395 396 * BIT 11-13 = output emphasis
396 397 * BIT 14-15 = Reserved
397 398 */
398 399 uint8_t swing_4g[2];
399 400
400 401 /* Offset 64 (40h). */
401 402 uint8_t reserved[32];
402 403 } isp2400;
403 404 struct {
404 405 /*
405 406 * Offset 56 (38h)
406 407 * Serial Link Control
407 408 * BIT 0 = Reserved
408 409 * BIT 1 = 25xx TX control enable
409 410 * BIT 2 = 25xx RX control enable (lmtg)
410 411 * BIT 3 = 25xx RX control enable (linear)
411 412 * BIT 4 = embedded HBA
412 413 * BIT 5 = unused
413 414 * BIT 6 = 25xx E7 Addr27 Preset
414 415 * BIT 7 = 25xx E6 Addr0 Ch0 enable
415 416 *
416 417 * BIT 8-15 = 25xx E6 Addr0 Ch0
417 418 *
418 419 * BIT 16-31 = Reserved
419 420 */
420 421 uint8_t swing_opt[4];
421 422
422 423 /*
423 424 * Offset 60 (3Ch)
424 425 * Serial Link TX Parameters
425 426 * BIT 0 = TX Amplitude
426 427 * BIT 1 = TX Amplitude
427 428 * BIT 2 = TX Amplitude
428 429 * BIT 3 = TX Amplitude
429 430 * BIT 4 = TX Amplitude
430 431 * BIT 5 = TX iPost
431 432 * BIT 6 = TX iPost
432 433 * BIT 7 = TX iPost
433 434 *
434 435 * BIT 8 = TX iPost
435 436 * BIT 9 = TX iPre
436 437 * BIT 10 = TX iPre
437 438 * BIT 11 = TX iPre
438 439 * BIT 12 = TX iPre
439 440 * BIT 13 = TX iMain
440 441 * BIT 14 = TX iMain
441 442 * BIT 15 = TX iMain
442 443 *
443 444 * BIT 16 = TX iMain
444 445 * BIT 17 = TX iMain
445 446 * BIT 18-23 = Reserved
446 447 *
447 448 * BIT 24-31 = Reserved
448 449 */
449 450 uint8_t tx_8g[4];
450 451 /* Offset 64 (40h) */
451 452 uint8_t tx_4g[4];
452 453 /* Offset 68 (44h) */
453 454 uint8_t tx_2g[4];
454 455
455 456 /*
456 457 * Offset 72 (48h)
457 458 * Serial Link RX Parameters
458 459 * BIT 0 = RX Z1Cnt
459 460 * BIT 1 = RX Z1Cnt
460 461 * BIT 2 = RX Z1Cnt
461 462 * BIT 3 = RX Z1Cnt
462 463 * BIT 4 = RX G1Cnt
463 464 * BIT 5 = RX ZCnt
464 465 * BIT 6 = RX ZCnt
465 466 * BIT 7 = RX ZCnt
466 467 *
467 468 * BIT 8 = RX ZCnt
468 469 * BIT 9 = RX ZCnt
469 470 * BIT 10 = RX TLTH
470 471 * BIT 11 = RX TLTH
471 472 * BIT 12 = RX TLTH
472 473 * BIT 13 = RX TLTH
473 474 * BIT 14 = RX TLTH
474 475 * BIT 15 = RX TLTH
475 476 *
476 477 * BIT 16 = RX DFELTH
477 478 * BIT 17 = RX DFELTH
478 479 * BIT 18 = RX DFELTH
479 480 * BIT 19 = RX DFELTH
480 481 * BIT 20 = RX DFELTH
481 482 * BIT 21 = RX DFELTH
482 483 * BIT 22-23 = Reserved
483 484 *
484 485 * BIT 24-31 = Reserved
485 486 */
486 487 uint8_t rx_limit_8g[4];
487 488 /* Offset 76 (4Ch) */
488 489 uint8_t rx_limit_4g[4];
489 490 /* Offset 80 (50h) */
490 491 uint8_t rx_limit_2g[4];
491 492 /* Offset 84 (54h) */
492 493 uint8_t rx_linear_8g[4];
493 494 /* Offset 88 (58h) */
494 495 uint8_t rx_linear_4g[4];
495 496 /* Offset 92 (5Ch) */
496 497 uint8_t rx_linear_2g[4];
497 498 } isp2500;
498 499 struct {
499 500 /* Offset 56 (38h) */
500 501 uint8_t reserved[8];
501 502
502 503 /* Offset 64 (40h). */
503 504 uint8_t e_node_mac_addr[6];
504 505
505 506 /* Offset 70 (46h). */
506 507 uint8_t reserved2[26];
507 508 } isp8001;
508 509 } fw;
509 510
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510 511 /*
511 512 * Offset 96 (60h)
512 513 * BIT 0 = initiator op
513 514 * BIT 1 = target op
514 515 * BIT 2 = VI op
515 516 * BIT 3-7 = Reserved
516 517 */
517 518 uint8_t oem_specific;
518 519 uint8_t reserved_4[15];
519 520
520 - /* Offset 112 (70h). */
521 - uint8_t reserved_5[16];
521 + /*
522 + * Offset 112 (70h).
523 + * BIT 0 = additional receive credits
524 + * BIT 1 = additional receive credits
525 + * BIT 2-15 = Reserved
526 + */
527 + uint8_t execute_fw_options[2];
528 + uint8_t reserved_5[14];
522 529
523 530 /*
524 531 * Offset 128 (80h).
525 532 * PCIe table entries.
526 533 * Firmware Extended Initialization Control Block.
527 534 */
528 535 ql_ext_icb_8100_t ext_blk;
529 536
530 537 /* Offset 192. */
531 538 uint8_t reserved_6[32];
532 539
533 540 /* Offset 224. */
534 541 uint8_t reserved_7[32];
535 542
536 543 /*
537 544 * BIT 0 = Enable spinup delay
538 545 * BIT 1 = Disable BIOS
539 546 * BIT 2 = Enable Memory Map BIOS
540 547 * BIT 3 = Enable Selectable Boot
541 548 * BIT 4 = Disable RISC code load
542 549 * BIT 5 = Disable serdes
543 550 * BIT 6 = Enable opt boot mode
544 551 * BIT 7 = Enable int mode BIOS
545 552 *
546 553 * BIT 8 = EV control enable
547 554 * BIT 9 = Enable lip reset
548 555 * BIT 10 = Enable lip full login
549 556 * BIT 11 = Enable target reset
550 557 * BIT 12 = Stop firmware
551 558 * BIT 13 = Default Node Name Option
552 559 * BIT 14 = Default WWPN valid
553 560 * BIT 15 = Enable alternate WWN
554 561 *
555 562 * CLP BIOS flags
556 563 *
557 564 * BIT 16 = clp lun string
558 565 * BIT 17 = clp target string
559 566 * BIT 18 = clp bios enable string
560 567 * BIT 19 = clp serdes_string
561 568 * BIT 20 = clp wwpn string
562 569 * BIT 21 = clp wwnn string
563 570 * BIT 22 = win reserverd 0
564 571 * BIT 23 = win reserverd 1
565 572 *
566 573 * BIT 24 = keep wwpn
567 574 * BIT 25 = temp wwpn
568 575 * BIT 26 = win reserverd 2
569 576 * BIT 27 = win reserverd 3
570 577 * BIT 28 = clear WBT in flash (win driver)
571 578 * BIT 29 = write WBT in flash (win driver)
572 579 * BIT 30 = load fw from flash (win driver)
573 580 * BIT 31 = enable alternate WWN (win driver)
574 581 */
575 582 uint8_t host_p[4];
576 583
577 584 uint8_t alternate_port_name[8];
578 585 uint8_t alternate_node_name[8];
579 586
580 587 uint8_t boot_port_name[8];
581 588 uint8_t boot_lun_number[2];
582 589 uint8_t reserved_8[2];
583 590
584 591 uint8_t alt1_boot_port_name[8];
585 592 uint8_t alt1_boot_lun_number[2];
586 593 uint8_t reserved_9[2];
587 594
588 595 uint8_t alt2_boot_port_name[8];
589 596 uint8_t alt2_boot_lun_number[2];
590 597 uint8_t reserved_10[2];
591 598
592 599 uint8_t alt3_boot_port_name[8];
593 600 uint8_t alt3_boot_lun_number[2];
594 601 uint8_t reserved_11[2];
595 602
596 603 /*
597 604 * BIT 0 = Selective Login
598 605 * BIT 1 = Alt-Boot Enable
599 606 * BIT 2 = Reserved
600 607 * BIT 3 = Enable Boot Order List
601 608 * BIT 4 = Reserved
602 609 * BIT 5 = Enable Selective LUN
603 610 * BIT 6 = Reserved
604 611 * BIT 7-31 =
605 612 */
606 613 uint8_t efi_parameters[4];
607 614
608 615 uint8_t reset_delay;
609 616 uint8_t reserved_12;
610 617 uint8_t reserved_13[2];
611 618
612 619 uint8_t boot_id_number[2];
613 620 uint8_t reserved_14[2];
614 621
615 622 uint8_t max_luns_per_target[2];
616 623 uint8_t reserved_15[2];
617 624
618 625 uint8_t port_down_retry_count[2];
619 626 uint8_t link_down_timeout[2];
620 627
621 628 /*
622 629 * FCode parameters word (offset 344)
623 630 *
624 631 * BIT 0 = Enable BIOS pathname
625 632 * BIT 1 = fcode qlc
626 633 * BIT 2 = fcode host
627 634 * BIT 3 = fcode sunid
628 635 * BIT 4-7 =
629 636 */
630 637 uint8_t fcode_p0;
631 638 uint8_t reserved_16[7];
632 639
633 640 /*
634 641 * Offset 352 (160h).
635 642 * uint8_t prev_drv_ver_major;
636 643 * uint8_t prev_drv_ver_submajob;
637 644 * uint8_t prev_drv_ver_minor;
638 645 * uint8_t prev_drv_ver_subminor;
639 646 * uint8_t prev_bios_ver_major[2];
640 647 * uint8_t prev_bios_ver_minor[2];
641 648 * uint8_t prev_efi_ver_major[2];
642 649 * uint8_t prev_efi_ver_minor[2];
643 650 * uint8_t prev_fw_ver_major[2];
644 651 * uint8_t prev_fw_ver_minor;
645 652 * uint8_t prev_fw_ver_subminor;
646 653 * uint8_t reserved[16];
647 654 */
648 655 uint8_t mac_address[6];
649 656 uint8_t clp_flag[2];
650 657 uint8_t reserved_18[24];
651 658
652 659 /* Offset 384 (180h). */
653 660 uint8_t def_port_name[8];
654 661 uint8_t def_node_name[8];
655 662 uint8_t clp_flag1[2];
656 663 uint8_t clp_flag2[2];
657 664
658 665 /* Offset 404 (194h). */
659 666 uint8_t default_firmware_options[2];
660 667
661 668 /* Offset 406 (196h). */
662 669 uint8_t enhanced_features[2];
663 670 uint8_t serdes_index[2];
664 671 uint8_t reserved_19[6];
665 672
666 673 /* Offset 416 (1A0h). */
667 674 uint8_t alt4_boot_port_name[8];
668 675 uint8_t alt4_boot_lun_number[2];
669 676 uint8_t reserved_20[2];
670 677
671 678 /* Offset 428 (1ACh). */
672 679 uint8_t alt5_boot_port_name[8];
673 680 uint8_t alt5_boot_lun_number[2];
674 681 uint8_t reserved_21[2];
675 682
676 683 /* Offset 440 (1B8h). */
677 684 uint8_t alt6_boot_port_name[8];
678 685 uint8_t alt6_boot_lun_number[2];
679 686 uint8_t reserved_22[2];
680 687
681 688 /* Offset 452 (1C4h). */
682 689 uint8_t alt7_boot_port_name[8];
683 690 uint8_t alt7_boot_lun_number[2];
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684 691 uint8_t reserved_23[2];
685 692
686 693 /* Offset 464 (1D0h). */
687 694 uint8_t reserved_24[12];
688 695
689 696 /* Offset 476 (1DCh). */
690 697 uint8_t fw_table_offset[2];
691 698 uint8_t fw_table_sig[2];
692 699
693 700 /* Offset 480 (1E0h). */
694 - int8_t model_name[4];
695 - int8_t model_name1[12]; /* 24xx power_table[8]. */
701 + int8_t model_name[4];
702 + int8_t model_name1[12]; /* 24xx power_table[8]. */
696 703
697 704 /* Offset 496 (1F0h). */
698 705 uint8_t feature_mask_l[2];
699 706 uint8_t feature_mask_h[2];
700 707 uint8_t reserved_25[4];
701 708
702 709 /* Offset 504 (1F8h). */
703 710 uint8_t subsystem_vendor_id[2];
704 711 uint8_t subsystem_device_id[2];
705 712
706 713 uint8_t checksum[4];
707 714 } nvram_24xx_t;
708 715
709 716 /*
710 717 * Firmware Dump structure definition
711 718 */
712 -#define QL_2200_FW_DUMP_SIZE 0x68000 /* bytes */
713 -#define QL_2300_FW_DUMP_SIZE 0xE2000 /* bytes */
714 -#define QL_6322_FW_DUMP_SIZE 0xE2000 /* bytes */
715 -#define QL_24XX_FW_DUMP_SIZE 0x0330000 /* bytes */
716 -#define QL_25XX_FW_DUMP_SIZE 0x0330000 /* bytes */
719 +#define QL_2200_FW_DUMP_SIZE 0x100000 /* 86e15 bytes */
720 +#define QL_2300_FW_DUMP_SIZE 0x100000 /* fc6d3 bytes */
721 +#define QL_6322_FW_DUMP_SIZE 0x100000 /* fc6d8 bytes */
722 +#define QL_24XX_FW_DUMP_SIZE 0x300000 /* 2cef71 bytes */
723 +#define QL_25XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */
724 +#define QL_81XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */
725 +#define QL_27XX_FW_DUMP_SIZE 0x600000 /* 5c3e69 bytes */
726 +#define QL_83XX_FW_DUMP_SIZE 0x400000 /* 372792 bytes */
717 727
718 728 #define QL_24XX_VPD_SIZE 0x200 /* bytes */
719 729 #define QL_24XX_SFP_SIZE 0x200 /* bytes */
720 730
721 731 /*
722 732 * firmware dump struct for 2300 is a superset of firmware dump struct
723 733 * for 2200. Fields which are 2300 only or are enhanced for 2300 are
724 734 * marked below.
725 735 */
726 736 typedef struct ql_fw_dump {
727 737 uint16_t pbiu_reg[8];
728 738 uint16_t risc_host_reg[8]; /* 2300 only. */
729 739 uint16_t mailbox_reg[16]; /* 2200 only needs 8 */
730 740 uint16_t resp_dma_reg[32]; /* 2300 only. */
731 741 uint16_t dma_reg[48];
732 742 uint16_t risc_hdw_reg[16];
733 743 uint16_t risc_gp0_reg[16];
734 744 uint16_t risc_gp1_reg[16];
735 745 uint16_t risc_gp2_reg[16];
736 746 uint16_t risc_gp3_reg[16];
737 747 uint16_t risc_gp4_reg[16];
738 748 uint16_t risc_gp5_reg[16];
739 749 uint16_t risc_gp6_reg[16];
740 750 uint16_t risc_gp7_reg[16];
741 751 uint16_t frame_buf_hdw_reg[64]; /* 2200 has only 16 */
742 752 uint16_t fpm_b0_reg[64];
743 753 uint16_t fpm_b1_reg[64];
744 754 uint16_t risc_ram[0xf800]; /* 2200 needs only 0xf000 */
745 755 uint16_t stack_ram[0x800]; /* 2300 only */
746 756 uint16_t data_ram[0xf800]; /* 2300 only */
747 757 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
748 758 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
749 759 } ql_fw_dump_t;
750 760
751 761 typedef struct ql_24xx_fw_dump {
752 762 uint32_t hccr;
753 763 uint32_t host_reg[32];
754 764 uint16_t mailbox_reg[32];
755 765 uint32_t xseq_gp_reg[128];
756 766 uint32_t xseq_0_reg[16];
757 767 uint32_t xseq_1_reg[16];
758 768 uint32_t rseq_gp_reg[128];
759 769 uint32_t rseq_0_reg[16];
760 770 uint32_t rseq_1_reg[16];
761 771 uint32_t rseq_2_reg[16];
762 772 uint32_t cmd_dma_reg[16];
763 773 uint32_t req0_dma_reg[15];
764 774 uint32_t resp0_dma_reg[15];
765 775 uint32_t req1_dma_reg[15];
766 776 uint32_t xmt0_dma_reg[32];
767 777 uint32_t xmt1_dma_reg[32];
768 778 uint32_t xmt2_dma_reg[32];
769 779 uint32_t xmt3_dma_reg[32];
770 780 uint32_t xmt4_dma_reg[32];
771 781 uint32_t xmt_data_dma_reg[16];
772 782 uint32_t rcvt0_data_dma_reg[32];
773 783 uint32_t rcvt1_data_dma_reg[32];
774 784 uint32_t risc_gp_reg[128];
775 785 uint32_t shadow_reg[7];
776 786 uint32_t lmc_reg[112];
777 787 uint32_t fpm_hdw_reg[192];
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778 788 uint32_t fb_hdw_reg[176];
779 789 uint32_t code_ram[0x2000];
780 790 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
781 791 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
782 792 uint32_t ext_trace_buf[FWEXTSIZE / 4];
783 793 uint32_t fce_trace_buf[FWFCESIZE / 4];
784 794 uint32_t ext_mem[1];
785 795 } ql_24xx_fw_dump_t;
786 796
787 797 typedef struct ql_25xx_fw_dump {
798 + uint32_t hccr;
788 799 uint32_t r2h_status;
800 + uint32_t aer_ues;
789 801 uint32_t hostrisc_reg[32];
790 802 uint32_t pcie_reg[4];
791 803 uint32_t host_reg[32];
792 804 uint16_t mailbox_reg[32];
793 805 uint32_t xseq_gp_reg[128];
794 806 uint32_t xseq_0_reg[48];
795 807 uint32_t xseq_1_reg[16];
796 808 uint32_t rseq_gp_reg[128];
797 809 uint32_t rseq_0_reg[32];
798 810 uint32_t rseq_1_reg[16];
799 811 uint32_t rseq_2_reg[16];
800 812 uint32_t aseq_gp_reg[128];
801 813 uint32_t aseq_0_reg[32];
802 814 uint32_t aseq_1_reg[16];
803 815 uint32_t aseq_2_reg[16];
804 816 uint32_t cmd_dma_reg[16];
805 817 uint32_t req0_dma_reg[15];
806 818 uint32_t resp0_dma_reg[15];
807 819 uint32_t req1_dma_reg[15];
808 820 uint32_t xmt0_dma_reg[32];
809 821 uint32_t xmt1_dma_reg[32];
810 822 uint32_t xmt2_dma_reg[32];
811 823 uint32_t xmt3_dma_reg[32];
812 824 uint32_t xmt4_dma_reg[32];
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813 825 uint32_t xmt_data_dma_reg[16];
814 826 uint32_t rcvt0_data_dma_reg[32];
815 827 uint32_t rcvt1_data_dma_reg[32];
816 828 uint32_t risc_gp_reg[128];
817 829 uint32_t shadow_reg[11];
818 830 uint32_t risc_io;
819 831 uint32_t lmc_reg[128];
820 832 uint32_t fpm_hdw_reg[192];
821 833 uint32_t fb_hdw_reg[192];
822 834 uint32_t code_ram[0x2000];
823 - uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
824 - uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
825 835 uint32_t ext_trace_buf[FWEXTSIZE / 4];
826 836 uint32_t fce_trace_buf[FWFCESIZE / 4];
827 - uint32_t ext_mem[1];
837 + uint32_t req_q_size[2];
838 + uint32_t rsp_q_size;
839 + uint32_t req_rsp_ext_mem[1];
828 840 } ql_25xx_fw_dump_t;
829 841
830 842 typedef struct ql_81xx_fw_dump {
843 + uint32_t hccr;
831 844 uint32_t r2h_status;
845 + uint32_t aer_ues;
832 846 uint32_t hostrisc_reg[32];
833 847 uint32_t pcie_reg[4];
834 848 uint32_t host_reg[32];
835 849 uint16_t mailbox_reg[32];
836 850 uint32_t xseq_gp_reg[128];
837 851 uint32_t xseq_0_reg[48];
838 852 uint32_t xseq_1_reg[16];
839 853 uint32_t rseq_gp_reg[128];
840 854 uint32_t rseq_0_reg[32];
841 855 uint32_t rseq_1_reg[16];
842 856 uint32_t rseq_2_reg[16];
843 857 uint32_t aseq_gp_reg[128];
844 858 uint32_t aseq_0_reg[32];
845 859 uint32_t aseq_1_reg[16];
846 860 uint32_t aseq_2_reg[16];
847 861 uint32_t cmd_dma_reg[16];
848 862 uint32_t req0_dma_reg[15];
849 863 uint32_t resp0_dma_reg[15];
850 864 uint32_t req1_dma_reg[15];
851 865 uint32_t xmt0_dma_reg[32];
852 866 uint32_t xmt1_dma_reg[32];
853 867 uint32_t xmt2_dma_reg[32];
854 868 uint32_t xmt3_dma_reg[32];
855 869 uint32_t xmt4_dma_reg[32];
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856 870 uint32_t xmt_data_dma_reg[16];
857 871 uint32_t rcvt0_data_dma_reg[32];
858 872 uint32_t rcvt1_data_dma_reg[32];
859 873 uint32_t risc_gp_reg[128];
860 874 uint32_t shadow_reg[11];
861 875 uint32_t risc_io;
862 876 uint32_t lmc_reg[128];
863 877 uint32_t fpm_hdw_reg[224];
864 878 uint32_t fb_hdw_reg[208];
865 879 uint32_t code_ram[0x2000];
866 - uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
867 - uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
868 880 uint32_t ext_trace_buf[FWEXTSIZE / 4];
869 881 uint32_t fce_trace_buf[FWFCESIZE / 4];
870 - uint32_t ext_mem[1];
882 + uint32_t req_q_size[2];
883 + uint32_t rsp_q_size;
884 + uint32_t req_rsp_ext_mem[1];
871 885 } ql_81xx_fw_dump_t;
872 886
887 +typedef struct ql_83xx_fw_dump {
888 + uint32_t hccr;
889 + uint32_t r2h_status;
890 + uint32_t aer_ues;
891 + uint32_t hostrisc_reg[48];
892 + uint32_t pcie_reg[4];
893 + uint32_t host_reg[32];
894 + uint16_t mailbox_reg[32];
895 + uint32_t xseq_gp_reg[256];
896 + uint32_t xseq_0_reg[48];
897 + uint32_t xseq_1_reg[16];
898 + uint32_t xseq_2_reg[16];
899 + uint32_t rseq_gp_reg[256];
900 + uint32_t rseq_0_reg[32];
901 + uint32_t rseq_1_reg[16];
902 + uint32_t rseq_2_reg[16];
903 + uint32_t rseq_3_reg[16];
904 + uint32_t aseq_gp_reg[256];
905 + uint32_t aseq_0_reg[32];
906 + uint32_t aseq_1_reg[16];
907 + uint32_t aseq_2_reg[16];
908 + uint32_t aseq_3_reg[16];
909 + uint32_t cmd_dma_reg[64];
910 + uint32_t req0_dma_reg[15];
911 + uint32_t resp0_dma_reg[15];
912 + uint32_t req1_dma_reg[15];
913 + uint32_t xmt0_dma_reg[32];
914 + uint32_t xmt1_dma_reg[32];
915 + uint32_t xmt2_dma_reg[32];
916 + uint32_t xmt3_dma_reg[32];
917 + uint32_t xmt4_dma_reg[32];
918 + uint32_t xmt_data_dma_reg[16];
919 + uint32_t rcvt0_data_dma_reg[32];
920 + uint32_t rcvt1_data_dma_reg[32];
921 + uint32_t risc_gp_reg[128];
922 + uint32_t shadow_reg[11];
923 + uint32_t risc_io;
924 + uint32_t lmc_reg[128];
925 + uint32_t fpm_hdw_reg[256];
926 + uint32_t rq0_array_reg[256];
927 + uint32_t rq1_array_reg[256];
928 + uint32_t rp0_array_reg[256];
929 + uint32_t rp1_array_reg[256];
930 + uint32_t ato_array_reg[128];
931 + uint32_t queue_control_reg[16];
932 + uint32_t fb_hdw_reg[432];
933 + uint32_t code_ram[0x2400];
934 + uint32_t ext_trace_buf[FWEXTSIZE / 4];
935 + uint32_t fce_trace_buf[FWFCESIZE / 4];
936 + uint32_t req_q_size[2];
937 + uint32_t rsp_q_size;
938 + uint32_t req_rsp_ext_mem[1];
939 +} ql_83xx_fw_dump_t;
940 +
873 941 #ifdef _KERNEL
874 942
875 943 /*
944 + * firmware dump Entry Types
945 + */
946 +#define DT_NOP 0
947 +#define DT_THDR 99
948 +#define DT_TEND 255
949 +#define DT_RIOB1 256
950 +#define DT_WIOB1 257
951 +#define DT_RIOB2 258
952 +#define DT_WIOB2 259
953 +#define DT_RPCI 260
954 +#define DT_WPCI 261
955 +#define DT_RRAM 262
956 +#define DT_GQUE 263
957 +#define DT_GFCE 264
958 +#define DT_PRISC 265
959 +#define DT_RRISC 266
960 +#define DT_DINT 267
961 +#define DT_GHBD 268
962 +#define DT_SCRA 269
963 +#define DT_RRREG 270
964 +#define DT_WRREG 271
965 +#define DT_RRRAM 272
966 +#define DT_RPCIC 273
967 +#define DT_GQUES 274
968 +#define DT_WDMP 275
969 +
970 +/*
971 + * firmware dump Template Header (Entry Type 99)
972 + */
973 +typedef struct ql_dt_hdr {
974 + uint32_t type;
975 + uint32_t first_entry_offset;
976 + uint32_t size_of_template;
977 + uint32_t rsv;
978 + uint32_t num_of_entries;
979 + uint32_t version;
980 + uint32_t driver_timestamp;
981 + uint32_t checksum;
982 + uint32_t rsv_1;
983 + uint32_t driver_info[3];
984 + uint32_t saved_state_area[16];
985 + uint32_t rsv_2[8];
986 + uint32_t ver_attr[5];
987 +} ql_dt_hdr_t;
988 +
989 +/*
990 + * firmware dump Common Entry Header
991 + */
992 +typedef struct ql_dt_entry_hdr {
993 + uint32_t type;
994 + uint32_t size;
995 + uint32_t rsv;
996 +#ifdef _BIG_ENDIAN
997 + uint8_t driver_flags;
998 + uint8_t rsv_2;
999 + uint8_t rsv_1;
1000 + uint8_t capture_flags;
1001 +#else
1002 + uint8_t capture_flags;
1003 + uint8_t rsv_1;
1004 + uint8_t rsv_2;
1005 + uint8_t driver_flags;
1006 +#endif
1007 +} ql_dt_entry_hdr_t;
1008 +
1009 +/*
1010 + * Capture Flags
1011 + */
1012 +#define PF_ONLY_FLAG BIT_0 /* Physical Function Only */
1013 +#define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */
1014 +
1015 +/*
1016 + * Driver Flags
1017 + */
1018 +#define SKIPPED_FLAG BIT_7 /* driver skipped this entry */
1019 +
1020 +/*
1021 + * firmware dump Entry Including Header
1022 + */
1023 +typedef struct ql_dt_entry {
1024 + ql_dt_entry_hdr_t h;
1025 + uint32_t data[1];
1026 +} ql_dt_entry_t;
1027 +
1028 +/*
1029 + * firmware dump Template image
1030 + */
1031 +typedef struct ql_dmp_template {
1032 + uint32_t rsv[2];
1033 + uint32_t len;
1034 + uint32_t major_ver;
1035 + uint32_t minor_ver;
1036 + uint32_t subminor_ver;
1037 + uint32_t attribute;
1038 + ql_dt_hdr_t hdr;
1039 + ql_dt_entry_t entries[1];
1040 +} ql_dmp_template_t;
1041 +
1042 +typedef struct ql_dt_riob1 {
1043 + ql_dt_entry_hdr_t h;
1044 + uint32_t addr;
1045 +#ifdef _BIG_ENDIAN
1046 + uint8_t pci_offset;
1047 + uint8_t reg_count_h;
1048 + uint8_t reg_count_l;
1049 + uint8_t reg_size;
1050 +#else
1051 + uint8_t reg_size;
1052 + uint8_t reg_count_l;
1053 + uint8_t reg_count_h;
1054 + uint8_t pci_offset;
1055 +#endif
1056 +} ql_dt_riob1_t;
1057 +
1058 +typedef struct ql_dt_wiob1 {
1059 + ql_dt_entry_hdr_t h;
1060 + uint32_t addr;
1061 + uint32_t data;
1062 +#ifdef _BIG_ENDIAN
1063 + uint8_t rsv[3];
1064 + uint8_t pci_offset;
1065 +#else
1066 + uint8_t pci_offset;
1067 + uint8_t rsv[3];
1068 +#endif
1069 +} ql_dt_wiob1_t;
1070 +
1071 +typedef struct ql_dt_riob2 {
1072 + ql_dt_entry_hdr_t h;
1073 + uint32_t addr;
1074 +#ifdef _BIG_ENDIAN
1075 + uint8_t pci_offset;
1076 + uint8_t reg_count_h;
1077 + uint8_t reg_count_l;
1078 + uint8_t reg_size;
1079 + uint8_t rsv[3];
1080 + uint8_t bank_sel_offset;
1081 +#else
1082 + uint8_t reg_size;
1083 + uint8_t reg_count_l;
1084 + uint8_t reg_count_h;
1085 + uint8_t pci_offset;
1086 + uint8_t bank_sel_offset;
1087 + uint8_t rsv[3];
1088 +#endif
1089 + uint32_t reg_bank;
1090 +} ql_dt_riob2_t;
1091 +
1092 +typedef struct ql_dt_wiob2 {
1093 + ql_dt_entry_hdr_t h;
1094 + uint32_t addr;
1095 +#ifdef _BIG_ENDIAN
1096 + uint8_t rsv[2];
1097 + uint8_t data_h;
1098 + uint8_t data_l;
1099 + uint8_t bank_sel_offset;
1100 + uint8_t pci_offset;
1101 + uint8_t rsv1[2];
1102 +#else
1103 + uint8_t data_l;
1104 + uint8_t data_h;
1105 + uint8_t rsv[2];
1106 + uint8_t rsv1[2];
1107 + uint8_t pci_offset;
1108 + uint8_t bank_sel_offset;
1109 +#endif
1110 + uint32_t reg_bank;
1111 +} ql_dt_wiob2_t;
1112 +
1113 +typedef struct ql_dt_rpci {
1114 + ql_dt_entry_hdr_t h;
1115 + uint32_t addr;
1116 +} ql_dt_rpci_t;
1117 +
1118 +typedef struct ql_dt_wpci {
1119 + ql_dt_entry_hdr_t h;
1120 + uint32_t addr;
1121 + uint32_t data;
1122 +} ql_dt_wpci_t, ql_dt_wrreg_t;
1123 +
1124 +typedef struct ql_dt_rram {
1125 + ql_dt_entry_hdr_t h;
1126 +#ifdef _BIG_ENDIAN
1127 + uint8_t rsv[3];
1128 + uint8_t ram_area;
1129 +#else
1130 + uint8_t ram_area;
1131 + uint8_t rsv[3];
1132 +#endif
1133 + uint32_t start_addr;
1134 + uint32_t end_addr;
1135 +} ql_dt_rram_t;
1136 +
1137 +typedef struct ql_dt_gque {
1138 + ql_dt_entry_hdr_t h;
1139 + uint32_t num_queues;
1140 +#ifdef _BIG_ENDIAN
1141 + uint8_t rsv[3];
1142 + uint8_t queue_type;
1143 +#else
1144 + uint8_t queue_type;
1145 + uint8_t rsv[3];
1146 +#endif
1147 +} ql_dt_gque_t, ql_dt_gques_t;
1148 +
1149 +typedef struct ql_dt_gfce {
1150 + ql_dt_entry_hdr_t h;
1151 + uint32_t fce_trace_size;
1152 + uint32_t write_pointer[2];
1153 + uint32_t base_pointer[2];
1154 + uint32_t fce_enable_mb0;
1155 + uint32_t fce_enable_mb2;
1156 + uint32_t fce_enable_mb3;
1157 + uint32_t fce_enable_mb4;
1158 + uint32_t fce_enable_mb5;
1159 + uint32_t fce_enable_mb6;
1160 +} ql_dt_gfce_t;
1161 +
1162 +typedef struct ql_dt_prisc {
1163 + ql_dt_entry_hdr_t h;
1164 +} ql_dt_prisc_t, ql_dt_rrisc_t;
1165 +
1166 +typedef struct ql_dt_dint {
1167 + ql_dt_entry_hdr_t h;
1168 +#ifdef _BIG_ENDIAN
1169 + uint8_t rsv[3];
1170 + uint8_t pci_offset;
1171 +#else
1172 + uint8_t pci_offset;
1173 + uint8_t rsv[3];
1174 +#endif
1175 + uint32_t data;
1176 +} ql_dt_dint_t;
1177 +
1178 +typedef struct ql_dt_ghbd {
1179 + ql_dt_entry_hdr_t h;
1180 +#ifdef _BIG_ENDIAN
1181 + uint8_t rsv[3];
1182 + uint8_t host_buf_type;
1183 +#else
1184 + uint8_t host_buf_type;
1185 + uint8_t rsv[3];
1186 +#endif
1187 + uint32_t buf_size;
1188 + uint32_t start_addr;
1189 +} ql_dt_ghbd_t;
1190 +
1191 +typedef struct ql_dt_scra {
1192 + ql_dt_entry_hdr_t h;
1193 + uint32_t scratch_size;
1194 +} ql_dt_scra_t;
1195 +
1196 +typedef struct ql_dt_rrreg {
1197 + ql_dt_entry_hdr_t h;
1198 + uint32_t addr;
1199 + uint32_t count;
1200 +} ql_dt_rrreg_t, ql_dt_rrram_t, ql_dt_rpcic_t;
1201 +
1202 +typedef struct ql_dt_wdmp {
1203 + ql_dt_entry_hdr_t h;
1204 + uint32_t length;
1205 + uint32_t data[1];
1206 +} ql_dt_wdmp_t;
1207 +
1208 +/*
876 1209 * ql_lock_nvram() flags
877 1210 */
878 1211 #define LNF_NVRAM_DATA BIT_0 /* get nvram */
879 1212 #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */
880 1213
881 1214 /*
882 1215 * ISP product identification definitions in mailboxes after reset.
883 1216 */
884 1217 #define PROD_ID_1 0x4953
885 1218 #define PROD_ID_2 0x0000
886 1219 #define PROD_ID_2a 0x5020
887 1220 #define PROD_ID_3 0x2020
888 1221
889 1222 /*
890 1223 * NVRAM Command values.
891 1224 */
892 1225 #define NV_START_BIT BIT_2
893 -#define NV_WRITE_OP (BIT_26+BIT_24)
894 -#define NV_READ_OP (BIT_26+BIT_25)
895 -#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
896 -#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1226 +#define NV_WRITE_OP (BIT_26 + BIT_24)
1227 +#define NV_READ_OP (BIT_26 + BIT_25)
1228 +#define NV_ERASE_OP (BIT_26 + BIT_25 + BIT_24)
1229 +#define NV_MASK_OP (BIT_26 + BIT_25 + BIT_24)
897 1230 #define NV_DELAY_COUNT 10
898 1231
899 1232 /*
900 1233 * Deivce ID list definitions.
901 1234 */
902 1235 struct ql_dev_id {
903 1236 uint8_t al_pa;
904 1237 uint8_t area;
905 1238 uint8_t domain;
906 1239 uint8_t loop_id;
907 1240 };
908 1241
909 1242 struct ql_ex_dev_id {
910 1243 uint8_t al_pa;
911 1244 uint8_t area;
912 1245 uint8_t domain;
913 1246 uint8_t reserved;
914 1247 uint8_t loop_id_l;
915 1248 uint8_t loop_id_h;
916 1249 };
917 1250
918 1251 struct ql_24_dev_id {
919 1252 uint8_t al_pa;
920 1253 uint8_t area;
921 1254 uint8_t domain;
922 1255 uint8_t reserved;
923 1256 uint8_t n_port_hdl_l;
924 1257 uint8_t n_port_hdl_h;
925 1258 uint8_t reserved_1[2];
926 1259 };
927 1260
928 1261 typedef union ql_dev_id_list {
929 1262 struct ql_dev_id d;
930 1263 struct ql_ex_dev_id d_ex;
931 1264 struct ql_24_dev_id d_24;
932 1265 } ql_dev_id_list_t;
933 1266
934 1267 /* Define maximum number of device list entries.. */
935 1268 #define DEVICE_LIST_ENTRIES MAX_24_FIBRE_DEVICES
936 1269
937 1270 /*
938 1271 * Global Data in ql_init.c source file.
939 1272 */
940 1273
941 1274 /*
942 1275 * Global Function Prototypes in ql_init.c source file.
943 1276 */
944 1277 int ql_initialize_adapter(ql_adapter_state_t *);
945 1278 int ql_pci_sbus_config(ql_adapter_state_t *);
946 1279 int ql_nvram_config(ql_adapter_state_t *);
947 1280 uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t);
948 1281 void ql_nv_write(ql_adapter_state_t *, uint16_t);
949 1282 void ql_nv_delay(void);
950 1283 int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t);
951 1284 void ql_release_nvram(ql_adapter_state_t *);
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952 1285 void ql_common_properties(ql_adapter_state_t *);
953 1286 uint32_t ql_get_prop(ql_adapter_state_t *, char *);
954 1287 int ql_load_isp_firmware(ql_adapter_state_t *);
955 1288 int ql_start_firmware(ql_adapter_state_t *);
956 1289 int ql_set_cache_line(ql_adapter_state_t *);
957 1290 int ql_init_rings(ql_adapter_state_t *);
958 1291 int ql_fw_ready(ql_adapter_state_t *, uint8_t);
959 1292 void ql_dev_list(ql_adapter_state_t *, ql_dev_id_list_t *, uint32_t,
960 1293 port_id_t *, uint16_t *);
961 1294 void ql_reset_chip(ql_adapter_state_t *);
962 -void ql_reset_24xx_chip(ql_adapter_state_t *);
963 1295 int ql_abort_isp(ql_adapter_state_t *);
1296 +void ql_requeue_all_cmds(ql_adapter_state_t *);
964 1297 int ql_vport_control(ql_adapter_state_t *, uint8_t);
965 1298 int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t);
966 1299 int ql_vport_enable(ql_adapter_state_t *);
967 1300 ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t);
968 1301 void ql_vport_destroy(ql_adapter_state_t *);
969 1302 #endif /* _KERNEL */
970 1303
971 1304 #ifdef __cplusplus
972 1305 }
973 1306 #endif
974 1307
975 1308 #endif /* _QL_INIT_H */
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