2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright 2009 QLogic Corporation */
23
24 /*
25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
26 * Use is subject to license terms.
27 */
28
29 #ifndef _QL_INIT_H
30 #define _QL_INIT_H
31
32 /*
33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
34 *
35 * ***********************************************************************
36 * * **
37 * * NOTICE **
38 * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION **
39 * * ALL RIGHTS RESERVED **
40 * * **
41 * ***********************************************************************
42 *
43 */
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /*
50 * ISP2200 NVRAM structure definition.
51 * Little endian except where noted.
52 */
53 typedef struct nvram {
54 /*
55 * NVRAM header
56 */
57 uint8_t id[4];
58 uint8_t nvram_version;
59 uint8_t reserved_0;
60
61 /*
62 * NVRAM RISC parameter block
63 */
64 uint8_t parameter_block_version;
65 uint8_t reserved_1;
66
67 /*
68 * LSB BIT 0 = enable_hard_loop_id
500 uint8_t reserved[8];
501
502 /* Offset 64 (40h). */
503 uint8_t e_node_mac_addr[6];
504
505 /* Offset 70 (46h). */
506 uint8_t reserved2[26];
507 } isp8001;
508 } fw;
509
510 /*
511 * Offset 96 (60h)
512 * BIT 0 = initiator op
513 * BIT 1 = target op
514 * BIT 2 = VI op
515 * BIT 3-7 = Reserved
516 */
517 uint8_t oem_specific;
518 uint8_t reserved_4[15];
519
520 /* Offset 112 (70h). */
521 uint8_t reserved_5[16];
522
523 /*
524 * Offset 128 (80h).
525 * PCIe table entries.
526 * Firmware Extended Initialization Control Block.
527 */
528 ql_ext_icb_8100_t ext_blk;
529
530 /* Offset 192. */
531 uint8_t reserved_6[32];
532
533 /* Offset 224. */
534 uint8_t reserved_7[32];
535
536 /*
537 * BIT 0 = Enable spinup delay
538 * BIT 1 = Disable BIOS
539 * BIT 2 = Enable Memory Map BIOS
540 * BIT 3 = Enable Selectable Boot
541 * BIT 4 = Disable RISC code load
692
693 /* Offset 480 (1E0h). */
694 int8_t model_name[4];
695 int8_t model_name1[12]; /* 24xx power_table[8]. */
696
697 /* Offset 496 (1F0h). */
698 uint8_t feature_mask_l[2];
699 uint8_t feature_mask_h[2];
700 uint8_t reserved_25[4];
701
702 /* Offset 504 (1F8h). */
703 uint8_t subsystem_vendor_id[2];
704 uint8_t subsystem_device_id[2];
705
706 uint8_t checksum[4];
707 } nvram_24xx_t;
708
709 /*
710 * Firmware Dump structure definition
711 */
712 #define QL_2200_FW_DUMP_SIZE 0x68000 /* bytes */
713 #define QL_2300_FW_DUMP_SIZE 0xE2000 /* bytes */
714 #define QL_6322_FW_DUMP_SIZE 0xE2000 /* bytes */
715 #define QL_24XX_FW_DUMP_SIZE 0x0330000 /* bytes */
716 #define QL_25XX_FW_DUMP_SIZE 0x0330000 /* bytes */
717
718 #define QL_24XX_VPD_SIZE 0x200 /* bytes */
719 #define QL_24XX_SFP_SIZE 0x200 /* bytes */
720
721 /*
722 * firmware dump struct for 2300 is a superset of firmware dump struct
723 * for 2200. Fields which are 2300 only or are enhanced for 2300 are
724 * marked below.
725 */
726 typedef struct ql_fw_dump {
727 uint16_t pbiu_reg[8];
728 uint16_t risc_host_reg[8]; /* 2300 only. */
729 uint16_t mailbox_reg[16]; /* 2200 only needs 8 */
730 uint16_t resp_dma_reg[32]; /* 2300 only. */
731 uint16_t dma_reg[48];
732 uint16_t risc_hdw_reg[16];
733 uint16_t risc_gp0_reg[16];
734 uint16_t risc_gp1_reg[16];
735 uint16_t risc_gp2_reg[16];
736 uint16_t risc_gp3_reg[16];
768 uint32_t xmt2_dma_reg[32];
769 uint32_t xmt3_dma_reg[32];
770 uint32_t xmt4_dma_reg[32];
771 uint32_t xmt_data_dma_reg[16];
772 uint32_t rcvt0_data_dma_reg[32];
773 uint32_t rcvt1_data_dma_reg[32];
774 uint32_t risc_gp_reg[128];
775 uint32_t shadow_reg[7];
776 uint32_t lmc_reg[112];
777 uint32_t fpm_hdw_reg[192];
778 uint32_t fb_hdw_reg[176];
779 uint32_t code_ram[0x2000];
780 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
781 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
782 uint32_t ext_trace_buf[FWEXTSIZE / 4];
783 uint32_t fce_trace_buf[FWFCESIZE / 4];
784 uint32_t ext_mem[1];
785 } ql_24xx_fw_dump_t;
786
787 typedef struct ql_25xx_fw_dump {
788 uint32_t r2h_status;
789 uint32_t hostrisc_reg[32];
790 uint32_t pcie_reg[4];
791 uint32_t host_reg[32];
792 uint16_t mailbox_reg[32];
793 uint32_t xseq_gp_reg[128];
794 uint32_t xseq_0_reg[48];
795 uint32_t xseq_1_reg[16];
796 uint32_t rseq_gp_reg[128];
797 uint32_t rseq_0_reg[32];
798 uint32_t rseq_1_reg[16];
799 uint32_t rseq_2_reg[16];
800 uint32_t aseq_gp_reg[128];
801 uint32_t aseq_0_reg[32];
802 uint32_t aseq_1_reg[16];
803 uint32_t aseq_2_reg[16];
804 uint32_t cmd_dma_reg[16];
805 uint32_t req0_dma_reg[15];
806 uint32_t resp0_dma_reg[15];
807 uint32_t req1_dma_reg[15];
808 uint32_t xmt0_dma_reg[32];
809 uint32_t xmt1_dma_reg[32];
810 uint32_t xmt2_dma_reg[32];
811 uint32_t xmt3_dma_reg[32];
812 uint32_t xmt4_dma_reg[32];
813 uint32_t xmt_data_dma_reg[16];
814 uint32_t rcvt0_data_dma_reg[32];
815 uint32_t rcvt1_data_dma_reg[32];
816 uint32_t risc_gp_reg[128];
817 uint32_t shadow_reg[11];
818 uint32_t risc_io;
819 uint32_t lmc_reg[128];
820 uint32_t fpm_hdw_reg[192];
821 uint32_t fb_hdw_reg[192];
822 uint32_t code_ram[0x2000];
823 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
824 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
825 uint32_t ext_trace_buf[FWEXTSIZE / 4];
826 uint32_t fce_trace_buf[FWFCESIZE / 4];
827 uint32_t ext_mem[1];
828 } ql_25xx_fw_dump_t;
829
830 typedef struct ql_81xx_fw_dump {
831 uint32_t r2h_status;
832 uint32_t hostrisc_reg[32];
833 uint32_t pcie_reg[4];
834 uint32_t host_reg[32];
835 uint16_t mailbox_reg[32];
836 uint32_t xseq_gp_reg[128];
837 uint32_t xseq_0_reg[48];
838 uint32_t xseq_1_reg[16];
839 uint32_t rseq_gp_reg[128];
840 uint32_t rseq_0_reg[32];
841 uint32_t rseq_1_reg[16];
842 uint32_t rseq_2_reg[16];
843 uint32_t aseq_gp_reg[128];
844 uint32_t aseq_0_reg[32];
845 uint32_t aseq_1_reg[16];
846 uint32_t aseq_2_reg[16];
847 uint32_t cmd_dma_reg[16];
848 uint32_t req0_dma_reg[15];
849 uint32_t resp0_dma_reg[15];
850 uint32_t req1_dma_reg[15];
851 uint32_t xmt0_dma_reg[32];
852 uint32_t xmt1_dma_reg[32];
853 uint32_t xmt2_dma_reg[32];
854 uint32_t xmt3_dma_reg[32];
855 uint32_t xmt4_dma_reg[32];
856 uint32_t xmt_data_dma_reg[16];
857 uint32_t rcvt0_data_dma_reg[32];
858 uint32_t rcvt1_data_dma_reg[32];
859 uint32_t risc_gp_reg[128];
860 uint32_t shadow_reg[11];
861 uint32_t risc_io;
862 uint32_t lmc_reg[128];
863 uint32_t fpm_hdw_reg[224];
864 uint32_t fb_hdw_reg[208];
865 uint32_t code_ram[0x2000];
866 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
867 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
868 uint32_t ext_trace_buf[FWEXTSIZE / 4];
869 uint32_t fce_trace_buf[FWFCESIZE / 4];
870 uint32_t ext_mem[1];
871 } ql_81xx_fw_dump_t;
872
873 #ifdef _KERNEL
874
875 /*
876 * ql_lock_nvram() flags
877 */
878 #define LNF_NVRAM_DATA BIT_0 /* get nvram */
879 #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */
880
881 /*
882 * ISP product identification definitions in mailboxes after reset.
883 */
884 #define PROD_ID_1 0x4953
885 #define PROD_ID_2 0x0000
886 #define PROD_ID_2a 0x5020
887 #define PROD_ID_3 0x2020
888
889 /*
890 * NVRAM Command values.
891 */
892 #define NV_START_BIT BIT_2
893 #define NV_WRITE_OP (BIT_26+BIT_24)
894 #define NV_READ_OP (BIT_26+BIT_25)
895 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
896 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
897 #define NV_DELAY_COUNT 10
898
899 /*
900 * Deivce ID list definitions.
901 */
902 struct ql_dev_id {
903 uint8_t al_pa;
904 uint8_t area;
905 uint8_t domain;
906 uint8_t loop_id;
907 };
908
909 struct ql_ex_dev_id {
910 uint8_t al_pa;
911 uint8_t area;
912 uint8_t domain;
913 uint8_t reserved;
914 uint8_t loop_id_l;
915 uint8_t loop_id_h;
916 };
942 * Global Function Prototypes in ql_init.c source file.
943 */
944 int ql_initialize_adapter(ql_adapter_state_t *);
945 int ql_pci_sbus_config(ql_adapter_state_t *);
946 int ql_nvram_config(ql_adapter_state_t *);
947 uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t);
948 void ql_nv_write(ql_adapter_state_t *, uint16_t);
949 void ql_nv_delay(void);
950 int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t);
951 void ql_release_nvram(ql_adapter_state_t *);
952 void ql_common_properties(ql_adapter_state_t *);
953 uint32_t ql_get_prop(ql_adapter_state_t *, char *);
954 int ql_load_isp_firmware(ql_adapter_state_t *);
955 int ql_start_firmware(ql_adapter_state_t *);
956 int ql_set_cache_line(ql_adapter_state_t *);
957 int ql_init_rings(ql_adapter_state_t *);
958 int ql_fw_ready(ql_adapter_state_t *, uint8_t);
959 void ql_dev_list(ql_adapter_state_t *, ql_dev_id_list_t *, uint32_t,
960 port_id_t *, uint16_t *);
961 void ql_reset_chip(ql_adapter_state_t *);
962 void ql_reset_24xx_chip(ql_adapter_state_t *);
963 int ql_abort_isp(ql_adapter_state_t *);
964 int ql_vport_control(ql_adapter_state_t *, uint8_t);
965 int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t);
966 int ql_vport_enable(ql_adapter_state_t *);
967 ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t);
968 void ql_vport_destroy(ql_adapter_state_t *);
969 #endif /* _KERNEL */
970
971 #ifdef __cplusplus
972 }
973 #endif
974
975 #endif /* _QL_INIT_H */
|
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright 2015 QLogic Corporation */
23
24 /*
25 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
26 */
27
28 #ifndef _QL_INIT_H
29 #define _QL_INIT_H
30
31 /*
32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
33 *
34 * ***********************************************************************
35 * * **
36 * * NOTICE **
37 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
38 * * ALL RIGHTS RESERVED **
39 * * **
40 * ***********************************************************************
41 *
42 */
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 extern uint32_t ql_task_cb_dly;
49
50 /*
51 * ISP2200 NVRAM structure definition.
52 * Little endian except where noted.
53 */
54 typedef struct nvram {
55 /*
56 * NVRAM header
57 */
58 uint8_t id[4];
59 uint8_t nvram_version;
60 uint8_t reserved_0;
61
62 /*
63 * NVRAM RISC parameter block
64 */
65 uint8_t parameter_block_version;
66 uint8_t reserved_1;
67
68 /*
69 * LSB BIT 0 = enable_hard_loop_id
501 uint8_t reserved[8];
502
503 /* Offset 64 (40h). */
504 uint8_t e_node_mac_addr[6];
505
506 /* Offset 70 (46h). */
507 uint8_t reserved2[26];
508 } isp8001;
509 } fw;
510
511 /*
512 * Offset 96 (60h)
513 * BIT 0 = initiator op
514 * BIT 1 = target op
515 * BIT 2 = VI op
516 * BIT 3-7 = Reserved
517 */
518 uint8_t oem_specific;
519 uint8_t reserved_4[15];
520
521 /*
522 * Offset 112 (70h).
523 * BIT 0 = additional receive credits
524 * BIT 1 = additional receive credits
525 * BIT 2-15 = Reserved
526 */
527 uint8_t execute_fw_options[2];
528 uint8_t reserved_5[14];
529
530 /*
531 * Offset 128 (80h).
532 * PCIe table entries.
533 * Firmware Extended Initialization Control Block.
534 */
535 ql_ext_icb_8100_t ext_blk;
536
537 /* Offset 192. */
538 uint8_t reserved_6[32];
539
540 /* Offset 224. */
541 uint8_t reserved_7[32];
542
543 /*
544 * BIT 0 = Enable spinup delay
545 * BIT 1 = Disable BIOS
546 * BIT 2 = Enable Memory Map BIOS
547 * BIT 3 = Enable Selectable Boot
548 * BIT 4 = Disable RISC code load
699
700 /* Offset 480 (1E0h). */
701 int8_t model_name[4];
702 int8_t model_name1[12]; /* 24xx power_table[8]. */
703
704 /* Offset 496 (1F0h). */
705 uint8_t feature_mask_l[2];
706 uint8_t feature_mask_h[2];
707 uint8_t reserved_25[4];
708
709 /* Offset 504 (1F8h). */
710 uint8_t subsystem_vendor_id[2];
711 uint8_t subsystem_device_id[2];
712
713 uint8_t checksum[4];
714 } nvram_24xx_t;
715
716 /*
717 * Firmware Dump structure definition
718 */
719 #define QL_2200_FW_DUMP_SIZE 0x100000 /* 86e15 bytes */
720 #define QL_2300_FW_DUMP_SIZE 0x100000 /* fc6d3 bytes */
721 #define QL_6322_FW_DUMP_SIZE 0x100000 /* fc6d8 bytes */
722 #define QL_24XX_FW_DUMP_SIZE 0x300000 /* 2cef71 bytes */
723 #define QL_25XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */
724 #define QL_81XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */
725 #define QL_27XX_FW_DUMP_SIZE 0x600000 /* 5c3e69 bytes */
726 #define QL_83XX_FW_DUMP_SIZE 0x400000 /* 372792 bytes */
727
728 #define QL_24XX_VPD_SIZE 0x200 /* bytes */
729 #define QL_24XX_SFP_SIZE 0x200 /* bytes */
730
731 /*
732 * firmware dump struct for 2300 is a superset of firmware dump struct
733 * for 2200. Fields which are 2300 only or are enhanced for 2300 are
734 * marked below.
735 */
736 typedef struct ql_fw_dump {
737 uint16_t pbiu_reg[8];
738 uint16_t risc_host_reg[8]; /* 2300 only. */
739 uint16_t mailbox_reg[16]; /* 2200 only needs 8 */
740 uint16_t resp_dma_reg[32]; /* 2300 only. */
741 uint16_t dma_reg[48];
742 uint16_t risc_hdw_reg[16];
743 uint16_t risc_gp0_reg[16];
744 uint16_t risc_gp1_reg[16];
745 uint16_t risc_gp2_reg[16];
746 uint16_t risc_gp3_reg[16];
778 uint32_t xmt2_dma_reg[32];
779 uint32_t xmt3_dma_reg[32];
780 uint32_t xmt4_dma_reg[32];
781 uint32_t xmt_data_dma_reg[16];
782 uint32_t rcvt0_data_dma_reg[32];
783 uint32_t rcvt1_data_dma_reg[32];
784 uint32_t risc_gp_reg[128];
785 uint32_t shadow_reg[7];
786 uint32_t lmc_reg[112];
787 uint32_t fpm_hdw_reg[192];
788 uint32_t fb_hdw_reg[176];
789 uint32_t code_ram[0x2000];
790 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
791 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
792 uint32_t ext_trace_buf[FWEXTSIZE / 4];
793 uint32_t fce_trace_buf[FWFCESIZE / 4];
794 uint32_t ext_mem[1];
795 } ql_24xx_fw_dump_t;
796
797 typedef struct ql_25xx_fw_dump {
798 uint32_t hccr;
799 uint32_t r2h_status;
800 uint32_t aer_ues;
801 uint32_t hostrisc_reg[32];
802 uint32_t pcie_reg[4];
803 uint32_t host_reg[32];
804 uint16_t mailbox_reg[32];
805 uint32_t xseq_gp_reg[128];
806 uint32_t xseq_0_reg[48];
807 uint32_t xseq_1_reg[16];
808 uint32_t rseq_gp_reg[128];
809 uint32_t rseq_0_reg[32];
810 uint32_t rseq_1_reg[16];
811 uint32_t rseq_2_reg[16];
812 uint32_t aseq_gp_reg[128];
813 uint32_t aseq_0_reg[32];
814 uint32_t aseq_1_reg[16];
815 uint32_t aseq_2_reg[16];
816 uint32_t cmd_dma_reg[16];
817 uint32_t req0_dma_reg[15];
818 uint32_t resp0_dma_reg[15];
819 uint32_t req1_dma_reg[15];
820 uint32_t xmt0_dma_reg[32];
821 uint32_t xmt1_dma_reg[32];
822 uint32_t xmt2_dma_reg[32];
823 uint32_t xmt3_dma_reg[32];
824 uint32_t xmt4_dma_reg[32];
825 uint32_t xmt_data_dma_reg[16];
826 uint32_t rcvt0_data_dma_reg[32];
827 uint32_t rcvt1_data_dma_reg[32];
828 uint32_t risc_gp_reg[128];
829 uint32_t shadow_reg[11];
830 uint32_t risc_io;
831 uint32_t lmc_reg[128];
832 uint32_t fpm_hdw_reg[192];
833 uint32_t fb_hdw_reg[192];
834 uint32_t code_ram[0x2000];
835 uint32_t ext_trace_buf[FWEXTSIZE / 4];
836 uint32_t fce_trace_buf[FWFCESIZE / 4];
837 uint32_t req_q_size[2];
838 uint32_t rsp_q_size;
839 uint32_t req_rsp_ext_mem[1];
840 } ql_25xx_fw_dump_t;
841
842 typedef struct ql_81xx_fw_dump {
843 uint32_t hccr;
844 uint32_t r2h_status;
845 uint32_t aer_ues;
846 uint32_t hostrisc_reg[32];
847 uint32_t pcie_reg[4];
848 uint32_t host_reg[32];
849 uint16_t mailbox_reg[32];
850 uint32_t xseq_gp_reg[128];
851 uint32_t xseq_0_reg[48];
852 uint32_t xseq_1_reg[16];
853 uint32_t rseq_gp_reg[128];
854 uint32_t rseq_0_reg[32];
855 uint32_t rseq_1_reg[16];
856 uint32_t rseq_2_reg[16];
857 uint32_t aseq_gp_reg[128];
858 uint32_t aseq_0_reg[32];
859 uint32_t aseq_1_reg[16];
860 uint32_t aseq_2_reg[16];
861 uint32_t cmd_dma_reg[16];
862 uint32_t req0_dma_reg[15];
863 uint32_t resp0_dma_reg[15];
864 uint32_t req1_dma_reg[15];
865 uint32_t xmt0_dma_reg[32];
866 uint32_t xmt1_dma_reg[32];
867 uint32_t xmt2_dma_reg[32];
868 uint32_t xmt3_dma_reg[32];
869 uint32_t xmt4_dma_reg[32];
870 uint32_t xmt_data_dma_reg[16];
871 uint32_t rcvt0_data_dma_reg[32];
872 uint32_t rcvt1_data_dma_reg[32];
873 uint32_t risc_gp_reg[128];
874 uint32_t shadow_reg[11];
875 uint32_t risc_io;
876 uint32_t lmc_reg[128];
877 uint32_t fpm_hdw_reg[224];
878 uint32_t fb_hdw_reg[208];
879 uint32_t code_ram[0x2000];
880 uint32_t ext_trace_buf[FWEXTSIZE / 4];
881 uint32_t fce_trace_buf[FWFCESIZE / 4];
882 uint32_t req_q_size[2];
883 uint32_t rsp_q_size;
884 uint32_t req_rsp_ext_mem[1];
885 } ql_81xx_fw_dump_t;
886
887 typedef struct ql_83xx_fw_dump {
888 uint32_t hccr;
889 uint32_t r2h_status;
890 uint32_t aer_ues;
891 uint32_t hostrisc_reg[48];
892 uint32_t pcie_reg[4];
893 uint32_t host_reg[32];
894 uint16_t mailbox_reg[32];
895 uint32_t xseq_gp_reg[256];
896 uint32_t xseq_0_reg[48];
897 uint32_t xseq_1_reg[16];
898 uint32_t xseq_2_reg[16];
899 uint32_t rseq_gp_reg[256];
900 uint32_t rseq_0_reg[32];
901 uint32_t rseq_1_reg[16];
902 uint32_t rseq_2_reg[16];
903 uint32_t rseq_3_reg[16];
904 uint32_t aseq_gp_reg[256];
905 uint32_t aseq_0_reg[32];
906 uint32_t aseq_1_reg[16];
907 uint32_t aseq_2_reg[16];
908 uint32_t aseq_3_reg[16];
909 uint32_t cmd_dma_reg[64];
910 uint32_t req0_dma_reg[15];
911 uint32_t resp0_dma_reg[15];
912 uint32_t req1_dma_reg[15];
913 uint32_t xmt0_dma_reg[32];
914 uint32_t xmt1_dma_reg[32];
915 uint32_t xmt2_dma_reg[32];
916 uint32_t xmt3_dma_reg[32];
917 uint32_t xmt4_dma_reg[32];
918 uint32_t xmt_data_dma_reg[16];
919 uint32_t rcvt0_data_dma_reg[32];
920 uint32_t rcvt1_data_dma_reg[32];
921 uint32_t risc_gp_reg[128];
922 uint32_t shadow_reg[11];
923 uint32_t risc_io;
924 uint32_t lmc_reg[128];
925 uint32_t fpm_hdw_reg[256];
926 uint32_t rq0_array_reg[256];
927 uint32_t rq1_array_reg[256];
928 uint32_t rp0_array_reg[256];
929 uint32_t rp1_array_reg[256];
930 uint32_t ato_array_reg[128];
931 uint32_t queue_control_reg[16];
932 uint32_t fb_hdw_reg[432];
933 uint32_t code_ram[0x2400];
934 uint32_t ext_trace_buf[FWEXTSIZE / 4];
935 uint32_t fce_trace_buf[FWFCESIZE / 4];
936 uint32_t req_q_size[2];
937 uint32_t rsp_q_size;
938 uint32_t req_rsp_ext_mem[1];
939 } ql_83xx_fw_dump_t;
940
941 #ifdef _KERNEL
942
943 /*
944 * firmware dump Entry Types
945 */
946 #define DT_NOP 0
947 #define DT_THDR 99
948 #define DT_TEND 255
949 #define DT_RIOB1 256
950 #define DT_WIOB1 257
951 #define DT_RIOB2 258
952 #define DT_WIOB2 259
953 #define DT_RPCI 260
954 #define DT_WPCI 261
955 #define DT_RRAM 262
956 #define DT_GQUE 263
957 #define DT_GFCE 264
958 #define DT_PRISC 265
959 #define DT_RRISC 266
960 #define DT_DINT 267
961 #define DT_GHBD 268
962 #define DT_SCRA 269
963 #define DT_RRREG 270
964 #define DT_WRREG 271
965 #define DT_RRRAM 272
966 #define DT_RPCIC 273
967 #define DT_GQUES 274
968 #define DT_WDMP 275
969
970 /*
971 * firmware dump Template Header (Entry Type 99)
972 */
973 typedef struct ql_dt_hdr {
974 uint32_t type;
975 uint32_t first_entry_offset;
976 uint32_t size_of_template;
977 uint32_t rsv;
978 uint32_t num_of_entries;
979 uint32_t version;
980 uint32_t driver_timestamp;
981 uint32_t checksum;
982 uint32_t rsv_1;
983 uint32_t driver_info[3];
984 uint32_t saved_state_area[16];
985 uint32_t rsv_2[8];
986 uint32_t ver_attr[5];
987 } ql_dt_hdr_t;
988
989 /*
990 * firmware dump Common Entry Header
991 */
992 typedef struct ql_dt_entry_hdr {
993 uint32_t type;
994 uint32_t size;
995 uint32_t rsv;
996 #ifdef _BIG_ENDIAN
997 uint8_t driver_flags;
998 uint8_t rsv_2;
999 uint8_t rsv_1;
1000 uint8_t capture_flags;
1001 #else
1002 uint8_t capture_flags;
1003 uint8_t rsv_1;
1004 uint8_t rsv_2;
1005 uint8_t driver_flags;
1006 #endif
1007 } ql_dt_entry_hdr_t;
1008
1009 /*
1010 * Capture Flags
1011 */
1012 #define PF_ONLY_FLAG BIT_0 /* Physical Function Only */
1013 #define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */
1014
1015 /*
1016 * Driver Flags
1017 */
1018 #define SKIPPED_FLAG BIT_7 /* driver skipped this entry */
1019
1020 /*
1021 * firmware dump Entry Including Header
1022 */
1023 typedef struct ql_dt_entry {
1024 ql_dt_entry_hdr_t h;
1025 uint32_t data[1];
1026 } ql_dt_entry_t;
1027
1028 /*
1029 * firmware dump Template image
1030 */
1031 typedef struct ql_dmp_template {
1032 uint32_t rsv[2];
1033 uint32_t len;
1034 uint32_t major_ver;
1035 uint32_t minor_ver;
1036 uint32_t subminor_ver;
1037 uint32_t attribute;
1038 ql_dt_hdr_t hdr;
1039 ql_dt_entry_t entries[1];
1040 } ql_dmp_template_t;
1041
1042 typedef struct ql_dt_riob1 {
1043 ql_dt_entry_hdr_t h;
1044 uint32_t addr;
1045 #ifdef _BIG_ENDIAN
1046 uint8_t pci_offset;
1047 uint8_t reg_count_h;
1048 uint8_t reg_count_l;
1049 uint8_t reg_size;
1050 #else
1051 uint8_t reg_size;
1052 uint8_t reg_count_l;
1053 uint8_t reg_count_h;
1054 uint8_t pci_offset;
1055 #endif
1056 } ql_dt_riob1_t;
1057
1058 typedef struct ql_dt_wiob1 {
1059 ql_dt_entry_hdr_t h;
1060 uint32_t addr;
1061 uint32_t data;
1062 #ifdef _BIG_ENDIAN
1063 uint8_t rsv[3];
1064 uint8_t pci_offset;
1065 #else
1066 uint8_t pci_offset;
1067 uint8_t rsv[3];
1068 #endif
1069 } ql_dt_wiob1_t;
1070
1071 typedef struct ql_dt_riob2 {
1072 ql_dt_entry_hdr_t h;
1073 uint32_t addr;
1074 #ifdef _BIG_ENDIAN
1075 uint8_t pci_offset;
1076 uint8_t reg_count_h;
1077 uint8_t reg_count_l;
1078 uint8_t reg_size;
1079 uint8_t rsv[3];
1080 uint8_t bank_sel_offset;
1081 #else
1082 uint8_t reg_size;
1083 uint8_t reg_count_l;
1084 uint8_t reg_count_h;
1085 uint8_t pci_offset;
1086 uint8_t bank_sel_offset;
1087 uint8_t rsv[3];
1088 #endif
1089 uint32_t reg_bank;
1090 } ql_dt_riob2_t;
1091
1092 typedef struct ql_dt_wiob2 {
1093 ql_dt_entry_hdr_t h;
1094 uint32_t addr;
1095 #ifdef _BIG_ENDIAN
1096 uint8_t rsv[2];
1097 uint8_t data_h;
1098 uint8_t data_l;
1099 uint8_t bank_sel_offset;
1100 uint8_t pci_offset;
1101 uint8_t rsv1[2];
1102 #else
1103 uint8_t data_l;
1104 uint8_t data_h;
1105 uint8_t rsv[2];
1106 uint8_t rsv1[2];
1107 uint8_t pci_offset;
1108 uint8_t bank_sel_offset;
1109 #endif
1110 uint32_t reg_bank;
1111 } ql_dt_wiob2_t;
1112
1113 typedef struct ql_dt_rpci {
1114 ql_dt_entry_hdr_t h;
1115 uint32_t addr;
1116 } ql_dt_rpci_t;
1117
1118 typedef struct ql_dt_wpci {
1119 ql_dt_entry_hdr_t h;
1120 uint32_t addr;
1121 uint32_t data;
1122 } ql_dt_wpci_t, ql_dt_wrreg_t;
1123
1124 typedef struct ql_dt_rram {
1125 ql_dt_entry_hdr_t h;
1126 #ifdef _BIG_ENDIAN
1127 uint8_t rsv[3];
1128 uint8_t ram_area;
1129 #else
1130 uint8_t ram_area;
1131 uint8_t rsv[3];
1132 #endif
1133 uint32_t start_addr;
1134 uint32_t end_addr;
1135 } ql_dt_rram_t;
1136
1137 typedef struct ql_dt_gque {
1138 ql_dt_entry_hdr_t h;
1139 uint32_t num_queues;
1140 #ifdef _BIG_ENDIAN
1141 uint8_t rsv[3];
1142 uint8_t queue_type;
1143 #else
1144 uint8_t queue_type;
1145 uint8_t rsv[3];
1146 #endif
1147 } ql_dt_gque_t, ql_dt_gques_t;
1148
1149 typedef struct ql_dt_gfce {
1150 ql_dt_entry_hdr_t h;
1151 uint32_t fce_trace_size;
1152 uint32_t write_pointer[2];
1153 uint32_t base_pointer[2];
1154 uint32_t fce_enable_mb0;
1155 uint32_t fce_enable_mb2;
1156 uint32_t fce_enable_mb3;
1157 uint32_t fce_enable_mb4;
1158 uint32_t fce_enable_mb5;
1159 uint32_t fce_enable_mb6;
1160 } ql_dt_gfce_t;
1161
1162 typedef struct ql_dt_prisc {
1163 ql_dt_entry_hdr_t h;
1164 } ql_dt_prisc_t, ql_dt_rrisc_t;
1165
1166 typedef struct ql_dt_dint {
1167 ql_dt_entry_hdr_t h;
1168 #ifdef _BIG_ENDIAN
1169 uint8_t rsv[3];
1170 uint8_t pci_offset;
1171 #else
1172 uint8_t pci_offset;
1173 uint8_t rsv[3];
1174 #endif
1175 uint32_t data;
1176 } ql_dt_dint_t;
1177
1178 typedef struct ql_dt_ghbd {
1179 ql_dt_entry_hdr_t h;
1180 #ifdef _BIG_ENDIAN
1181 uint8_t rsv[3];
1182 uint8_t host_buf_type;
1183 #else
1184 uint8_t host_buf_type;
1185 uint8_t rsv[3];
1186 #endif
1187 uint32_t buf_size;
1188 uint32_t start_addr;
1189 } ql_dt_ghbd_t;
1190
1191 typedef struct ql_dt_scra {
1192 ql_dt_entry_hdr_t h;
1193 uint32_t scratch_size;
1194 } ql_dt_scra_t;
1195
1196 typedef struct ql_dt_rrreg {
1197 ql_dt_entry_hdr_t h;
1198 uint32_t addr;
1199 uint32_t count;
1200 } ql_dt_rrreg_t, ql_dt_rrram_t, ql_dt_rpcic_t;
1201
1202 typedef struct ql_dt_wdmp {
1203 ql_dt_entry_hdr_t h;
1204 uint32_t length;
1205 uint32_t data[1];
1206 } ql_dt_wdmp_t;
1207
1208 /*
1209 * ql_lock_nvram() flags
1210 */
1211 #define LNF_NVRAM_DATA BIT_0 /* get nvram */
1212 #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */
1213
1214 /*
1215 * ISP product identification definitions in mailboxes after reset.
1216 */
1217 #define PROD_ID_1 0x4953
1218 #define PROD_ID_2 0x0000
1219 #define PROD_ID_2a 0x5020
1220 #define PROD_ID_3 0x2020
1221
1222 /*
1223 * NVRAM Command values.
1224 */
1225 #define NV_START_BIT BIT_2
1226 #define NV_WRITE_OP (BIT_26 + BIT_24)
1227 #define NV_READ_OP (BIT_26 + BIT_25)
1228 #define NV_ERASE_OP (BIT_26 + BIT_25 + BIT_24)
1229 #define NV_MASK_OP (BIT_26 + BIT_25 + BIT_24)
1230 #define NV_DELAY_COUNT 10
1231
1232 /*
1233 * Deivce ID list definitions.
1234 */
1235 struct ql_dev_id {
1236 uint8_t al_pa;
1237 uint8_t area;
1238 uint8_t domain;
1239 uint8_t loop_id;
1240 };
1241
1242 struct ql_ex_dev_id {
1243 uint8_t al_pa;
1244 uint8_t area;
1245 uint8_t domain;
1246 uint8_t reserved;
1247 uint8_t loop_id_l;
1248 uint8_t loop_id_h;
1249 };
1275 * Global Function Prototypes in ql_init.c source file.
1276 */
1277 int ql_initialize_adapter(ql_adapter_state_t *);
1278 int ql_pci_sbus_config(ql_adapter_state_t *);
1279 int ql_nvram_config(ql_adapter_state_t *);
1280 uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t);
1281 void ql_nv_write(ql_adapter_state_t *, uint16_t);
1282 void ql_nv_delay(void);
1283 int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t);
1284 void ql_release_nvram(ql_adapter_state_t *);
1285 void ql_common_properties(ql_adapter_state_t *);
1286 uint32_t ql_get_prop(ql_adapter_state_t *, char *);
1287 int ql_load_isp_firmware(ql_adapter_state_t *);
1288 int ql_start_firmware(ql_adapter_state_t *);
1289 int ql_set_cache_line(ql_adapter_state_t *);
1290 int ql_init_rings(ql_adapter_state_t *);
1291 int ql_fw_ready(ql_adapter_state_t *, uint8_t);
1292 void ql_dev_list(ql_adapter_state_t *, ql_dev_id_list_t *, uint32_t,
1293 port_id_t *, uint16_t *);
1294 void ql_reset_chip(ql_adapter_state_t *);
1295 int ql_abort_isp(ql_adapter_state_t *);
1296 void ql_requeue_all_cmds(ql_adapter_state_t *);
1297 int ql_vport_control(ql_adapter_state_t *, uint8_t);
1298 int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t);
1299 int ql_vport_enable(ql_adapter_state_t *);
1300 ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t);
1301 void ql_vport_destroy(ql_adapter_state_t *);
1302 #endif /* _KERNEL */
1303
1304 #ifdef __cplusplus
1305 }
1306 #endif
1307
1308 #endif /* _QL_INIT_H */
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