1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright 2015 QLogic Corporation */
23
24 /*
25 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
26 */
27
28 #ifndef _QL_INIT_H
29 #define _QL_INIT_H
30
31 /*
32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
33 *
34 * ***********************************************************************
35 * * **
36 * * NOTICE **
37 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
38 * * ALL RIGHTS RESERVED **
39 * * **
40 * ***********************************************************************
41 *
42 */
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 extern uint32_t ql_task_cb_dly;
49
50 /*
51 * ISP2200 NVRAM structure definition.
52 * Little endian except where noted.
53 */
54 typedef struct nvram {
55 /*
56 * NVRAM header
57 */
58 uint8_t id[4];
59 uint8_t nvram_version;
60 uint8_t reserved_0;
61
62 /*
63 * NVRAM RISC parameter block
64 */
65 uint8_t parameter_block_version;
66 uint8_t reserved_1;
67
68 /*
69 * LSB BIT 0 = enable_hard_loop_id
70 * LSB BIT 1 = enable_fairness
71 * LSB BIT 2 = enable_full_duplex
72 * LSB BIT 3 = enable_fast_posting
73 * LSB BIT 4 = enable_target_mode
74 * LSB BIT 5 = disable_initiator_mode
75 * LSB BIT 6 = enable_adisc
76 * LSB BIT 7 = enable_target_inquiry_data
77 *
78 * MSB BIT 0 = enable_port_update_ae
79 * MSB BIT 1 = disable_initial_lip
80 * MSB BIT 2 = enable_decending_soft_assign
81 * MSB BIT 3 = previous_assigned_addressing
82 * MSB BIT 4 = enable_stop_q_on_full
83 * MSB BIT 5 = enable_full_login_on_lip
84 * MSB BIT 6 = enable_node_name
85 * MSB BIT 7 = extended_control_block
86 */
87 uint8_t firmware_options[2];
88
89 uint8_t max_frame_length[2];
90 uint8_t max_iocb_allocation[2];
91 uint8_t execution_throttle[2];
92 uint8_t login_retry_count;
93 uint8_t retry_delay; /* unused */
94 uint8_t port_name[8]; /* Big endian. */
95 uint8_t hard_address[2];
96 uint8_t inquiry;
97 uint8_t login_timeout;
98 uint8_t node_name[8]; /* Big endian. */
99
100 /*
101 * LSB BIT 0 = Timer operation mode bit 0
102 * LSB BIT 1 = Timer operation mode bit 1
103 * LSB BIT 2 = Timer operation mode bit 2
104 * LSB BIT 3 = Timer operation mode bit 3
105 * LSB BIT 4 = P2P Connection option bit 0
106 * LSB BIT 5 = P2P Connection option bit 1
107 * LSB BIT 6 = P2P Connection option bit 2
108 * LSB BIT 7 = Enable Non part on LIHA failure
109 *
110 * MSB BIT 0 = Enable class 2
111 * MSB BIT 1 = Enable ACK0
112 * MSB BIT 2 =
113 * MSB BIT 3 =
114 * MSB BIT 4 = FC Tape Enable
115 * MSB BIT 5 = Enable FC Confirm
116 * MSB BIT 6 = Enable command queuing in target mode
117 * MSB BIT 7 = No Logo On Link Down
118 */
119 uint8_t add_fw_opt[2];
120 uint8_t response_accumulation_timer;
121 uint8_t interrupt_delay_timer;
122
123 /*
124 * LSB BIT 0 = Enable Read xfr_rdy
125 * LSB BIT 1 = Soft ID only
126 * LSB BIT 2 =
127 * LSB BIT 3 =
128 * LSB BIT 4 = FCP RSP Payload [0]
129 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
130 * LSB BIT 6 =
131 * LSB BIT 7 =
132 *
133 * MSB BIT 0 = Sbus enable - 2300
134 * MSB BIT 1 =
135 * MSB BIT 2 =
136 * MSB BIT 3 =
137 * MSB BIT 4 =
138 * MSB BIT 5 = Enable 50 ohm termination
139 * MSB BIT 6 = Data Rate (2300 only)
140 * MSB BIT 7 = Data Rate (2300 only)
141 */
142 uint8_t special_options[2];
143
144 /* Reserved for expanded RISC parameter block */
145 uint8_t reserved_4[26];
146
147 /*
148 * NVRAM host parameter block
149 *
150 * LSB BIT 0 = unused
151 * LSB BIT 1 = disable_bios
152 * LSB BIT 2 = disable_luns
153 * LSB BIT 3 = enable_selectable_boot
154 * LSB BIT 4 = disable_risc_code_load
155 * LSB BIT 5 = set_cache_line_size_1
156 * LSB BIT 6 = pci_parity_disable
157 * LSB BIT 7 = enable_extended_logging
158 *
159 * MSB BIT 0 = enable_64bit_addressing
160 * MSB BIT 1 = enable_lip_reset
161 * MSB BIT 2 = enable_lip_full_login
162 * MSB BIT 3 = enable_target_reset
163 * MSB BIT 4 = enable_database_storage
164 * MSB BIT 5 = unused
165 * MSB BIT 6 = unused
166 * MSB BIT 7 = unused
167 */
168 uint8_t host_p[2];
169
170 uint8_t boot_node_name[8];
171 uint8_t boot_lun_number;
172 uint8_t reset_delay;
173 uint8_t port_down_retry_count;
174 uint8_t reserved_5;
175
176 uint8_t maximum_luns_per_target[2];
177
178 uint8_t reserved_6[14];
179
180 /* Offset 100 */
181 uint8_t reverved_7[12];
182
183 /* offset 112 */
184 uint8_t adapInfo[16]; /* Sun OEM HBA's 23xx only */
185
186 uint8_t reserved_8[22];
187
188 /* Offset 150 */
189 uint8_t reserved_9[50];
190
191 /* Offset 200 */
192 uint8_t reserved_10[32];
193
194 /*
195 * NVRAM Adapter Features offset 232-239
196 *
197 * LSB BIT 0 = External GBIC
198 * LSB BIT 1 = Risc RAM parity
199 * LSB BIT 2 = Buffer Plus Module
200 * LSB BIT 3 = Multi Chip Adapter
201 * LSB BIT 4 =
202 * LSB BIT 5 =
203 * LSB BIT 6 =
204 * LSB BIT 7 =
205 *
206 * MSB BIT 0 =
207 * MSB BIT 1 =
208 * MSB BIT 2 =
209 * MSB BIT 3 =
210 * MSB BIT 4 =
211 * MSB BIT 5 =
212 * MSB BIT 6 =
213 * MSB BIT 7 =
214 */
215 uint8_t adapter_features[2];
216 uint8_t reserved_11[6];
217
218 /*
219 * Resrved for use with ISP2300 - offset 240
220 */
221 uint8_t reserved_12[4];
222
223 /* Subsystem ID must be at offset 244 */
224 uint8_t subsystem_vendor_id[2];
225
226 uint8_t reserved_13[2];
227
228 /* Subsystem device ID must be at offset 248 */
229 uint8_t subsystem_device_id[2];
230
231 /* Subsystem vendor ID for ISP2200 */
232 uint8_t subsystem_vendor_id_2200[2];
233
234 /* Subsystem device ID for ISP2200 */
235 uint8_t subsystem_device_id_2200[2];
236
237 uint8_t reserved_14;
238 uint8_t checksum;
239 } nvram_t;
240
241 /*
242 * NVRAM structure definition.
243 */
244 typedef struct nvram_24xx {
245 /* NVRAM header. */
246 uint8_t id[4];
247 uint8_t nvram_version[2];
248 uint8_t reserved_0[2];
249
250 /* Firmware Initialization Control Block. */
251 uint8_t version[2];
252 uint8_t reserved_1[2];
253 uint8_t max_frame_length[2];
254 uint8_t execution_throttle[2];
255 uint8_t exchange_count[2];
256 uint8_t hard_address[2];
257 uint8_t port_name[8];
258 uint8_t node_name[8];
259 uint8_t login_retry_count[2];
260 uint8_t link_down_on_nos[2];
261 uint8_t interrupt_delay_timer[2];
262 uint8_t login_timeout[2];
263
264 /*
265 * BIT 0 = Hard Assigned Loop ID
266 * BIT 1 = Enable Fairness
267 * BIT 2 = Enable Full-Duplex
268 * BIT 3 = Reserved
269 * BIT 4 = Target Mode Enable
270 * BIT 5 = Initiator Mode Disable
271 * BIT 6 = Reserved
272 * BIT 7 = Reserved
273 *
274 * BIT 8 = Reserved
275 * BIT 9 = Disable Initial LIP
276 * BIT 10 = Descending Loop ID Search
277 * BIT 11 = Previous Assigned Loop ID
278 * BIT 12 = Reserved
279 * BIT 13 = Full Login after LIP
280 * BIT 14 = Node Name Option
281 * BIT 15 = Reserved
282 *
283 * BIT 16-31 = Reserved
284 */
285 uint8_t firmware_options_1[4];
286
287 /*
288 * BIT 0 = Operation Mode bit 0
289 * BIT 1 = Operation Mode bit 1
290 * BIT 2 = Operation Mode bit 2
291 * BIT 3 = Operation Mode bit 3
292 * BIT 4 = Connection Options bit 0
293 * BIT 5 = Connection Options bit 1
294 * BIT 6 = Connection Options bit 2
295 * BIT 7 = Enable Non part on LIHA failure
296 *
297 * BIT 8 = Enable Class 2
298 * BIT 9 = Enable ACK0
299 * BIT 10 = Enable Virtual Fabric
300 * BIT 11 = Enable FC-SP Security
301 * BIT 12 = FC Tape Enable
302 * BIT 13 = Reserved
303 * BIT 14 = Target PRLI Control
304 * BIT 15 = Reserved
305 *
306 * BIT 16 = Enable Emulated MSIX
307 * BIT 17 = Reserved
308 * BIT 18 = Enable Alternate Device Number
309 * BIT 19 = Enable Alternate Bus Number
310 * BIT 20 = Enable Translated Address
311 * BIT 21 = Enable VM Security
312 * BIT 22 = Enable Interrupt Handshake
313 * BIT 23 = Enable Multiple Queue
314 *
315 * BIT 24 = IOCB Security
316 * BIT 25 = qos
317 * BIT 26-31 = Reserved
318 */
319 uint8_t firmware_options_2[4];
320
321 /*
322 * BIT 0 = Reserved
323 * BIT 1 = Soft ID only
324 * BIT 2 = Reserved
325 * BIT 3 = disable split completion timeout
326 * BIT 4 = FCP RSP Payload bit 0
327 * BIT 5 = FCP RSP Payload bit 1
328 * BIT 6 = Enable Rec Out-of-Order data frame handling
329 * BIT 7 = Disable Automatic PLOGI on Local Loop
330 *
331 * BIT 8 = Reserved
332 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
333 * offset handling
334 * BIT 10 = Reserved
335 * BIT 11 = Reserved
336 * BIT 12 = Reserved
337 * BIT 13 = Data Rate bit 0
338 * BIT 14 = Data Rate bit 1
339 * BIT 15 = Data Rate bit 2
340 *
341 * BIT 16 = 75-ohm Termination Select
342 * BIT 17 = Enable Multiple FCFs
343 * BIT 18 = MAC Addressing Mode
344 * BIT 19 = MAC Addressing Mode
345 * BIT 20 = MAC Addressing Mode
346 * BIT 21 = Ethernet Data Rate
347 * BIT 22 = Ethernet Data Rate
348 * BIT 23 = Ethernet Data Rate
349 *
350 * BIT 24 = Ethernet Data Rate
351 * BIT 25 = Ethernet Data Rate
352 * BIT 26 = Enable Ethernet Header ATIO Queue
353 * BIT 27 = Enable Ethernet Header Response Queue
354 * BIT 28 = SPMA Selection
355 * BIT 29 = SPMA Selection
356 * BIT 30 = Reserved
357 * BIT 31 = Reserved
358 */
359 uint8_t firmware_options_3[4];
360
361 union {
362 struct {
363 /*
364 * Offset 56 (38h)
365 * Serial Link Control
366 * BIT 0 = control enable
367 * BIT 1-15 = Reserved
368 */
369 uint8_t swing_opt[2];
370 /*
371 * Offset 58 (3Ah)
372 * Serial Link Control 1G
373 * BIT 0-7 = Reserved
374 *
375 * BIT 8-10 = output swing
376 * BIT 11-13 = output emphasis
377 * BIT 14-15 = Reserved
378 */
379 uint8_t swing_1g[2];
380 /*
381 * Offset 60 (3Ch)
382 * Serial Link Control 2G
383 * BIT 0-7 = Reserved
384 *
385 * BIT 8-10 = output swing
386 * BIT 11-13 = output emphasis
387 * BIT 14-15 = Reserved
388 */
389 uint8_t swing_2g[2];
390 /*
391 * Offset 62 (3Eh)
392 * Serial Link Control 4G
393 * BIT 0-7 = Reserved
394 *
395 * BIT 8-10 = output swing
396 * BIT 11-13 = output emphasis
397 * BIT 14-15 = Reserved
398 */
399 uint8_t swing_4g[2];
400
401 /* Offset 64 (40h). */
402 uint8_t reserved[32];
403 } isp2400;
404 struct {
405 /*
406 * Offset 56 (38h)
407 * Serial Link Control
408 * BIT 0 = Reserved
409 * BIT 1 = 25xx TX control enable
410 * BIT 2 = 25xx RX control enable (lmtg)
411 * BIT 3 = 25xx RX control enable (linear)
412 * BIT 4 = embedded HBA
413 * BIT 5 = unused
414 * BIT 6 = 25xx E7 Addr27 Preset
415 * BIT 7 = 25xx E6 Addr0 Ch0 enable
416 *
417 * BIT 8-15 = 25xx E6 Addr0 Ch0
418 *
419 * BIT 16-31 = Reserved
420 */
421 uint8_t swing_opt[4];
422
423 /*
424 * Offset 60 (3Ch)
425 * Serial Link TX Parameters
426 * BIT 0 = TX Amplitude
427 * BIT 1 = TX Amplitude
428 * BIT 2 = TX Amplitude
429 * BIT 3 = TX Amplitude
430 * BIT 4 = TX Amplitude
431 * BIT 5 = TX iPost
432 * BIT 6 = TX iPost
433 * BIT 7 = TX iPost
434 *
435 * BIT 8 = TX iPost
436 * BIT 9 = TX iPre
437 * BIT 10 = TX iPre
438 * BIT 11 = TX iPre
439 * BIT 12 = TX iPre
440 * BIT 13 = TX iMain
441 * BIT 14 = TX iMain
442 * BIT 15 = TX iMain
443 *
444 * BIT 16 = TX iMain
445 * BIT 17 = TX iMain
446 * BIT 18-23 = Reserved
447 *
448 * BIT 24-31 = Reserved
449 */
450 uint8_t tx_8g[4];
451 /* Offset 64 (40h) */
452 uint8_t tx_4g[4];
453 /* Offset 68 (44h) */
454 uint8_t tx_2g[4];
455
456 /*
457 * Offset 72 (48h)
458 * Serial Link RX Parameters
459 * BIT 0 = RX Z1Cnt
460 * BIT 1 = RX Z1Cnt
461 * BIT 2 = RX Z1Cnt
462 * BIT 3 = RX Z1Cnt
463 * BIT 4 = RX G1Cnt
464 * BIT 5 = RX ZCnt
465 * BIT 6 = RX ZCnt
466 * BIT 7 = RX ZCnt
467 *
468 * BIT 8 = RX ZCnt
469 * BIT 9 = RX ZCnt
470 * BIT 10 = RX TLTH
471 * BIT 11 = RX TLTH
472 * BIT 12 = RX TLTH
473 * BIT 13 = RX TLTH
474 * BIT 14 = RX TLTH
475 * BIT 15 = RX TLTH
476 *
477 * BIT 16 = RX DFELTH
478 * BIT 17 = RX DFELTH
479 * BIT 18 = RX DFELTH
480 * BIT 19 = RX DFELTH
481 * BIT 20 = RX DFELTH
482 * BIT 21 = RX DFELTH
483 * BIT 22-23 = Reserved
484 *
485 * BIT 24-31 = Reserved
486 */
487 uint8_t rx_limit_8g[4];
488 /* Offset 76 (4Ch) */
489 uint8_t rx_limit_4g[4];
490 /* Offset 80 (50h) */
491 uint8_t rx_limit_2g[4];
492 /* Offset 84 (54h) */
493 uint8_t rx_linear_8g[4];
494 /* Offset 88 (58h) */
495 uint8_t rx_linear_4g[4];
496 /* Offset 92 (5Ch) */
497 uint8_t rx_linear_2g[4];
498 } isp2500;
499 struct {
500 /* Offset 56 (38h) */
501 uint8_t reserved[8];
502
503 /* Offset 64 (40h). */
504 uint8_t e_node_mac_addr[6];
505
506 /* Offset 70 (46h). */
507 uint8_t reserved2[26];
508 } isp8001;
509 } fw;
510
511 /*
512 * Offset 96 (60h)
513 * BIT 0 = initiator op
514 * BIT 1 = target op
515 * BIT 2 = VI op
516 * BIT 3-7 = Reserved
517 */
518 uint8_t oem_specific;
519 uint8_t reserved_4[15];
520
521 /*
522 * Offset 112 (70h).
523 * BIT 0 = additional receive credits
524 * BIT 1 = additional receive credits
525 * BIT 2-15 = Reserved
526 */
527 uint8_t execute_fw_options[2];
528 uint8_t reserved_5[14];
529
530 /*
531 * Offset 128 (80h).
532 * PCIe table entries.
533 * Firmware Extended Initialization Control Block.
534 */
535 ql_ext_icb_8100_t ext_blk;
536
537 /* Offset 192. */
538 uint8_t reserved_6[32];
539
540 /* Offset 224. */
541 uint8_t reserved_7[32];
542
543 /*
544 * BIT 0 = Enable spinup delay
545 * BIT 1 = Disable BIOS
546 * BIT 2 = Enable Memory Map BIOS
547 * BIT 3 = Enable Selectable Boot
548 * BIT 4 = Disable RISC code load
549 * BIT 5 = Disable serdes
550 * BIT 6 = Enable opt boot mode
551 * BIT 7 = Enable int mode BIOS
552 *
553 * BIT 8 = EV control enable
554 * BIT 9 = Enable lip reset
555 * BIT 10 = Enable lip full login
556 * BIT 11 = Enable target reset
557 * BIT 12 = Stop firmware
558 * BIT 13 = Default Node Name Option
559 * BIT 14 = Default WWPN valid
560 * BIT 15 = Enable alternate WWN
561 *
562 * CLP BIOS flags
563 *
564 * BIT 16 = clp lun string
565 * BIT 17 = clp target string
566 * BIT 18 = clp bios enable string
567 * BIT 19 = clp serdes_string
568 * BIT 20 = clp wwpn string
569 * BIT 21 = clp wwnn string
570 * BIT 22 = win reserverd 0
571 * BIT 23 = win reserverd 1
572 *
573 * BIT 24 = keep wwpn
574 * BIT 25 = temp wwpn
575 * BIT 26 = win reserverd 2
576 * BIT 27 = win reserverd 3
577 * BIT 28 = clear WBT in flash (win driver)
578 * BIT 29 = write WBT in flash (win driver)
579 * BIT 30 = load fw from flash (win driver)
580 * BIT 31 = enable alternate WWN (win driver)
581 */
582 uint8_t host_p[4];
583
584 uint8_t alternate_port_name[8];
585 uint8_t alternate_node_name[8];
586
587 uint8_t boot_port_name[8];
588 uint8_t boot_lun_number[2];
589 uint8_t reserved_8[2];
590
591 uint8_t alt1_boot_port_name[8];
592 uint8_t alt1_boot_lun_number[2];
593 uint8_t reserved_9[2];
594
595 uint8_t alt2_boot_port_name[8];
596 uint8_t alt2_boot_lun_number[2];
597 uint8_t reserved_10[2];
598
599 uint8_t alt3_boot_port_name[8];
600 uint8_t alt3_boot_lun_number[2];
601 uint8_t reserved_11[2];
602
603 /*
604 * BIT 0 = Selective Login
605 * BIT 1 = Alt-Boot Enable
606 * BIT 2 = Reserved
607 * BIT 3 = Enable Boot Order List
608 * BIT 4 = Reserved
609 * BIT 5 = Enable Selective LUN
610 * BIT 6 = Reserved
611 * BIT 7-31 =
612 */
613 uint8_t efi_parameters[4];
614
615 uint8_t reset_delay;
616 uint8_t reserved_12;
617 uint8_t reserved_13[2];
618
619 uint8_t boot_id_number[2];
620 uint8_t reserved_14[2];
621
622 uint8_t max_luns_per_target[2];
623 uint8_t reserved_15[2];
624
625 uint8_t port_down_retry_count[2];
626 uint8_t link_down_timeout[2];
627
628 /*
629 * FCode parameters word (offset 344)
630 *
631 * BIT 0 = Enable BIOS pathname
632 * BIT 1 = fcode qlc
633 * BIT 2 = fcode host
634 * BIT 3 = fcode sunid
635 * BIT 4-7 =
636 */
637 uint8_t fcode_p0;
638 uint8_t reserved_16[7];
639
640 /*
641 * Offset 352 (160h).
642 * uint8_t prev_drv_ver_major;
643 * uint8_t prev_drv_ver_submajob;
644 * uint8_t prev_drv_ver_minor;
645 * uint8_t prev_drv_ver_subminor;
646 * uint8_t prev_bios_ver_major[2];
647 * uint8_t prev_bios_ver_minor[2];
648 * uint8_t prev_efi_ver_major[2];
649 * uint8_t prev_efi_ver_minor[2];
650 * uint8_t prev_fw_ver_major[2];
651 * uint8_t prev_fw_ver_minor;
652 * uint8_t prev_fw_ver_subminor;
653 * uint8_t reserved[16];
654 */
655 uint8_t mac_address[6];
656 uint8_t clp_flag[2];
657 uint8_t reserved_18[24];
658
659 /* Offset 384 (180h). */
660 uint8_t def_port_name[8];
661 uint8_t def_node_name[8];
662 uint8_t clp_flag1[2];
663 uint8_t clp_flag2[2];
664
665 /* Offset 404 (194h). */
666 uint8_t default_firmware_options[2];
667
668 /* Offset 406 (196h). */
669 uint8_t enhanced_features[2];
670 uint8_t serdes_index[2];
671 uint8_t reserved_19[6];
672
673 /* Offset 416 (1A0h). */
674 uint8_t alt4_boot_port_name[8];
675 uint8_t alt4_boot_lun_number[2];
676 uint8_t reserved_20[2];
677
678 /* Offset 428 (1ACh). */
679 uint8_t alt5_boot_port_name[8];
680 uint8_t alt5_boot_lun_number[2];
681 uint8_t reserved_21[2];
682
683 /* Offset 440 (1B8h). */
684 uint8_t alt6_boot_port_name[8];
685 uint8_t alt6_boot_lun_number[2];
686 uint8_t reserved_22[2];
687
688 /* Offset 452 (1C4h). */
689 uint8_t alt7_boot_port_name[8];
690 uint8_t alt7_boot_lun_number[2];
691 uint8_t reserved_23[2];
692
693 /* Offset 464 (1D0h). */
694 uint8_t reserved_24[12];
695
696 /* Offset 476 (1DCh). */
697 uint8_t fw_table_offset[2];
698 uint8_t fw_table_sig[2];
699
700 /* Offset 480 (1E0h). */
701 int8_t model_name[4];
702 int8_t model_name1[12]; /* 24xx power_table[8]. */
703
704 /* Offset 496 (1F0h). */
705 uint8_t feature_mask_l[2];
706 uint8_t feature_mask_h[2];
707 uint8_t reserved_25[4];
708
709 /* Offset 504 (1F8h). */
710 uint8_t subsystem_vendor_id[2];
711 uint8_t subsystem_device_id[2];
712
713 uint8_t checksum[4];
714 } nvram_24xx_t;
715
716 /*
717 * Firmware Dump structure definition
718 */
719 #define QL_2200_FW_DUMP_SIZE 0x100000 /* 86e15 bytes */
720 #define QL_2300_FW_DUMP_SIZE 0x100000 /* fc6d3 bytes */
721 #define QL_6322_FW_DUMP_SIZE 0x100000 /* fc6d8 bytes */
722 #define QL_24XX_FW_DUMP_SIZE 0x300000 /* 2cef71 bytes */
723 #define QL_25XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */
724 #define QL_81XX_FW_DUMP_SIZE 0x400000 /* 356c97 bytes */
725 #define QL_27XX_FW_DUMP_SIZE 0x600000 /* 5c3e69 bytes */
726 #define QL_83XX_FW_DUMP_SIZE 0x400000 /* 372792 bytes */
727
728 #define QL_24XX_VPD_SIZE 0x200 /* bytes */
729 #define QL_24XX_SFP_SIZE 0x200 /* bytes */
730
731 /*
732 * firmware dump struct for 2300 is a superset of firmware dump struct
733 * for 2200. Fields which are 2300 only or are enhanced for 2300 are
734 * marked below.
735 */
736 typedef struct ql_fw_dump {
737 uint16_t pbiu_reg[8];
738 uint16_t risc_host_reg[8]; /* 2300 only. */
739 uint16_t mailbox_reg[16]; /* 2200 only needs 8 */
740 uint16_t resp_dma_reg[32]; /* 2300 only. */
741 uint16_t dma_reg[48];
742 uint16_t risc_hdw_reg[16];
743 uint16_t risc_gp0_reg[16];
744 uint16_t risc_gp1_reg[16];
745 uint16_t risc_gp2_reg[16];
746 uint16_t risc_gp3_reg[16];
747 uint16_t risc_gp4_reg[16];
748 uint16_t risc_gp5_reg[16];
749 uint16_t risc_gp6_reg[16];
750 uint16_t risc_gp7_reg[16];
751 uint16_t frame_buf_hdw_reg[64]; /* 2200 has only 16 */
752 uint16_t fpm_b0_reg[64];
753 uint16_t fpm_b1_reg[64];
754 uint16_t risc_ram[0xf800]; /* 2200 needs only 0xf000 */
755 uint16_t stack_ram[0x800]; /* 2300 only */
756 uint16_t data_ram[0xf800]; /* 2300 only */
757 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
758 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
759 } ql_fw_dump_t;
760
761 typedef struct ql_24xx_fw_dump {
762 uint32_t hccr;
763 uint32_t host_reg[32];
764 uint16_t mailbox_reg[32];
765 uint32_t xseq_gp_reg[128];
766 uint32_t xseq_0_reg[16];
767 uint32_t xseq_1_reg[16];
768 uint32_t rseq_gp_reg[128];
769 uint32_t rseq_0_reg[16];
770 uint32_t rseq_1_reg[16];
771 uint32_t rseq_2_reg[16];
772 uint32_t cmd_dma_reg[16];
773 uint32_t req0_dma_reg[15];
774 uint32_t resp0_dma_reg[15];
775 uint32_t req1_dma_reg[15];
776 uint32_t xmt0_dma_reg[32];
777 uint32_t xmt1_dma_reg[32];
778 uint32_t xmt2_dma_reg[32];
779 uint32_t xmt3_dma_reg[32];
780 uint32_t xmt4_dma_reg[32];
781 uint32_t xmt_data_dma_reg[16];
782 uint32_t rcvt0_data_dma_reg[32];
783 uint32_t rcvt1_data_dma_reg[32];
784 uint32_t risc_gp_reg[128];
785 uint32_t shadow_reg[7];
786 uint32_t lmc_reg[112];
787 uint32_t fpm_hdw_reg[192];
788 uint32_t fb_hdw_reg[176];
789 uint32_t code_ram[0x2000];
790 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
791 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
792 uint32_t ext_trace_buf[FWEXTSIZE / 4];
793 uint32_t fce_trace_buf[FWFCESIZE / 4];
794 uint32_t ext_mem[1];
795 } ql_24xx_fw_dump_t;
796
797 typedef struct ql_25xx_fw_dump {
798 uint32_t hccr;
799 uint32_t r2h_status;
800 uint32_t aer_ues;
801 uint32_t hostrisc_reg[32];
802 uint32_t pcie_reg[4];
803 uint32_t host_reg[32];
804 uint16_t mailbox_reg[32];
805 uint32_t xseq_gp_reg[128];
806 uint32_t xseq_0_reg[48];
807 uint32_t xseq_1_reg[16];
808 uint32_t rseq_gp_reg[128];
809 uint32_t rseq_0_reg[32];
810 uint32_t rseq_1_reg[16];
811 uint32_t rseq_2_reg[16];
812 uint32_t aseq_gp_reg[128];
813 uint32_t aseq_0_reg[32];
814 uint32_t aseq_1_reg[16];
815 uint32_t aseq_2_reg[16];
816 uint32_t cmd_dma_reg[16];
817 uint32_t req0_dma_reg[15];
818 uint32_t resp0_dma_reg[15];
819 uint32_t req1_dma_reg[15];
820 uint32_t xmt0_dma_reg[32];
821 uint32_t xmt1_dma_reg[32];
822 uint32_t xmt2_dma_reg[32];
823 uint32_t xmt3_dma_reg[32];
824 uint32_t xmt4_dma_reg[32];
825 uint32_t xmt_data_dma_reg[16];
826 uint32_t rcvt0_data_dma_reg[32];
827 uint32_t rcvt1_data_dma_reg[32];
828 uint32_t risc_gp_reg[128];
829 uint32_t shadow_reg[11];
830 uint32_t risc_io;
831 uint32_t lmc_reg[128];
832 uint32_t fpm_hdw_reg[192];
833 uint32_t fb_hdw_reg[192];
834 uint32_t code_ram[0x2000];
835 uint32_t ext_trace_buf[FWEXTSIZE / 4];
836 uint32_t fce_trace_buf[FWFCESIZE / 4];
837 uint32_t req_q_size[2];
838 uint32_t rsp_q_size;
839 uint32_t req_rsp_ext_mem[1];
840 } ql_25xx_fw_dump_t;
841
842 typedef struct ql_81xx_fw_dump {
843 uint32_t hccr;
844 uint32_t r2h_status;
845 uint32_t aer_ues;
846 uint32_t hostrisc_reg[32];
847 uint32_t pcie_reg[4];
848 uint32_t host_reg[32];
849 uint16_t mailbox_reg[32];
850 uint32_t xseq_gp_reg[128];
851 uint32_t xseq_0_reg[48];
852 uint32_t xseq_1_reg[16];
853 uint32_t rseq_gp_reg[128];
854 uint32_t rseq_0_reg[32];
855 uint32_t rseq_1_reg[16];
856 uint32_t rseq_2_reg[16];
857 uint32_t aseq_gp_reg[128];
858 uint32_t aseq_0_reg[32];
859 uint32_t aseq_1_reg[16];
860 uint32_t aseq_2_reg[16];
861 uint32_t cmd_dma_reg[16];
862 uint32_t req0_dma_reg[15];
863 uint32_t resp0_dma_reg[15];
864 uint32_t req1_dma_reg[15];
865 uint32_t xmt0_dma_reg[32];
866 uint32_t xmt1_dma_reg[32];
867 uint32_t xmt2_dma_reg[32];
868 uint32_t xmt3_dma_reg[32];
869 uint32_t xmt4_dma_reg[32];
870 uint32_t xmt_data_dma_reg[16];
871 uint32_t rcvt0_data_dma_reg[32];
872 uint32_t rcvt1_data_dma_reg[32];
873 uint32_t risc_gp_reg[128];
874 uint32_t shadow_reg[11];
875 uint32_t risc_io;
876 uint32_t lmc_reg[128];
877 uint32_t fpm_hdw_reg[224];
878 uint32_t fb_hdw_reg[208];
879 uint32_t code_ram[0x2000];
880 uint32_t ext_trace_buf[FWEXTSIZE / 4];
881 uint32_t fce_trace_buf[FWFCESIZE / 4];
882 uint32_t req_q_size[2];
883 uint32_t rsp_q_size;
884 uint32_t req_rsp_ext_mem[1];
885 } ql_81xx_fw_dump_t;
886
887 typedef struct ql_83xx_fw_dump {
888 uint32_t hccr;
889 uint32_t r2h_status;
890 uint32_t aer_ues;
891 uint32_t hostrisc_reg[48];
892 uint32_t pcie_reg[4];
893 uint32_t host_reg[32];
894 uint16_t mailbox_reg[32];
895 uint32_t xseq_gp_reg[256];
896 uint32_t xseq_0_reg[48];
897 uint32_t xseq_1_reg[16];
898 uint32_t xseq_2_reg[16];
899 uint32_t rseq_gp_reg[256];
900 uint32_t rseq_0_reg[32];
901 uint32_t rseq_1_reg[16];
902 uint32_t rseq_2_reg[16];
903 uint32_t rseq_3_reg[16];
904 uint32_t aseq_gp_reg[256];
905 uint32_t aseq_0_reg[32];
906 uint32_t aseq_1_reg[16];
907 uint32_t aseq_2_reg[16];
908 uint32_t aseq_3_reg[16];
909 uint32_t cmd_dma_reg[64];
910 uint32_t req0_dma_reg[15];
911 uint32_t resp0_dma_reg[15];
912 uint32_t req1_dma_reg[15];
913 uint32_t xmt0_dma_reg[32];
914 uint32_t xmt1_dma_reg[32];
915 uint32_t xmt2_dma_reg[32];
916 uint32_t xmt3_dma_reg[32];
917 uint32_t xmt4_dma_reg[32];
918 uint32_t xmt_data_dma_reg[16];
919 uint32_t rcvt0_data_dma_reg[32];
920 uint32_t rcvt1_data_dma_reg[32];
921 uint32_t risc_gp_reg[128];
922 uint32_t shadow_reg[11];
923 uint32_t risc_io;
924 uint32_t lmc_reg[128];
925 uint32_t fpm_hdw_reg[256];
926 uint32_t rq0_array_reg[256];
927 uint32_t rq1_array_reg[256];
928 uint32_t rp0_array_reg[256];
929 uint32_t rp1_array_reg[256];
930 uint32_t ato_array_reg[128];
931 uint32_t queue_control_reg[16];
932 uint32_t fb_hdw_reg[432];
933 uint32_t code_ram[0x2400];
934 uint32_t ext_trace_buf[FWEXTSIZE / 4];
935 uint32_t fce_trace_buf[FWFCESIZE / 4];
936 uint32_t req_q_size[2];
937 uint32_t rsp_q_size;
938 uint32_t req_rsp_ext_mem[1];
939 } ql_83xx_fw_dump_t;
940
941 #ifdef _KERNEL
942
943 /*
944 * firmware dump Entry Types
945 */
946 #define DT_NOP 0
947 #define DT_THDR 99
948 #define DT_TEND 255
949 #define DT_RIOB1 256
950 #define DT_WIOB1 257
951 #define DT_RIOB2 258
952 #define DT_WIOB2 259
953 #define DT_RPCI 260
954 #define DT_WPCI 261
955 #define DT_RRAM 262
956 #define DT_GQUE 263
957 #define DT_GFCE 264
958 #define DT_PRISC 265
959 #define DT_RRISC 266
960 #define DT_DINT 267
961 #define DT_GHBD 268
962 #define DT_SCRA 269
963 #define DT_RRREG 270
964 #define DT_WRREG 271
965 #define DT_RRRAM 272
966 #define DT_RPCIC 273
967 #define DT_GQUES 274
968 #define DT_WDMP 275
969
970 /*
971 * firmware dump Template Header (Entry Type 99)
972 */
973 typedef struct ql_dt_hdr {
974 uint32_t type;
975 uint32_t first_entry_offset;
976 uint32_t size_of_template;
977 uint32_t rsv;
978 uint32_t num_of_entries;
979 uint32_t version;
980 uint32_t driver_timestamp;
981 uint32_t checksum;
982 uint32_t rsv_1;
983 uint32_t driver_info[3];
984 uint32_t saved_state_area[16];
985 uint32_t rsv_2[8];
986 uint32_t ver_attr[5];
987 } ql_dt_hdr_t;
988
989 /*
990 * firmware dump Common Entry Header
991 */
992 typedef struct ql_dt_entry_hdr {
993 uint32_t type;
994 uint32_t size;
995 uint32_t rsv;
996 #ifdef _BIG_ENDIAN
997 uint8_t driver_flags;
998 uint8_t rsv_2;
999 uint8_t rsv_1;
1000 uint8_t capture_flags;
1001 #else
1002 uint8_t capture_flags;
1003 uint8_t rsv_1;
1004 uint8_t rsv_2;
1005 uint8_t driver_flags;
1006 #endif
1007 } ql_dt_entry_hdr_t;
1008
1009 /*
1010 * Capture Flags
1011 */
1012 #define PF_ONLY_FLAG BIT_0 /* Physical Function Only */
1013 #define PF_VF_FLAG BIT_1 /* Physical and Virtual Functions */
1014
1015 /*
1016 * Driver Flags
1017 */
1018 #define SKIPPED_FLAG BIT_7 /* driver skipped this entry */
1019
1020 /*
1021 * firmware dump Entry Including Header
1022 */
1023 typedef struct ql_dt_entry {
1024 ql_dt_entry_hdr_t h;
1025 uint32_t data[1];
1026 } ql_dt_entry_t;
1027
1028 /*
1029 * firmware dump Template image
1030 */
1031 typedef struct ql_dmp_template {
1032 uint32_t rsv[2];
1033 uint32_t len;
1034 uint32_t major_ver;
1035 uint32_t minor_ver;
1036 uint32_t subminor_ver;
1037 uint32_t attribute;
1038 ql_dt_hdr_t hdr;
1039 ql_dt_entry_t entries[1];
1040 } ql_dmp_template_t;
1041
1042 typedef struct ql_dt_riob1 {
1043 ql_dt_entry_hdr_t h;
1044 uint32_t addr;
1045 #ifdef _BIG_ENDIAN
1046 uint8_t pci_offset;
1047 uint8_t reg_count_h;
1048 uint8_t reg_count_l;
1049 uint8_t reg_size;
1050 #else
1051 uint8_t reg_size;
1052 uint8_t reg_count_l;
1053 uint8_t reg_count_h;
1054 uint8_t pci_offset;
1055 #endif
1056 } ql_dt_riob1_t;
1057
1058 typedef struct ql_dt_wiob1 {
1059 ql_dt_entry_hdr_t h;
1060 uint32_t addr;
1061 uint32_t data;
1062 #ifdef _BIG_ENDIAN
1063 uint8_t rsv[3];
1064 uint8_t pci_offset;
1065 #else
1066 uint8_t pci_offset;
1067 uint8_t rsv[3];
1068 #endif
1069 } ql_dt_wiob1_t;
1070
1071 typedef struct ql_dt_riob2 {
1072 ql_dt_entry_hdr_t h;
1073 uint32_t addr;
1074 #ifdef _BIG_ENDIAN
1075 uint8_t pci_offset;
1076 uint8_t reg_count_h;
1077 uint8_t reg_count_l;
1078 uint8_t reg_size;
1079 uint8_t rsv[3];
1080 uint8_t bank_sel_offset;
1081 #else
1082 uint8_t reg_size;
1083 uint8_t reg_count_l;
1084 uint8_t reg_count_h;
1085 uint8_t pci_offset;
1086 uint8_t bank_sel_offset;
1087 uint8_t rsv[3];
1088 #endif
1089 uint32_t reg_bank;
1090 } ql_dt_riob2_t;
1091
1092 typedef struct ql_dt_wiob2 {
1093 ql_dt_entry_hdr_t h;
1094 uint32_t addr;
1095 #ifdef _BIG_ENDIAN
1096 uint8_t rsv[2];
1097 uint8_t data_h;
1098 uint8_t data_l;
1099 uint8_t bank_sel_offset;
1100 uint8_t pci_offset;
1101 uint8_t rsv1[2];
1102 #else
1103 uint8_t data_l;
1104 uint8_t data_h;
1105 uint8_t rsv[2];
1106 uint8_t rsv1[2];
1107 uint8_t pci_offset;
1108 uint8_t bank_sel_offset;
1109 #endif
1110 uint32_t reg_bank;
1111 } ql_dt_wiob2_t;
1112
1113 typedef struct ql_dt_rpci {
1114 ql_dt_entry_hdr_t h;
1115 uint32_t addr;
1116 } ql_dt_rpci_t;
1117
1118 typedef struct ql_dt_wpci {
1119 ql_dt_entry_hdr_t h;
1120 uint32_t addr;
1121 uint32_t data;
1122 } ql_dt_wpci_t, ql_dt_wrreg_t;
1123
1124 typedef struct ql_dt_rram {
1125 ql_dt_entry_hdr_t h;
1126 #ifdef _BIG_ENDIAN
1127 uint8_t rsv[3];
1128 uint8_t ram_area;
1129 #else
1130 uint8_t ram_area;
1131 uint8_t rsv[3];
1132 #endif
1133 uint32_t start_addr;
1134 uint32_t end_addr;
1135 } ql_dt_rram_t;
1136
1137 typedef struct ql_dt_gque {
1138 ql_dt_entry_hdr_t h;
1139 uint32_t num_queues;
1140 #ifdef _BIG_ENDIAN
1141 uint8_t rsv[3];
1142 uint8_t queue_type;
1143 #else
1144 uint8_t queue_type;
1145 uint8_t rsv[3];
1146 #endif
1147 } ql_dt_gque_t, ql_dt_gques_t;
1148
1149 typedef struct ql_dt_gfce {
1150 ql_dt_entry_hdr_t h;
1151 uint32_t fce_trace_size;
1152 uint32_t write_pointer[2];
1153 uint32_t base_pointer[2];
1154 uint32_t fce_enable_mb0;
1155 uint32_t fce_enable_mb2;
1156 uint32_t fce_enable_mb3;
1157 uint32_t fce_enable_mb4;
1158 uint32_t fce_enable_mb5;
1159 uint32_t fce_enable_mb6;
1160 } ql_dt_gfce_t;
1161
1162 typedef struct ql_dt_prisc {
1163 ql_dt_entry_hdr_t h;
1164 } ql_dt_prisc_t, ql_dt_rrisc_t;
1165
1166 typedef struct ql_dt_dint {
1167 ql_dt_entry_hdr_t h;
1168 #ifdef _BIG_ENDIAN
1169 uint8_t rsv[3];
1170 uint8_t pci_offset;
1171 #else
1172 uint8_t pci_offset;
1173 uint8_t rsv[3];
1174 #endif
1175 uint32_t data;
1176 } ql_dt_dint_t;
1177
1178 typedef struct ql_dt_ghbd {
1179 ql_dt_entry_hdr_t h;
1180 #ifdef _BIG_ENDIAN
1181 uint8_t rsv[3];
1182 uint8_t host_buf_type;
1183 #else
1184 uint8_t host_buf_type;
1185 uint8_t rsv[3];
1186 #endif
1187 uint32_t buf_size;
1188 uint32_t start_addr;
1189 } ql_dt_ghbd_t;
1190
1191 typedef struct ql_dt_scra {
1192 ql_dt_entry_hdr_t h;
1193 uint32_t scratch_size;
1194 } ql_dt_scra_t;
1195
1196 typedef struct ql_dt_rrreg {
1197 ql_dt_entry_hdr_t h;
1198 uint32_t addr;
1199 uint32_t count;
1200 } ql_dt_rrreg_t, ql_dt_rrram_t, ql_dt_rpcic_t;
1201
1202 typedef struct ql_dt_wdmp {
1203 ql_dt_entry_hdr_t h;
1204 uint32_t length;
1205 uint32_t data[1];
1206 } ql_dt_wdmp_t;
1207
1208 /*
1209 * ql_lock_nvram() flags
1210 */
1211 #define LNF_NVRAM_DATA BIT_0 /* get nvram */
1212 #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */
1213
1214 /*
1215 * ISP product identification definitions in mailboxes after reset.
1216 */
1217 #define PROD_ID_1 0x4953
1218 #define PROD_ID_2 0x0000
1219 #define PROD_ID_2a 0x5020
1220 #define PROD_ID_3 0x2020
1221
1222 /*
1223 * NVRAM Command values.
1224 */
1225 #define NV_START_BIT BIT_2
1226 #define NV_WRITE_OP (BIT_26 + BIT_24)
1227 #define NV_READ_OP (BIT_26 + BIT_25)
1228 #define NV_ERASE_OP (BIT_26 + BIT_25 + BIT_24)
1229 #define NV_MASK_OP (BIT_26 + BIT_25 + BIT_24)
1230 #define NV_DELAY_COUNT 10
1231
1232 /*
1233 * Deivce ID list definitions.
1234 */
1235 struct ql_dev_id {
1236 uint8_t al_pa;
1237 uint8_t area;
1238 uint8_t domain;
1239 uint8_t loop_id;
1240 };
1241
1242 struct ql_ex_dev_id {
1243 uint8_t al_pa;
1244 uint8_t area;
1245 uint8_t domain;
1246 uint8_t reserved;
1247 uint8_t loop_id_l;
1248 uint8_t loop_id_h;
1249 };
1250
1251 struct ql_24_dev_id {
1252 uint8_t al_pa;
1253 uint8_t area;
1254 uint8_t domain;
1255 uint8_t reserved;
1256 uint8_t n_port_hdl_l;
1257 uint8_t n_port_hdl_h;
1258 uint8_t reserved_1[2];
1259 };
1260
1261 typedef union ql_dev_id_list {
1262 struct ql_dev_id d;
1263 struct ql_ex_dev_id d_ex;
1264 struct ql_24_dev_id d_24;
1265 } ql_dev_id_list_t;
1266
1267 /* Define maximum number of device list entries.. */
1268 #define DEVICE_LIST_ENTRIES MAX_24_FIBRE_DEVICES
1269
1270 /*
1271 * Global Data in ql_init.c source file.
1272 */
1273
1274 /*
1275 * Global Function Prototypes in ql_init.c source file.
1276 */
1277 int ql_initialize_adapter(ql_adapter_state_t *);
1278 int ql_pci_sbus_config(ql_adapter_state_t *);
1279 int ql_nvram_config(ql_adapter_state_t *);
1280 uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t);
1281 void ql_nv_write(ql_adapter_state_t *, uint16_t);
1282 void ql_nv_delay(void);
1283 int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t);
1284 void ql_release_nvram(ql_adapter_state_t *);
1285 void ql_common_properties(ql_adapter_state_t *);
1286 uint32_t ql_get_prop(ql_adapter_state_t *, char *);
1287 int ql_load_isp_firmware(ql_adapter_state_t *);
1288 int ql_start_firmware(ql_adapter_state_t *);
1289 int ql_set_cache_line(ql_adapter_state_t *);
1290 int ql_init_rings(ql_adapter_state_t *);
1291 int ql_fw_ready(ql_adapter_state_t *, uint8_t);
1292 void ql_dev_list(ql_adapter_state_t *, ql_dev_id_list_t *, uint32_t,
1293 port_id_t *, uint16_t *);
1294 void ql_reset_chip(ql_adapter_state_t *);
1295 int ql_abort_isp(ql_adapter_state_t *);
1296 void ql_requeue_all_cmds(ql_adapter_state_t *);
1297 int ql_vport_control(ql_adapter_state_t *, uint8_t);
1298 int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t);
1299 int ql_vport_enable(ql_adapter_state_t *);
1300 ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t);
1301 void ql_vport_destroy(ql_adapter_state_t *);
1302 #endif /* _KERNEL */
1303
1304 #ifdef __cplusplus
1305 }
1306 #endif
1307
1308 #endif /* _QL_INIT_H */