1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright 2009 QLogic Corporation */
23
24 /*
25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
26 * Use is subject to license terms.
27 */
28
29 #ifndef _QL_INIT_H
30 #define _QL_INIT_H
31
32 /*
33 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
34 *
35 * ***********************************************************************
36 * * **
37 * * NOTICE **
38 * * COPYRIGHT (C) 1996-2009 QLOGIC CORPORATION **
39 * * ALL RIGHTS RESERVED **
40 * * **
41 * ***********************************************************************
42 *
43 */
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /*
50 * ISP2200 NVRAM structure definition.
51 * Little endian except where noted.
52 */
53 typedef struct nvram {
54 /*
55 * NVRAM header
56 */
57 uint8_t id[4];
58 uint8_t nvram_version;
59 uint8_t reserved_0;
60
61 /*
62 * NVRAM RISC parameter block
63 */
64 uint8_t parameter_block_version;
65 uint8_t reserved_1;
66
67 /*
68 * LSB BIT 0 = enable_hard_loop_id
69 * LSB BIT 1 = enable_fairness
70 * LSB BIT 2 = enable_full_duplex
71 * LSB BIT 3 = enable_fast_posting
72 * LSB BIT 4 = enable_target_mode
73 * LSB BIT 5 = disable_initiator_mode
74 * LSB BIT 6 = enable_adisc
75 * LSB BIT 7 = enable_target_inquiry_data
76 *
77 * MSB BIT 0 = enable_port_update_ae
78 * MSB BIT 1 = disable_initial_lip
79 * MSB BIT 2 = enable_decending_soft_assign
80 * MSB BIT 3 = previous_assigned_addressing
81 * MSB BIT 4 = enable_stop_q_on_full
82 * MSB BIT 5 = enable_full_login_on_lip
83 * MSB BIT 6 = enable_node_name
84 * MSB BIT 7 = extended_control_block
85 */
86 uint8_t firmware_options[2];
87
88 uint8_t max_frame_length[2];
89 uint8_t max_iocb_allocation[2];
90 uint8_t execution_throttle[2];
91 uint8_t login_retry_count;
92 uint8_t retry_delay; /* unused */
93 uint8_t port_name[8]; /* Big endian. */
94 uint8_t hard_address[2];
95 uint8_t inquiry;
96 uint8_t login_timeout;
97 uint8_t node_name[8]; /* Big endian. */
98
99 /*
100 * LSB BIT 0 = Timer operation mode bit 0
101 * LSB BIT 1 = Timer operation mode bit 1
102 * LSB BIT 2 = Timer operation mode bit 2
103 * LSB BIT 3 = Timer operation mode bit 3
104 * LSB BIT 4 = P2P Connection option bit 0
105 * LSB BIT 5 = P2P Connection option bit 1
106 * LSB BIT 6 = P2P Connection option bit 2
107 * LSB BIT 7 = Enable Non part on LIHA failure
108 *
109 * MSB BIT 0 = Enable class 2
110 * MSB BIT 1 = Enable ACK0
111 * MSB BIT 2 =
112 * MSB BIT 3 =
113 * MSB BIT 4 = FC Tape Enable
114 * MSB BIT 5 = Enable FC Confirm
115 * MSB BIT 6 = Enable command queuing in target mode
116 * MSB BIT 7 = No Logo On Link Down
117 */
118 uint8_t add_fw_opt[2];
119 uint8_t response_accumulation_timer;
120 uint8_t interrupt_delay_timer;
121
122 /*
123 * LSB BIT 0 = Enable Read xfr_rdy
124 * LSB BIT 1 = Soft ID only
125 * LSB BIT 2 =
126 * LSB BIT 3 =
127 * LSB BIT 4 = FCP RSP Payload [0]
128 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
129 * LSB BIT 6 =
130 * LSB BIT 7 =
131 *
132 * MSB BIT 0 = Sbus enable - 2300
133 * MSB BIT 1 =
134 * MSB BIT 2 =
135 * MSB BIT 3 =
136 * MSB BIT 4 =
137 * MSB BIT 5 = Enable 50 ohm termination
138 * MSB BIT 6 = Data Rate (2300 only)
139 * MSB BIT 7 = Data Rate (2300 only)
140 */
141 uint8_t special_options[2];
142
143 /* Reserved for expanded RISC parameter block */
144 uint8_t reserved_4[26];
145
146 /*
147 * NVRAM host parameter block
148 *
149 * LSB BIT 0 = unused
150 * LSB BIT 1 = disable_bios
151 * LSB BIT 2 = disable_luns
152 * LSB BIT 3 = enable_selectable_boot
153 * LSB BIT 4 = disable_risc_code_load
154 * LSB BIT 5 = set_cache_line_size_1
155 * LSB BIT 6 = pci_parity_disable
156 * LSB BIT 7 = enable_extended_logging
157 *
158 * MSB BIT 0 = enable_64bit_addressing
159 * MSB BIT 1 = enable_lip_reset
160 * MSB BIT 2 = enable_lip_full_login
161 * MSB BIT 3 = enable_target_reset
162 * MSB BIT 4 = enable_database_storage
163 * MSB BIT 5 = unused
164 * MSB BIT 6 = unused
165 * MSB BIT 7 = unused
166 */
167 uint8_t host_p[2];
168
169 uint8_t boot_node_name[8];
170 uint8_t boot_lun_number;
171 uint8_t reset_delay;
172 uint8_t port_down_retry_count;
173 uint8_t reserved_5;
174
175 uint8_t maximum_luns_per_target[2];
176
177 uint8_t reserved_6[14];
178
179 /* Offset 100 */
180 uint8_t reverved_7[12];
181
182 /* offset 112 */
183 uint8_t adapInfo[16]; /* Sun OEM HBA's 23xx only */
184
185 uint8_t reserved_8[22];
186
187 /* Offset 150 */
188 uint8_t reserved_9[50];
189
190 /* Offset 200 */
191 uint8_t reserved_10[32];
192
193 /*
194 * NVRAM Adapter Features offset 232-239
195 *
196 * LSB BIT 0 = External GBIC
197 * LSB BIT 1 = Risc RAM parity
198 * LSB BIT 2 = Buffer Plus Module
199 * LSB BIT 3 = Multi Chip Adapter
200 * LSB BIT 4 =
201 * LSB BIT 5 =
202 * LSB BIT 6 =
203 * LSB BIT 7 =
204 *
205 * MSB BIT 0 =
206 * MSB BIT 1 =
207 * MSB BIT 2 =
208 * MSB BIT 3 =
209 * MSB BIT 4 =
210 * MSB BIT 5 =
211 * MSB BIT 6 =
212 * MSB BIT 7 =
213 */
214 uint8_t adapter_features[2];
215 uint8_t reserved_11[6];
216
217 /*
218 * Resrved for use with ISP2300 - offset 240
219 */
220 uint8_t reserved_12[4];
221
222 /* Subsystem ID must be at offset 244 */
223 uint8_t subsystem_vendor_id[2];
224
225 uint8_t reserved_13[2];
226
227 /* Subsystem device ID must be at offset 248 */
228 uint8_t subsystem_device_id[2];
229
230 /* Subsystem vendor ID for ISP2200 */
231 uint8_t subsystem_vendor_id_2200[2];
232
233 /* Subsystem device ID for ISP2200 */
234 uint8_t subsystem_device_id_2200[2];
235
236 uint8_t reserved_14;
237 uint8_t checksum;
238 } nvram_t;
239
240 /*
241 * NVRAM structure definition.
242 */
243 typedef struct nvram_24xx {
244 /* NVRAM header. */
245 uint8_t id[4];
246 uint8_t nvram_version[2];
247 uint8_t reserved_0[2];
248
249 /* Firmware Initialization Control Block. */
250 uint8_t version[2];
251 uint8_t reserved_1[2];
252 uint8_t max_frame_length[2];
253 uint8_t execution_throttle[2];
254 uint8_t exchange_count[2];
255 uint8_t hard_address[2];
256 uint8_t port_name[8];
257 uint8_t node_name[8];
258 uint8_t login_retry_count[2];
259 uint8_t link_down_on_nos[2];
260 uint8_t interrupt_delay_timer[2];
261 uint8_t login_timeout[2];
262
263 /*
264 * BIT 0 = Hard Assigned Loop ID
265 * BIT 1 = Enable Fairness
266 * BIT 2 = Enable Full-Duplex
267 * BIT 3 = Reserved
268 * BIT 4 = Target Mode Enable
269 * BIT 5 = Initiator Mode Disable
270 * BIT 6 = Reserved
271 * BIT 7 = Reserved
272 *
273 * BIT 8 = Reserved
274 * BIT 9 = Disable Initial LIP
275 * BIT 10 = Descending Loop ID Search
276 * BIT 11 = Previous Assigned Loop ID
277 * BIT 12 = Reserved
278 * BIT 13 = Full Login after LIP
279 * BIT 14 = Node Name Option
280 * BIT 15 = Reserved
281 *
282 * BIT 16-31 = Reserved
283 */
284 uint8_t firmware_options_1[4];
285
286 /*
287 * BIT 0 = Operation Mode bit 0
288 * BIT 1 = Operation Mode bit 1
289 * BIT 2 = Operation Mode bit 2
290 * BIT 3 = Operation Mode bit 3
291 * BIT 4 = Connection Options bit 0
292 * BIT 5 = Connection Options bit 1
293 * BIT 6 = Connection Options bit 2
294 * BIT 7 = Enable Non part on LIHA failure
295 *
296 * BIT 8 = Enable Class 2
297 * BIT 9 = Enable ACK0
298 * BIT 10 = Enable Virtual Fabric
299 * BIT 11 = Enable FC-SP Security
300 * BIT 12 = FC Tape Enable
301 * BIT 13 = Reserved
302 * BIT 14 = Target PRLI Control
303 * BIT 15 = Reserved
304 *
305 * BIT 16 = Enable Emulated MSIX
306 * BIT 17 = Reserved
307 * BIT 18 = Enable Alternate Device Number
308 * BIT 19 = Enable Alternate Bus Number
309 * BIT 20 = Enable Translated Address
310 * BIT 21 = Enable VM Security
311 * BIT 22 = Enable Interrupt Handshake
312 * BIT 23 = Enable Multiple Queue
313 *
314 * BIT 24 = IOCB Security
315 * BIT 25 = qos
316 * BIT 26-31 = Reserved
317 */
318 uint8_t firmware_options_2[4];
319
320 /*
321 * BIT 0 = Reserved
322 * BIT 1 = Soft ID only
323 * BIT 2 = Reserved
324 * BIT 3 = disable split completion timeout
325 * BIT 4 = FCP RSP Payload bit 0
326 * BIT 5 = FCP RSP Payload bit 1
327 * BIT 6 = Enable Rec Out-of-Order data frame handling
328 * BIT 7 = Disable Automatic PLOGI on Local Loop
329 *
330 * BIT 8 = Reserved
331 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
332 * offset handling
333 * BIT 10 = Reserved
334 * BIT 11 = Reserved
335 * BIT 12 = Reserved
336 * BIT 13 = Data Rate bit 0
337 * BIT 14 = Data Rate bit 1
338 * BIT 15 = Data Rate bit 2
339 *
340 * BIT 16 = 75-ohm Termination Select
341 * BIT 17 = Enable Multiple FCFs
342 * BIT 18 = MAC Addressing Mode
343 * BIT 19 = MAC Addressing Mode
344 * BIT 20 = MAC Addressing Mode
345 * BIT 21 = Ethernet Data Rate
346 * BIT 22 = Ethernet Data Rate
347 * BIT 23 = Ethernet Data Rate
348 *
349 * BIT 24 = Ethernet Data Rate
350 * BIT 25 = Ethernet Data Rate
351 * BIT 26 = Enable Ethernet Header ATIO Queue
352 * BIT 27 = Enable Ethernet Header Response Queue
353 * BIT 28 = SPMA Selection
354 * BIT 29 = SPMA Selection
355 * BIT 30 = Reserved
356 * BIT 31 = Reserved
357 */
358 uint8_t firmware_options_3[4];
359
360 union {
361 struct {
362 /*
363 * Offset 56 (38h)
364 * Serial Link Control
365 * BIT 0 = control enable
366 * BIT 1-15 = Reserved
367 */
368 uint8_t swing_opt[2];
369 /*
370 * Offset 58 (3Ah)
371 * Serial Link Control 1G
372 * BIT 0-7 = Reserved
373 *
374 * BIT 8-10 = output swing
375 * BIT 11-13 = output emphasis
376 * BIT 14-15 = Reserved
377 */
378 uint8_t swing_1g[2];
379 /*
380 * Offset 60 (3Ch)
381 * Serial Link Control 2G
382 * BIT 0-7 = Reserved
383 *
384 * BIT 8-10 = output swing
385 * BIT 11-13 = output emphasis
386 * BIT 14-15 = Reserved
387 */
388 uint8_t swing_2g[2];
389 /*
390 * Offset 62 (3Eh)
391 * Serial Link Control 4G
392 * BIT 0-7 = Reserved
393 *
394 * BIT 8-10 = output swing
395 * BIT 11-13 = output emphasis
396 * BIT 14-15 = Reserved
397 */
398 uint8_t swing_4g[2];
399
400 /* Offset 64 (40h). */
401 uint8_t reserved[32];
402 } isp2400;
403 struct {
404 /*
405 * Offset 56 (38h)
406 * Serial Link Control
407 * BIT 0 = Reserved
408 * BIT 1 = 25xx TX control enable
409 * BIT 2 = 25xx RX control enable (lmtg)
410 * BIT 3 = 25xx RX control enable (linear)
411 * BIT 4 = embedded HBA
412 * BIT 5 = unused
413 * BIT 6 = 25xx E7 Addr27 Preset
414 * BIT 7 = 25xx E6 Addr0 Ch0 enable
415 *
416 * BIT 8-15 = 25xx E6 Addr0 Ch0
417 *
418 * BIT 16-31 = Reserved
419 */
420 uint8_t swing_opt[4];
421
422 /*
423 * Offset 60 (3Ch)
424 * Serial Link TX Parameters
425 * BIT 0 = TX Amplitude
426 * BIT 1 = TX Amplitude
427 * BIT 2 = TX Amplitude
428 * BIT 3 = TX Amplitude
429 * BIT 4 = TX Amplitude
430 * BIT 5 = TX iPost
431 * BIT 6 = TX iPost
432 * BIT 7 = TX iPost
433 *
434 * BIT 8 = TX iPost
435 * BIT 9 = TX iPre
436 * BIT 10 = TX iPre
437 * BIT 11 = TX iPre
438 * BIT 12 = TX iPre
439 * BIT 13 = TX iMain
440 * BIT 14 = TX iMain
441 * BIT 15 = TX iMain
442 *
443 * BIT 16 = TX iMain
444 * BIT 17 = TX iMain
445 * BIT 18-23 = Reserved
446 *
447 * BIT 24-31 = Reserved
448 */
449 uint8_t tx_8g[4];
450 /* Offset 64 (40h) */
451 uint8_t tx_4g[4];
452 /* Offset 68 (44h) */
453 uint8_t tx_2g[4];
454
455 /*
456 * Offset 72 (48h)
457 * Serial Link RX Parameters
458 * BIT 0 = RX Z1Cnt
459 * BIT 1 = RX Z1Cnt
460 * BIT 2 = RX Z1Cnt
461 * BIT 3 = RX Z1Cnt
462 * BIT 4 = RX G1Cnt
463 * BIT 5 = RX ZCnt
464 * BIT 6 = RX ZCnt
465 * BIT 7 = RX ZCnt
466 *
467 * BIT 8 = RX ZCnt
468 * BIT 9 = RX ZCnt
469 * BIT 10 = RX TLTH
470 * BIT 11 = RX TLTH
471 * BIT 12 = RX TLTH
472 * BIT 13 = RX TLTH
473 * BIT 14 = RX TLTH
474 * BIT 15 = RX TLTH
475 *
476 * BIT 16 = RX DFELTH
477 * BIT 17 = RX DFELTH
478 * BIT 18 = RX DFELTH
479 * BIT 19 = RX DFELTH
480 * BIT 20 = RX DFELTH
481 * BIT 21 = RX DFELTH
482 * BIT 22-23 = Reserved
483 *
484 * BIT 24-31 = Reserved
485 */
486 uint8_t rx_limit_8g[4];
487 /* Offset 76 (4Ch) */
488 uint8_t rx_limit_4g[4];
489 /* Offset 80 (50h) */
490 uint8_t rx_limit_2g[4];
491 /* Offset 84 (54h) */
492 uint8_t rx_linear_8g[4];
493 /* Offset 88 (58h) */
494 uint8_t rx_linear_4g[4];
495 /* Offset 92 (5Ch) */
496 uint8_t rx_linear_2g[4];
497 } isp2500;
498 struct {
499 /* Offset 56 (38h) */
500 uint8_t reserved[8];
501
502 /* Offset 64 (40h). */
503 uint8_t e_node_mac_addr[6];
504
505 /* Offset 70 (46h). */
506 uint8_t reserved2[26];
507 } isp8001;
508 } fw;
509
510 /*
511 * Offset 96 (60h)
512 * BIT 0 = initiator op
513 * BIT 1 = target op
514 * BIT 2 = VI op
515 * BIT 3-7 = Reserved
516 */
517 uint8_t oem_specific;
518 uint8_t reserved_4[15];
519
520 /* Offset 112 (70h). */
521 uint8_t reserved_5[16];
522
523 /*
524 * Offset 128 (80h).
525 * PCIe table entries.
526 * Firmware Extended Initialization Control Block.
527 */
528 ql_ext_icb_8100_t ext_blk;
529
530 /* Offset 192. */
531 uint8_t reserved_6[32];
532
533 /* Offset 224. */
534 uint8_t reserved_7[32];
535
536 /*
537 * BIT 0 = Enable spinup delay
538 * BIT 1 = Disable BIOS
539 * BIT 2 = Enable Memory Map BIOS
540 * BIT 3 = Enable Selectable Boot
541 * BIT 4 = Disable RISC code load
542 * BIT 5 = Disable serdes
543 * BIT 6 = Enable opt boot mode
544 * BIT 7 = Enable int mode BIOS
545 *
546 * BIT 8 = EV control enable
547 * BIT 9 = Enable lip reset
548 * BIT 10 = Enable lip full login
549 * BIT 11 = Enable target reset
550 * BIT 12 = Stop firmware
551 * BIT 13 = Default Node Name Option
552 * BIT 14 = Default WWPN valid
553 * BIT 15 = Enable alternate WWN
554 *
555 * CLP BIOS flags
556 *
557 * BIT 16 = clp lun string
558 * BIT 17 = clp target string
559 * BIT 18 = clp bios enable string
560 * BIT 19 = clp serdes_string
561 * BIT 20 = clp wwpn string
562 * BIT 21 = clp wwnn string
563 * BIT 22 = win reserverd 0
564 * BIT 23 = win reserverd 1
565 *
566 * BIT 24 = keep wwpn
567 * BIT 25 = temp wwpn
568 * BIT 26 = win reserverd 2
569 * BIT 27 = win reserverd 3
570 * BIT 28 = clear WBT in flash (win driver)
571 * BIT 29 = write WBT in flash (win driver)
572 * BIT 30 = load fw from flash (win driver)
573 * BIT 31 = enable alternate WWN (win driver)
574 */
575 uint8_t host_p[4];
576
577 uint8_t alternate_port_name[8];
578 uint8_t alternate_node_name[8];
579
580 uint8_t boot_port_name[8];
581 uint8_t boot_lun_number[2];
582 uint8_t reserved_8[2];
583
584 uint8_t alt1_boot_port_name[8];
585 uint8_t alt1_boot_lun_number[2];
586 uint8_t reserved_9[2];
587
588 uint8_t alt2_boot_port_name[8];
589 uint8_t alt2_boot_lun_number[2];
590 uint8_t reserved_10[2];
591
592 uint8_t alt3_boot_port_name[8];
593 uint8_t alt3_boot_lun_number[2];
594 uint8_t reserved_11[2];
595
596 /*
597 * BIT 0 = Selective Login
598 * BIT 1 = Alt-Boot Enable
599 * BIT 2 = Reserved
600 * BIT 3 = Enable Boot Order List
601 * BIT 4 = Reserved
602 * BIT 5 = Enable Selective LUN
603 * BIT 6 = Reserved
604 * BIT 7-31 =
605 */
606 uint8_t efi_parameters[4];
607
608 uint8_t reset_delay;
609 uint8_t reserved_12;
610 uint8_t reserved_13[2];
611
612 uint8_t boot_id_number[2];
613 uint8_t reserved_14[2];
614
615 uint8_t max_luns_per_target[2];
616 uint8_t reserved_15[2];
617
618 uint8_t port_down_retry_count[2];
619 uint8_t link_down_timeout[2];
620
621 /*
622 * FCode parameters word (offset 344)
623 *
624 * BIT 0 = Enable BIOS pathname
625 * BIT 1 = fcode qlc
626 * BIT 2 = fcode host
627 * BIT 3 = fcode sunid
628 * BIT 4-7 =
629 */
630 uint8_t fcode_p0;
631 uint8_t reserved_16[7];
632
633 /*
634 * Offset 352 (160h).
635 * uint8_t prev_drv_ver_major;
636 * uint8_t prev_drv_ver_submajob;
637 * uint8_t prev_drv_ver_minor;
638 * uint8_t prev_drv_ver_subminor;
639 * uint8_t prev_bios_ver_major[2];
640 * uint8_t prev_bios_ver_minor[2];
641 * uint8_t prev_efi_ver_major[2];
642 * uint8_t prev_efi_ver_minor[2];
643 * uint8_t prev_fw_ver_major[2];
644 * uint8_t prev_fw_ver_minor;
645 * uint8_t prev_fw_ver_subminor;
646 * uint8_t reserved[16];
647 */
648 uint8_t mac_address[6];
649 uint8_t clp_flag[2];
650 uint8_t reserved_18[24];
651
652 /* Offset 384 (180h). */
653 uint8_t def_port_name[8];
654 uint8_t def_node_name[8];
655 uint8_t clp_flag1[2];
656 uint8_t clp_flag2[2];
657
658 /* Offset 404 (194h). */
659 uint8_t default_firmware_options[2];
660
661 /* Offset 406 (196h). */
662 uint8_t enhanced_features[2];
663 uint8_t serdes_index[2];
664 uint8_t reserved_19[6];
665
666 /* Offset 416 (1A0h). */
667 uint8_t alt4_boot_port_name[8];
668 uint8_t alt4_boot_lun_number[2];
669 uint8_t reserved_20[2];
670
671 /* Offset 428 (1ACh). */
672 uint8_t alt5_boot_port_name[8];
673 uint8_t alt5_boot_lun_number[2];
674 uint8_t reserved_21[2];
675
676 /* Offset 440 (1B8h). */
677 uint8_t alt6_boot_port_name[8];
678 uint8_t alt6_boot_lun_number[2];
679 uint8_t reserved_22[2];
680
681 /* Offset 452 (1C4h). */
682 uint8_t alt7_boot_port_name[8];
683 uint8_t alt7_boot_lun_number[2];
684 uint8_t reserved_23[2];
685
686 /* Offset 464 (1D0h). */
687 uint8_t reserved_24[12];
688
689 /* Offset 476 (1DCh). */
690 uint8_t fw_table_offset[2];
691 uint8_t fw_table_sig[2];
692
693 /* Offset 480 (1E0h). */
694 int8_t model_name[4];
695 int8_t model_name1[12]; /* 24xx power_table[8]. */
696
697 /* Offset 496 (1F0h). */
698 uint8_t feature_mask_l[2];
699 uint8_t feature_mask_h[2];
700 uint8_t reserved_25[4];
701
702 /* Offset 504 (1F8h). */
703 uint8_t subsystem_vendor_id[2];
704 uint8_t subsystem_device_id[2];
705
706 uint8_t checksum[4];
707 } nvram_24xx_t;
708
709 /*
710 * Firmware Dump structure definition
711 */
712 #define QL_2200_FW_DUMP_SIZE 0x68000 /* bytes */
713 #define QL_2300_FW_DUMP_SIZE 0xE2000 /* bytes */
714 #define QL_6322_FW_DUMP_SIZE 0xE2000 /* bytes */
715 #define QL_24XX_FW_DUMP_SIZE 0x0330000 /* bytes */
716 #define QL_25XX_FW_DUMP_SIZE 0x0330000 /* bytes */
717
718 #define QL_24XX_VPD_SIZE 0x200 /* bytes */
719 #define QL_24XX_SFP_SIZE 0x200 /* bytes */
720
721 /*
722 * firmware dump struct for 2300 is a superset of firmware dump struct
723 * for 2200. Fields which are 2300 only or are enhanced for 2300 are
724 * marked below.
725 */
726 typedef struct ql_fw_dump {
727 uint16_t pbiu_reg[8];
728 uint16_t risc_host_reg[8]; /* 2300 only. */
729 uint16_t mailbox_reg[16]; /* 2200 only needs 8 */
730 uint16_t resp_dma_reg[32]; /* 2300 only. */
731 uint16_t dma_reg[48];
732 uint16_t risc_hdw_reg[16];
733 uint16_t risc_gp0_reg[16];
734 uint16_t risc_gp1_reg[16];
735 uint16_t risc_gp2_reg[16];
736 uint16_t risc_gp3_reg[16];
737 uint16_t risc_gp4_reg[16];
738 uint16_t risc_gp5_reg[16];
739 uint16_t risc_gp6_reg[16];
740 uint16_t risc_gp7_reg[16];
741 uint16_t frame_buf_hdw_reg[64]; /* 2200 has only 16 */
742 uint16_t fpm_b0_reg[64];
743 uint16_t fpm_b1_reg[64];
744 uint16_t risc_ram[0xf800]; /* 2200 needs only 0xf000 */
745 uint16_t stack_ram[0x800]; /* 2300 only */
746 uint16_t data_ram[0xf800]; /* 2300 only */
747 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
748 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
749 } ql_fw_dump_t;
750
751 typedef struct ql_24xx_fw_dump {
752 uint32_t hccr;
753 uint32_t host_reg[32];
754 uint16_t mailbox_reg[32];
755 uint32_t xseq_gp_reg[128];
756 uint32_t xseq_0_reg[16];
757 uint32_t xseq_1_reg[16];
758 uint32_t rseq_gp_reg[128];
759 uint32_t rseq_0_reg[16];
760 uint32_t rseq_1_reg[16];
761 uint32_t rseq_2_reg[16];
762 uint32_t cmd_dma_reg[16];
763 uint32_t req0_dma_reg[15];
764 uint32_t resp0_dma_reg[15];
765 uint32_t req1_dma_reg[15];
766 uint32_t xmt0_dma_reg[32];
767 uint32_t xmt1_dma_reg[32];
768 uint32_t xmt2_dma_reg[32];
769 uint32_t xmt3_dma_reg[32];
770 uint32_t xmt4_dma_reg[32];
771 uint32_t xmt_data_dma_reg[16];
772 uint32_t rcvt0_data_dma_reg[32];
773 uint32_t rcvt1_data_dma_reg[32];
774 uint32_t risc_gp_reg[128];
775 uint32_t shadow_reg[7];
776 uint32_t lmc_reg[112];
777 uint32_t fpm_hdw_reg[192];
778 uint32_t fb_hdw_reg[176];
779 uint32_t code_ram[0x2000];
780 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
781 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
782 uint32_t ext_trace_buf[FWEXTSIZE / 4];
783 uint32_t fce_trace_buf[FWFCESIZE / 4];
784 uint32_t ext_mem[1];
785 } ql_24xx_fw_dump_t;
786
787 typedef struct ql_25xx_fw_dump {
788 uint32_t r2h_status;
789 uint32_t hostrisc_reg[32];
790 uint32_t pcie_reg[4];
791 uint32_t host_reg[32];
792 uint16_t mailbox_reg[32];
793 uint32_t xseq_gp_reg[128];
794 uint32_t xseq_0_reg[48];
795 uint32_t xseq_1_reg[16];
796 uint32_t rseq_gp_reg[128];
797 uint32_t rseq_0_reg[32];
798 uint32_t rseq_1_reg[16];
799 uint32_t rseq_2_reg[16];
800 uint32_t aseq_gp_reg[128];
801 uint32_t aseq_0_reg[32];
802 uint32_t aseq_1_reg[16];
803 uint32_t aseq_2_reg[16];
804 uint32_t cmd_dma_reg[16];
805 uint32_t req0_dma_reg[15];
806 uint32_t resp0_dma_reg[15];
807 uint32_t req1_dma_reg[15];
808 uint32_t xmt0_dma_reg[32];
809 uint32_t xmt1_dma_reg[32];
810 uint32_t xmt2_dma_reg[32];
811 uint32_t xmt3_dma_reg[32];
812 uint32_t xmt4_dma_reg[32];
813 uint32_t xmt_data_dma_reg[16];
814 uint32_t rcvt0_data_dma_reg[32];
815 uint32_t rcvt1_data_dma_reg[32];
816 uint32_t risc_gp_reg[128];
817 uint32_t shadow_reg[11];
818 uint32_t risc_io;
819 uint32_t lmc_reg[128];
820 uint32_t fpm_hdw_reg[192];
821 uint32_t fb_hdw_reg[192];
822 uint32_t code_ram[0x2000];
823 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
824 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
825 uint32_t ext_trace_buf[FWEXTSIZE / 4];
826 uint32_t fce_trace_buf[FWFCESIZE / 4];
827 uint32_t ext_mem[1];
828 } ql_25xx_fw_dump_t;
829
830 typedef struct ql_81xx_fw_dump {
831 uint32_t r2h_status;
832 uint32_t hostrisc_reg[32];
833 uint32_t pcie_reg[4];
834 uint32_t host_reg[32];
835 uint16_t mailbox_reg[32];
836 uint32_t xseq_gp_reg[128];
837 uint32_t xseq_0_reg[48];
838 uint32_t xseq_1_reg[16];
839 uint32_t rseq_gp_reg[128];
840 uint32_t rseq_0_reg[32];
841 uint32_t rseq_1_reg[16];
842 uint32_t rseq_2_reg[16];
843 uint32_t aseq_gp_reg[128];
844 uint32_t aseq_0_reg[32];
845 uint32_t aseq_1_reg[16];
846 uint32_t aseq_2_reg[16];
847 uint32_t cmd_dma_reg[16];
848 uint32_t req0_dma_reg[15];
849 uint32_t resp0_dma_reg[15];
850 uint32_t req1_dma_reg[15];
851 uint32_t xmt0_dma_reg[32];
852 uint32_t xmt1_dma_reg[32];
853 uint32_t xmt2_dma_reg[32];
854 uint32_t xmt3_dma_reg[32];
855 uint32_t xmt4_dma_reg[32];
856 uint32_t xmt_data_dma_reg[16];
857 uint32_t rcvt0_data_dma_reg[32];
858 uint32_t rcvt1_data_dma_reg[32];
859 uint32_t risc_gp_reg[128];
860 uint32_t shadow_reg[11];
861 uint32_t risc_io;
862 uint32_t lmc_reg[128];
863 uint32_t fpm_hdw_reg[224];
864 uint32_t fb_hdw_reg[208];
865 uint32_t code_ram[0x2000];
866 uint32_t req_q[REQUEST_QUEUE_SIZE / 4];
867 uint32_t rsp_q[RESPONSE_QUEUE_SIZE / 4];
868 uint32_t ext_trace_buf[FWEXTSIZE / 4];
869 uint32_t fce_trace_buf[FWFCESIZE / 4];
870 uint32_t ext_mem[1];
871 } ql_81xx_fw_dump_t;
872
873 #ifdef _KERNEL
874
875 /*
876 * ql_lock_nvram() flags
877 */
878 #define LNF_NVRAM_DATA BIT_0 /* get nvram */
879 #define LNF_VPD_DATA BIT_1 /* get vpd data (24xx only) */
880
881 /*
882 * ISP product identification definitions in mailboxes after reset.
883 */
884 #define PROD_ID_1 0x4953
885 #define PROD_ID_2 0x0000
886 #define PROD_ID_2a 0x5020
887 #define PROD_ID_3 0x2020
888
889 /*
890 * NVRAM Command values.
891 */
892 #define NV_START_BIT BIT_2
893 #define NV_WRITE_OP (BIT_26+BIT_24)
894 #define NV_READ_OP (BIT_26+BIT_25)
895 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
896 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
897 #define NV_DELAY_COUNT 10
898
899 /*
900 * Deivce ID list definitions.
901 */
902 struct ql_dev_id {
903 uint8_t al_pa;
904 uint8_t area;
905 uint8_t domain;
906 uint8_t loop_id;
907 };
908
909 struct ql_ex_dev_id {
910 uint8_t al_pa;
911 uint8_t area;
912 uint8_t domain;
913 uint8_t reserved;
914 uint8_t loop_id_l;
915 uint8_t loop_id_h;
916 };
917
918 struct ql_24_dev_id {
919 uint8_t al_pa;
920 uint8_t area;
921 uint8_t domain;
922 uint8_t reserved;
923 uint8_t n_port_hdl_l;
924 uint8_t n_port_hdl_h;
925 uint8_t reserved_1[2];
926 };
927
928 typedef union ql_dev_id_list {
929 struct ql_dev_id d;
930 struct ql_ex_dev_id d_ex;
931 struct ql_24_dev_id d_24;
932 } ql_dev_id_list_t;
933
934 /* Define maximum number of device list entries.. */
935 #define DEVICE_LIST_ENTRIES MAX_24_FIBRE_DEVICES
936
937 /*
938 * Global Data in ql_init.c source file.
939 */
940
941 /*
942 * Global Function Prototypes in ql_init.c source file.
943 */
944 int ql_initialize_adapter(ql_adapter_state_t *);
945 int ql_pci_sbus_config(ql_adapter_state_t *);
946 int ql_nvram_config(ql_adapter_state_t *);
947 uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t);
948 void ql_nv_write(ql_adapter_state_t *, uint16_t);
949 void ql_nv_delay(void);
950 int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t);
951 void ql_release_nvram(ql_adapter_state_t *);
952 void ql_common_properties(ql_adapter_state_t *);
953 uint32_t ql_get_prop(ql_adapter_state_t *, char *);
954 int ql_load_isp_firmware(ql_adapter_state_t *);
955 int ql_start_firmware(ql_adapter_state_t *);
956 int ql_set_cache_line(ql_adapter_state_t *);
957 int ql_init_rings(ql_adapter_state_t *);
958 int ql_fw_ready(ql_adapter_state_t *, uint8_t);
959 void ql_dev_list(ql_adapter_state_t *, ql_dev_id_list_t *, uint32_t,
960 port_id_t *, uint16_t *);
961 void ql_reset_chip(ql_adapter_state_t *);
962 void ql_reset_24xx_chip(ql_adapter_state_t *);
963 int ql_abort_isp(ql_adapter_state_t *);
964 int ql_vport_control(ql_adapter_state_t *, uint8_t);
965 int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t);
966 int ql_vport_enable(ql_adapter_state_t *);
967 ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t);
968 void ql_vport_destroy(ql_adapter_state_t *);
969 #endif /* _KERNEL */
970
971 #ifdef __cplusplus
972 }
973 #endif
974
975 #endif /* _QL_INIT_H */