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NEX-5717 import QLogic 16G FC drivers
Reviewed by: Steve Peng <steve.peng@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
NEX-4957 Panic in qlc with QLE2460 in PCI passthrough mode on ESXi
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
Reviewed by: Gordon Ross <gordon.ross@nexenta.com>
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--- old/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_api.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_api.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 -/* Copyright 2010 QLogic Corporation */
22 +/* Copyright 2015 QLogic Corporation */
23 23
24 24 /*
25 - * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
25 + * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
26 26 */
27 27
28 28 #ifndef _QL_API_H
29 29 #define _QL_API_H
30 30
31 31 /*
32 32 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
33 33 *
34 34 * ***********************************************************************
35 35 * * **
36 36 * * NOTICE **
37 - * * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
37 + * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
38 38 * * ALL RIGHTS RESERVED **
39 39 * * **
40 40 * ***********************************************************************
41 41 *
42 42 */
43 43
44 44 #ifdef __cplusplus
45 45 extern "C" {
46 46 #endif
47 47
48 48 /* OS include files. */
49 49 #include <sys/scsi/scsi_types.h>
50 50 #include <sys/byteorder.h>
51 51 #include <sys/pci.h>
52 52 #include <sys/utsname.h>
53 53 #include <sys/file.h>
54 54 #include <sys/param.h>
55 +#include <sys/time.h>
56 +#include <sys/ddifm.h>
57 +#include <sys/sunddi.h>
58 +#include <sys/fm/protocol.h>
59 +#include <sys/fm/io/ddi.h>
55 60 #include <ql_open.h>
56 61
62 +#ifdef __x86
63 +#include <sys/x86_archext.h>
64 +#endif
65 +
57 66 #include <sys/fibre-channel/fc.h>
58 67 #include <sys/fibre-channel/impl/fc_fcaif.h>
59 68
60 69 #ifndef DDI_INTR_TYPE_FIXED
61 70 #define DDI_INTR_TYPE_FIXED 0x1
62 71 #endif
63 72 #ifndef DDI_INTR_TYPE_MSI
64 73 #define DDI_INTR_TYPE_MSI 0x2
65 74 #endif
66 75 #ifndef DDI_INTR_TYPE_MSIX
67 76 #define DDI_INTR_TYPE_MSIX 0x4
68 77 #endif
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69 78 #ifndef DDI_INTR_FLAG_BLOCK
70 79 #define DDI_INTR_FLAG_BLOCK 0x100
71 80 #endif
72 81 #ifndef DDI_INTR_ALLOC_NORMAL
73 82 #define DDI_INTR_ALLOC_NORMAL 0
74 83 #endif
75 84 #ifndef DDI_INTR_ALLOC_STRICT
76 85 #define DDI_INTR_ALLOC_STRICT 1
77 86 #endif
78 87
88 +#define PCI_PCIE_DEVICE_CONTROL 0x8 /* Device control reg offset */
89 +#define PCI_MSI_CONTROL 0x2 /* MSI Control reg offset */
90 +#define PCI_MSI_MSG_ADDR 0x4 /* MSI Msg Addr reg offset */
91 +#define PCI_MSI_MSG_UPPER_ADDR 0x8 /* MSI MSI Msg Upper Addr reg */
92 +/* offset */
93 +#define PCI_MSI_MSG_DATA 0xc /* MSI Msg Data reg offset */
94 +#define PCI_MSI_X_CONTROL 0x2 /* MSI-X Control reg offset */
95 +#define MSI_X_TABLE_SIZE_MASK 0x7ff /* MSI-X Table Size mask */
96 +
97 +#define PCIE_EXT_CAP_PTR 0x100
98 +#define PCIE_EXT_CAP_NEXT_SHIFT 20
99 +#define PCIE_EXT_CAP_ID_SRIOV 0x0010 /* SRIOV capabilities offset */
100 +#define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0xe
101 +#define PCIE_SRIOV_PAGE_SIZE_MULTIPLIER 4096
102 +
79 103 /*
80 104 * NPIV defines
81 105 */
82 106 #ifndef FC_NPIV_FDISC_FAILED
83 107 #define FC_NPIV_FDISC_FAILED 0x45
84 108 #endif
85 109 #ifndef FC_NPIV_FDISC_WWN_INUSE
86 110 #define FC_NPIV_FDISC_WWN_INUSE 0x46
87 111 #endif
88 112 #ifndef FC_NPIV_NOT_SUPPORTED
89 113 #define FC_NPIV_NOT_SUPPORTED 0x47
90 114 #endif
91 115 #ifndef FC_NPIV_WRONG_TOPOLOGY
92 116 #define FC_NPIV_WRONG_TOPOLOGY 0x48
93 117 #endif
94 118 #ifndef FC_NPIV_NPIV_BOUND
95 119 #define FC_NPIV_NPIV_BOUND 0x49
96 120 #endif
121 +#ifndef FC_HBA_PORTSPEED_32GBIT
122 +#define FC_HBA_PORTSPEED_32GBIT 64
123 +#endif
97 124
98 125 #pragma weak ddi_intr_get_supported_types
99 126 #pragma weak ddi_intr_get_nintrs
100 127 #pragma weak ddi_intr_alloc
101 128 #pragma weak ddi_intr_free
102 129 #pragma weak ddi_intr_get_pri
103 130 #pragma weak ddi_intr_add_handler
104 131 #pragma weak ddi_intr_dup_handler
105 132 #pragma weak ddi_intr_get_navail
106 133 #pragma weak ddi_intr_block_disable
107 134 #pragma weak ddi_intr_block_enable
108 135 #pragma weak ddi_intr_disable
109 136 #pragma weak ddi_intr_enable
110 137 #pragma weak ddi_intr_get_cap
111 138 #pragma weak ddi_intr_remove_handler
112 139 extern int ddi_intr_get_supported_types();
113 140 extern int ddi_intr_get_nintrs();
114 141 extern int ddi_intr_alloc();
115 142 extern int ddi_intr_free();
116 143 extern int ddi_intr_get_pri();
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117 144 extern int ddi_intr_add_handler();
118 145 extern int ddi_intr_dup_handler();
119 146 extern int ddi_intr_get_navail();
120 147 extern int ddi_intr_block_disable();
121 148 extern int ddi_intr_block_enable();
122 149 extern int ddi_intr_disable();
123 150 extern int ddi_intr_enable();
124 151 extern int ddi_intr_get_cap();
125 152 extern int ddi_intr_remove_handler();
126 153
127 -#ifndef QL_DRV_HARDENING
128 -#define ddi_devstate_t int
129 -#define DDI_DEVSTATE_UP 0
130 -#define ddi_get_devstate(a) DDI_DEVSTATE_UP
131 -#define ddi_dev_report_fault(a, b, c, d)
132 -#define ddi_check_dma_handle(a) DDI_SUCCESS
133 -#define ddi_check_acc_handle(a) DDI_SUCCESS
134 -#define QL_CLEAR_DMA_HANDLE(x)
135 -#else
136 154 #define QL_CLEAR_DMA_HANDLE(x) ((ddi_dma_impl_t *)x)->dmai_fault_notify = 0; \
137 - ((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \
138 - ((ddi_dma_impl_t *)x)->dmai_fault = 0
139 -#endif
155 + ((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \
156 + ((ddi_dma_impl_t *)x)->dmai_fault = 0
140 157
141 158 #ifndef FC_STATE_1GBIT_SPEED
142 159 #define FC_STATE_1GBIT_SPEED 0x0100 /* 1 Gbit/sec */
143 160 #endif
144 161 #ifndef FC_STATE_2GBIT_SPEED
145 162 #define FC_STATE_2GBIT_SPEED 0x0400 /* 2 Gbit/sec */
146 163 #endif
147 164 #ifndef FC_STATE_4GBIT_SPEED
148 165 #define FC_STATE_4GBIT_SPEED 0x0500 /* 4 Gbit/sec */
149 166 #endif
150 167 #ifndef FC_STATE_8GBIT_SPEED
151 168 #define FC_STATE_8GBIT_SPEED 0x0700 /* 8 Gbit/sec */
152 169 #endif
153 170 #ifndef FC_STATE_10GBIT_SPEED
154 171 #define FC_STATE_10GBIT_SPEED 0x0600 /* 10 Gbit/sec */
155 172 #endif
173 +#ifndef FC_STATE_16GBIT_SPEED
174 +#define FC_STATE_16GBIT_SPEED 0x0800 /* 16 Gbit/sec */
175 +#endif
176 +#ifndef FC_STATE_32GBIT_SPEED
177 +#define FC_STATE_32GBIT_SPEED 0x1000 /* 32 Gbit/sec */
178 +#endif
156 179
157 180 /*
158 181 * Data bit definitions.
159 182 */
160 -#define BIT_0 0x1
161 -#define BIT_1 0x2
162 -#define BIT_2 0x4
163 -#define BIT_3 0x8
164 -#define BIT_4 0x10
165 -#define BIT_5 0x20
166 -#define BIT_6 0x40
167 -#define BIT_7 0x80
168 -#define BIT_8 0x100
169 -#define BIT_9 0x200
170 -#define BIT_10 0x400
171 -#define BIT_11 0x800
172 -#define BIT_12 0x1000
173 -#define BIT_13 0x2000
174 -#define BIT_14 0x4000
175 -#define BIT_15 0x8000
176 -#define BIT_16 0x10000
177 -#define BIT_17 0x20000
178 -#define BIT_18 0x40000
179 -#define BIT_19 0x80000
180 -#define BIT_20 0x100000
181 -#define BIT_21 0x200000
182 -#define BIT_22 0x400000
183 -#define BIT_23 0x800000
184 -#define BIT_24 0x1000000
185 -#define BIT_25 0x2000000
186 -#define BIT_26 0x4000000
187 -#define BIT_27 0x8000000
188 -#define BIT_28 0x10000000
189 -#define BIT_29 0x20000000
190 -#define BIT_30 0x40000000
191 -#define BIT_31 0x80000000
183 +#define BIT_0 0x1
184 +#define BIT_1 0x2
185 +#define BIT_2 0x4
186 +#define BIT_3 0x8
187 +#define BIT_4 0x10
188 +#define BIT_5 0x20
189 +#define BIT_6 0x40
190 +#define BIT_7 0x80
191 +#define BIT_8 0x100
192 +#define BIT_9 0x200
193 +#define BIT_10 0x400
194 +#define BIT_11 0x800
195 +#define BIT_12 0x1000
196 +#define BIT_13 0x2000
197 +#define BIT_14 0x4000
198 +#define BIT_15 0x8000
199 +#define BIT_16 0x10000
200 +#define BIT_17 0x20000
201 +#define BIT_18 0x40000
202 +#define BIT_19 0x80000
203 +#define BIT_20 0x100000
204 +#define BIT_21 0x200000
205 +#define BIT_22 0x400000
206 +#define BIT_23 0x800000
207 +#define BIT_24 0x1000000
208 +#define BIT_25 0x2000000
209 +#define BIT_26 0x4000000
210 +#define BIT_27 0x8000000
211 +#define BIT_28 0x10000000
212 +#define BIT_29 0x20000000
213 +#define BIT_30 0x40000000
214 +#define BIT_31 0x80000000
215 +#define BIT_32 0x100000000
216 +#define BIT_33 0x200000000
217 +#define BIT_34 0x400000000
218 +#define BIT_35 0x800000000
219 +#define BIT_36 0x1000000000
220 +#define BIT_37 0x2000000000
221 +#define BIT_38 0x4000000000
222 +#define BIT_39 0x8000000000
223 +#define BIT_40 0x10000000000
224 +#define BIT_41 0x20000000000
225 +#define BIT_42 0x40000000000
226 +#define BIT_43 0x80000000000
227 +#define BIT_44 0x100000000000
228 +#define BIT_45 0x200000000000
229 +#define BIT_46 0x400000000000
230 +#define BIT_47 0x800000000000
231 +#define BIT_48 0x1000000000000
232 +#define BIT_49 0x2000000000000
233 +#define BIT_50 0x4000000000000
234 +#define BIT_51 0x8000000000000
235 +#define BIT_52 0x10000000000000
236 +#define BIT_53 0x20000000000000
237 +#define BIT_54 0x40000000000000
238 +#define BIT_55 0x80000000000000
239 +#define BIT_56 0x100000000000000
240 +#define BIT_57 0x200000000000000
241 +#define BIT_58 0x400000000000000
242 +#define BIT_59 0x800000000000000
243 +#define BIT_60 0x1000000000000000
244 +#define BIT_61 0x2000000000000000
245 +#define BIT_62 0x4000000000000000
246 +#define BIT_63 0x8000000000000000
192 247
193 248 /*
194 249 * Local Macro Definitions.
195 250 */
196 251 #ifndef TRUE
197 252 #define TRUE B_TRUE
198 253 #endif
199 254
200 255 #ifndef FALSE
201 256 #define FALSE B_FALSE
202 257 #endif
203 258
204 259 /*
205 260 * I/O register
206 261 */
207 262 #define RD_REG_BYTE(ha, addr) \
208 263 (uint8_t)ddi_get8(ha->dev_handle, (uint8_t *)(addr))
209 264 #define RD_REG_WORD(ha, addr) \
210 265 (uint16_t)ddi_get16(ha->dev_handle, (uint16_t *)(addr))
211 266 #define RD_REG_DWORD(ha, addr) \
212 267 (uint32_t)ddi_get32(ha->dev_handle, (uint32_t *)(addr))
213 268 #define RD_REG_DDWORD(ha, addr) \
214 269 (uint64_t)ddi_get64(ha->dev_handle, (uint64_t *)(addr))
215 270
216 271 #define WRT_REG_BYTE(ha, addr, data) \
217 272 ddi_put8(ha->dev_handle, (uint8_t *)(addr), (uint8_t)(data))
218 273 #define WRT_REG_WORD(ha, addr, data) \
219 274 ddi_put16(ha->dev_handle, (uint16_t *)(addr), (uint16_t)(data))
220 275 #define WRT_REG_DWORD(ha, addr, data) \
221 276 ddi_put32(ha->dev_handle, (uint32_t *)(addr), (uint32_t)(data))
222 277 #define WRT_REG_DDWORD(ha, addr, data) \
223 278 ddi_put64(ha->dev_handle, (uint64_t *)(addr), (uint64_t)(data))
224 279
225 280 #define RD8_IO_REG(ha, regname) \
226 281 RD_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname))
227 282 #define RD16_IO_REG(ha, regname) \
228 283 RD_REG_WORD(ha, (ha->iobase + ha->reg_off->regname))
229 284 #define RD32_IO_REG(ha, regname) \
230 285 RD_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname))
231 286
232 287 #define WRT8_IO_REG(ha, regname, data) \
233 288 WRT_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname), (data))
234 289 #define WRT16_IO_REG(ha, regname, data) \
235 290 WRT_REG_WORD(ha, (ha->iobase + ha->reg_off->regname), (data))
236 291 #define WRT32_IO_REG(ha, regname, data) \
237 292 WRT_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname), (data))
238 293
239 294 #define RD_IOREG_BYTE(ha, addr) \
240 295 (uint8_t)ddi_get8(ha->iomap_dev_handle, (uint8_t *)(addr))
241 296 #define RD_IOREG_WORD(ha, addr) \
242 297 (uint16_t)ddi_get16(ha->iomap_dev_handle, (uint16_t *)(addr))
243 298 #define RD_IOREG_DWORD(ha, addr) \
244 299 (uint32_t)ddi_get32(ha->iomap_dev_handle, (uint32_t *)(addr))
245 300
246 301 #define WRT_IOREG_BYTE(ha, addr, data) \
247 302 ddi_put8(ha->iomap_dev_handle, (uint8_t *)addr, (uint8_t)(data))
248 303 #define WRT_IOREG_WORD(ha, addr, data) \
249 304 ddi_put16(ha->iomap_dev_handle, (uint16_t *)addr, (uint16_t)(data))
250 305 #define WRT_IOREG_DWORD(ha, addr, data) \
251 306 ddi_put32(ha->iomap_dev_handle, (uint32_t *)addr, (uint32_t)(data))
252 307
253 308 #define RD8_IOMAP_REG(ha, regname) \
254 309 RD_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname))
255 310 #define RD16_IOMAP_REG(ha, regname) \
256 311 RD_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname))
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257 312 #define RD32_IOMAP_REG(ha, regname) \
258 313 RD_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname))
259 314
260 315 #define WRT8_IOMAP_REG(ha, regname, data) \
261 316 WRT_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname), (data))
262 317 #define WRT16_IOMAP_REG(ha, regname, data) \
263 318 WRT_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname), (data))
264 319 #define WRT32_IOMAP_REG(ha, regname, data) \
265 320 WRT_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname), (data))
266 321
322 +#define RD8_MBAR_REG(ha, ofst) \
323 + (uint8_t)ddi_get8(ha->mbar_dev_handle, \
324 + (uint8_t *)(ha->mbar + (ofst)))
325 +#define RD16_MBAR_REG(ha, ofst) \
326 + (uint16_t)ddi_get16(ha->mbar_dev_handle, \
327 + (uint16_t *)(ha->mbar + (ofst)))
328 +#define RD32_MBAR_REG(ha, ofst) \
329 + (uint32_t)ddi_get32(ha->mbar_dev_handle, \
330 + (uint32_t *)(ha->mbar + (ofst)))
331 +#define RD64_MBAR_REG(ha, ofst) \
332 + (uint64_t)ddi_get64(ha->mbar_dev_handle, \
333 + (uint64_t *)(ha->mbar + (ofst)))
334 +
335 +#define WR8_MBAR_REG(ha, ofst, data) \
336 + ddi_put8(ha->mbar_dev_handle, \
337 + (uint8_t *)(ha->mbar + (ofst)), \
338 + (uint8_t)(data))
339 +#define WR16_MBAR_REG(ha, ofst, data) \
340 + ddi_put16(ha->mbar_dev_handle, \
341 + (uint16_t *)(ha->mbar + (ofst)), \
342 + (uint16_t)(data))
343 +#define WR32_MBAR_REG(ha, ofst, data) \
344 + ddi_put32(ha->mbar_dev_handle, \
345 + (uint32_t *)(ha->mbar + (ofst)), \
346 + (uint32_t)(data))
347 +#define WR64_MBAR_REG(ha, ofst, data) \
348 + ddi_put64(ha->mbar_dev_handle, \
349 + (uint64_t *)(ha->mbar + (ofst)), \
350 + (uint64_t)(data))
351 +
267 352 /*
268 353 * FCA definitions
269 354 */
270 355 #define MAX_LUNS 16384
271 356 #define QL_FCA_BRAND 0x0fca2200
272 357
273 358 /* Following to be removed when defined by OS. */
274 359 /* ************************************************************************ */
275 360 #define LA_ELS_FARP_REQ 0x54
276 361 #define LA_ELS_FARP_REPLY 0x55
277 362 #define LA_ELS_LPC 0x71
278 363 #define LA_ELS_LSTS 0x72
279 364
280 365 typedef struct {
281 366 ls_code_t ls_code;
282 367 uint8_t rsvd[3];
283 368 uint8_t port_control;
284 369 uint8_t lpb[16];
285 370 uint8_t lpe[16];
286 371 } ql_lpc_t;
287 372
288 373 typedef struct {
289 374 ls_code_t ls_code;
290 375 } ql_acc_rjt_t;
291 376
292 377 typedef fc_linit_resp_t ql_lpc_resp_t;
293 378 typedef fc_scr_resp_t ql_rscn_resp_t;
294 379
295 380 typedef struct {
296 381 uint16_t class_valid_svc_opt;
297 382 uint16_t initiator_ctl;
298 383 uint16_t recipient_ctl;
299 384 uint16_t rcv_data_size;
300 385 uint16_t conc_sequences;
301 386 uint16_t n_port_end_to_end_credit;
302 387 uint16_t open_sequences_per_exch;
303 388 uint16_t unused;
304 389 } class_svc_param_t;
305 390
306 391 typedef struct {
307 392 uint8_t type;
308 393 uint8_t rsvd;
309 394 uint16_t process_assoc_flags;
310 395 uint32_t originator_process;
311 396 uint32_t responder_process;
312 397 uint32_t process_flags;
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313 398 } prli_svc_param_t;
314 399 /* *********************************************************************** */
315 400
316 401 /*
317 402 * Fibre Channel device definitions.
318 403 */
319 404 #define MAX_22_FIBRE_DEVICES 256
320 405 #define MAX_24_FIBRE_DEVICES 2048
321 406 #define MAX_24_VIRTUAL_PORTS 127
322 407 #define MAX_25_VIRTUAL_PORTS 254
408 +#define MAX_27_VIRTUAL_PORTS 252
409 +#define MAX_8021_VIRTUAL_PORTS 63
410 +#define MAX_81XX_VIRTUAL_PORTS 254
411 +#define MAX_83_VIRTUAL_PORTS 254
323 412
324 413 #define LAST_LOCAL_LOOP_ID 0x7d
325 414 #define FL_PORT_LOOP_ID 0x7e /* FFFFFE Fabric F_Port */
326 415 #define SWITCH_FABRIC_CONTROLLER_LOOP_ID 0x7f /* FFFFFD Fabric Controller */
327 416 #define SIMPLE_NAME_SERVER_LOOP_ID 0x80 /* FFFFFC Directory Server */
328 417 #define SNS_FIRST_LOOP_ID 0x81
329 418 #define SNS_LAST_LOOP_ID 0xfe
330 419 #define IP_BROADCAST_LOOP_ID 0xff /* FFFFFF Broadcast */
331 420 #define BROADCAST_ADDR 0xffffff /* FFFFFF Broadcast */
332 421
333 422 /*
334 423 * Fibre Channel 24xx device definitions.
335 424 */
336 425 #define LAST_N_PORT_HDL 0x7ef
337 426 #define SNS_24XX_HDL 0x7FC /* SNS FFFFFCh */
338 427 #define SFC_24XX_HDL 0x7FD /* fabric controller FFFFFDh */
339 428 #define FL_PORT_24XX_HDL 0x7FE /* F_Port FFFFFEh */
340 429 #define BROADCAST_24XX_HDL 0x7FF /* IP broadcast FFFFFFh */
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341 430
342 431 /* Loop ID's used as flags, must be higher than any valid Loop ID */
343 432 #define PORT_NO_LOOP_ID 0x8000 /* Device does not have loop ID. */
344 433 #define PORT_LOST_ID 0x4000 /* Device has been lost. */
345 434
346 435 /* Fibre Channel Topoploy. */
347 436 #define QL_N_PORT BIT_0
348 437 #define QL_NL_PORT BIT_1
349 438 #define QL_F_PORT BIT_2
350 439 #define QL_FL_PORT BIT_3
351 -#define QL_SNS_CONNECTION BIT_4
352 440 #define QL_LOOP_CONNECTION (QL_NL_PORT | QL_FL_PORT)
353 441 #define QL_P2P_CONNECTION (QL_F_PORT | QL_N_PORT)
442 +#define QL_FABRIC_CONNECTION (QL_F_PORT | QL_FL_PORT)
354 443
355 444 /* Timeout timer counts in seconds (must greater than 1 second). */
356 445 #define WATCHDOG_TIME 5 /* 0 - 255 */
357 446 #define PORT_RETRY_TIME 2 /* 0 - 255 */
358 447 #define LOOP_DOWN_TIMER_OFF 0
359 448 #define LOOP_DOWN_TIMER_START 240 /* 0 - 255 */
360 449 #define LOOP_DOWN_TIMER_END 1
361 450 #define LOOP_DOWN_RESET (LOOP_DOWN_TIMER_START - 45) /* 0 - 255 */
362 451 #define R_A_TOV_DEFAULT 20 /* 0 - 65535 */
363 452 #define IDLE_CHECK_TIMER 300 /* 0 - 65535 */
364 453 #define MAX_DEVICE_LOST_RETRY 16 /* 0 - 255 */
365 454 #define TIMEOUT_THRESHOLD 16 /* 0 - 255 */
366 455
367 456 /* Maximum outstanding commands in ISP queues (1-4095) */
368 -#define MAX_OUTSTANDING_COMMANDS 0x400
369 -#define OSC_INDEX_MASK 0xfff
370 -#define OSC_INDEX_SHIFT 12
457 +#define OSC_INDEX_MASK 0xfff
458 +#define OSC_INDEX_SHIFT 12
371 459
372 460 /* Maximum unsolicited buffers (1-65535) */
373 461 #define QL_UB_LIMIT 256
374 462
375 463 /* ISP request, response and receive buffer entry counts */
376 464 #define REQUEST_ENTRY_CNT 512 /* Request entries (205-65535) */
377 465 #define RESPONSE_ENTRY_CNT 256 /* Response entries (1-65535) */
378 466 #define RCVBUF_CONTAINER_CNT 64 /* Rcv buffer containers (8-1024) */
379 467
380 468 /*
381 469 * ISP request, response, mailbox and receive buffer queue sizes
382 470 */
471 +#define SHADOW_ENTRY_SIZE 4
383 472 #define REQUEST_ENTRY_SIZE 64
384 473 #define REQUEST_QUEUE_SIZE (REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT)
385 474
386 475 #define RESPONSE_ENTRY_SIZE 64
387 476 #define RESPONSE_QUEUE_SIZE (RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT)
388 477
389 -#define MAILBOX_BUFFER_SIZE 0x4000
390 -
391 478 #define RCVBUF_CONTAINER_SIZE 12
392 479 #define RCVBUF_QUEUE_SIZE (RCVBUF_CONTAINER_SIZE * RCVBUF_CONTAINER_CNT)
393 480
394 481 /*
395 - * ISP DMA buffer definitions
396 - */
397 -#define REQUEST_Q_BUFFER_OFFSET 0
398 -#define RESPONSE_Q_BUFFER_OFFSET (REQUEST_Q_BUFFER_OFFSET + REQUEST_QUEUE_SIZE)
399 -#define RCVBUF_Q_BUFFER_OFFSET (RESPONSE_Q_BUFFER_OFFSET + RESPONSE_QUEUE_SIZE)
400 -
401 -/*
402 482 * DMA attributes definitions.
403 483 */
404 484 #define QL_DMA_LOW_ADDRESS (uint64_t)0
405 485 #define QL_DMA_HIGH_64BIT_ADDRESS (uint64_t)0xffffffffffffffff
406 486 #define QL_DMA_HIGH_32BIT_ADDRESS (uint64_t)0xffffffff
407 487 #define QL_DMA_XFER_COUNTER (uint64_t)0xffffffff
408 488 #define QL_DMA_ADDRESS_ALIGNMENT (uint64_t)8
409 489 #define QL_DMA_ALIGN_8_BYTE_BOUNDARY (uint64_t)BIT_3
410 490 #define QL_DMA_RING_ADDRESS_ALIGNMENT (uint64_t)64
411 491 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6
412 492 #define QL_DMA_BURSTSIZES 0xff
413 493 #define QL_DMA_MIN_XFER_SIZE 1
414 494 #define QL_DMA_MAX_XFER_SIZE (uint64_t)0xffffffff
415 495 #define QL_DMA_SEGMENT_BOUNDARY (uint64_t)0xffffffff
416 496
417 497 #ifdef __sparc
418 498 #define QL_DMA_SG_LIST_LENGTH 1
419 499 #define QL_FCSM_CMD_SGLLEN 1
420 500 #define QL_FCSM_RSP_SGLLEN 1
421 501 #define QL_FCIP_CMD_SGLLEN 1
422 502 #define QL_FCIP_RSP_SGLLEN 1
423 503 #define QL_FCP_CMD_SGLLEN 1
424 504 #define QL_FCP_RSP_SGLLEN 1
425 505 #else
426 506 #define QL_DMA_SG_LIST_LENGTH 1024
427 507 #define QL_FCSM_CMD_SGLLEN 1
428 508 #define QL_FCSM_RSP_SGLLEN 6
429 509 /*
430 510 * QL_FCIP_CMD_SGLLEN needs to be increased as we changed the max fcip packet
431 511 * size to about 64K. With this, we need to increase the maximum number of
432 512 * scatter-gather elements allowable from the existing 7. We want it to be more
433 513 * like 17 (max fragments for an fcip packet that is unaligned). (64K / 4K) + 1
434 514 * or whatever. Otherwise the DMA breakup routines will give bad results.
435 515 */
436 516 #define QL_FCIP_CMD_SGLLEN 17
437 517 #define QL_FCIP_RSP_SGLLEN 1
438 518 #define QL_FCP_CMD_SGLLEN 1
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439 519 #define QL_FCP_RSP_SGLLEN 1
440 520 #endif
441 521
442 522 #ifndef DDI_DMA_RELAXED_ORDERING
443 523 #define DDI_DMA_RELAXED_ORDERING 0x400
444 524 #endif
445 525
446 526 #define QL_DMA_GRANULARITY 1
447 527 #define QL_DMA_XFER_FLAGS 0
448 528
449 -typedef union {
529 +typedef union {
450 530 uint64_t size64; /* 1 X 64 bit number */
451 531 uint32_t size32[2]; /* 2 x 32 bit number */
452 532 uint16_t size16[4]; /* 4 x 16 bit number */
453 533 uint8_t size8[8]; /* 8 x 8 bit number */
454 534 } conv_num_t;
455 535
456 536 /*
457 537 * Device register offsets.
458 538 */
459 539 #define MAX_MBOX_COUNT 32
460 540 typedef struct {
461 541 uint16_t flash_address; /* Flash BIOS address */
462 542 uint16_t flash_data; /* Flash BIOS data */
463 543 uint16_t ctrl_status; /* Control/Status */
464 544 uint16_t ictrl; /* Interrupt control */
465 545 uint16_t istatus; /* Interrupt status */
466 546 uint16_t semaphore; /* Semaphore */
467 547 uint16_t nvram; /* NVRAM register. */
468 548 uint16_t req_in; /* for 2200 MBX 4 Write */
469 549 uint16_t req_out; /* for 2200 MBX 4 read */
470 550 uint16_t resp_in; /* for 2200 MBX 5 Read */
471 551 uint16_t resp_out; /* for 2200 MBX 5 Write */
472 552 uint16_t risc2host;
473 553 uint16_t mbox_cnt; /* Number of mailboxes */
474 554 uint16_t mailbox_in[MAX_MBOX_COUNT]; /* Mailbox registers */
475 555 uint16_t mailbox_out[MAX_MBOX_COUNT]; /* Mailbox registers */
476 556 uint16_t fpm_diag_config;
477 557 uint16_t pcr; /* Processor Control Register. */
478 558 uint16_t mctr; /* Memory Configuration and Timing. */
479 559 uint16_t fb_cmd;
480 560 uint16_t hccr; /* Host command & control register. */
481 561 uint16_t gpiod; /* GPIO Data register. */
482 562 uint16_t gpioe; /* GPIO Enable register. */
483 563 uint16_t host_to_host_sema; /* 2312 resource lock register */
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484 564 uint16_t pri_req_in; /* 2400 */
485 565 uint16_t pri_req_out; /* 2400 */
486 566 uint16_t atio_req_in; /* 2400 */
487 567 uint16_t atio_req_out; /* 2400 */
488 568 uint16_t io_base_addr; /* 2400 */
489 569 uint16_t nx_host_int; /* NetXen */
490 570 uint16_t nx_risc_int; /* NetXen */
491 571 } reg_off_t;
492 572
493 573 /*
574 + * Multi-Queue, Mem BAR 2 definition.
575 + */
576 +#define MBAR2_REQ_IN 0x0
577 +#define MBAR2_REQ_OUT 0x4
578 +#define MBAR2_RESP_IN 0x8
579 +#define MBAR2_RESP_OUT 0xc
580 +#define MBAR2_MULTI_Q_MAX 256
581 +#define MBAR2_REG_OFFSET 4096
582 +
583 +/*
494 584 * Mbox-8 read maximum debounce count.
495 585 * Reading Mbox-8 could be debouncing, before getting stable value.
496 586 * This is the recommended driver fix from Qlogic along with firmware fix.
497 587 * During testing, maximum count did not cross 3.
498 588 */
499 589 #define QL_MAX_DEBOUNCE 10
500 590
501 591 /*
502 592 * Control Status register definitions
503 593 */
504 594 #define ISP_FUNC_NUM_MASK (BIT_15 | BIT_14)
505 595 #define ISP_FLASH_64K_BANK BIT_3 /* Flash BIOS 64K Bank Select */
506 596 #define ISP_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
507 597 #define ISP_RESET BIT_0 /* ISP soft reset */
508 598
509 599 /*
510 600 * Control Status 24xx register definitions
511 601 */
512 602 #define FLASH_NVRAM_ACCESS_ERROR BIT_18
513 603 #define DMA_ACTIVE BIT_17
514 604 #define DMA_SHUTDOWN BIT_16
515 605 #define FUNCTION_NUMBER BIT_15
516 606
517 607 #define MWB_4096_BYTES (BIT_5 | BIT_4)
518 608 #define MWB_2048_BYTES BIT_5
519 609 #define MWB_1024_BYTES BIT_4
520 610 #define MWB_512_BYTES 0
521 611
522 612 /*
523 613 * Interrupt Control register definitions
524 614 */
525 615 #define ISP_EN_INT BIT_15 /* ISP enable interrupts. */
526 616 #define ISP_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
527 617
528 618 /*
529 619 * Interrupt Status register definitions
530 620 */
531 621 #define RISC_INT BIT_3 /* RISC interrupt */
532 622
533 623 /*
534 624 * NetXen Host/Risc Interrupt register definitions
535 625 */
536 626 #define NX_MBX_CMD BIT_0 /* Mailbox command present */
537 627 #define NX_RISC_INT BIT_0 /* RISC interrupt present */
538 628
539 629 /*
540 630 * NVRAM register definitions.
541 631 */
542 632 #define NV_DESELECT 0
543 633 #define NV_CLOCK BIT_0
544 634 #define NV_SELECT BIT_1
545 635 #define NV_DATA_OUT BIT_2
546 636 #define NV_DATA_IN BIT_3
547 637 #define NV_PR_ENABLE BIT_13 /* protection register enable */
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548 638 #define NV_WR_ENABLE BIT_14 /* write enable */
549 639 #define NV_BUSY BIT_15
550 640
551 641 /*
552 642 * Flash/NVRAM 24xx definitions
553 643 */
554 644 #define FLASH_DATA_FLAG BIT_31
555 645 #define FLASH_CONF_ADDR 0x7FFD0000
556 646 #define FLASH_24_25_DATA_ADDR 0x7FF00000
557 647 #define FLASH_8100_DATA_ADDR 0x7F800000
648 +#define FLASH_8300_DATA_ADDR 0x7F800000
649 +#define FLASH_2700_DATA_ADDR 0x7F800000
558 650 #define FLASH_ADDR_MASK 0x7FFF0000
559 651
560 652 #define NVRAM_CONF_ADDR 0x7FFF0000
561 653 #define NVRAM_DATA_ADDR 0x7FFE0000
562 654
563 655 #define NVRAM_2200_FUNC0_ADDR 0x0
564 656 #define NVRAM_2300_FUNC0_ADDR 0x0
565 657 #define NVRAM_2300_FUNC1_ADDR 0x80
566 658 #define NVRAM_2400_FUNC0_ADDR 0x80
567 659 #define NVRAM_2400_FUNC1_ADDR 0x180
568 660 #define NVRAM_2500_FUNC0_ADDR 0x48080
569 661 #define NVRAM_2500_FUNC1_ADDR 0x48180
570 662 #define NVRAM_8100_FUNC0_ADDR 0xD0080
571 663 #define NVRAM_8100_FUNC1_ADDR 0xD0180
572 664 #define NVRAM_8021_FUNC0_ADDR 0xF0080
573 665 #define NVRAM_8021_FUNC1_ADDR 0xF0180
666 +#define NVRAM_8300_FC_FUNC0_ADDR 0x270080
667 +#define NVRAM_8300_FC_FUNC1_ADDR 0x270180
668 +#define NVRAM_8300_FCOE_FUNC0_ADDR 0x274080
669 +#define NVRAM_8300_FCOE_FUNC1_ADDR 0x274180
670 +#define NVRAM_2700_FUNC0_ADDR 0x270080
671 +#define NVRAM_2700_FUNC1_ADDR 0x270180
672 +#define NVRAM_2700_FUNC2_ADDR 0x270280
673 +#define NVRAM_2700_FUNC3_ADDR 0x270380
574 674
575 675 #define VPD_2400_FUNC0_ADDR 0
576 676 #define VPD_2400_FUNC1_ADDR 0x100
577 677 #define VPD_2500_FUNC0_ADDR 0x48000
578 678 #define VPD_2500_FUNC1_ADDR 0x48100
579 679 #define VPD_8100_FUNC0_ADDR 0xD0000
580 680 #define VPD_8100_FUNC1_ADDR 0xD0400
581 681 #define VPD_8021_FUNC0_ADDR 0xFA300
582 682 #define VPD_8021_FUNC1_ADDR 0xFA300
683 +#define VPD_8300_FC_FUNC0_ADDR 0x270000
684 +#define VPD_8300_FC_FUNC1_ADDR 0x270100
685 +#define VPD_8300_FCOE_FUNC0_ADDR 0xFA300
686 +#define VPD_8300_FCOE_FUNC1_ADDR 0xFA300
687 +#define VPD_2700_FUNC0_ADDR 0x270000
688 +#define VPD_2700_FUNC1_ADDR 0x270100
689 +#define VPD_2700_FUNC2_ADDR 0x270200
690 +#define VPD_2700_FUNC3_ADDR 0x270300
583 691 #define VPD_SIZE 0x80
584 692
585 693 #define FLASH_2200_FIRMWARE_ADDR 0x20000
586 694 #define FLASH_2300_FIRMWARE_ADDR 0x20000
587 695 #define FLASH_2400_FIRMWARE_ADDR 0x20000
588 696 #define FLASH_2500_FIRMWARE_ADDR 0x20000
589 697 #define FLASH_8100_FIRMWARE_ADDR 0xA0000
590 698 #define FLASH_8021_FIRMWARE_ADDR 0x40000
591 699 #define FLASH_8021_FIRMWARE_SIZE 0x80000
700 +#define FLASH_8300_FC_FIRMWARE_ADDR 0x240000
701 +#define FLASH_8300_FCOE_FIRMWARE_ADDR 0x220000
702 +#define FLASH_8300_FIRMWARE_SIZE 0x20000
703 +#define FLASH_2700_FIRMWARE_ADDR 0x240000
704 +#define FLASH_2700_FIRMWARE_SIZE 0x20000
705 +
592 706 #define FLASH_8021_BOOTLOADER_ADDR 0x4000
593 707 #define FLASH_8021_BOOTLOADER_SIZE 0x8000
708 +#define FLASH_8300_BOOTLOADER_ADDR 0x4000
709 +#define FLASH_8300_BOOTLOADER_SIZE 0x8000
594 710
711 +#define FLASH_2200_BOOT_CODE_ADDR 0
712 +#define FLASH_2300_BOOT_CODE_ADDR 0
713 +#define FLASH_2400_BOOT_CODE_ADDR 0
714 +#define FLASH_2500_BOOT_CODE_ADDR 0
715 +#define FLASH_2700_BOOT_CODE_ADDR 0x200000
716 +#define FLASH_8100_BOOT_CODE_ADDR 0x80000
717 +#define FLASH_8021_BOOT_CODE_ADDR 0x20000
718 +#define FLASH_8300_BOOT_CODE_ADDR 0x200000
719 +
720 +#define BEACON_8300_FC_FUNC0_ADDR 0x00201320
721 +#define BEACON_8300_FC_FUNC1_ADDR 0x00201328
722 +#define BEACON_8300_FCOE_FUNC0_ADDR 0x00201324
723 +#define BEACON_8300_FCOE_FUNC1_ADDR 0x0020132c
724 +#define BEACON_2700_FUNC0_ADDR 0x00201320
725 +#define BEACON_2700_FUNC1_ADDR 0x00201328
726 +#define BEACON_2700_FUNC2_ADDR 0x00201330
727 +#define BEACON_2700_FUNC3_ADDR 0x00201338
728 +
595 729 #define FLASH_2400_ERRLOG_START_ADDR_0 0
596 730 #define FLASH_2400_ERRLOG_START_ADDR_1 0
597 731 #define FLASH_2500_ERRLOG_START_ADDR_0 0x54000
598 732 #define FLASH_2500_ERRLOG_START_ADDR_1 0x54400
599 733 #define FLASH_8100_ERRLOG_START_ADDR_0 0xDC000
600 734 #define FLASH_8100_ERRLOG_START_ADDR_1 0xDC400
735 +#define FLASH_8300_ERRLOG_START_ADDR_0 0x280000
736 +#define FLASH_8300_ERRLOG_START_ADDR_1 0x280400
601 737 #define FLASH_ERRLOG_SIZE 0x200
602 738 #define FLASH_ERRLOG_ENTRY_SIZE 4
603 739
604 740 #define FLASH_2400_DESCRIPTOR_TABLE 0
605 741 #define FLASH_2500_DESCRIPTOR_TABLE 0x50000
606 742 #define FLASH_8100_DESCRIPTOR_TABLE 0xD8000
607 743 #define FLASH_8021_DESCRIPTOR_TABLE 0
744 +#define FLASH_8300_DESCRIPTOR_TABLE 0xFC000
745 +#define FLASH_2700_DESCRIPTOR_TABLE 0xFC000
608 746
609 747 #define FLASH_2400_LAYOUT_TABLE 0x11400
610 748 #define FLASH_2500_LAYOUT_TABLE 0x50400
611 749 #define FLASH_8100_LAYOUT_TABLE 0xD8400
612 750 #define FLASH_8021_LAYOUT_TABLE 0xFC400
751 +#define FLASH_8300_LAYOUT_TABLE 0xFC400
752 +#define FLASH_2700_LAYOUT_TABLE 0xFC400
613 753
614 754 /*
615 755 * Flash Error Log Event Codes.
616 756 */
617 757 #define FLASH_ERRLOG_AEN_8002 0x8002
618 758 #define FLASH_ERRLOG_AEN_8003 0x8003
619 759 #define FLASH_ERRLOG_AEN_8004 0x8004
620 760 #define FLASH_ERRLOG_RESET_ERR 0xF00B
621 761 #define FLASH_ERRLOG_ISP_ERR 0xF020
622 762 #define FLASH_ERRLOG_PARITY_ERR 0xF022
623 763 #define FLASH_ERRLOG_NVRAM_CHKSUM_ERR 0xF023
624 764 #define FLASH_ERRLOG_FLASH_FW_ERR 0xF024
625 765
626 766 #define VPD_TAG_END 0x78
627 767 #define VPD_TAG_CHKSUM "RV"
628 768 #define VPD_TAG_SN "SN"
629 769 #define VPD_TAG_PN "PN"
630 770 #define VPD_TAG_PRODID "\x82"
631 771 #define VPD_TAG_LRT 0x90
632 772 #define VPD_TAG_LRTC 0x91
633 773
634 774 /*
635 775 * RISC to Host Status register definitions.
636 776 */
637 777 #define RH_RISC_INT BIT_15 /* RISC to Host Intrpt Req */
638 778 #define RH_RISC_PAUSED BIT_8 /* RISC Paused bit. */
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639 779
640 780 /*
641 781 * RISC to Host Status register status field definitions.
642 782 */
643 783 #define ROM_MBX_SUCCESS 0x01
644 784 #define ROM_MBX_ERR 0x02
645 785 #define MBX_SUCCESS 0x10
646 786 #define MBX_ERR 0x11
647 787 #define ASYNC_EVENT 0x12
648 788 #define RESP_UPDATE 0x13
649 -#define REQ_UPDATE 0x14
789 +#define MULTI_Q_RSP_UPDATE 0x14
650 790 #define SCSI_FAST_POST_16 0x15
651 791 #define SCSI_FAST_POST_32 0x16
652 792 #define CTIO_FAST_POST 0x17
653 793 #define IP_FAST_POST_XMT 0x18
654 794 #define IP_FAST_POST_RCV 0x19
655 795 #define IP_FAST_POST_BRD 0x1a
656 796 #define IP_FAST_POST_RCV_ALN 0x1b
657 797 #define ATIO_UPDATE 0x1c
658 798 #define ATIO_RESP_UPDATE 0x1d
659 799
660 800 /*
661 801 * HCCR commands.
662 802 */
663 803 #define HC_RESET_RISC 0x1000 /* Reset RISC */
664 804 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */
665 805 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */
666 806 #define HC_DISABLE_PARITY_PAUSE 0x4001 /* qla2200/2300 - disable parity err */
667 807 /* RISC pause. */
668 808 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */
669 809 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
670 810 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
671 811 #define HC_HOST_INT BIT_7 /* Host interrupt bit */
672 812 #define HC_RISC_PAUSE BIT_5 /* Pause mode bit */
673 813
674 814 /*
675 815 * HCCR commands for 24xx and 25xx.
676 816 */
677 817 #define HC24_RESET_RISC 0x10000000 /* Reset RISC */
678 818 #define HC24_CLEAR_RISC_RESET 0x20000000 /* Release RISC from reset. */
679 819 #define HC24_PAUSE_RISC 0x30000000 /* Pause RISC */
680 820 #define HC24_RELEASE_PAUSE 0x40000000 /* Release RISC from pause */
681 821 #define HC24_SET_HOST_INT 0x50000000 /* Set host interrupt */
682 822 #define HC24_CLR_HOST_INT 0x60000000 /* Clear HOST interrupt */
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683 823 #define HC24_CLR_RISC_INT 0xA0000000 /* Clear RISC interrupt */
684 824 #define HC24_HOST_INT BIT_6 /* Host to RISC intrpt bit */
685 825 #define HC24_RISC_RESET BIT_5 /* RISC Reset mode bit. */
686 826
687 827 /*
688 828 * ISP Initialization Control Blocks.
689 829 * Little endian except where noted.
690 830 */
691 831 #define ICB_VERSION 1
692 832 typedef struct ql_init_cb {
693 - uint8_t version;
694 - uint8_t reserved;
833 + uint8_t version;
834 + uint8_t reserved;
695 835
696 836 /*
697 837 * LSB BIT 0 = enable_hard_loop_id
698 838 * LSB BIT 1 = enable_fairness
699 839 * LSB BIT 2 = enable_full_duplex
700 840 * LSB BIT 3 = enable_fast_posting
701 841 * LSB BIT 4 = enable_target_mode
702 842 * LSB BIT 5 = disable_initiator_mode
703 843 * LSB BIT 6 = enable_adisc
704 844 * LSB BIT 7 = enable_target_inquiry_data
705 845 *
706 846 * MSB BIT 0 = enable_port_update_ae
707 847 * MSB BIT 1 = disable_initial_lip
708 848 * MSB BIT 2 = enable_decending_soft_assign
709 849 * MSB BIT 3 = previous_assigned_addressing
710 850 * MSB BIT 4 = enable_stop_q_on_full
711 851 * MSB BIT 5 = enable_full_login_on_lip
712 852 * MSB BIT 6 = enable_node_name
713 853 * MSB BIT 7 = extended_control_block
714 854 */
715 855 uint8_t firmware_options[2];
716 856
717 857 uint8_t max_frame_length[2];
718 858 uint8_t max_iocb_allocation[2];
719 859 uint8_t execution_throttle[2];
720 860 uint8_t login_retry_count;
721 861 uint8_t retry_delay; /* unused */
722 862 uint8_t port_name[8]; /* Big endian. */
723 863 uint8_t hard_address[2]; /* option bit 0 */
724 864 uint8_t inquiry; /* option bit 7 */
725 865 uint8_t login_timeout;
726 866 uint8_t node_name[8]; /* Big endian */
727 867 uint8_t request_q_outpointer[2];
728 868 uint8_t response_q_inpointer[2];
729 869 uint8_t request_q_length[2];
730 870 uint8_t response_q_length[2];
731 871 uint8_t request_q_address[8];
732 872 uint8_t response_q_address[8];
733 873 uint8_t lun_enables[2];
734 874 uint8_t command_resouce_count;
735 875 uint8_t immediate_notify_resouce_count;
736 876 uint8_t timeout[2];
737 877 uint8_t reserved_2[2];
738 878
739 879 /*
740 880 * LSB BIT 0 = Timer operation mode bit 0
741 881 * LSB BIT 1 = Timer operation mode bit 1
742 882 * LSB BIT 2 = Timer operation mode bit 2
743 883 * LSB BIT 3 = Timer operation mode bit 3
744 884 * LSB BIT 4 = P2P Connection option bit 0
745 885 * LSB BIT 5 = P2P Connection option bit 1
746 886 * LSB BIT 6 = P2P Connection option bit 2
747 887 * LSB BIT 7 = Enable Non part on LIHA failure
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748 888 *
749 889 * MSB BIT 0 = Enable class 2
750 890 * MSB BIT 1 = Enable ACK0
751 891 * MSB BIT 2 =
752 892 * MSB BIT 3 =
753 893 * MSB BIT 4 = FC Tape Enable
754 894 * MSB BIT 5 = Enable FC Confirm
755 895 * MSB BIT 6 = Enable CRN
756 896 * MSB BIT 7 =
757 897 */
758 - uint8_t add_fw_opt[2];
898 + uint8_t add_fw_opt[2];
759 899
760 - uint8_t response_accumulation_timer;
761 - uint8_t interrupt_delay_timer;
900 + uint8_t response_accumulation_timer;
901 + uint8_t interrupt_delay_timer;
762 902
763 903 /*
764 904 * LSB BIT 0 = Enable Read xfr_rdy
765 905 * LSB BIT 1 = Soft ID only
766 906 * LSB BIT 2 =
767 907 * LSB BIT 3 =
768 908 * LSB BIT 4 = FCP RSP Payload [0]
769 909 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
770 910 * LSB BIT 6 =
771 911 * LSB BIT 7 =
772 912 *
773 913 * MSB BIT 0 = Sbus enable - 2300
774 914 * MSB BIT 1 =
775 915 * MSB BIT 2 =
776 916 * MSB BIT 3 =
777 917 * MSB BIT 4 =
778 918 * MSB BIT 5 = enable 50 ohm termination
779 919 * MSB BIT 6 = Data Rate (2300 only)
780 920 * MSB BIT 7 = Data Rate (2300 only)
781 921 */
782 - uint8_t special_options[2];
922 + uint8_t special_options[2];
783 923
784 - uint8_t reserved_3[26];
924 + uint8_t reserved_3[26];
785 925 } ql_init_cb_t;
786 926
787 927 /*
788 928 * Virtual port definition.
789 929 */
790 930 typedef struct ql_vp_cfg {
791 - uint8_t reserved[2];
792 - uint8_t options;
793 - uint8_t hard_prev_addr;
794 - uint8_t port_name[8];
795 - uint8_t node_name[8];
931 + uint8_t reserved[2];
932 + uint8_t options;
933 + uint8_t hard_prev_addr;
934 + uint8_t port_name[8];
935 + uint8_t node_name[8];
796 936 } ql_vp_cfg_t;
797 937
798 938 /*
799 939 * VP options.
800 940 */
801 941 #define VPO_ENABLE_SNS_LOGIN_SCR BIT_6
802 942 #define VPO_TARGET_MODE_DISABLED BIT_5
803 943 #define VPO_INITIATOR_MODE_ENABLED BIT_4
804 944 #define VPO_ENABLED BIT_3
805 945 #define VPO_ID_NOT_ACQUIRED BIT_2
806 946 #define VPO_PREVIOUSLY_ASSIGNED_ID BIT_1
807 947 #define VPO_HARD_ASSIGNED_ID BIT_0
808 948
809 949 #define ICB_24XX_VERSION 1
810 950 typedef struct ql_init_24xx_cb {
811 951 uint8_t version[2];
812 952 uint8_t reserved_1[2];
813 953 uint8_t max_frame_length[2];
814 954 uint8_t execution_throttle[2];
815 955 uint8_t exchange_count[2];
816 956 uint8_t hard_address[2];
817 957 uint8_t port_name[8]; /* Big endian. */
818 958 uint8_t node_name[8]; /* Big endian. */
819 959
820 960 uint8_t response_q_inpointer[2];
821 961 uint8_t request_q_outpointer[2];
822 962
823 963 uint8_t login_retry_count[2];
824 964
825 965 uint8_t prio_request_q_outpointer[2];
826 966
827 967 uint8_t response_q_length[2];
828 968 uint8_t request_q_length[2];
829 969
830 970 uint8_t link_down_on_nos[2];
831 971
832 972 uint8_t prio_request_q_length[2];
833 973 uint8_t request_q_address[8];
834 974 uint8_t response_q_address[8];
835 975 uint8_t prio_request_q_address[8];
836 976 uint8_t msi_x_vector[2];
837 977 uint8_t reserved_2[6];
838 978 uint8_t atio_q_inpointer[2];
839 979 uint8_t atio_q_length[2];
840 980 uint8_t atio_q_address[8];
841 981
842 982 uint8_t interrupt_delay_timer[2]; /* 100us per */
843 983 uint8_t login_timeout[2];
844 984 /*
845 985 * BIT 0 = Hard Assigned Loop ID
846 986 * BIT 1 = Enable Fairness
847 987 * BIT 2 = Enable Full-Duplex
848 988 * BIT 3 = Reserved
849 989 * BIT 4 = Target Mode Enable
850 990 * BIT 5 = Initiator Mode Disable
851 991 * BIT 6 = Reserved
852 992 * BIT 7 = Reserved
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853 993 *
854 994 * BIT 8 = Reserved
855 995 * BIT 9 = Disable Initial LIP
856 996 * BIT 10 = Descending Loop ID Search
857 997 * BIT 11 = Previous Assigned Loop ID
858 998 * BIT 12 = Reserved
859 999 * BIT 13 = Full Login after LIP
860 1000 * BIT 14 = Node Name Option
861 1001 * BIT 15-31 = Reserved
862 1002 */
863 - uint8_t firmware_options_1[4];
1003 + uint8_t firmware_options_1[4];
864 1004
865 1005 /*
866 1006 * BIT 0 = Operation Mode bit 0
867 1007 * BIT 1 = Operation Mode bit 1
868 1008 * BIT 2 = Operation Mode bit 2
869 1009 * BIT 3 = Operation Mode bit 3
870 1010 * BIT 4 = Connection Options bit 0
871 1011 * BIT 5 = Connection Options bit 1
872 1012 * BIT 6 = Connection Options bit 2
873 1013 * BIT 7 = Enable Non part on LIHA failure
874 1014 *
875 1015 * BIT 8 = Enable Class 2
876 1016 * BIT 9 = Enable ACK0
877 1017 * BIT 10 = Reserved
878 1018 * BIT 11 = Enable FC-SP Security
879 1019 * BIT 12 = FC Tape Enable
880 1020 * BIT 13 = Reserved
881 1021 * BIT 14 = Target PRLI Control
882 1022 * BIT 15 = Reserved
883 1023 *
884 1024 * BIT 16 = Enable Emulated MSIX
885 1025 * BIT 17 = Reserved
886 1026 * BIT 18 = Enable Alternate Device Number
887 1027 * BIT 19 = Enable Alternate Bus Number
888 1028 * BIT 20 = Enable Translated Address
889 1029 * BIT 21 = Enable VM Security
890 1030 * BIT 22 = Enable Interrupt Handshake
891 1031 * BIT 23 = Enable Multiple Queue
892 1032 *
893 1033 * BIT 24 = IOCB Security
894 1034 * BIT 25 = qos
895 1035 * BIT 26-31 = Reserved
896 1036 */
897 1037 uint8_t firmware_options_2[4];
898 1038
899 1039 /*
900 1040 * BIT 0 = Reserved
901 1041 * BIT 1 = Soft ID only
902 1042 * BIT 2 = Reserved
903 1043 * BIT 3 = Reserved
904 1044 * BIT 4 = FCP RSP Payload bit 0
905 1045 * BIT 5 = FCP RSP Payload bit 1
906 1046 * BIT 6 = Enable Rec Out-of-Order data frame handling
907 1047 * BIT 7 = Disable Automatic PLOGI on Local Loop
908 1048 *
909 1049 * BIT 8 = Reserved
910 1050 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
911 1051 * offset handling
912 1052 * BIT 10 = Reserved
913 1053 * BIT 11 = Reserved
914 1054 * BIT 12 = Reserved
915 1055 * BIT 13 = Data Rate bit 0
916 1056 * BIT 14 = Data Rate bit 1
917 1057 * BIT 15 = Data Rate bit 2
918 1058 *
919 1059 * BIT 16 = 75-ohm Termination Select
920 1060 * BIT 17 = Enable Multiple FCFs
921 1061 * BIT 18 = MAC Addressing Mode
922 1062 * BIT 19 = MAC Addressing Mode
923 1063 * BIT 20 = MAC Addressing Mode
924 1064 * BIT 21 = Ethernet Data Rate
925 1065 * BIT 22 = Ethernet Data Rate
926 1066 * BIT 23 = Ethernet Data Rate
927 1067 *
928 1068 * BIT 24 = Ethernet Data Rate
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929 1069 * BIT 25 = Ethernet Data Rate
930 1070 * BIT 26 = Enable Ethernet Header ATIO Queue
931 1071 * BIT 27 = Enable Ethernet Header Response Queue
932 1072 * BIT 28 = SPMA Selection
933 1073 * BIT 29 = SPMA Selection
934 1074 * BIT 30 = Reserved
935 1075 * BIT 31 = Reserved
936 1076 */
937 1077 uint8_t firmware_options_3[4];
938 1078
939 - uint8_t qos[2];
940 - uint8_t rid[2];
1079 + uint8_t qos[2];
1080 + uint8_t rid[2];
941 1081
942 - uint8_t reserved_3[4];
1082 + uint8_t reserved_3[4];
943 1083
944 - uint8_t enode_mac_addr[6];
1084 + uint8_t enode_mac_addr[6];
945 1085
946 - uint8_t reserved_4[10];
1086 + uint8_t reserved_4[10];
947 1087
948 1088 /*
949 1089 * Multi-ID firmware.
950 1090 */
951 - uint8_t vp_count[2];
1091 + uint8_t vp_count[2];
952 1092
953 1093 /*
954 1094 * BIT 1 = Allows mode 2 connection option
955 1095 */
956 1096 uint8_t global_vp_option[2];
957 1097
958 1098 ql_vp_cfg_t vpc[MAX_25_VIRTUAL_PORTS + 1];
959 1099
960 1100 /*
961 1101 * Extended Initialization Control Block
962 1102 */
963 1103 ql_ext_icb_8100_t ext_blk;
964 1104 } ql_init_24xx_cb_t;
965 1105
966 1106 typedef union ql_comb_init_cb {
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967 1107 ql_init_cb_t cb;
968 1108 ql_init_24xx_cb_t cb24;
969 1109 } ql_comb_init_cb_t;
970 1110
971 1111 /*
972 1112 * ISP IP Initialization Control Block.
973 1113 * Little endian except where noted.
974 1114 */
975 1115 #define IP_ICB_VERSION 1
976 1116 typedef struct ql_ip_init_cb {
977 - uint8_t version;
978 - uint8_t reserved;
1117 + uint8_t version;
1118 + uint8_t reserved;
979 1119
980 1120 /*
981 1121 * LSB BIT 0 = receive_buffer_address_length
982 1122 * LSB BIT 1 = fast post broadcast received
983 1123 * LSB BIT 2 = allow out of receive buffers AE
984 1124 */
985 1125 uint8_t ip_firmware_options[2];
986 1126 uint8_t ip_header_size[2];
987 1127 uint8_t mtu_size[2]; /* max value is 65280 */
988 1128 uint8_t buf_size[2];
989 1129 uint8_t reserved_1[8];
990 1130 uint8_t queue_size[2]; /* 8-1024 */
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991 1131 uint8_t low_water_mark[2];
992 1132 uint8_t queue_address[8];
993 1133 uint8_t queue_inpointer[2];
994 1134 uint8_t fast_post_reg_count[2]; /* 0-14 */
995 1135 uint8_t cc[2];
996 1136 uint8_t reserved_2[28];
997 1137 } ql_ip_init_cb_t;
998 1138
999 1139 #define IP_ICB_24XX_VERSION 1
1000 1140 typedef struct ql_ip_init_24xx_cb {
1001 - uint8_t version;
1002 - uint8_t reserved;
1141 + uint8_t version;
1142 + uint8_t reserved;
1003 1143 /*
1004 1144 * LSB BIT 2 = allow out of receive buffers AE
1005 1145 */
1006 1146 uint8_t ip_firmware_options[2];
1007 1147 uint8_t ip_header_size[2];
1008 1148 uint8_t mtu_size[2];
1009 1149 uint8_t buf_size[2];
1010 1150 uint8_t reserved_1[10];
1011 1151 uint8_t low_water_mark[2];
1012 1152 uint8_t reserved_3[12];
1013 1153 uint8_t cc[2];
1014 1154 uint8_t reserved_2[28];
1015 1155 } ql_ip_init_24xx_cb_t;
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1016 1156
1017 1157 typedef union ql_comb_ip_init_cb {
1018 1158 ql_ip_init_cb_t cb;
1019 1159 ql_ip_init_24xx_cb_t cb24;
1020 1160 } ql_comb_ip_init_cb_t;
1021 1161
1022 1162 /*
1023 1163 * f/w module table
1024 1164 */
1025 1165 struct fw_table {
1026 - uint16_t fw_class;
1166 + uint32_t fw_class;
1027 1167 int8_t *fw_version;
1028 1168 };
1029 1169
1030 1170 /*
1031 - * aif function table
1032 - */
1033 -typedef struct ql_ifunc {
1034 - uint_t (*ifunc)();
1035 -} ql_ifunc_t;
1036 -
1037 -#define QL_MSIX_AIF 0x0
1038 -#define QL_MSIX_RSPQ 0x1
1039 -#define QL_MSIX_MAXAIF QL_MSIX_RSPQ + 1
1040 -
1041 -/*
1042 1171 * DMA memory type.
1043 1172 */
1044 1173 typedef enum mem_alloc_type {
1045 1174 UNKNOWN_MEMORY,
1046 1175 TASK_MEMORY,
1047 1176 LITTLE_ENDIAN_DMA,
1048 1177 BIG_ENDIAN_DMA,
1049 1178 KERNEL_MEM,
1050 - NO_SWAP_DMA,
1051 - STRUCT_BUF_MEMORY
1179 + NO_SWAP_DMA
1052 1180 } mem_alloc_type_t;
1053 1181
1054 1182 /*
1055 1183 * DMA memory alignment type.
1056 1184 */
1057 1185 typedef enum men_align_type {
1058 1186 QL_DMA_DATA_ALIGN,
1059 1187 QL_DMA_RING_ALIGN,
1060 1188 } mem_alignment_t;
1061 1189
1062 1190 /*
1063 1191 * DMA memory object.
1064 1192 */
1065 1193 typedef struct dma_mem {
1066 1194 uint64_t alignment;
1067 1195 void *bp;
1068 1196 ddi_dma_cookie_t *cookies;
1069 1197 ddi_acc_handle_t acc_handle;
1070 1198 ddi_dma_handle_t dma_handle;
1071 1199 ddi_dma_cookie_t cookie;
1200 + uint32_t max_cookie_count;
1072 1201 uint32_t cookie_count;
1073 1202 uint32_t size;
1074 1203 uint32_t memflags;
1075 1204 mem_alloc_type_t type;
1076 1205 uint32_t flags; /* Solaris DMA flags. */
1077 1206 } dma_mem_t;
1078 1207
1079 1208 /*
1080 - * dma_mem_t memflags defines
1081 - */
1082 -#define MFLG_32BIT_ONLY BIT_0
1083 -
1084 -/*
1085 1209 * 24 bit port ID type definition.
1086 1210 */
1087 1211 typedef union {
1088 1212 struct {
1089 1213 uint8_t d_id[3];
1090 1214 uint8_t rsvd_1;
1091 1215 }r;
1092 1216
1093 1217 uint32_t b24 : 24;
1094 1218
1095 1219 #if defined(_BIT_FIELDS_LTOH)
1096 1220 struct {
1097 1221 uint8_t al_pa;
1098 1222 uint8_t area;
1099 1223 uint8_t domain;
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1100 1224 uint8_t rsvd_1;
1101 1225 }b;
1102 1226 #elif defined(_BIT_FIELDS_HTOL)
1103 1227 struct {
1104 1228 uint8_t domain;
1105 1229 uint8_t area;
1106 1230 uint8_t al_pa;
1107 1231 uint8_t rsvd_1;
1108 1232 }b;
1109 1233 #else
1110 -#error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
1234 +#error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
1111 1235 #endif
1112 1236 } port_id_t;
1113 1237
1114 1238 /*
1115 1239 * Link list definitions.
1116 1240 */
1117 1241 typedef struct ql_link {
1118 - struct ql_link *prev;
1119 - struct ql_link *next;
1120 - void *base_address;
1121 - struct ql_head *head; /* the queue this link is on */
1242 + struct ql_link *prev;
1243 + struct ql_link *next;
1244 + void *base_address;
1245 + struct ql_head *head; /* the queue this link is on */
1122 1246 } ql_link_t;
1123 1247
1124 1248 typedef struct ql_head {
1125 - ql_link_t *first;
1126 - ql_link_t *last;
1249 + ql_link_t *first;
1250 + ql_link_t *last;
1127 1251 } ql_head_t;
1128 1252
1129 1253 /*
1254 + * ISP request queue context
1255 + */
1256 +typedef struct ql_request_q {
1257 + struct cmd_entry *req_ring_ptr;
1258 + dma_mem_t req_ring;
1259 + uint32_t *req_out_shadow_ptr;
1260 + uint32_t req_out_shadow_ofst;
1261 + uint32_t mbar_req_in;
1262 + uint32_t mbar_req_out;
1263 + uint16_t req_ring_index;
1264 + uint16_t req_entry_cnt;
1265 + uint16_t req_q_cnt; /* # of available entries. */
1266 + uint16_t req_q_number;
1267 +} ql_request_q_t;
1268 +
1269 +/*
1270 + * ISP response queue context
1271 + */
1272 +typedef struct ql_response_q {
1273 + struct ql_srb *status_srb;
1274 + struct sts_entry *rsp_ring_ptr;
1275 + dma_mem_t rsp_ring;
1276 + kmutex_t intr_mutex;
1277 + uint32_t *rsp_in_shadow_ptr;
1278 + uint32_t rsp_in_shadow_ofst;
1279 + uint32_t mbar_rsp_in;
1280 + uint32_t mbar_rsp_out;
1281 + uint16_t rsp_ring_index;
1282 + uint16_t rsp_entry_cnt;
1283 + uint16_t isp_rsp_index;
1284 + uint16_t rsp_q_number;
1285 + uint16_t msi_x_vector;
1286 +} ql_response_q_t;
1287 +
1288 +/*
1130 1289 * This is the per-command structure
1131 1290 */
1132 1291 typedef struct ql_srb {
1133 1292 /* Command link. */
1134 1293 ql_link_t cmd;
1135 1294
1136 1295 /* Watchdog link and timer. */
1137 1296 ql_link_t wdg;
1138 1297 time_t wdg_q_time;
1139 1298 time_t init_wdg_q_time;
1140 1299 uint16_t isp_timeout;
1141 1300
1142 1301 /* FCA and FC Transport data. */
1143 1302 fc_packet_t *pkt;
1144 1303 struct ql_adapter_state *ha;
1145 1304 uint32_t magic_number;
1146 1305
1147 1306 /* unsolicited buffer context. */
1148 1307 dma_mem_t ub_buffer;
1149 1308 uint32_t ub_type;
1150 1309 uint32_t ub_size;
1151 1310
1152 1311 /* FCP command. */
1153 1312 fcp_cmd_t *fcp;
1154 1313
1155 1314 /* Request sense. */
1156 1315 uint32_t request_sense_length;
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1157 1316 caddr_t request_sense_ptr;
1158 1317
1159 1318 /* Device queue pointer. */
1160 1319 struct ql_lun *lun_queue;
1161 1320
1162 1321 /* Command state/status flags. */
1163 1322 volatile uint32_t flags;
1164 1323
1165 1324 /* Command IOCB context. */
1166 1325 void (*iocb)(struct ql_adapter_state *,
1167 - struct ql_srb *, void *);
1326 + ql_request_q_t *, struct ql_srb *, void *);
1168 1327 struct cmd_entry *request_ring_ptr;
1169 1328 uint32_t handle;
1329 + uint16_t req_q_number;
1170 1330 uint16_t req_cnt;
1171 1331 uint8_t retry_count;
1332 + uint8_t rsp_q_number;
1172 1333 dma_mem_t sg_dma;
1173 1334 } ql_srb_t;
1174 1335
1175 -#define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */
1176 -#define SRB_ISP_COMPLETED BIT_1 /* ISP finished with command. */
1177 -#define SRB_RETRY BIT_2 /* Driver retrying command. */
1178 -#define SRB_POLL BIT_3 /* Poll for completion. */
1179 -#define SRB_WATCHDOG_ENABLED BIT_4 /* Command on watchdog list. */
1180 -#define SRB_ABORT BIT_5 /* SRB to be aborted. */
1181 -#define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */
1182 -#define SRB_UB_IN_ISP BIT_7 /* ISP holds unsolicited buffer */
1183 -#define SRB_UB_CALLBACK BIT_8 /* Unsolicited callback needed. */
1184 -#define SRB_UB_RSCN BIT_9 /* Unsolicited RSCN callback. */
1185 -#define SRB_UB_FCP BIT_10 /* Unsolicited RSCN callback. */
1186 -#define SRB_FCP_CMD_PKT BIT_11 /* FCP command type packet. */
1187 -#define SRB_FCP_DATA_PKT BIT_12 /* FCP data type packet. */
1188 -#define SRB_FCP_RSP_PKT BIT_13 /* FCP response type packet. */
1189 -#define SRB_IP_PKT BIT_14 /* IP type packet. */
1190 -#define SRB_GENERIC_SERVICES_PKT BIT_15 /* Generic services type packet */
1191 -#define SRB_COMMAND_TIMEOUT BIT_16 /* Command timed out. */
1192 -#define SRB_ABORTING BIT_17 /* SRB aborting. */
1193 -#define SRB_IN_DEVICE_QUEUE BIT_18 /* In Device Queue */
1194 -#define SRB_IN_TOKEN_ARRAY BIT_19 /* In Token Array */
1195 -#define SRB_UB_FREE_REQUESTED BIT_20 /* UB Free requested */
1196 -#define SRB_UB_ACQUIRED BIT_21 /* UB selected for upcall */
1197 -#define SRB_MS_PKT BIT_22 /* Management Service pkt */
1198 -#define SRB_ELS_PKT BIT_23 /* Extended Link Services pkt */
1336 +#define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */
1337 +#define SRB_ISP_COMPLETED BIT_1 /* ISP finished with command. */
1338 +#define SRB_RETRY BIT_2 /* Driver retrying command. */
1339 +#define SRB_POLL BIT_3 /* Poll for completion. */
1199 1340
1341 +#define SRB_WATCHDOG_ENABLED BIT_4 /* Command on watchdog list. */
1342 +#define SRB_ELS_PKT BIT_5 /* Extended Link Services pkt */
1343 +#define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */
1344 +#define SRB_UB_IN_ISP BIT_7 /* ISP holds unsolicited buffer */
1345 +
1346 +#define SRB_UB_CALLBACK BIT_8 /* Unsolicited callback needed. */
1347 +#define SRB_UB_RSCN BIT_9 /* Unsolicited RSCN callback. */
1348 +#define SRB_UB_FCP BIT_10 /* Unsolicited RSCN callback. */
1349 +#define SRB_FCP_CMD_PKT BIT_11 /* FCP command type packet. */
1350 +
1351 +#define SRB_FCP_DATA_PKT BIT_12 /* FCP data type packet. */
1352 +#define SRB_FCP_RSP_PKT BIT_13 /* FCP response type packet. */
1353 +#define SRB_IP_PKT BIT_14 /* IP type packet. */
1354 +#define SRB_GENERIC_SERVICES_PKT BIT_15 /* Generic services type packet */
1355 +
1356 +#define SRB_COMMAND_TIMEOUT BIT_16 /* Command timed out. */
1357 +#define SRB_ABORTING BIT_17 /* SRB aborting. */
1358 +#define SRB_IN_DEVICE_QUEUE BIT_18 /* In Device Queue */
1359 +#define SRB_IN_TOKEN_ARRAY BIT_19 /* In Token Array */
1360 +
1361 +#define SRB_UB_FREE_REQUESTED BIT_20 /* UB Free requested */
1362 +#define SRB_UB_ACQUIRED BIT_21 /* UB selected for upcall */
1363 +#define SRB_MS_PKT BIT_22 /* Management Service pkt */
1364 +
1200 1365 /*
1201 1366 * This byte will be used to define flags for the LUN on the target.
1202 1367 * Presently, we have untagged-command as one flag. Others can be
1203 1368 * added later, if needed.
1204 1369 */
1205 1370 typedef struct tgt_lun_flags {
1206 1371 uint8_t
1207 1372 untagged_pending:1,
1208 1373 unused_bits:7;
1209 1374 } tgt_lun_flags_t;
1210 1375
1211 1376 #define QL_IS_UNTAGGED_PENDING(q, lun_num) \
1212 1377 ((q->lun_flags[lun_num].untagged_pending == TRUE) ? 1 : 0)
1213 1378 #define QL_SET_UNTAGGED_PENDING(q, lun_num) \
1214 1379 (q->lun_flags[lun_num].untagged_pending = TRUE)
1215 1380 #define QL_CLEAR_UNTAGGED_PENDING(q, lun_num) \
1216 1381 (q->lun_flags[lun_num].untagged_pending = FALSE)
1217 1382
1218 1383 /*
1219 1384 * Fibre Channel LUN Queue structure
1220 1385 */
1221 1386 typedef struct ql_lun {
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1222 1387 /* Head command link. */
1223 1388 ql_head_t cmd;
1224 1389
1225 1390 struct ql_target *target_queue;
1226 1391
1227 1392 uint32_t flags;
1228 1393
1229 1394 /* LUN execution throttle. */
1230 1395 uint16_t lun_outcnt;
1231 1396
1397 + /* LUN number as reported by REPORT LUNS */
1232 1398 uint16_t lun_no;
1233 1399
1400 + /*
1401 + * Logical unit number in SCSI3 format, also
1402 + * referred to as FCP lun or FCP entity address.
1403 + */
1404 + uint64_t lun_addr;
1405 +
1234 1406 ql_link_t link;
1235 1407 } ql_lun_t;
1236 1408
1237 1409 /*
1238 1410 * LUN Queue flags
1239 1411 */
1240 1412 #define LQF_UNTAGGED_PENDING BIT_0
1241 1413
1242 1414 /*
1415 + * SCSI standard defined lun addressing methods.
1416 + */
1417 +#define QL_LUN_AM_MASK 0xC0 /* Address Method Mask */
1418 +#define QL_LUN_AM_PDEV 0x00 /* Peripheral device AM */
1419 +#define QL_LUN_AM_FLAT 0x40 /* Flat space AM */
1420 +#define QL_LUN_AM_LUN 0x80 /* Logical unit AM */
1421 +#define QL_LUN_AM_EFLAT 0xC0 /* Extended flat space AM */
1422 +#define QL_LUN_AM_ELUN 0xC0 /* Extended logical unit AM */
1423 +
1424 +/*
1243 1425 * Fibre Channel Device Queue structure
1244 1426 */
1245 1427 typedef struct ql_target {
1246 1428 /* Device queue lock. */
1247 1429 kmutex_t mutex;
1248 1430
1249 - /* Head target command link. */
1250 - ql_head_t tgt_cmd;
1251 -
1252 1431 volatile uint32_t flags;
1253 1432 port_id_t d_id;
1254 1433 uint16_t loop_id;
1255 1434 volatile uint16_t outcnt; /* # of cmds running in ISP */
1256 1435 uint32_t iidma_rate;
1257 1436
1258 1437 /* Device link. */
1259 1438 ql_link_t device;
1260 1439
1261 1440 /* Head watchdog link. */
1262 1441 ql_head_t wdg;
1263 1442
1264 1443 /* Unsolicited buffer IP data. */
1265 1444 uint32_t ub_frame_ro;
1266 1445 uint16_t ub_sequence_length;
1267 1446 uint16_t ub_loop_id;
1268 1447 uint8_t ub_total_seg_cnt;
1269 1448 uint8_t ub_seq_cnt;
1270 1449 uint8_t ub_seq_id;
1271 1450
1272 1451 /* Port down retry counter. */
1273 1452 uint16_t port_down_retry_count;
1274 1453 uint16_t qfull_retry_count;
1275 1454
1276 1455 /* logout sent state */
1277 1456 uint8_t logout_sent;
1278 1457
1279 1458 /* Data from Port database matches machine type. */
1280 1459 uint8_t master_state;
1281 1460 uint8_t slave_state;
1282 1461 port_id_t hard_addr;
1283 1462 uint8_t port_name[8];
1284 1463 uint8_t node_name[8];
1285 1464 uint16_t cmn_features;
1286 1465 uint16_t conc_sequences;
1287 1466 uint16_t relative_offset;
1288 1467 uint16_t class3_recipient_ctl;
1289 1468 uint16_t class3_rcv_data_size;
1290 1469 uint16_t class3_conc_sequences;
1291 1470 uint16_t class3_open_sequences_per_exch;
1292 1471 uint16_t prli_payload_length;
1293 1472 uint16_t prli_svc_param_word_0;
1294 1473 uint16_t prli_svc_param_word_3;
1295 1474
1296 1475 /* LUN context. */
1297 1476 ql_head_t lun_queues;
1298 1477 ql_lun_t *last_lun_queue;
1299 1478 } ql_tgt_t;
1300 1479
1301 1480 /*
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1302 1481 * Target Queue flags
1303 1482 */
1304 1483 #define TQF_TAPE_DEVICE BIT_0
1305 1484 #define TQF_QUEUE_SUSPENDED BIT_1 /* Queue suspended. */
1306 1485 #define TQF_FABRIC_DEVICE BIT_2
1307 1486 #define TQF_INITIATOR_DEVICE BIT_3
1308 1487 #define TQF_RSCN_RCVD BIT_4
1309 1488 #define TQF_NEED_AUTHENTICATION BIT_5
1310 1489 #define TQF_PLOGI_PROGRS BIT_6
1311 1490 #define TQF_IIDMA_NEEDED BIT_7
1491 +#define TQF_LOGIN_NEEDED BIT_8
1492 +
1312 1493 /*
1313 1494 * Tempoary N_Port information
1314 1495 */
1315 1496 typedef struct ql_n_port_info {
1316 1497 uint16_t n_port_handle;
1317 1498 uint8_t port_name[8]; /* Big endian. */
1318 1499 uint8_t node_name[8]; /* Big endian. */
1500 + port_id_t d_id;
1319 1501 } ql_n_port_info_t;
1320 1502
1321 1503 /*
1322 1504 * iiDMA
1323 1505 */
1324 1506 #define IIDMA_RATE_INIT 0xffffffff /* init state */
1325 1507 #define IIDMA_RATE_NDEF 0xfffffffe /* not defined in conf file */
1326 1508 #define IIDMA_RATE_1GB 0x0
1327 1509 #define IIDMA_RATE_2GB 0x1
1510 +#define IIDMA_RATE_AUTO 0x2
1328 1511 #define IIDMA_RATE_4GB 0x3
1329 1512 #define IIDMA_RATE_8GB 0x4
1513 +#define IIDMA_RATE_16GB 0x5
1514 +#define IIDMA_RATE_32GB 0x6
1330 1515 #define IIDMA_RATE_10GB 0x13
1331 1516 #define IIDMA_RATE_MAX IIDMA_RATE_10GB
1332 1517
1333 1518 /*
1334 1519 * Kernel statistic structure definitions.
1335 1520 */
1336 1521 typedef struct ql_device_stat {
1337 1522 int logouts_recvd;
1338 1523 int task_mgmt_failures;
1339 1524 int data_ro_mismatches;
1340 1525 int dl_len_mismatches;
1341 1526 } ql_device_stat_t;
1342 1527
1343 1528 typedef struct ql_adapter_24xx_stat {
1344 1529 int version; /* version of this struct */
1345 1530 int lip_count; /* lips forced */
1346 1531 int ncmds; /* outstanding commands */
1347 1532 ql_adapter_revlvl_t revlvl; /* adapter revision levels */
1348 1533 ql_device_stat_t d_stats[MAX_24_FIBRE_DEVICES]; /* per device stats */
1349 1534 } ql_adapter_stat_t;
1350 1535
1351 1536 /*
1352 1537 * Firmware code segment.
1353 1538 */
1354 1539 #define MAX_RISC_CODE_SEGMENTS 3
1355 1540 typedef struct fw_code {
1356 1541 caddr_t code;
1357 1542 uint32_t addr;
1358 1543 uint32_t length;
1359 1544 } ql_fw_code_t;
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1360 1545
1361 1546 /* diagnostic els ECHO defines */
1362 1547 #define QL_ECHO_CMD 0x10000000 /* echo opcode */
1363 1548 #define QL_ECHO_CMD_LENGTH 220 /* command length */
1364 1549
1365 1550 /* DUMP state flags. */
1366 1551 #define QL_DUMPING BIT_0
1367 1552 #define QL_DUMP_VALID BIT_1
1368 1553 #define QL_DUMP_UPLOADED BIT_2
1369 1554
1555 +#define QL_LOG_ENTRIES 256 /* max # of EL entries */
1556 +#define QL_LOG_LENGTH 128 /* max # of bytes in each EL entry */
1557 +
1558 +typedef struct ql_trace_entry {
1559 + timespec_t hs_time; /* high resolution timestamp */
1560 + char buf[QL_LOG_LENGTH];
1561 +} ql_trace_entry_t;
1562 +
1563 +/* per instance based extended logging trace descriptor */
1370 1564 typedef struct el_trace_desc {
1371 1565 kmutex_t mutex;
1372 - uint16_t next;
1373 - uint32_t trace_buffer_size;
1374 - char *trace_buffer;
1375 -} el_trace_desc_t;
1566 + uint32_t nentries; /* max number of entries */
1567 + uint16_t nindex; /* next index to fill */
1568 + uint32_t start; /* starting point */
1569 + uint32_t end; /* ending point */
1570 + uint32_t csize; /* current filled queue size */
1571 + uint32_t count; /* sequence number */
1572 + size_t trace_buffer_size;
1573 + ql_trace_entry_t *trace_buffer;
1574 +} ql_trace_desc_t;
1376 1575
1377 1576 /*
1378 1577 * NVRAM cache descriptor.
1379 1578 */
1380 1579 typedef struct nvram_cache_desc {
1381 - kmutex_t mutex;
1382 1580 uint32_t valid;
1383 1581 uint32_t size;
1384 1582 void *cache;
1385 1583 } nvram_cache_desc_t;
1386 1584
1387 1585 /*
1586 + * Plogi retry parameters
1587 + */
1588 +typedef struct plogi_params_desc {
1589 + uint32_t retry_cnt;
1590 + uint32_t retry_dly_usec;
1591 +} plogi_params_desc_t;
1592 +
1593 +/*
1388 1594 * ql attach progress indication
1389 1595 */
1390 1596 #define QL_SOFT_STATE_ALLOCED BIT_0
1391 1597 #define QL_REGS_MAPPED BIT_1
1392 1598 #define QL_HBA_BUFFER_SETUP BIT_2
1393 1599 #define QL_MUTEX_CV_INITED BIT_3
1394 1600 #define QL_INTR_ADDED BIT_4
1395 1601 #define QL_CONFIG_SPACE_SETUP BIT_5
1396 1602 #define QL_TASK_DAEMON_STARTED BIT_6
1397 1603 #define QL_KSTAT_CREATED BIT_7
1398 1604 #define QL_MINOR_NODE_CREATED BIT_8
1399 1605 #define QL_FCA_TRAN_ALLOCED BIT_9
1400 1606 #define QL_FCA_ATTACH_DONE BIT_10
1401 1607 #define QL_IOMAP_IOBASE_MAPPED BIT_11
1402 1608 #define QL_N_PORT_INFO_CREATED BIT_12
1403 1609 #define QL_DB_IOBASE_MAPPED BIT_13
1610 +#define QL_FCA_INIT_FM BIT_14
1611 +#define QL_NVRAM_CACHE_CREATED BIT_15
1612 +#define QL_PLOGI_PARAMS_CREATED BIT_16
1613 +
1404 1614 /* Device queue head list size (based on AL_PA address). */
1405 1615 #define DEVICE_HEAD_LIST_SIZE 0x81
1406 1616
1407 1617 struct legacy_intr_set {
1408 1618 uint32_t int_vec_bit;
1409 1619 uint32_t tgt_status_reg;
1410 1620 uint32_t tgt_mask_reg;
1411 1621 uint32_t pci_int_reg;
1412 1622 };
1413 1623
1624 +/* Returned Mailbox registers. */
1625 +typedef struct ql_mbx_data {
1626 + uint16_t mb[MAX_MBOX_COUNT];
1627 +} ql_mbx_data_t;
1628 +
1629 +typedef struct ql_ledstate {
1630 + uint32_t BeaconState;
1631 + uint32_t LEDflags;
1632 + uint32_t flags;
1633 + uint32_t led_blink_on;
1634 + uint32_t select;
1635 + ql_mbx_data_t cfg;
1636 +} ql_ledstate_t;
1637 +
1414 1638 /*
1415 1639 * Adapter state structure.
1416 1640 */
1417 1641 typedef struct ql_adapter_state {
1418 1642 ql_link_t hba;
1419 1643
1420 1644 kmutex_t mutex;
1421 - volatile uint32_t flags; /* State flags. */
1645 + volatile uint64_t flags; /* State flags. */
1422 1646 uint32_t state;
1423 1647 port_id_t d_id;
1424 1648 uint16_t loop_id;
1425 - uint8_t topology;
1426 1649 uint16_t sfp_stat;
1427 -
1428 1650 uint16_t idle_timer;
1651 + uint16_t r_a_tov; /* 2 * R_A_TOV + 5 */
1652 + uint8_t topology;
1653 + uint8_t bbcr_runtime;
1654 + uint8_t bbcr_initial;
1429 1655 uint8_t loop_down_abort_time;
1430 1656 uint8_t port_retry_timer;
1431 1657 uint8_t loop_down_timer;
1432 1658 uint8_t watchdog_timer;
1433 - uint16_t r_a_tov; /* 2 * R_A_TOV + 5 */
1434 1659
1435 1660 /* Task Daemon context. */
1436 - callb_cpr_t cprinfo;
1661 + ql_head_t unsol_callback_queue;
1662 + ddi_taskq_t *driver_thread_taskq;
1437 1663 kmutex_t task_daemon_mutex;
1438 - kcondvar_t cv_dr_suspended;
1439 1664 kcondvar_t cv_task_daemon;
1440 - volatile uint32_t task_daemon_flags;
1441 - ql_head_t callback_queue;
1665 + kcondvar_t cv_dr_suspended;
1666 + volatile uint64_t task_daemon_flags;
1667 + uint32_t driver_thread_awake;
1668 + uint64_t df;
1669 + uint64_t sf;
1670 + uint64_t cf;
1442 1671
1672 + /* Completion thread context */
1673 + ddi_taskq_t *completion_taskq;
1674 + ql_head_t comp_q;
1675 + kmutex_t comp_q_mutex;
1676 + kcondvar_t cv_comp_thread;
1677 + uint8_t comp_thds_active;
1678 + uint8_t comp_thds_awake;
1679 + uint8_t completion_thds;
1680 +
1443 1681 /* Interrupt context. */
1444 - kmutex_t intr_mutex;
1445 - caddr_t iobase;
1446 - uint8_t rev_id;
1447 - uint16_t device_id;
1448 - uint16_t subsys_id;
1449 - uint16_t subven_id;
1450 - uint16_t ven_id;
1451 - uint16_t fw_class;
1452 - ql_srb_t *status_srb;
1682 + ddi_iblock_cookie_t iblock_cookie;
1683 + ddi_intr_handle_t *htable;
1684 + uint32_t hsize;
1685 + int32_t intr_cnt;
1686 + void *intr_pri;
1687 + int32_t intr_cap;
1688 + uint32_t iflags;
1453 1689 volatile uint8_t intr_claimed;
1690 + uint8_t mq_msix_vectors;
1691 + uint8_t interrupt_count;
1454 1692
1455 - /*
1456 - * ISP request queue, response queue, mailbox buffer and
1457 - * IP receive queue buffer.
1458 - */
1459 - dma_mem_t hba_buf;
1460 -
1461 - /* ISP request queue context. */
1462 - kmutex_t req_ring_mutex;
1463 - struct cmd_entry *request_ring_bp;
1464 - struct cmd_entry *request_ring_ptr;
1465 - uint64_t request_dvma;
1466 - uint16_t req_ring_index;
1467 - uint16_t req_q_cnt; /* # of available entries. */
1693 + /* Outstanding ISP commands. */
1468 1694 ql_head_t pending_cmds;
1469 1695 ql_srb_t **outstanding_cmds;
1470 1696 uint16_t osc_index;
1697 + uint16_t osc_max_cnt;
1471 1698
1699 + /* ISP request queue context. */
1700 + kmutex_t req_ring_mutex;
1701 + ql_request_q_t *req_q[2];
1702 +
1472 1703 /* ISP response queue context. */
1473 - struct sts_entry *response_ring_bp;
1474 - struct sts_entry *response_ring_ptr;
1475 - uint64_t response_dvma;
1476 - uint16_t rsp_ring_index;
1477 - uint16_t isp_rsp_index;
1704 + ql_response_q_t **rsp_queues;
1705 + uint32_t rsp_queues_size;
1706 + uint8_t rsp_queues_cnt;
1707 + uint8_t rsp_q_number;
1708 + uint8_t io_min_rsp_q_number;
1478 1709
1710 + /* IP receive buffer queue context. */
1711 + ql_tgt_t *rcv_dev_q;
1712 + dma_mem_t rcv_ring;
1713 + struct rcvbuf *rcvbuf_ring_ptr;
1714 + uint16_t rcvbuf_ring_index;
1715 +
1479 1716 /* Mailbox context. */
1480 1717 kmutex_t mbx_mutex;
1481 - caddr_t mbx_bp;
1482 1718 struct mbx_cmd *mcp;
1483 1719 kcondvar_t cv_mbx_wait;
1484 1720 kcondvar_t cv_mbx_intr;
1485 1721 volatile uint8_t mailbox_flags;
1486 1722
1487 - /* ISP receive buffer queue context. */
1488 - ql_tgt_t *rcv_dev_q;
1489 - struct rcvbuf *rcvbuf_ring_bp;
1490 - struct rcvbuf *rcvbuf_ring_ptr;
1491 - uint64_t rcvbuf_dvma;
1492 - uint16_t rcvbuf_ring_index;
1493 -
1494 1723 /* Unsolicited buffer data. */
1495 1724 uint16_t ub_outcnt;
1496 1725 uint8_t ub_seq_id;
1497 1726 uint8_t ub_command_count;
1498 1727 uint8_t ub_notify_count;
1499 1728 uint32_t ub_allocated;
1500 1729 kmutex_t ub_mutex;
1501 1730 kcondvar_t cv_ub;
1502 1731 fc_unsol_buf_t **ub_array;
1503 1732
1504 1733 /* Head of device queue list. */
1505 1734 ql_head_t *dev;
1506 1735
1507 1736 /* Kernel statistics. */
1508 1737 kstat_t *k_stats;
1509 1738 ql_adapter_stat_t *adapter_stats;
1510 1739
1511 - /* Solaris adapter configuration data */
1512 - ddi_acc_handle_t dev_handle;
1740 + /* PCI context */
1513 1741 ddi_acc_handle_t pci_handle; /* config space */
1742 + ddi_acc_handle_t dev_handle;
1743 + caddr_t iobase;
1514 1744 ddi_acc_handle_t iomap_dev_handle;
1515 1745 caddr_t iomap_iobase;
1746 + ddi_acc_handle_t mbar_dev_handle;
1747 + caddr_t mbar;
1748 + uint32_t mbar_size;
1749 + uint32_t mbar_queue_offset;
1750 + uint16_t device_id;
1751 + uint16_t subsys_id;
1752 + uint16_t subven_id;
1753 + uint16_t ven_id;
1754 + uint16_t pci_max_read_req;
1755 + uint8_t rev_id;
1756 + uint8_t pci_function_number;
1757 +
1758 + /* Solaris adapter configuration data */
1516 1759 dev_info_t *dip;
1517 - ddi_iblock_cookie_t iblock_cookie;
1518 1760 fc_fca_tran_t *tran;
1519 1761 uint32_t instance;
1520 1762 int8_t *devpath;
1521 - uint32_t fru_hba_index;
1522 - uint32_t fru_port_index;
1763 + uint32_t fru_hba_index;
1764 + uint32_t fru_port_index;
1523 1765 uint8_t adapInfo[18];
1524 1766
1525 1767 /* Adapter context */
1526 1768 la_els_logi_t loginparams;
1527 1769 fc_fca_bind_info_t bind_info;
1528 1770 ddi_modhandle_t fw_module;
1529 1771 uint32_t fw_major_version;
1530 1772 uint32_t fw_minor_version;
1531 1773 uint32_t fw_subminor_version;
1532 - uint16_t fw_attributes;
1774 + uint32_t fw_attributes;
1775 + uint32_t fw_ext_attributes;
1776 + uint32_t fw_ext_memory_end;
1533 1777 uint32_t fw_ext_memory_size;
1778 + uint32_t fw_shared_ram_start;
1779 + uint32_t fw_shared_ram_end;
1780 + uint32_t fw_ddr_ram_start;
1781 + uint32_t fw_ddr_ram_end;
1534 1782 uint32_t parity_pause_errors;
1535 1783 boolean_t log_parity_pause;
1784 + uint32_t fw_class;
1785 + uint16_t fw_state[7];
1786 + uint16_t rom_status;
1787 + ql_ledstate_t ledstate;
1536 1788 uint16_t parity_hccr_err;
1537 1789 uint32_t parity_stat_err;
1538 1790 reg_off_t *reg_off;
1539 1791 caddr_t risc_code;
1540 1792 uint32_t risc_code_size;
1541 1793 ql_fw_code_t risc_fw[MAX_RISC_CODE_SEGMENTS];
1542 1794 uint32_t risc_dump_size;
1543 1795 void (*fcp_cmd)(struct ql_adapter_state *,
1544 - ql_srb_t *, void *);
1796 + ql_request_q_t *, ql_srb_t *, void *);
1545 1797 void (*ip_cmd)(struct ql_adapter_state *,
1546 - ql_srb_t *, void *);
1798 + ql_request_q_t *, ql_srb_t *, void *);
1547 1799 void (*ms_cmd)(struct ql_adapter_state *,
1548 - ql_srb_t *, void *);
1800 + ql_request_q_t *, ql_srb_t *, void *);
1801 + void (*els_cmd)(struct ql_adapter_state *,
1802 + ql_request_q_t *, ql_srb_t *, void *);
1549 1803 uint8_t cmd_segs;
1550 1804 uint8_t cmd_cont_segs;
1551 1805
1552 1806 /* NVRAM configuration data */
1553 - uint32_t cfg_flags;
1807 + uint64_t cfg_flags;
1554 1808 ql_comb_init_cb_t init_ctrl_blk;
1555 1809 ql_comb_ip_init_cb_t ip_init_ctrl_blk;
1556 - uint16_t nvram_version;
1557 - uint16_t adapter_features;
1558 1810 uint32_t fw_transfer_size;
1811 + uint16_t adapter_features;
1559 1812 uint16_t execution_throttle;
1560 1813 uint16_t port_down_retry_count;
1814 + uint16_t serdes_param[4];
1815 + uint16_t maximum_luns_per_target;
1561 1816 uint8_t port_down_retry_delay;
1562 1817 uint8_t qfull_retry_count;
1563 1818 uint8_t qfull_retry_delay;
1564 - uint16_t serdes_param[4];
1565 1819 uint8_t loop_reset_delay;
1566 1820
1567 1821 /* Power management context. */
1568 1822 kmutex_t pm_mutex;
1569 - uint32_t busy;
1823 + uint32_t pm_busy;
1570 1824 uint8_t power_level;
1571 1825 uint8_t pm_capable;
1572 1826 uint8_t config_saved;
1573 1827 uint8_t lip_on_panic;
1574 - port_id_t port_hard_address;
1575 1828
1576 1829 /* sbus card data */
1577 1830 caddr_t sbus_fpga_iobase;
1578 1831 ddi_acc_handle_t sbus_fpga_dev_handle;
1579 1832 ddi_acc_handle_t sbus_config_handle;
1580 1833 caddr_t sbus_config_base;
1581 1834
1582 1835 /* XIOCTL context pointer. */
1583 1836 struct ql_xioctl *xioctl;
1584 1837
1585 - kmutex_t cache_mutex;
1586 1838 struct ql_fcache *fcache;
1587 1839 int8_t *vcache;
1840 + nvram_cache_desc_t *nvram_cache;
1588 1841
1589 - /* AIF (Advanced Interrupt Framework) support */
1590 - ddi_intr_handle_t *htable;
1591 - uint32_t hsize;
1592 - int32_t intr_cnt;
1593 - uint32_t intr_pri;
1594 - int32_t intr_cap;
1595 - uint32_t iflags;
1596 -
1597 - /* PCI maximum read request override */
1598 - uint16_t pci_max_read_req;
1599 -
1600 - /* port manage mutex */
1601 - kmutex_t portmutex;
1602 - uint16_t maximum_luns_per_target;
1603 -
1604 1842 /* f/w dump mutex */
1605 1843 uint32_t ql_dump_size;
1606 1844 uint32_t ql_dump_state;
1607 1845 void *ql_dump_ptr;
1608 1846 kmutex_t dump_mutex;
1609 1847
1610 1848 uint8_t fwwait;
1611 1849
1612 1850 dma_mem_t fwexttracebuf; /* extended trace */
1613 1851 dma_mem_t fwfcetracebuf; /* event trace */
1852 + ql_mbx_data_t fw_fce_trace_enable;
1614 1853 uint32_t fwfcetraceopt;
1615 1854 uint32_t flash_errlog_start; /* 32bit word addr */
1616 1855 uint32_t flash_errlog_ptr; /* 32bit word addr */
1617 1856 uint8_t send_plogi_timer;
1618 1857
1858 + /* Plogi retry parameters */
1859 + plogi_params_desc_t *plogi_params;
1860 +
1619 1861 /* Virtual port context. */
1620 1862 fca_port_attrs_t *pi_attrs;
1621 1863 struct ql_adapter_state *pha;
1622 1864 struct ql_adapter_state *vp_next;
1623 1865 uint8_t vp_index;
1866 + uint8_t max_vports;
1624 1867
1625 1868 uint16_t free_loop_id;
1626 1869
1627 1870 /* Tempoary N_Port information */
1628 1871 struct ql_n_port_info *n_port;
1629 1872
1630 - void (*els_cmd)(struct ql_adapter_state *,
1631 - ql_srb_t *, void *);
1632 - el_trace_desc_t *el_trace_desc;
1873 + ql_trace_desc_t *ql_trace_desc;
1633 1874
1634 1875 uint32_t flash_data_addr;
1635 1876 uint32_t flash_fw_addr;
1636 1877 uint32_t flash_golden_fw_addr;
1878 + uint32_t boot_code_addr;
1637 1879 uint32_t flash_vpd_addr;
1638 1880 uint32_t flash_nvram_addr;
1639 1881 uint32_t flash_desc_addr;
1640 1882 uint32_t mpi_capability_list;
1641 1883 uint8_t phy_fw_major_version;
1642 1884 uint8_t phy_fw_minor_version;
1643 1885 uint8_t phy_fw_subminor_version;
1644 1886 uint8_t mpi_fw_major_version;
1645 1887 uint8_t mpi_fw_minor_version;
1646 1888 uint8_t mpi_fw_subminor_version;
1647 1889
1648 - uint8_t idc_flash_acc;
1649 - uint8_t idc_restart_cnt;
1650 1890 uint16_t idc_mb[8];
1651 1891 uint8_t idc_restart_timer;
1652 - uint8_t idc_flash_acc_timer;
1653 1892
1654 1893 /* VLAN ID and MAC address */
1655 1894 uint8_t fcoe_vnport_mac[6];
1656 1895 uint16_t fabric_params;
1657 1896 uint16_t fcoe_vlan_id;
1658 1897 uint16_t fcoe_fcf_idx;
1659 - nvram_cache_desc_t *nvram_cache;
1660 1898
1661 1899 /* NetXen context */
1662 1900 ddi_acc_handle_t db_dev_handle;
1663 1901 caddr_t db_iobase;
1664 - uint64_t first_page_group_start;
1665 - uint64_t first_page_group_end;
1666 - uint64_t mn_win_crb;
1667 1902 caddr_t nx_pcibase; /* BAR0 base I/O address */
1668 - uint32_t crb_win;
1669 - uint32_t ddr_mn_window;
1670 1903 uint32_t qdr_sn_window;
1671 1904 uint32_t *nx_req_in;
1672 1905 caddr_t db_read;
1673 1906 uint32_t pci_bus_addr;
1674 1907 struct legacy_intr_set nx_legacy_intr;
1675 1908 uint32_t bootloader_size;
1676 1909 uint32_t bootloader_addr;
1677 1910 uint32_t flash_fw_size;
1911 + uint32_t dev_state;
1912 + uint32_t fw_heartbeat_counter;
1913 + dma_mem_t dmp_template;
1914 + uint32_t md_capture_mask;
1915 + uint32_t md_capture_size;
1678 1916 uint16_t iidma_rate;
1679 1917 uint8_t function_number;
1680 1918 uint8_t timeout_cnt;
1919 + uint8_t seconds_since_last_heartbeat;
1920 +
1921 + /* default dma attributes */
1922 + ddi_dma_attr_t bit32_io_dma_attr;
1923 + ddi_dma_attr_t bit64_io_dma_attr;
1924 +
1925 + ddi_dma_attr_t io_dma_attr;
1926 + ddi_dma_attr_t fcsm_cmd_dma_attr;
1927 + ddi_dma_attr_t fcsm_rsp_dma_attr;
1928 + ddi_dma_attr_t fcip_cmd_dma_attr;
1929 + ddi_dma_attr_t fcip_rsp_dma_attr;
1930 + ddi_dma_attr_t fcp_cmd_dma_attr;
1931 + ddi_dma_attr_t fcp_rsp_dma_attr;
1932 + ddi_dma_attr_t fcp_data_dma_attr;
1933 +
1934 + int fm_capabilities;
1935 + uint16_t errlog[4];
1681 1936 } ql_adapter_state_t;
1682 1937
1683 1938 /*
1684 1939 * adapter state flags
1685 1940 */
1686 -#define FCA_BOUND BIT_0
1687 -#define QL_OPENED BIT_1
1688 -#define ONLINE BIT_2
1689 -#define INTERRUPTS_ENABLED BIT_3
1690 -#define ABORT_CMDS_LOOP_DOWN_TMO BIT_4
1691 -#define POINT_TO_POINT BIT_5
1692 -#define IP_ENABLED BIT_6
1693 -#define IP_INITIALIZED BIT_7
1694 -#define MENLO_LOGIN_OPERATIONAL BIT_8
1695 -#define ADAPTER_SUSPENDED BIT_9
1696 -#define ADAPTER_TIMER_BUSY BIT_10
1697 -#define PARITY_ERROR BIT_11
1698 -#define FLASH_ERRLOG_MARKER BIT_12
1699 -#define VP_ENABLED BIT_13
1700 -#define FDISC_ENABLED BIT_14
1701 -#define FUNCTION_1 BIT_15
1702 -#define MPI_RESET_NEEDED BIT_16
1941 +#define FCA_BOUND (uint64_t)BIT_0
1942 +#define QL_OPENED (uint64_t)BIT_1
1943 +#define ONLINE (uint64_t)BIT_2
1944 +#define INTERRUPTS_ENABLED (uint64_t)BIT_3
1703 1945
1946 +#define ABORT_CMDS_LOOP_DOWN_TMO (uint64_t)BIT_4
1947 +#define POINT_TO_POINT (uint64_t)BIT_5
1948 +#define IP_ENABLED (uint64_t)BIT_6
1949 +#define IP_INITIALIZED (uint64_t)BIT_7
1950 +
1951 +#define MENLO_LOGIN_OPERATIONAL (uint64_t)BIT_8
1952 +#define ADAPTER_SUSPENDED (uint64_t)BIT_9
1953 +#define FW_DUMP_NEEDED (uint64_t)BIT_10
1954 +#define PARITY_ERROR (uint64_t)BIT_11
1955 +
1956 +#define FLASH_ERRLOG_MARKER (uint64_t)BIT_12
1957 +#define VP_ENABLED (uint64_t)BIT_13
1958 +#define FDISC_ENABLED (uint64_t)BIT_14
1959 +#define MULTI_QUEUE (uint64_t)BIT_15
1960 +
1961 +#define MPI_RESET_NEEDED (uint64_t)BIT_16
1962 +#define VP_ID_NOT_ACQUIRED (uint64_t)BIT_17
1963 +#define IDC_STALL_NEEDED (uint64_t)BIT_18
1964 +#define POLL_INTR (uint64_t)BIT_19
1965 +
1966 +#define IDC_RESTART_NEEDED (uint64_t)BIT_20
1967 +#define IDC_ACK_NEEDED (uint64_t)BIT_21
1968 +#define LOOPBACK_ACTIVE (uint64_t)BIT_22
1969 +#define QUEUE_SHADOW_PTRS (uint64_t)BIT_23
1970 +
1971 +#define NO_INTR_HANDSHAKE (uint64_t)BIT_24
1972 +#define COMP_THD_TERMINATE (uint64_t)BIT_25
1973 +#define DISABLE_NIC_FW_DMP (uint64_t)BIT_26
1974 +#define MULTI_CHIP_ADAPTER (uint64_t)BIT_27
1975 +
1704 1976 /*
1705 1977 * task daemon flags
1706 1978 */
1707 -#define TASK_DAEMON_STOP_FLG BIT_0
1708 -#define TASK_DAEMON_SLEEPING_FLG BIT_1
1709 -#define TASK_DAEMON_ALIVE_FLG BIT_2
1710 -#define TASK_DAEMON_IDLE_CHK_FLG BIT_3
1711 -#define SUSPENDED_WAKEUP_FLG BIT_4
1712 -#define FC_STATE_CHANGE BIT_5
1713 -#define NEED_UNSOLICITED_BUFFERS BIT_6
1714 -#define RESET_MARKER_NEEDED BIT_7
1715 -#define RESET_ACTIVE BIT_8
1716 -#define ISP_ABORT_NEEDED BIT_9
1717 -#define ABORT_ISP_ACTIVE BIT_10
1718 -#define LOOP_RESYNC_NEEDED BIT_11
1719 -#define LOOP_RESYNC_ACTIVE BIT_12
1720 -#define LOOP_DOWN BIT_13
1721 -#define DRIVER_STALL BIT_14
1722 -#define COMMAND_WAIT_NEEDED BIT_15
1723 -#define COMMAND_WAIT_ACTIVE BIT_16
1724 -#define STATE_ONLINE BIT_17
1725 -#define ABORT_QUEUES_NEEDED BIT_18
1726 -#define TASK_DAEMON_STALLED_FLG BIT_19
1727 -#define TASK_THREAD_CALLED BIT_20
1728 -#define FIRMWARE_UP BIT_21
1729 -#define LIP_RESET_PENDING BIT_22
1730 -#define FIRMWARE_LOADED BIT_23
1731 -#define RSCN_UPDATE_NEEDED BIT_24
1732 -#define HANDLE_PORT_BYPASS_CHANGE BIT_25
1733 -#define PORT_RETRY_NEEDED BIT_26
1734 -#define TASK_DAEMON_POWERING_DOWN BIT_27
1735 -#define TD_IIDMA_NEEDED BIT_28
1736 -#define SEND_PLOGI BIT_29
1737 -#define IDC_EVENT BIT_30
1979 +#define TASK_DAEMON_STOP_FLG (uint64_t)BIT_0
1980 +#define TASK_DAEMON_SLEEPING_FLG (uint64_t)BIT_1
1981 +#define TASK_DAEMON_ALIVE_FLG (uint64_t)BIT_2
1982 +#define TASK_DAEMON_IDLE_CHK_FLG (uint64_t)BIT_3
1738 1983
1984 +#define SUSPENDED_WAKEUP_FLG (uint64_t)BIT_4
1985 +#define FC_STATE_CHANGE (uint64_t)BIT_5
1986 +#define NEED_UNSOLICITED_BUFFERS (uint64_t)BIT_6
1987 +#define MARKER_NEEDED (uint64_t)BIT_7
1988 +
1989 +#define MARKER_ACTIVE (uint64_t)BIT_8
1990 +#define ISP_ABORT_NEEDED (uint64_t)BIT_9
1991 +#define ABORT_ISP_ACTIVE (uint64_t)BIT_10
1992 +#define LOOP_RESYNC_NEEDED (uint64_t)BIT_11
1993 +
1994 +#define LOOP_RESYNC_ACTIVE (uint64_t)BIT_12
1995 +#define LOOP_DOWN (uint64_t)BIT_13
1996 +#define DRIVER_STALL (uint64_t)BIT_14
1997 +#define COMMAND_WAIT_NEEDED (uint64_t)BIT_15
1998 +
1999 +#define COMMAND_WAIT_ACTIVE (uint64_t)BIT_16
2000 +#define STATE_ONLINE (uint64_t)BIT_17
2001 +#define ABORT_QUEUES_NEEDED (uint64_t)BIT_18
2002 +#define TASK_DAEMON_STALLED_FLG (uint64_t)BIT_19
2003 +
2004 +#define SEND_PLOGI (uint64_t)BIT_20
2005 +#define FIRMWARE_UP (uint64_t)BIT_21
2006 +#define IDC_POLL_NEEDED (uint64_t)BIT_22
2007 +#define FIRMWARE_LOADED (uint64_t)BIT_23
2008 +
2009 +#define RSCN_UPDATE_NEEDED (uint64_t)BIT_24
2010 +#define HANDLE_PORT_BYPASS_CHANGE (uint64_t)BIT_25
2011 +#define PORT_RETRY_NEEDED (uint64_t)BIT_26
2012 +#define TASK_DAEMON_POWERING_DOWN (uint64_t)BIT_27
2013 +
2014 +#define TD_IIDMA_NEEDED (uint64_t)BIT_28
2015 +#define WATCHDOG_NEEDED (uint64_t)BIT_29
2016 +#define LED_BLINK (uint64_t)BIT_30
2017 +
2018 +#define DTF_EL_MSG_SKIP_FLGS (IDC_POLL_NEEDED | WATCHDOG_NEEDED | \
2019 + TASK_DAEMON_IDLE_CHK_FLG | LED_BLINK)
1739 2020 /*
1740 2021 * Mailbox flags
1741 2022 */
1742 2023 #define MBX_WANT_FLG BIT_0
1743 2024 #define MBX_BUSY_FLG BIT_1
1744 2025 #define MBX_INTERRUPT BIT_2
1745 2026 #define MBX_ABORT BIT_3
1746 2027
1747 2028 /*
1748 2029 * Configuration flags
1749 2030 */
1750 -#define CFG_ENABLE_HARD_ADDRESS BIT_0
1751 -#define CFG_ENABLE_64BIT_ADDRESSING BIT_1
1752 -#define CFG_ENABLE_LIP_RESET BIT_2
1753 -#define CFG_ENABLE_FULL_LIP_LOGIN BIT_3
1754 -#define CFG_ENABLE_TARGET_RESET BIT_4
1755 -#define CFG_ENABLE_LINK_DOWN_REPORTING BIT_5
1756 -#define CFG_DISABLE_EXTENDED_LOGGING_TRACE BIT_6
1757 -#define CFG_ENABLE_FCP_2_SUPPORT BIT_7
1758 -#define CFG_MULTI_CHIP_ADAPTER BIT_8
1759 -#define CFG_SBUS_CARD BIT_9
1760 -#define CFG_CTRL_2300 BIT_10
1761 -#define CFG_CTRL_6322 BIT_11
1762 -#define CFG_CTRL_2200 BIT_12
1763 -#define CFG_CTRL_2422 BIT_13
1764 -#define CFG_CTRL_25XX BIT_14
1765 -#define CFG_ENABLE_EXTENDED_LOGGING BIT_15
1766 -#define CFG_DISABLE_RISC_CODE_LOAD BIT_16
1767 -#define CFG_SET_CACHE_LINE_SIZE_1 BIT_17
1768 -#define CFG_CTRL_MENLO BIT_18
1769 -#define CFG_EXT_FW_INTERFACE BIT_19
1770 -#define CFG_LOAD_FLASH_FW BIT_20
1771 -#define CFG_DUMP_MAILBOX_TIMEOUT BIT_21
1772 -#define CFG_DUMP_ISP_SYSTEM_ERROR BIT_22
1773 -#define CFG_DUMP_DRIVER_COMMAND_TIMEOUT BIT_23
1774 -#define CFG_DUMP_LOOP_OFFLINE_TIMEOUT BIT_24
1775 -#define CFG_ENABLE_FWEXTTRACE BIT_25
1776 -#define CFG_ENABLE_FWFCETRACE BIT_26
1777 -#define CFG_FW_MISMATCH BIT_27
1778 -#define CFG_CTRL_81XX BIT_28
1779 -#define CFG_CTRL_8021 BIT_29
1780 -#define CFG_FAST_TIMEOUT BIT_30
1781 -#define CFG_LR_SUPPORT BIT_31
2031 +#define CFG_CTRL_27XX (uint64_t)BIT_0
2032 +#define CFG_ENABLE_64BIT_ADDRESSING (uint64_t)BIT_1
2033 +#define CFG_ENABLE_LIP_RESET (uint64_t)BIT_2
2034 +#define CFG_ENABLE_FULL_LIP_LOGIN (uint64_t)BIT_3
1782 2035
1783 -#define CFG_CTRL_2425 (CFG_CTRL_2422 | CFG_CTRL_25XX)
1784 -#define CFG_CTRL_8081 (CFG_CTRL_8021 | CFG_CTRL_81XX)
1785 -#define CFG_CTRL_2581 (CFG_CTRL_25XX | CFG_CTRL_81XX)
1786 -#define CFG_CTRL_242581 (CFG_CTRL_2422 | CFG_CTRL_25XX | CFG_CTRL_81XX)
1787 -#define CFG_CTRL_24258081 (CFG_CTRL_2425 | CFG_CTRL_8081)
1788 -#define CFG_CTRL_258081 (CFG_CTRL_25XX | CFG_CTRL_8081)
1789 -#define CFG_CTRL_2480 (CFG_CTRL_2422 | CFG_CTRL_8021)
2036 +#define CFG_ENABLE_TARGET_RESET (uint64_t)BIT_4
2037 +#define CFG_ENABLE_LINK_DOWN_REPORTING (uint64_t)BIT_5
2038 +#define CFG_LR_SUPPORT (uint64_t)BIT_6
2039 +#define CFG_ENABLE_FCP_2_SUPPORT (uint64_t)BIT_7
1790 2040
1791 -#define CFG_IST(ha, cfgflags) (ha->cfg_flags & cfgflags)
2041 +#define CFG_CTRL_83XX (uint64_t)BIT_8
2042 +#define CFG_SBUS_CARD (uint64_t)BIT_9
2043 +#define CFG_CTRL_23XX (uint64_t)BIT_10
2044 +#define CFG_CTRL_63XX (uint64_t)BIT_11
1792 2045
2046 +#define CFG_CTRL_22XX (uint64_t)BIT_12
2047 +#define CFG_CTRL_24XX (uint64_t)BIT_13
2048 +#define CFG_CTRL_25XX (uint64_t)BIT_14
2049 +#define CFG_ENABLE_EXTENDED_LOGGING (uint64_t)BIT_15
2050 +
2051 +#define CFG_DISABLE_RISC_CODE_LOAD (uint64_t)BIT_16
2052 +#define CFG_SET_CACHE_LINE_SIZE_1 (uint64_t)BIT_17
2053 +#define CFG_CTRL_MENLO (uint64_t)BIT_18
2054 +#define CFG_EXT_FW_INTERFACE (uint64_t)BIT_19
2055 +
2056 +#define CFG_LOAD_FLASH_FW (uint64_t)BIT_20
2057 +#define CFG_DUMP_MAILBOX_TIMEOUT (uint64_t)BIT_21
2058 +#define CFG_DUMP_ISP_SYSTEM_ERROR (uint64_t)BIT_22
2059 +#define CFG_DUMP_DRIVER_COMMAND_TIMEOUT (uint64_t)BIT_23
2060 +
2061 +#define CFG_DUMP_LOOP_OFFLINE_TIMEOUT (uint64_t)BIT_24
2062 +#define CFG_ENABLE_FWEXTTRACE (uint64_t)BIT_25
2063 +#define CFG_ENABLE_FWFCETRACE (uint64_t)BIT_26
2064 +#define CFG_CTRL_80XX (uint64_t)BIT_27
2065 +
2066 +#define CFG_CTRL_81XX (uint64_t)BIT_28
2067 +#define CFG_CTRL_82XX (uint64_t)BIT_29
2068 +#define CFG_FAST_TIMEOUT (uint64_t)BIT_30
2069 +
2070 +#define CFG_CTRL_2363 (CFG_CTRL_23XX | CFG_CTRL_63XX)
2071 +#define CFG_CTRL_2425 (CFG_CTRL_24XX | CFG_CTRL_25XX)
2072 +#define CFG_CTRL_2783 (CFG_CTRL_27XX | CFG_CTRL_83XX)
2073 +#define CFG_CTRL_8081 (CFG_CTRL_80XX | CFG_CTRL_81XX)
2074 +#define CFG_CTRL_278083 (CFG_CTRL_80XX | CFG_CTRL_2783)
2075 +#define CFG_CTRL_27808183 (CFG_CTRL_8081 | CFG_CTRL_2783)
2076 +#define CFG_CTRL_2527808183 (CFG_CTRL_25XX | CFG_CTRL_27808183)
2077 +#define CFG_CTRL_252780818283 (CFG_CTRL_82XX | CFG_CTRL_2527808183)
2078 +
2079 +#define CFG_ISP_FW_TYPE_1 (CFG_CTRL_22XX | CFG_CTRL_2363)
2080 +#define CFG_ISP_FW_TYPE_2 (CFG_CTRL_24XX | CFG_CTRL_252780818283)
2081 +#define CFG_FCIP_TYPE_1 (CFG_CTRL_22XX | CFG_CTRL_23XX)
2082 +#define CFG_FCIP_SUPPORT (CFG_FCIP_TYPE_1 | CFG_CTRL_24XX)
2083 +#define CFG_FCOE_SUPPORT (CFG_CTRL_82XX | CFG_CTRL_8081)
2084 +#define CFG_N2N_SUPPORT (CFG_CTRL_2425 | CFG_CTRL_2783)
2085 +#define CFG_FC_TYPE_1 (CFG_CTRL_22XX | CFG_CTRL_2363)
2086 +#define CFG_FC_TYPE_2 (CFG_CTRL_2425 | CFG_CTRL_2783)
2087 +#define CFG_FC_TYPE (CFG_FC_TYPE_1 | CFG_FC_TYPE_2)
2088 +#define CFG_NO_INTR_HSHAKE_SUP (CFG_CTRL_27808183)
2089 +#define CFG_MWB_4096_SUPPORT (CFG_CTRL_2425 | CFG_CTRL_81XX)
2090 +#define CFG_IIDMA_SUPPORT (CFG_CTRL_8081 | CFG_FC_TYPE_2)
2091 +#define CFG_FLASH_ACC_SUPPORT (CFG_CTRL_27808183)
2092 +#define CFG_FLASH_DMA_SUPPORT (CFG_CTRL_2527808183)
2093 +#define CFG_LOOP_POINT_SUPPORT (CFG_CTRL_8081)
2094 +#define CFG_LB_ECHO_SUPPORT (CFG_CTRL_2363 | CFG_ISP_FW_TYPE_2)
2095 +#define CFG_SET_LEDS_SUPPORT (CFG_CTRL_2363 | CFG_ISP_FW_TYPE_2)
2096 +#define CFG_SERDES_SUPPORT (CFG_CTRL_2783)
2097 +#define CFG_BBCR_SUPPORT (CFG_CTRL_2783)
2098 +#define CFG_MSI_SUPPORT (CFG_CTRL_2425 | CFG_CTRL_81XX | CFG_CTRL_82XX)
2099 +
2100 +
2101 +#define CFG_IST(ha, cfgflags) (ha->cfg_flags & (cfgflags))
2102 +
1793 2103 /*
1794 2104 * Interrupt configuration flags
1795 2105 */
1796 2106 #define IFLG_INTR_LEGACY BIT_0
1797 2107 #define IFLG_INTR_FIXED BIT_1
1798 2108 #define IFLG_INTR_MSI BIT_2
1799 2109 #define IFLG_INTR_MSIX BIT_3
1800 2110
1801 2111 #define IFLG_INTR_AIF (IFLG_INTR_MSI | IFLG_INTR_FIXED | IFLG_INTR_MSIX)
1802 2112
1803 2113 /*
1804 2114 * Macros to help code, maintain, etc.
1805 2115 */
1806 2116 #define LSB(x) (uint8_t)(x)
1807 2117 #define MSB(x) (uint8_t)((uint16_t)(x) >> 8)
1808 2118 #define MSW(x) (uint16_t)((uint32_t)(x) >> 16)
1809 2119 #define LSW(x) (uint16_t)(x)
1810 2120 #define LSD(x) (uint32_t)(x)
1811 2121 #define MSD(x) (uint32_t)((uint64_t)(x) >> 32)
1812 2122
1813 -#define SHORT_TO_LONG(lsw, msw) (uint32_t)((uint16_t)msw << 16 | (uint16_t)lsw)
1814 -#define CHAR_TO_SHORT(lsb, msb) (uint16_t)((uint8_t)msb << 8 | (uint8_t)lsb)
2123 +#define LONG_TO_LLONG(lsl, msl) (uint64_t)((uint64_t)(msl) << 32 | \
2124 + (uint32_t)(lsl))
2125 +#define SHORT_TO_LONG(lsw, msw) (uint32_t)((uint32_t)msw << 16 | (uint16_t)lsw)
2126 +#define CHAR_TO_SHORT(lsb, msb) (uint16_t)((uint16_t)msb << 8 | (uint8_t)lsb)
1815 2127 #define CHAR_TO_LONG(lsb, b1, b2, msb) \
1816 2128 (uint32_t)(SHORT_TO_LONG(CHAR_TO_SHORT(lsb, b1), \
1817 2129 CHAR_TO_SHORT(b2, msb)))
1818 2130
1819 2131 /* Little endian machine correction defines. */
1820 2132 #ifdef _LITTLE_ENDIAN
1821 2133 #define LITTLE_ENDIAN_16(x)
1822 2134 #define LITTLE_ENDIAN_24(x)
1823 2135 #define LITTLE_ENDIAN_32(x)
1824 2136 #define LITTLE_ENDIAN_64(x)
1825 2137 #define LITTLE_ENDIAN(bp, bytes)
1826 2138 #define BIG_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2)
1827 2139 #define BIG_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3)
1828 2140 #define BIG_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4)
1829 2141 #define BIG_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8)
1830 2142 #define BIG_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes)
1831 2143 #endif /* _LITTLE_ENDIAN */
1832 2144
1833 2145 /* Big endian machine correction defines. */
1834 2146 #ifdef _BIG_ENDIAN
1835 2147 #define LITTLE_ENDIAN_16(x) ql_chg_endian((uint8_t *)x, 2)
1836 2148 #define LITTLE_ENDIAN_24(x) ql_chg_endian((uint8_t *)x, 3)
1837 2149 #define LITTLE_ENDIAN_32(x) ql_chg_endian((uint8_t *)x, 4)
1838 2150 #define LITTLE_ENDIAN_64(x) ql_chg_endian((uint8_t *)x, 8)
1839 2151 #define LITTLE_ENDIAN(bp, bytes) ql_chg_endian((uint8_t *)bp, bytes)
1840 2152 #define BIG_ENDIAN_16(x)
1841 2153 #define BIG_ENDIAN_24(x)
1842 2154 #define BIG_ENDIAN_32(x)
1843 2155 #define BIG_ENDIAN_64(x)
1844 2156 #define BIG_ENDIAN(bp, bytes)
1845 2157 #endif /* _BIG_ENDIAN */
1846 2158
1847 2159 #define LOCAL_LOOP_ID(x) (x <= LAST_LOCAL_LOOP_ID)
1848 2160
1849 2161 #define FABRIC_LOOP_ID(x) (x == FL_PORT_LOOP_ID || \
1850 2162 x == SIMPLE_NAME_SERVER_LOOP_ID)
1851 2163
1852 2164 #define SNS_LOOP_ID(x) (x >= SNS_FIRST_LOOP_ID && \
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1853 2165 x <= SNS_LAST_LOOP_ID)
1854 2166
1855 2167 #define BROADCAST_LOOP_ID(x) (x == IP_BROADCAST_LOOP_ID)
1856 2168
1857 2169 #define VALID_LOOP_ID(x) (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x) || \
1858 2170 FABRIC_LOOP_ID(x) || BROADCAST_LOOP_ID(x))
1859 2171
1860 2172 #define VALID_N_PORT_HDL(x) (x <= LAST_N_PORT_HDL || \
1861 2173 (x >= SNS_24XX_HDL && x <= BROADCAST_24XX_HDL))
1862 2174
1863 -#define VALID_DEVICE_ID(ha, x) (CFG_IST(ha, CFG_CTRL_24258081) ? \
2175 +#define VALID_DEVICE_ID(ha, x) (CFG_IST(ha, CFG_ISP_FW_TYPE_2) ? \
1864 2176 VALID_N_PORT_HDL(x) : VALID_LOOP_ID(x))
1865 2177
1866 -#define VALID_TARGET_ID(ha, x) (CFG_IST(ha, CFG_CTRL_24258081) ? \
2178 +#define VALID_TARGET_ID(ha, x) (CFG_IST(ha, CFG_ISP_FW_TYPE_2) ? \
1867 2179 (x <= LAST_N_PORT_HDL) : (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x)))
1868 2180
1869 -#define RESERVED_LOOP_ID(ha, x) (CFG_IST(ha, CFG_CTRL_24258081) ? \
2181 +#define RESERVED_LOOP_ID(ha, x) (CFG_IST(ha, CFG_ISP_FW_TYPE_2) ? \
1870 2182 (x > LAST_N_PORT_HDL && x <= FL_PORT_24XX_HDL) : \
1871 2183 (x >= FL_PORT_LOOP_ID && x <= SIMPLE_NAME_SERVER_LOOP_ID))
1872 2184
1873 -#define QL_LOOP_TRANSITION (RESET_MARKER_NEEDED | RESET_ACTIVE | \
2185 +#define QL_LOOP_TRANSITION (MARKER_NEEDED | MARKER_ACTIVE | \
1874 2186 ISP_ABORT_NEEDED | ABORT_ISP_ACTIVE | \
1875 2187 LOOP_RESYNC_NEEDED | LOOP_RESYNC_ACTIVE | \
1876 2188 COMMAND_WAIT_NEEDED | COMMAND_WAIT_ACTIVE)
1877 2189
1878 -#define QL_SUSPENDED (QL_LOOP_TRANSITION | LOOP_DOWN | DRIVER_STALL)
1879 -
1880 2190 #define LOOP_RECONFIGURE(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \
1881 2191 DRIVER_STALL))
1882 2192
1883 -#define DRIVER_SUSPENDED(ha) (ha->task_daemon_flags & QL_SUSPENDED)
2193 +#define DRIVER_SUSPENDED(ha) (ha->task_daemon_flags & (LOOP_DOWN | \
2194 + QL_LOOP_TRANSITION | DRIVER_STALL))
1884 2195
1885 2196 #define LOOP_NOT_READY(ha) (ha->task_daemon_flags & (QL_LOOP_TRANSITION | \
1886 2197 LOOP_DOWN))
1887 2198
1888 2199 #define LOOP_READY(ha) (LOOP_NOT_READY(ha) == 0)
1889 2200
1890 2201 #define QL_TASK_PENDING(ha) ( \
1891 2202 ha->task_daemon_flags & (QL_LOOP_TRANSITION | ABORT_QUEUES_NEEDED | \
1892 - PORT_RETRY_NEEDED) || ha->callback_queue.first != NULL)
2203 + PORT_RETRY_NEEDED) || ha->unsol_callback_queue.first != NULL)
1893 2204
1894 2205 #define QL_DAEMON_NOT_ACTIVE(ha) ( \
1895 2206 !(ha->task_daemon_flags & TASK_DAEMON_ALIVE_FLG) || \
1896 2207 ha->task_daemon_flags & (TASK_DAEMON_SLEEPING_FLG | \
1897 2208 TASK_DAEMON_STOP_FLG))
1898 2209
1899 -#define QL_DAEMON_SUSPENDED(ha) (\
1900 - (((ha)->cprinfo.cc_events & CALLB_CPR_START) ||\
1901 - ((ha)->flags & ADAPTER_SUSPENDED)))
2210 +#define QL_ABORTED_SRB(ha) ((ql_srb_t *)ha)
1902 2211
1903 -#define INTERRUPT_PENDING(ha) (CFG_IST(ha, CFG_CTRL_8021) ? \
2212 +#define INTERRUPT_PENDING(ha) (CFG_IST(ha, CFG_CTRL_82XX) ? \
1904 2213 RD32_IO_REG(ha, nx_risc_int) & NX_RISC_INT : \
1905 2214 RD16_IO_REG(ha, istatus) & RISC_INT)
1906 -
1907 -#define QL_MAX_FRAME_SIZE(ha) \
1908 - (uint16_t)(CFG_IST(ha, CFG_CTRL_24258081) ? CHAR_TO_SHORT( \
1909 - ha->init_ctrl_blk.cb24.max_frame_length[0], \
1910 - ha->init_ctrl_blk.cb24.max_frame_length[1]) : CHAR_TO_SHORT( \
1911 - ha->init_ctrl_blk.cb.max_frame_length[0], \
1912 - ha->init_ctrl_blk.cb.max_frame_length[1]))
1913 -
1914 2215 /*
1915 2216 * Locking Macro Definitions
1916 2217 */
1917 2218 #define GLOBAL_STATE_LOCK() mutex_enter(&ql_global_mutex)
1918 2219 #define GLOBAL_STATE_UNLOCK() mutex_exit(&ql_global_mutex)
1919 2220
2221 +#define GLOBAL_TIMER_LOCK() mutex_enter(&ql_global_timer_mutex)
2222 +#define GLOBAL_TIMER_UNLOCK() mutex_exit(&ql_global_timer_mutex)
2223 +
1920 2224 #define TRY_DEVICE_QUEUE_LOCK(q) mutex_tryenter(&q->mutex)
1921 2225 #define DEVICE_QUEUE_LOCK(q) mutex_enter(&q->mutex)
1922 2226 #define DEVICE_QUEUE_UNLOCK(q) mutex_exit(&q->mutex)
1923 2227
1924 2228 #define TRY_MBX_REGISTER_LOCK(ha) mutex_tryenter(&ha->pha->mbx_mutex)
1925 2229 #define MBX_REGISTER_LOCK_OWNER(ha) mutex_owner(&ha->pha->mbx_mutex)
1926 2230 #define MBX_REGISTER_LOCK(ha) mutex_enter(&ha->pha->mbx_mutex)
1927 2231 #define MBX_REGISTER_UNLOCK(ha) mutex_exit(&ha->pha->mbx_mutex)
1928 2232
1929 -#define INTR_LOCK(ha) mutex_enter(&ha->pha->intr_mutex)
1930 -#define INTR_UNLOCK(ha) mutex_exit(&ha->pha->intr_mutex)
2233 +#define INTR_LOCK(ha) ql_intr_lock(ha->pha)
2234 +#define INTR_UNLOCK(ha) ql_intr_unlock(ha->pha)
1931 2235
2236 +#define INDX_INTR_LOCK(ha, i) mutex_enter(&ha->pha->rsp_queues[i]->intr_mutex)
2237 +#define INDX_INTR_UNLOCK(ha, i) mutex_exit(&ha->pha->rsp_queues[i]->intr_mutex)
2238 +
1932 2239 #define TASK_DAEMON_LOCK(ha) mutex_enter(&ha->pha->task_daemon_mutex)
1933 2240 #define TASK_DAEMON_UNLOCK(ha) mutex_exit(&ha->pha->task_daemon_mutex)
1934 2241
1935 2242 #define REQUEST_RING_LOCK(ha) mutex_enter(&ha->pha->req_ring_mutex)
1936 2243 #define REQUEST_RING_UNLOCK(ha) mutex_exit(&ha->pha->req_ring_mutex)
1937 2244
1938 -#define CACHE_LOCK(ha) mutex_enter(&ha->pha->cache_mutex);
1939 -#define CACHE_UNLOCK(ha) mutex_exit(&ha->pha->cache_mutex);
2245 +#define COMP_Q_LOCK(ha) mutex_enter(&ha->pha->comp_q_mutex)
2246 +#define COMP_Q_UNLOCK(ha) mutex_exit(&ha->pha->comp_q_mutex)
1940 2247
1941 -#define PORTMANAGE_LOCK(ha) mutex_enter(&ha->pha->portmutex);
1942 -#define PORTMANAGE_UNLOCK(ha) mutex_exit(&ha->pha->portmutex);
1943 -
1944 2248 #define ADAPTER_STATE_LOCK(ha) mutex_enter(&ha->pha->mutex)
1945 2249 #define ADAPTER_STATE_UNLOCK(ha) mutex_exit(&ha->pha->mutex)
1946 2250
1947 2251 #define QL_DUMP_LOCK(ha) mutex_enter(&ha->pha->dump_mutex)
1948 2252 #define QL_DUMP_UNLOCK(ha) mutex_exit(&ha->pha->dump_mutex)
1949 2253
1950 2254 #define QL_PM_LOCK(ha) mutex_enter(&ha->pha->pm_mutex)
1951 2255 #define QL_PM_UNLOCK(ha) mutex_exit(&ha->pha->pm_mutex)
1952 2256
1953 2257 #define QL_UB_LOCK(ha) mutex_enter(&ha->pha->ub_mutex)
1954 2258 #define QL_UB_UNLOCK(ha) mutex_exit(&ha->pha->ub_mutex)
1955 2259
1956 2260 #define GLOBAL_HW_LOCK() mutex_enter(&ql_global_hw_mutex)
1957 2261 #define GLOBAL_HW_UNLOCK() mutex_exit(&ql_global_hw_mutex)
1958 2262
1959 -#define NVRAM_CACHE_LOCK(ha) mutex_enter(&ha->nvram_cache->mutex);
1960 -#define NVRAM_CACHE_UNLOCK(ha) mutex_exit(&ha->nvram_cache->mutex);
1961 -
1962 2263 /*
1963 2264 * PCI power management control/status register location
1964 2265 */
1965 2266 #define QL_PM_CS_REG 0x48
1966 2267
1967 2268 /*
1968 2269 * ql component
1969 2270 */
1970 2271 #define QL_POWER_COMPONENT 0
1971 2272
1972 2273 typedef struct ql_config_space {
1973 2274 uint16_t chs_command;
1974 2275 uint8_t chs_cache_line_size;
1975 2276 uint8_t chs_latency_timer;
1976 2277 uint8_t chs_header_type;
1977 2278 uint8_t chs_sec_latency_timer;
1978 2279 uint8_t chs_bridge_control;
1979 2280 uint32_t chs_base0;
1980 2281 uint32_t chs_base1;
1981 2282 uint32_t chs_base2;
1982 2283 uint32_t chs_base3;
1983 2284 uint32_t chs_base4;
1984 2285 uint32_t chs_base5;
1985 2286 } ql_config_space_t;
1986 2287
1987 2288 #ifdef USE_DDI_INTERFACES
1988 2289
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1989 2290 #define QL_SAVE_CONFIG_REGS(dip) pci_save_config_regs(dip)
1990 2291 #define QL_RESTORE_CONFIG_REGS(dip) pci_restore_config_regs(dip)
1991 2292
1992 2293 #else /* USE_DDI_INTERFACES */
1993 2294
1994 2295 #define QL_SAVE_CONFIG_REGS(dip) ql_save_config_regs(dip)
1995 2296 #define QL_RESTORE_CONFIG_REGS(dip) ql_restore_config_regs(dip)
1996 2297
1997 2298 #endif /* USE_DDI_INTERFACES */
1998 2299
1999 -#define QL_IS_SET(x, y) (((x) & (y)) == (y))
2000 -
2001 2300 /*
2002 2301 * QL local function return status codes
2003 2302 */
2004 2303 #define QL_SUCCESS 0x4000
2005 2304 #define QL_INVALID_COMMAND 0x4001
2006 2305 #define QL_INTERFACE_ERROR 0x4002
2007 2306 #define QL_TEST_FAILED 0x4003
2008 2307 #define QL_COMMAND_ERROR 0x4005
2009 2308 #define QL_PARAMETER_ERROR 0x4006
2010 2309 #define QL_PORT_ID_USED 0x4007
2011 2310 #define QL_LOOP_ID_USED 0x4008
2012 2311 #define QL_ALL_IDS_IN_USE 0x4009
2013 2312 #define QL_NOT_LOGGED_IN 0x400A
2014 2313 #define QL_LOOP_DOWN 0x400B
2015 2314 #define QL_LOOP_BACK_ERROR 0x400C
2016 2315 #define QL_CHECKSUM_ERROR 0x4010
2017 2316 #define QL_CONSUMED 0x4011
2018 2317
2019 2318 #define QL_FUNCTION_TIMEOUT 0x100
2020 2319 #define QL_FUNCTION_PARAMETER_ERROR 0x101
2021 2320 #define QL_FUNCTION_FAILED 0x102
2022 2321 #define QL_MEMORY_ALLOC_FAILED 0x103
2023 2322 #define QL_FABRIC_NOT_INITIALIZED 0x104
2024 2323 #define QL_LOCK_TIMEOUT 0x105
2025 2324 #define QL_ABORTED 0x106
2026 2325 #define QL_FUNCTION_SUSPENDED 0x107
2027 2326 #define QL_END_OF_DATA 0x108
2028 2327 #define QL_IP_UNSUPPORTED 0x109
2029 2328 #define QL_PM_ERROR 0x10a
2030 2329 #define QL_DATA_EXISTS 0x10b
2031 2330 #define QL_NOT_SUPPORTED 0x10c
2032 2331 #define QL_MEMORY_FULL 0x10d
2033 2332 #define QL_FW_NOT_SUPPORTED 0x10e
2034 2333 #define QL_FWMODLOAD_FAILED 0x10f
2035 2334 #define QL_FWSYM_NOT_FOUND 0x110
2036 2335 #define QL_LOGIN_NOT_SUPPORTED 0x111
2037 2336
2038 2337 /*
2039 2338 * SBus card FPGA register offsets.
2040 2339 */
2041 2340 #define FPGA_CONF 0x100
2042 2341 #define FPGA_EEPROM_LOADDR 0x102
2043 2342 #define FPGA_EEPROM_HIADDR 0x104
2044 2343 #define FPGA_EEPROM_DATA 0x106
2045 2344 #define FPGA_REVISION 0x108
2046 2345
2047 2346 #define SBUS_FLASH_WRITE_ENABLE 0x0080
2048 2347 #define QL_SBUS_FCODE_SIZE 0x30000
2049 2348 #define QL_FCODE_OFFSET 0
2050 2349 #define QL_FPGA_SIZE 0x40000
2051 2350 #define QL_FPGA_OFFSET 0x40000
2052 2351
2053 2352 #define READ_PORT_ID(addr) ((uint32_t)((((uint32_t)((addr)[0])) << 16) | \
2054 2353 (((uint32_t)((addr)[1])) << 8) | \
2055 2354 (((uint32_t)((addr)[2])))))
2056 2355 #define READ_PORT_NAME(addr) ((u_longlong_t)((((uint64_t)((addr)[0])) << 56) | \
2057 2356 (((uint64_t)((addr)[1])) << 48) | \
2058 2357 (((uint64_t)((addr)[2])) << 40) | \
2059 2358 (((uint64_t)((addr)[3])) << 32) | \
2060 2359 (((uint64_t)((addr)[4])) << 24) | \
2061 2360 (((uint64_t)((addr)[5])) << 16) | \
2062 2361 (((uint64_t)((addr)[6])) << 8) | \
2063 2362 (((uint64_t)((addr)[7])))))
2064 2363 /*
2065 2364 * Structure used to associate cmds with strings which describe them.
2066 2365 */
2067 2366 typedef struct cmd_table_entry {
2068 2367 uint16_t cmd;
2069 2368 char *string;
2070 2369 } cmd_table_t;
2071 2370
2072 2371 /*
2073 2372 * ELS command table initializer
2074 2373 */
2075 2374 #define ELS_CMD_TABLE() \
2076 2375 { \
2077 2376 {LA_ELS_RJT, "LA_ELS_RJT"}, \
2078 2377 {LA_ELS_ACC, "LA_ELS_ACC"}, \
2079 2378 {LA_ELS_PLOGI, "LA_ELS_PLOGI"}, \
2080 2379 {LA_ELS_PDISC, "LA_ELS_PDISC"}, \
2081 2380 {LA_ELS_FLOGI, "LA_ELS_FLOGI"}, \
2082 2381 {LA_ELS_FDISC, "LA_ELS_FDISC"}, \
2083 2382 {LA_ELS_LOGO, "LA_ELS_LOGO"}, \
2084 2383 {LA_ELS_PRLI, "LA_ELS_PRLI"}, \
2085 2384 {LA_ELS_PRLO, "LA_ELS_PRLO"}, \
2086 2385 {LA_ELS_ADISC, "LA_ELS_ADISC"}, \
2087 2386 {LA_ELS_LINIT, "LA_ELS_LINIT"}, \
2088 2387 {LA_ELS_LPC, "LA_ELS_LPC"}, \
2089 2388 {LA_ELS_LSTS, "LA_ELS_LSTS"}, \
2090 2389 {LA_ELS_SCR, "LA_ELS_SCR"}, \
2091 2390 {LA_ELS_RSCN, "LA_ELS_RSCN"}, \
2092 2391 {LA_ELS_FARP_REQ, "LA_ELS_FARP_REQ"}, \
2093 2392 {LA_ELS_FARP_REPLY, "LA_ELS_FARP_REPLY"}, \
2094 2393 {LA_ELS_RLS, "LA_ELS_RLS"}, \
2095 2394 {LA_ELS_RNID, "LA_ELS_RNID"}, \
2096 2395 {NULL, NULL} \
2097 2396 }
2098 2397
2099 2398 /*
2100 2399 * ELS Passthru IOCB data segment descriptor.
2101 2400 */
2102 2401 typedef struct data_seg_desc {
2103 2402 uint32_t addr[2];
2104 2403 uint32_t length;
2105 2404 } data_seg_desc_t;
2106 2405
2107 2406 /*
2108 2407 * ELS descriptor used to abstract the hosts fibre channel packet
2109 2408 * from the ISP ELS code.
2110 2409 */
2111 2410 typedef struct els_desc {
2112 2411 uint8_t els; /* the ELS command code */
2113 2412 ddi_acc_handle_t els_handle;
2114 2413 uint16_t n_port_handle;
2115 2414 port_id_t d_id;
2116 2415 port_id_t s_id;
2117 2416 uint16_t control_flags;
2118 2417 uint32_t cmd_byte_count;
2119 2418 uint32_t rsp_byte_count;
2120 2419 data_seg_desc_t tx_dsd; /* FC frame payload */
2121 2420 data_seg_desc_t rx_dsd; /* ELS resp payload buffer */
2122 2421 } els_descriptor_t;
2123 2422
2124 2423 typedef struct prli_svc_pram_resp_page {
2125 2424 uint8_t type_code;
2126 2425 uint8_t type_code_ext;
2127 2426 uint16_t prli_resp_flags;
2128 2427 uint32_t orig_process_associator;
2129 2428 uint32_t resp_process_associator;
2130 2429 uint32_t common_parameters;
2131 2430 } prli_svc_pram_resp_page_t;
2132 2431
2133 2432 /*
2134 2433 * PRLI accept Service Parameter Page Word 3
2135 2434 */
2136 2435 #define PRLI_W3_WRITE_FCP_XFR_RDY_DISABLED BIT_0
2137 2436 #define PRLI_W3_READ_FCP_XFR_RDY_DISABLED BIT_1
2138 2437 #define PRLI_W3_OBSOLETE_BIT_2 BIT_2
2139 2438 #define PRLI_W3_OBSOLETE_BIT_3 BIT_3
2140 2439 #define PRLI_W3_TARGET_FUNCTION BIT_4
2141 2440 #define PRLI_W3_INITIATOR_FUNCTION BIT_5
2142 2441 #define PRLI_W3_DATA_OVERLAY_ALLOWED BIT_6
2143 2442 #define PRLI_W3_CONFIRMED_COMP_ALLOWED BIT_7
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2144 2443 #define PRLI_W3_RETRY BIT_8
2145 2444 #define PRLI_W3_TASK_RETRY_ID_REQUESTED BIT_9
2146 2445
2147 2446 typedef struct prli_acc_resp {
2148 2447 uint8_t ls_code;
2149 2448 uint8_t page_length;
2150 2449 uint16_t payload_length;
2151 2450 struct prli_svc_pram_resp_page svc_params;
2152 2451 } prli_acc_resp_t;
2153 2452
2154 -#define EL_TRACE_BUF_SIZE 8192
2453 +#define EL_TRACE_BUF_SIZE 8192
2155 2454
2455 +#define QL_PORT_ID_MASK 0xffffff
2456 +
2457 +#define QL_PLOGI_RETRY_CNT (5)
2458 +#define QL_PLOGI_RETRY_DLY_USEC (10 * MILLISEC)
2459 +
2156 2460 /*
2157 2461 * Global Data in ql_api.c source file.
2158 2462 */
2159 2463 extern void *ql_state; /* for soft state routine */
2160 2464 extern uint32_t ql_os_release_level;
2161 2465 extern ql_head_t ql_hba;
2162 2466 extern kmutex_t ql_global_mutex;
2163 2467 extern kmutex_t ql_global_hw_mutex;
2164 2468 extern kmutex_t ql_global_el_mutex;
2165 2469 extern uint8_t ql_ip_fast_post_count;
2166 2470 extern uint32_t ql_ip_buffer_count;
2167 2471 extern uint32_t ql_ip_low_water;
2168 2472 extern uint8_t ql_alpa_to_index[];
2169 2473 extern uint32_t ql_gfru_hba_index;
2170 2474 extern uint32_t ql_enable_ets;
2171 2475 extern uint16_t ql_osc_wait_count;
2172 2476
2173 2477 /*
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2174 2478 * Global Function Prototypes in ql_api.c source file.
2175 2479 */
2176 2480 void ql_chg_endian(uint8_t *, size_t);
2177 2481 void ql_populate_hba_fru_details(ql_adapter_state_t *, fc_fca_port_info_t *);
2178 2482 void ql_setup_fruinfo(ql_adapter_state_t *);
2179 2483 uint16_t ql_pci_config_get16(ql_adapter_state_t *, off_t);
2180 2484 uint32_t ql_pci_config_get32(ql_adapter_state_t *, off_t);
2181 2485 void ql_pci_config_put8(ql_adapter_state_t *, off_t, uint8_t);
2182 2486 void ql_pci_config_put16(ql_adapter_state_t *, off_t, uint16_t);
2183 2487 void ql_delay(ql_adapter_state_t *, clock_t);
2184 -void ql_awaken_task_daemon(ql_adapter_state_t *, ql_srb_t *, uint32_t,
2185 - uint32_t);
2488 +void ql_awaken_task_daemon(ql_adapter_state_t *, ql_srb_t *, uint64_t,
2489 + uint64_t);
2186 2490 int ql_abort_device(ql_adapter_state_t *, ql_tgt_t *, int);
2187 2491 int ql_binary_fw_dump(ql_adapter_state_t *, int);
2188 -void ql_done(ql_link_t *);
2492 +void ql_done(ql_link_t *, boolean_t);
2189 2493 int ql_24xx_flash_id(ql_adapter_state_t *);
2190 2494 int ql_24xx_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t);
2191 2495 int ql_poll_flash(ql_adapter_state_t *, uint32_t, uint8_t);
2192 2496 void ql_flash_disable(ql_adapter_state_t *);
2193 2497 void ql_flash_enable(ql_adapter_state_t *);
2194 2498 int ql_erase_flash(ql_adapter_state_t *, int);
2195 2499 void ql_write_flash_byte(ql_adapter_state_t *, uint32_t, uint8_t);
2196 2500 uint8_t ql_read_flash_byte(ql_adapter_state_t *, uint32_t);
2197 2501 int ql_24xx_read_flash(ql_adapter_state_t *, uint32_t, uint32_t *);
2198 2502 int ql_24xx_write_flash(ql_adapter_state_t *, uint32_t, uint32_t);
2199 2503 fc_unsol_buf_t *ql_get_unsolicited_buffer(ql_adapter_state_t *, uint32_t);
2504 +int ql_dump_firmware(ql_adapter_state_t *);
2200 2505 size_t ql_ascii_fw_dump(ql_adapter_state_t *, caddr_t);
2201 2506 void ql_add_link_b(ql_head_t *, ql_link_t *);
2202 2507 void ql_add_link_t(ql_head_t *, ql_link_t *);
2203 2508 void ql_remove_link(ql_head_t *, ql_link_t *);
2204 2509 void ql_next(ql_adapter_state_t *, ql_lun_t *);
2205 2510 void ql_send_logo(ql_adapter_state_t *, ql_tgt_t *, ql_head_t *);
2206 2511 void ql_cthdr_endian(ddi_acc_handle_t, caddr_t, boolean_t);
2207 2512 ql_tgt_t *ql_d_id_to_queue(ql_adapter_state_t *, port_id_t);
2208 2513 ql_tgt_t *ql_loop_id_to_queue(ql_adapter_state_t *, uint16_t);
2209 2514 void ql_cmd_wait(ql_adapter_state_t *);
2210 2515 void ql_loop_online(ql_adapter_state_t *);
2211 2516 ql_tgt_t *ql_dev_init(ql_adapter_state_t *, port_id_t, uint16_t);
2212 2517 int ql_ub_frame_hdr(ql_adapter_state_t *, ql_tgt_t *, uint16_t, ql_head_t *);
2213 2518 void ql_rcv_rscn_els(ql_adapter_state_t *, uint16_t *, ql_head_t *);
2214 2519 int ql_stall_driver(ql_adapter_state_t *, uint32_t);
2215 2520 void ql_restart_driver(ql_adapter_state_t *);
2216 2521 int ql_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t);
2217 2522 int ql_get_dma_mem(ql_adapter_state_t *, dma_mem_t *, uint32_t,
2218 2523 mem_alloc_type_t, mem_alignment_t);
2524 +void ql_free_dma_resource(ql_adapter_state_t *, dma_mem_t *);
2219 2525 int ql_alloc_phys(ql_adapter_state_t *, dma_mem_t *, int);
2220 2526 void ql_free_phys(ql_adapter_state_t *, dma_mem_t *);
2221 2527 void ql_24xx_protect_flash(ql_adapter_state_t *);
2222 -void ql_free_dma_resource(ql_adapter_state_t *, dma_mem_t *);
2223 2528 uint8_t ql_pci_config_get8(ql_adapter_state_t *, off_t);
2224 2529 void ql_pci_config_put32(ql_adapter_state_t *, off_t, uint32_t);
2225 2530 int ql_24xx_unprotect_flash(ql_adapter_state_t *);
2226 2531 char *els_cmd_text(int);
2227 2532 char *mbx_cmd_text(int);
2228 2533 char *cmd_text(cmd_table_t *, int);
2229 2534 uint32_t ql_fwmodule_resolve(ql_adapter_state_t *);
2230 2535 void ql_port_state(ql_adapter_state_t *, uint32_t, uint32_t);
2231 2536 void ql_isp_els_handle_cmd_endian(ql_adapter_state_t *ha, ql_srb_t *srb);
2232 2537 void ql_isp_els_handle_rsp_endian(ql_adapter_state_t *ha, ql_srb_t *srb);
2233 2538 void ql_isp_els_handle_endian(ql_adapter_state_t *ha, uint8_t *ptr,
2234 2539 uint8_t ls_code);
2235 -int ql_el_trace_desc_ctor(ql_adapter_state_t *);
2236 -int ql_el_trace_desc_dtor(ql_adapter_state_t *);
2540 +void ql_el_trace_alloc(ql_adapter_state_t *);
2541 +void ql_el_trace_dealloc(ql_adapter_state_t *);
2237 2542 int ql_nvram_cache_desc_ctor(ql_adapter_state_t *);
2238 2543 int ql_nvram_cache_desc_dtor(ql_adapter_state_t *);
2544 +int ql_plogi_params_desc_ctor(ql_adapter_state_t *);
2545 +int ql_plogi_params_desc_dtor(ql_adapter_state_t *);
2239 2546 int ql_wwn_cmp(ql_adapter_state_t *, la_wwn_t *, la_wwn_t *);
2240 2547 void ql_dev_free(ql_adapter_state_t *, ql_tgt_t *);
2548 +void ql_restart_queues(ql_adapter_state_t *);
2549 +void ql_abort_queues(ql_adapter_state_t *);
2550 +void ql_requeue_pending_cmds(ql_adapter_state_t *, ql_tgt_t *);
2551 +void ql_toggle_loop_state(ql_adapter_state_t *);
2552 +void ql_els_24xx_iocb(ql_adapter_state_t *, ql_request_q_t *, ql_srb_t *,
2553 + void *);
2554 +int ql_get_cap_ofst(ql_adapter_state_t *, uint8_t);
2555 +void ql_intr_lock(ql_adapter_state_t *);
2556 +void ql_intr_unlock(ql_adapter_state_t *);
2557 +void ql_io_comp(ql_srb_t *sp);
2558 +uint64_t ql_get_lun_addr(ql_tgt_t *, uint16_t);
2559 +int ql_2700_get_flash_dmp_template(ql_adapter_state_t *);
2560 +int ql_2700_get_module_dmp_template(ql_adapter_state_t *);
2241 2561
2242 2562 #ifdef __cplusplus
2243 2563 }
2244 2564 #endif
2245 2565
2246 2566 #endif /* _QL_API_H */
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