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NEX-1890 update oce from source provided by Emulex
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--- old/usr/src/uts/common/sys/fibre-channel/fca/oce/oce_impl.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/oce/oce_impl.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 -/* Copyright © 2003-2011 Emulex. All rights reserved. */
22 +/*
23 + * Copyright (c) 2009-2012 Emulex. All rights reserved.
24 + * Use is subject to license terms.
25 + */
23 26
27 +
28 +
24 29 /*
25 30 * Driver specific data structures and function prototypes
26 31 */
27 32
28 33 #ifndef _OCE_IMPL_H_
29 34 #define _OCE_IMPL_H_
30 35
31 36 #ifdef __cplusplus
32 37 extern "C" {
33 38 #endif
34 39
35 40 #include <sys/types.h>
36 41 #include <sys/dditypes.h>
42 +#include <sys/sysmacros.h>
37 43 #include <sys/kstat.h>
38 44 #include <sys/ddi_intr.h>
39 45 #include <sys/cmn_err.h>
40 46 #include <sys/byteorder.h>
47 +#include <netinet/ip6.h>
41 48 #include <sys/mac_provider.h>
42 49 #include <sys/mac_ether.h>
43 50 #include <sys/gld.h>
44 51 #include <sys/bitmap.h>
45 52 #include <sys/ddidmareq.h>
46 53 #include <sys/kmem.h>
47 54 #include <sys/ddi.h>
48 55 #include <sys/sunddi.h>
49 56 #include <sys/modctl.h>
50 57 #include <sys/devops.h>
51 58 #include <sys/systm.h>
52 59 #include <sys/conf.h>
53 60 #include <sys/dlpi.h>
54 61 #include <sys/ethernet.h>
55 62 #include <sys/strsun.h>
56 63 #include <sys/pattr.h>
57 64 #include <sys/strsubr.h>
58 65 #include <sys/ddifm.h>
59 66 #include <sys/fm/protocol.h>
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60 67 #include <sys/fm/util.h>
61 68 #include <sys/fm/io/ddi.h>
62 69 #include <sys/note.h>
63 70 #include <sys/pci.h>
64 71 #include <sys/random.h>
65 72 #include <oce_hw.h>
66 73 #include <oce_hw_eth.h>
67 74 #include <oce_io.h>
68 75 #include <oce_buf.h>
69 76 #include <oce_utils.h>
77 +#include <oce_ring.h>
70 78 #include <oce_version.h>
71 79
72 80 #define SIZE_128 128
73 81 #define SIZE_256 256
74 82 #define SIZE_512 512
75 83 #define SIZE_1K 1024
76 84 #define SIZE_2K (2 * 1024)
77 85 #define SIZE_4K (4 * 1024)
78 86 #define SIZE_8K (8 * 1024)
79 87
80 88 #define END 0xdeadface
81 89
82 -#define MAX_DEVS 32
83 -#define MAX_RSS_PER_ADAPTER 2
84 -
85 -#define OCE_MAX_ETH_FRAME_SIZE 1500
86 90 #define OCE_MAX_JUMBO_FRAME_SIZE 9018
87 -#define OCE_MIN_ETH_FRAME_SIZE 64
88 -#define OCE_LLC_SNAP_HDR_LEN 8
89 91
90 92 #define OCE_MIN_MTU 1500
91 93 #define OCE_MAX_MTU 9000
92 94 #define OCE_MAX_MCA 32
93 -#define OCE_RQ_MAX_FRAME_SZ 9018
94 95
95 -#define OCE_MAX_EQ 8
96 +#define OCE_MAX_EQ 16
96 97 #define OCE_MAX_CQ 1024
97 -#define OCE_MAX_WQ 8
98 -#define OCE_MAX_RQ 5
99 -#define OCE_MIN_RQ 1
100 98
101 -#define OCE_WQ_NUM_BUFFERS 2048
102 -#define OCE_WQ_BUF_SIZE 2048
103 -#define OCE_LSO_MAX_SIZE (64 * 1024)
99 +#define OCE_WQ_NUM_BUFFERS 2048
100 +#define OCE_WQ_BUF_SIZE 2048
101 +#define OCE_LSO_MAX_SIZE (64 * 1024)
104 102 #define OCE_DEFAULT_TX_BCOPY_LIMIT 512
105 103 #define OCE_DEFAULT_RX_BCOPY_LIMIT 128
106 -#define OCE_DEFAULT_WQ_EQD 16
104 +#define OCE_DEFAULT_WQ_EQD 16
107 105
108 -#define OCE_DEFAULT_TX_RING_SIZE 2048
109 -#define OCE_DEFAULT_RX_RING_SIZE 1024
110 -#define OCE_DEFAULT_WQS 1
111 -#if defined(__sparc)
112 -#define OCE_DEFAULT_RQS OCE_MAX_RQ
113 -#else
114 -#define OCE_DEFAULT_RQS OCE_MIN_RQ
115 -#endif
116 -
117 -#define OCE_DEFAULT_RX_PKT_PER_INTR (OCE_DEFAULT_RX_RING_SIZE / 2)
106 +#define OCE_DEFAULT_RX_PKTS_PER_INTR 64
118 107 #define OCE_DEFAULT_TX_RECLAIM_THRESHOLD 1024
119 -#define OCE_MAX_RQ_POSTS 255
120 -#define OCE_RQ_NUM_BUFFERS 2048
121 -#define OCE_RQ_BUF_SIZE 8192
122 -#define OCE_DEFAULT_RECHARGE_THRESHOLD OCE_MAX_RQ_POSTS
123 -#define OCE_NUM_USED_VECTORS 2
124 -#define OCE_ITBL_SIZE 64
125 -#define OCE_HKEY_SIZE 40
126 -#define OCE_DMA_ALIGNMENT 0x1000ull
127 108
128 -#define OCE_MIN_VECTORS 1
109 +#define OCE_MAX_RSS_RINGS 16
110 +#define OCE_MAX_RING_GROUPS 4
111 +#define OCE_MAX_RING_PER_GROUP (OCE_MAX_RSS_RINGS+1)
112 +#define OCE_MIN_RING_PER_GROUP 1
113 +#define OCE_MAX_RQ (OCE_MAX_EQ+1)
114 +#define OCE_MAX_WQ OCE_MAX_EQ
115 +#define OCE_MIN_RQ 1
116 +#define OCE_MIN_WQ 1
117 +#define OCE_DEF_RING_PER_GROUP OCE_MAX_RING_PER_GROUP
118 +#define OCE_DEFAULT_RQS 5
119 +#define OCE_DEFAULT_WQS 1
129 120
130 -#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
131 - MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
132 - MBX_RX_IFACE_FLAGS_UNTAGGED | \
133 - MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
134 - MBX_RX_IFACE_FLAGS_PASS_L3L4)
121 +#define OCE_MAX_SMAC_PER_DEV 128
122 +#define OCE_MAX_PMAC_PER_GRP OCE_MAX_SMAC_PER_DEV
135 123
136 -#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
137 - MBX_RX_IFACE_FLAGS_UNTAGGED | \
138 - MBX_RX_IFACE_FLAGS_PASS_L3L4)
124 +#define OCE_MAX_RQ_POSTS 255
125 +#define OCE_RQ_NUM_BUFFERS 2048
126 +#define OCE_RQ_BUF_SIZE 2048
127 +#define OCE_DEFAULT_RECHARGE_THRESHOLD 32
128 +#define OCE_ITBL_SIZE 64
129 +#define OCE_HKEY_SIZE 40
130 +#define OCE_DMA_ALIGNMENT 0x0000000000001000ull
131 +#define OCE_MIN_VECTORS 1
139 132
140 -#define OCE_FM_CAPABILITY (DDI_FM_EREPORT_CAPABLE | \
141 - DDI_FM_ACCCHK_CAPABLE | \
142 - DDI_FM_DMACHK_CAPABLE)
133 +#define OCE_DEFAULT_TX_RING_SIZE 2048
134 +#define OCE_DEFAULT_RX_RING_SIZE 1024
143 135
136 +#define OCE_FM_CAPABILITY (DDI_FM_EREPORT_CAPABLE | \
137 + DDI_FM_ACCCHK_CAPABLE | \
138 + DDI_FM_DMACHK_CAPABLE)
144 139 #define OCE_DEFAULT_RSS_TYPE (RSS_ENABLE_IPV4|RSS_ENABLE_TCP_IPV4)
145 140
146 141 /* flow control definitions */
147 142 #define OCE_FC_NONE 0x00000000
148 143 #define OCE_FC_TX 0x00000001
149 144 #define OCE_FC_RX 0x00000002
150 145 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
151 146
152 147 /* PCI Information */
153 148 #define OCE_DEV_CFG_BAR 0x01
154 149 #define OCE_PCI_CSR_BAR 0x02
155 150 #define OCE_PCI_DB_BAR 0x03
151 +/* Lancer DB Bar */
152 +#define OCE_PCI_LANCER_DB_BAR 0x01
156 153
157 154 /* macros for device IO */
158 155 #define OCE_READ_REG32(handle, addr) ddi_get32(handle, addr)
159 156 #define OCE_WRITE_REG32(handle, addr, value) ddi_put32(handle, addr, value)
160 157
161 158 #define OCE_CSR_READ32(dev, offset) \
162 159 OCE_READ_REG32((dev)->csr_handle, \
163 160 (uint32_t *)(void *)((dev)->csr_addr + offset))
164 161
165 162 #define OCE_CSR_WRITE32(dev, offset, value) \
166 163 OCE_WRITE_REG32((dev)->csr_handle, \
167 164 (uint32_t *)(void *)((dev)->csr_addr + offset), value)
168 165
169 166 #define OCE_DB_READ32(dev, offset) \
170 167 OCE_READ_REG32((dev)->db_handle, \
171 168 (uint32_t *)(void *)((dev)->db_addr + offset))
172 169
173 170 #define OCE_DB_WRITE32(dev, offset, value) \
174 171 OCE_WRITE_REG32((dev)->db_handle, \
175 172 (uint32_t *)(void *)((dev)->db_addr + offset), value)
176 173
177 174 #define OCE_CFG_READ32(dev, offset) \
178 175 OCE_READ_REG32((dev)->dev_cfg_handle, \
179 176 (uint32_t *)(void *)((dev)->dev_cfg_addr + offset))
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180 177
181 178 #define OCE_CFG_WRITE32(dev, offset, value) \
182 179 OCE_WRITE_REG32((dev)->dev_cfg_handle, \
183 180 (uint32_t *)(void *)((dev)->dev_cfg_addr + offset), value)
184 181
185 182 #define OCE_PCI_FUNC(dev) \
186 183 ((OCE_CFG_READ32(dev, PCICFG_INTR_CTRL) \
187 184 >> HOSTINTR_PFUNC_SHIFT) & HOSTINTR_PFUNC_MASK)
188 185
189 186 #define DEV_LOCK(dev) mutex_enter(&dev->dev_lock)
190 -
191 187 #define DEV_UNLOCK(dev) mutex_exit(&dev->dev_lock)
192 188
193 189 enum oce_ring_size {
194 190 RING_SIZE_256 = 256,
195 191 RING_SIZE_512 = 512,
196 192 RING_SIZE_1024 = 1024,
197 193 RING_SIZE_2048 = 2048
198 194 };
199 195
200 -enum oce_driver_state {
201 - STATE_INIT = 0x2,
196 +enum oce_device_state {
202 197 STATE_MAC_STARTED = 0x4,
203 - STATE_QUIESCE = 0x8,
204 - STATE_MAC_STOPPING = 0x10
198 + STATE_INTR_ENABLED = 0x8,
199 + STATE_MAC_STOPPING = 0x10,
200 + STATE_INTR_ADJUST = 0x20
205 201 };
206 202
203 +enum oce_group_state {
204 + GROUP_INIT = 0x01,
205 + GROUP_MAC_STARTED = 0x02,
206 + GROUP_SUSPEND = 0x04
207 +};
208 +
209 +#define ATTACH_DEV_INIT 0x1
210 +#define ATTACH_FM_INIT 0x2
211 +#define ATTACH_PCI_CFG 0x4
212 +#define ATTACH_LOCK_INIT 0x8
213 +#define ATTACH_PCI_INIT 0x10
214 +#define ATTACH_HW_INIT 0x20
215 +#define ATTACH_SETUP_INTR 0x100
216 +#define ATTACH_STAT_INIT 0x200
217 +#define ATTACH_MAC_REG 0x400
218 +#define ATTACH_CB_REG 0x1000
219 +#define ATTACH_ALLOC_QUEUES 0x2000
220 +#define ATTACH_REG_INTR_HANDLE 0x4000
221 +
222 +typedef union oce_ring_s {
223 + struct oce_rq *rx;
224 + struct oce_wq *tx;
225 +} oce_ring_t;
226 +
227 +
228 +typedef struct oce_group_s
229 +{
230 + kmutex_t grp_lock; /* lock for group data */
231 + mac_ring_type_t grp_type; /* tx or rx ring group */
232 + uint32_t grp_num; /* index into the group array */
233 + mac_group_handle_t handle; /* ring handle used by framework */
234 + boolean_t rss_enable; /* if rx, whether rss or not */
235 + uint32_t if_id; /* unique to a group */
236 + uint32_t num_pmac; /* number of pmacs in this group */
237 + uint32_t pmac_ids[OCE_MAX_PMAC_PER_GRP]; /* pmac ids of added pmacs */
238 + struct ether_addr mac_addr[OCE_MAX_PMAC_PER_GRP]; /* MAC Addresses */
239 + uint32_t num_rings;
240 + uint32_t eq_idx;
241 + oce_ring_t ring[OCE_MAX_RING_PER_GROUP];
242 + void *parent;
243 + enum oce_group_state state;
244 +
245 + uint16_t num_mca; /* MCA supported */
246 + struct ether_addr multi_cast[OCE_MAX_MCA]; /* MC TABLE */
247 +}oce_group_t;
248 +
207 249 struct oce_dev {
208 - kmutex_t bmbx_lock; /* Bootstrap Lock */
209 - kmutex_t dev_lock; /* lock for device */
250 + kmutex_t bmbx_lock; /* Bootstrap Lock */
251 + kmutex_t dev_lock; /* lock for device */
210 252
253 + uint16_t QnQ_tag;
254 + uint8_t QnQ_valid;
255 + uint8_t QnQ_queried;
256 +
257 + uint32_t rx_rings_per_group;
258 + uint32_t num_rx_groups;
259 + uint32_t num_tx_groups;
260 + oce_group_t rx_group[OCE_MAX_RING_GROUPS];
261 + /* ungrouped TX rings */
262 + oce_ring_t default_tx_rings[OCE_MAX_WQ];
263 + uint32_t rx_rings; /* total */
264 + uint32_t tx_rings; /* total */
265 + uint32_t rss_cnt;
266 +
211 267 /* Queues relarted */
212 - struct oce_wq *wq[OCE_MAX_WQ]; /* TXQ Array */
213 - struct oce_rq *rq[OCE_MAX_RQ]; /* RXQ Array */
214 - struct oce_cq *cq[OCE_MAX_CQ]; /* Completion Queues */
215 - struct oce_eq *eq[OCE_MAX_EQ]; /* Event Queues */
216 - struct oce_mq *mq; /* MQ ring */
268 + struct oce_wq *wq; /* TXQ Array */
269 + struct oce_rq *rq; /* RXQ Array */
270 + struct oce_cq **cq; /* Completion Queues */
271 + struct oce_eq *eq; /* Event Queues */
272 + struct oce_mq *mq; /* MQ ring */
217 273
218 274 /* driver state machine */
219 - enum oce_driver_state state; /* state */
275 + enum oce_device_state state; /* state */
220 276 boolean_t suspended; /* CPR */
221 277 uint32_t attach_state; /* attach progress */
222 278
223 - oce_dma_buf_t *bmbx; /* Bootstrap MailBox */
279 + oce_dma_buf_t bmbx; /* Bootstrap MailBox */
224 280
225 281 uint32_t tx_bcopy_limit; /* TX BCOPY Limit */
226 282 uint32_t rx_bcopy_limit; /* RX BCOPY Limit */
227 283 uint32_t tx_reclaim_threshold; /* Tx reclaim */
284 + uint32_t tx_reclaim; /* Tx reclaim */
228 285 uint32_t rx_pkt_per_intr; /* Rx pkts processed per intr */
229 286
230 287 /* BARS */
231 288 int num_bars;
232 289 ddi_acc_handle_t pci_cfg_handle; /* Config space handle */
233 290 ddi_acc_handle_t cfg_handle; /* MMIO PCI Config Space Regs */
234 291 ddi_acc_handle_t csr_handle; /* MMIO Control Status Regs */
235 292 caddr_t csr_addr;
236 293 caddr_t db_addr;
237 294 caddr_t dev_cfg_addr;
238 295 ddi_acc_handle_t db_handle; /* MMIO DoorBell Area */
239 296 ddi_acc_handle_t dev_cfg_handle; /* MMIO CONFIG SPACE */
240 297 mac_handle_t mac_handle; /* MAC HANDLE */
241 298
242 299 /* device stats */
243 300 kstat_t *oce_kstats; /* NIC STATS */
244 - oce_dma_buf_t *stats_dbuf; /* STATS BUFFER */
245 - struct mbx_get_nic_stats *hw_stats;
301 + oce_dma_buf_t stats_dbuf; /* STATS BUFFER */
302 + kmutex_t stat_lock;
303 +
246 304 /* dev stats */
247 305 uint32_t tx_errors;
248 306 uint32_t tx_noxmtbuf;
249 307
250 308 /* link status */
251 309 link_state_t link_status;
252 310 int32_t link_speed; /* Link speed in Mbps */
311 + int32_t link_duplex;
312 + uint16_t pvid;
313 + uint16_t reco_priority; /* Recommended priority */
314 + uint32_t vlan_prio_bmap; /* Available Vlan priorities bitmap */
253 315
316 + /* watch dog timer related */
317 + kmutex_t wd_lock;
318 + boolean_t wd_enable;
319 + timeout_id_t wd_id;
320 +
254 321 /* OS */
255 322 uint32_t dev_id; /* device ID or instance number */
256 323 dev_info_t *dip; /* device info structure for device tree node */
257 324
258 325 /* Interrupt related */
259 326 int intr_type; /* INTR TYPE USED */
260 327 int num_vectors; /* number of vectors used */
261 328 uint_t intr_pri; /* interrupt priority */
262 329 int intr_cap;
263 330 ddi_intr_handle_t *htable; /* intr handler table */
264 331 int32_t hsize;
332 + ddi_cb_handle_t cb_handle; /* IRM: callback handle */
333 + int max_vectors; /* IRM: max number of vectors */
265 334
266 335 /* device configuration */
267 336 uint32_t rq_max_bufs; /* maximum prealloced buffers */
268 337 uint32_t rq_frag_size; /* Rxq fragment size */
269 338 enum oce_ring_size tx_ring_size;
270 339 enum oce_ring_size rx_ring_size;
271 340 uint32_t neqs; /* No of event queues */
272 341 uint32_t nwqs; /* No of Work Queues */
273 342 uint32_t nrqs; /* No of Receive Queues */
274 - uint32_t nifs; /* No of interfaces created */
275 - uint32_t tx_rings;
276 - uint32_t rx_rings;
343 + uint32_t num_pmac; /* Total pmacs on this port */
277 344 uint32_t pmac_id; /* used to add or remove mac */
278 345 uint8_t unicast_addr[ETHERADDRL];
279 346 uint32_t num_smac;
280 347 uint32_t mtu;
281 348 int32_t fm_caps;
282 - boolean_t rss_enable; /* RSS support */
283 349 boolean_t lso_capable; /* LSO */
284 350 boolean_t promisc; /* PROMISC MODE */
285 - uint32_t if_cap_flags; /* IF CAPAB */
286 351 uint32_t flow_control; /* flow control settings */
287 352 uint8_t mac_addr[ETHERADDRL]; /* hardware mac address */
288 353 uint16_t num_mca; /* MCA supported */
289 354 struct ether_addr multi_cast[OCE_MAX_MCA]; /* MC TABLE */
290 355 uint32_t cookie; /* used during fw download */
291 356
292 357 /* fw config: only relevant fields */
293 358 uint32_t config_number;
294 359 uint32_t asic_revision;
295 360 uint32_t port_id;
296 361 uint32_t function_mode;
297 362 uint32_t function_caps;
363 + uint32_t drvfn_caps;
298 364 uint32_t chip_rev; /* Chip revision */
299 365 uint32_t max_tx_rings; /* Max Rx rings available */
300 366 uint32_t max_rx_rings; /* Max rx rings available */
301 367 int32_t if_id; /* IF ID */
302 368 uint8_t fn; /* function number */
303 369 uint8_t fw_version[32]; /* fw version string */
304 370
305 371 /* PCI related */
306 - uint16_t vendor_id;
307 - uint16_t device_id;
308 - uint16_t subsys_id;
309 - uint16_t subvendor_id;
310 - uint8_t pci_bus;
311 - uint8_t pci_device;
312 - uint8_t pci_function;
313 - uint8_t dev_list_index;
372 + uint16_t vendor_id;
373 + uint16_t device_id;
374 + uint16_t subsys_id;
375 + uint16_t subvendor_id;
314 376
315 377 /* Logging related */
316 378 uint16_t mod_mask; /* Log Mask */
317 379 int16_t severity; /* Log level */
380 +
381 + /* ue status */
382 + uint32_t ue_mask_lo;
383 + uint32_t ue_mask_hi;
384 + uint32_t sli_family;
318 385 };
319 386
320 387 /* GLD handler functions */
321 388 int oce_m_start(void *arg);
322 389 void oce_m_stop(void *arg);
323 390 mblk_t *oce_m_send(void *arg, mblk_t *pkt);
324 391 int oce_m_promiscuous(void *arg, boolean_t enable);
325 392 int oce_m_multicast(void *arg, boolean_t add, const uint8_t *mca);
326 393 int oce_m_unicast(void *arg, const uint8_t *uca);
327 394 boolean_t oce_m_getcap(void *arg, mac_capab_t cap, void *data);
328 395 void oce_m_ioctl(void *arg, queue_t *wq, mblk_t *mp);
329 396 int oce_m_setprop(void *arg, const char *name, mac_prop_id_t id,
330 397 uint_t size, const void *val);
331 398 int oce_m_getprop(void *arg, const char *name, mac_prop_id_t id,
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332 399 uint_t size, void *val);
333 400 void oce_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num,
334 401 mac_prop_info_handle_t prh);
335 402
336 403 int oce_m_stat(void *arg, uint_t stat, uint64_t *val);
337 404
338 405 /* Hardware start/stop functions */
339 406 int oce_start(struct oce_dev *dev);
340 407 void oce_stop(struct oce_dev *dev);
341 408 int oce_identify_hw(struct oce_dev *dev);
342 -int oce_get_bdf(struct oce_dev *dev);
343 409
344 410 /* FMA support Functions */
345 411 void oce_fm_init(struct oce_dev *dev);
346 412 void oce_fm_fini(struct oce_dev *dev);
347 413 void oce_set_dma_fma_flags(int fm_caps);
348 414 void oce_set_reg_fma_flags(int fm_caps);
349 415 void oce_set_tx_map_dma_fma_flags(int fm_caps);
350 416 void oce_fm_ereport(struct oce_dev *dev, char *detail);
351 417 int oce_fm_check_acc_handle(struct oce_dev *dev,
352 418 ddi_acc_handle_t acc_handle);
353 419 int oce_fm_check_dma_handle(struct oce_dev *dev,
354 420 ddi_dma_handle_t dma_handle);
355 421
356 422 /* Interrupt handling */
357 423 int oce_setup_intr(struct oce_dev *dev);
358 424 int oce_teardown_intr(struct oce_dev *dev);
359 425 int oce_setup_handlers(struct oce_dev *dev);
360 426 void oce_remove_handler(struct oce_dev *dev);
361 -void oce_ei(struct oce_dev *dev);
362 -void oce_di(struct oce_dev *dev);
427 +int oce_ei(struct oce_dev *dev);
428 +int oce_di(struct oce_dev *dev);
363 429 void oce_chip_ei(struct oce_dev *dev);
364 430 void oce_chip_di(struct oce_dev *dev);
365 431
366 432 /* HW initialisation */
367 433 int oce_hw_init(struct oce_dev *dev);
368 434 void oce_hw_fini(struct oce_dev *dev);
369 -int oce_setup_adapter(struct oce_dev *dev);
370 -void oce_unsetup_adapter(struct oce_dev *dev);
435 +int oce_create_group(struct oce_dev *dev, oce_group_t *grp, uint32_t mode);
436 +void oce_delete_group(struct oce_dev *dev, oce_group_t *grp);
437 +void oce_delete_nw_interface(struct oce_dev *dev, oce_group_t *grp,
438 + uint32_t mode);
439 +int oce_create_nw_interface(struct oce_dev *dev, oce_group_t *grp,
440 + uint32_t mode);
441 +int oce_rq_init(struct oce_dev *dev, struct oce_rq *, uint32_t q_len,
442 + uint32_t frag_size, uint32_t mtu);
443 +void oce_rq_fini(struct oce_dev *dev, struct oce_rq *rq);
371 444
445 +/* Timer related */
446 +void oce_enable_wd_timer(struct oce_dev *dev);
447 +void oce_disable_wd_timer(struct oce_dev *dev);
448 +boolean_t oce_check_ue(struct oce_dev *dev);
449 +boolean_t oce_tx_stall_check(struct oce_dev *dev);
450 +
451 +/* Helper functions for crossbow ring groups */
452 +int oce_start_group(oce_group_t *, boolean_t);
453 +void oce_stop_group(oce_group_t *, boolean_t);
454 +int oce_resume_group_rings(oce_group_t *);
455 +void oce_suspend_group_rings(oce_group_t *);
456 +void oce_group_create_itbl(oce_group_t *, char *);
457 +
372 458 #ifdef __cplusplus
373 459 }
374 460 #endif
375 461
376 462 #endif /* _OCE_IMPL_H_ */
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