2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright © 2003-2011 Emulex. All rights reserved. */
23
24 /*
25 * header file containing the data structure definitions for the NIC
26 * subsystetm
27 */
28
29 #ifndef _OCE_HW_ETH_H_
30 #define _OCE_HW_ETH_H_
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 #include <oce_hw.h>
37
38 #define NIC_WQE_SIZE 16
39 /* NIC packet type */
40 #define NIC_UNICAST 0x00
41 #define NIC_MULTICAST 0x01
42 #define NIC_BROADCAST 0x02
43
44 /* HDS type */
45 #define NIC_HDS_NO_SPLIT 0x00
46 #define NIC_HDS_SPLIT_L3PL 0x01
47 #define NIC_HDS_SPLIT_L4PL 0x02
48
49 /* NIC WQ types */
50 #define NIC_WQ_TYPE_FORWARDING 0x01
51 #define NIC_WQ_TYPE_STANDARD 0x02
52 #define NIC_WQ_TYPE_LOW_LATENCY 0x04
53
54 #pragma pack(1)
55 enum {
56 OPCODE_CONFIG_NIC_RSS = 1,
57 OPCODE_CONFIG_NIC_ACPI = 2,
58 OPCODE_CONFIG_NIC_PROMISCUOUS = 3,
59 OPCODE_GET_NIC_STATS = 4,
60 OPCODE_CREATE_NIC_WQ = 7,
61 OPCODE_CREATE_NIC_RQ = 8,
62 OPCODE_DELETE_NIC_WQ = 9,
63 OPCODE_DELETE_NIC_RQ = 10,
64 OPCODE_CREATE_NIC_RSS_CQ = 11,
65 OPCODE_DELETE_NIC_RSS_CQ = 12,
66 OPCODE_SET_RSS_EQ_MSI = 13,
67 OPCODE_CREATE_NIC_HDS_RQ = 14,
68 OPCODE_DELETE_NIC_HDS_RQ = 15,
69 OPCODE_CONFIG_NIC_RSS_ADVANCED = 16
70 };
71
72 enum {
73 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
74 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
75 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
76 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
77 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */
78
79 };
80 /* NIC header WQE */
81 struct oce_nic_hdr_wqe {
82 union {
83 struct {
84 #ifdef _BIG_ENDIAN
85 /* dw0 */
86 uint32_t rsvd0;
87
88 /* dw1 */
89 uint32_t last_seg_udp_len:14;
216 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
217
218 /* Receive Queue Entry (RQE) */
219 struct oce_nic_rqe {
220 union {
221 struct {
222 uint32_t frag_pa_hi;
223 uint32_t frag_pa_lo;
224 }s;
225 uint32_t dw[2];
226 }u0;
227 };
228
229 /* NIC Receive CQE */
230 struct oce_nic_rx_cqe {
231 union {
232 struct {
233 #ifdef _BIG_ENDIAN
234 /* dw 0 */
235 uint32_t ip_options:1;
236 uint32_t port:1;
237 uint32_t pkt_size:14;
238 uint32_t vlan_tag:16;
239
240 /* dw 1 */
241 uint32_t num_fragments:3;
242 uint32_t switched:1;
243 uint32_t ct:2;
244 uint32_t frag_index:10;
245 uint32_t rsvd0:1;
246 uint32_t vlan_tag_present:1;
247 uint32_t mac_dst:6;
248 uint32_t ip_ver:1;
249 uint32_t l4_cksum_pass:1;
250 uint32_t ip_cksum_pass:1;
251 uint32_t udpframe:1;
252 uint32_t tcpframe:1;
253 uint32_t ipframe:1;
254 uint32_t rss_hp:1;
255 uint32_t error:1;
256
257 /* dw 2 */
258 uint32_t valid:1;
259 uint32_t hds_type:2;
260 uint32_t lro_pkt:1;
261 uint32_t rsvd4:1;
262 uint32_t hds_hdr_size:12;
263 uint32_t hds_hdr_frag_index:10;
264 uint32_t rss_bank:1;
265 uint32_t qnq:1;
266 uint32_t pkt_type:2;
267 uint32_t rss_flush:1;
268
269 /* dw 3 */
270 uint32_t rss_hash_value;
271 #else
272 /* dw 0 */
273 uint32_t vlan_tag:16;
274 uint32_t pkt_size:14;
275 uint32_t port:1;
276 uint32_t ip_options:1;
277 /* dw 1 */
278 uint32_t error:1;
279 uint32_t rss_hp:1;
280 uint32_t ipframe:1;
281 uint32_t tcpframe:1;
282 uint32_t udpframe:1;
283 uint32_t ip_cksum_pass:1;
284 uint32_t l4_cksum_pass:1;
285 uint32_t ip_ver:1;
286 uint32_t mac_dst:6;
287 uint32_t vlan_tag_present:1;
288 uint32_t rsvd0:1;
289 uint32_t frag_index:10;
290 uint32_t ct:2;
291 uint32_t switched:1;
292 uint32_t num_fragments:3;
293
294 /* dw 2 */
295 uint32_t rss_flush:1;
296 uint32_t pkt_type:2;
297 uint32_t qnq:1;
298 uint32_t rss_bank:1;
299 uint32_t hds_hdr_frag_index:10;
300 uint32_t hds_hdr_size:12;
301 uint32_t rsvd4:1;
302 uint32_t lro_pkt:1;
303 uint32_t hds_type:2;
304 uint32_t valid:1;
305 /* dw 3 */
306 uint32_t rss_hash_value;
307 #endif
308 }s;
309 uint32_t dw[4];
310 }u0;
311 };
312 #define RQ_CQE_VALID_MASK 0x80
313 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
314 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
315
316 struct mbx_config_nic_promiscuous {
317 struct mbx_hdr hdr;
318 union {
319 struct {
320 #ifdef _BIG_ENDIAN
321 uint16_t rsvd0;
322 uint8_t port1_promisc;
323 uint8_t port0_promisc;
324 #else
325 uint8_t port0_promisc;
326 uint8_t port1_promisc;
327 uint16_t rsvd0;
328 #endif
329 }req;
330
331 struct {
332 uint32_t rsvd0;
333 }rsp;
334 }params;
335 };
336
337 /* [07] OPCODE_CREATE_NIC_WQ */
338 struct mbx_create_nic_wq {
339
340 /* dw0 - dw3 */
341 struct mbx_hdr hdr;
342 union {
343 struct {
344 #ifdef _BIG_ENDIAN
345 /* dw4 */
346 uint8_t rsvd1;
347 uint8_t nic_wq_type;
348 uint8_t rsvd0;
349 uint8_t num_pages;
350
351 /* dw5 */
352 uint32_t rsvd3:12;
353 uint32_t wq_size:4;
354 uint32_t rsvd2:16;
355
356 /* dw6 */
357 uint32_t valid:1;
358 uint32_t pd_id:9;
359 uint32_t pci_function_id:8;
360 uint32_t rsvd4:14;
361
362 /* dw7 */
363 uint32_t rsvd5:16;
364 uint32_t cq_id:16;
365 #else
366 /* dw4 */
367 uint8_t num_pages;
368 uint8_t rsvd0;
369 uint8_t nic_wq_type;
370 uint8_t rsvd1;
371
372 /* dw5 */
373 uint32_t rsvd2:16;
374 uint32_t wq_size:4;
375 uint32_t rsvd3:12;
376
377 /* dw6 */
378 uint32_t rsvd4:14;
379 uint32_t pci_function_id:8;
380 uint32_t pd_id:9;
381 uint32_t valid:1;
382
383 /* dw7 */
384 uint32_t cq_id:16;
385 uint32_t rsvd5:16;
386 #endif
387 /* dw8 - dw20 */
388 uint32_t rsvd6[13];
389 /* dw21 - dw36 */
390 struct phys_addr pages[8];
391 }req;
392
393 struct {
394 uint16_t wq_id;
395 uint16_t rsvd0;
396 }rsp;
397 }params;
398 };
399
400 /* [09] OPCODE_DELETE_NIC_WQ */
401 struct mbx_delete_nic_wq {
402 /* dw0 - dw3 */
403 struct mbx_hdr hdr;
404 union {
405 struct {
406 #ifdef _BIG_ENDIAN
407 /* dw4 */
408 uint16_t rsvd0;
474 union {
475 struct {
476 #ifdef _BIG_ENDIAN
477 /* dw4 */
478 uint16_t bypass_flush;
479 uint16_t rq_id;
480 #else
481 /* dw4 */
482 uint16_t rq_id;
483 uint16_t bypass_flush;
484 #endif
485 }req;
486
487 struct {
488 /* dw4 */
489 uint32_t rsvd0;
490 }rsp;
491 }params;
492 };
493
494 struct rx_port_stats {
495 uint32_t rx_bytes_lsd;
496 uint32_t rx_bytes_msd;
497 uint32_t rx_total_frames;
498 uint32_t rx_unicast_frames;
499 uint32_t rx_multicast_frames;
500 uint32_t rx_broadcast_frames;
501 uint32_t rx_crc_errors;
502 uint32_t rx_alignment_symbol_errors;
503 uint32_t rx_pause_frames;
504 uint32_t rx_control_frames;
505 uint32_t rx_in_range_errors;
506 uint32_t rx_out_range_errors;
507 uint32_t rx_frame_too_long;
508 uint32_t rx_address_match_errors;
509 uint32_t rx_vlan_mismatch;
510 uint32_t rx_dropped_too_small;
511 uint32_t rx_dropped_too_short;
512 uint32_t rx_dropped_header_too_small;
513 uint32_t rx_dropped_tcp_length;
514 uint32_t rx_dropped_runt;
543 uint32_t tx_bytes_msd;
544 uint32_t tx_unicast_frames;
545 uint32_t tx_multicast_frames;
546 uint32_t tx_broadcast_frames;
547 uint32_t tx_pause_frames;
548 uint32_t tx_control_frames;
549 uint32_t tx_64_byte_packets;
550 uint32_t tx_65_127_byte_packets;
551 uint32_t tx_128_256_byte_packets;
552 uint32_t tx_256_511_byte_packets;
553 uint32_t tx_512_1023_byte_packets;
554 uint32_t tx_1024_1518_byte_packets;
555 uint32_t tx_1519_2047_byte_packets;
556 uint32_t tx_2048_4095_byte_packets;
557 uint32_t tx_4096_8191_byte_packets;
558 uint32_t tx_8192_9216_byte_packets;
559 uint32_t rx_fifo_overflow;
560 uint32_t rx_input_fifo_overflow;
561 };
562
563 struct rx_stats {
564 /* dw 0-131 --2 X 66 */
565 struct rx_port_stats port[2];
566 /* dw 132-147 --16 */
567 uint32_t rx_drops_no_pbuf;
568 uint32_t rx_drops_no_txpb;
569 uint32_t rx_drops_no_erx_descr;
570 uint32_t rx_drops_no_tpre_descr;
571 uint32_t management_rx_port_packets;
572 uint32_t management_rx_port_bytes;
573 uint32_t management_rx_port_pause_frames;
574 uint32_t management_rx_port_errors;
575 uint32_t management_tx_port_packets;
576 uint32_t management_tx_port_bytes;
577 uint32_t management_tx_port_pause;
578 uint32_t management_rx_port_rxfifo_overflow;
579 uint32_t rx_drops_too_many_frags;
580 uint32_t rx_drops_invalid_ring;
581 uint32_t forwarded_packets;
582 uint32_t rx_drops_mtu;
583 /* fcoe is not relevent */
584 uint32_t rsvd[15];
585 };
586
587 struct tx_counter {
588 uint32_t pkts;
589 uint32_t lsd;
590 uint32_t msd;
591 };
592
593 struct tx_stats {
594 struct tx_counter ct1pt0_xmt_ipv4_ctrs;
595 struct tx_counter ct1pt0_xmt_ipv6_ctrs;
596 struct tx_counter ct1pt0_rexmt_ipv4_ctrs;
597 struct tx_counter ct1pt0_rexmt_ipv6_ctrs;
598 struct tx_counter ct1pt1_xmt_ipv4_ctrs;
599 struct tx_counter ct1pt1_xmt_ipv6_ctrs;
600 struct tx_counter ct1pt1_rexmt_ipv4_ctrs;
601 struct tx_counter ct1pt1_rexmt_ipv6_ctrs;
602 struct tx_counter ct2pt0_xmt_ipv4_ctrs;
603 struct tx_counter ct2pt0_xmt_ipv6_ctrs;
604 struct tx_counter ct2pt0_rexmt_ipv4_ctrs;
605 struct tx_counter ct2pt0_rexmt_ipv6_ctrs;
606 struct tx_counter ct2pt1_xmt_ipv4_ctrs;
607 struct tx_counter ct2pt1_xmt_ipv6_ctrs;
608 struct tx_counter ct2pt1_rexmt_ipv4_ctrs;
609 struct tx_counter ct2pt1_rexmt_ipv6_ctrs;
610 };
611
612 struct rx_err_stats {
613 uint32_t rx_drops_no_fragments[44];
614 uint32_t debug_wdma_sent_hold;
615 uint32_t debug_wdma_pbfree_sent_hold;
616 uint32_t debug_wdma_zerobyte_pbfree_sent_hold;
617 uint32_t debug_pmem_pbuf_dealloc;
618 };
619
620 struct mem_stats {
621 uint32_t eth_red_drops;
622 uint32_t lro_red_drops;
623 uint32_t ulp0_red_drops;
624 uint32_t ulp1_red_drops;
625 };
626
627 /* [04] OPCODE_GET_NIC_STATS */
628 struct mbx_get_nic_stats {
629 /* dw0 - dw3 */
630 struct mbx_hdr hdr;
631 union {
632 struct {
633 uint32_t rsvd0;
634 }req;
635
636 struct {
637 struct rx_stats rx;
638 struct tx_stats tx;
639 struct rx_err_stats err_rx;
640 struct mem_stats mem;
641 }rsp;
642 }params;
643 };
644
645 /* [01] OPCODE_CONFIG_NIC_RSS */
646 struct mbx_config_nic_rss {
647 struct mbx_hdr hdr;
648 union {
649 struct {
650 #ifdef _BIG_ENDIAN
651 uint32_t if_id;
652 uint16_t cpu_tbl_sz_log2;
653 uint16_t enable_rss;
654 uint32_t hash[10];
655 uint8_t cputable[128];
656 uint8_t rsvd[3];
657 uint8_t flush;
658 #else
659 uint32_t if_id;
660 uint16_t enable_rss;
|
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27
28
29 /*
30 * header file containing the data structure definitions for the NIC
31 * subsystetm
32 */
33
34 #ifndef _OCE_HW_ETH_H_
35 #define _OCE_HW_ETH_H_
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #include <oce_hw.h>
42
43 #define NIC_WQE_SIZE 16
44 /* NIC packet type */
45 #define NIC_UNICAST 0x00
46 #define NIC_MULTICAST 0x01
47 #define NIC_BROADCAST 0x02
48
49 /* HDS type */
50 #define NIC_HDS_NO_SPLIT 0x00
51 #define NIC_HDS_SPLIT_L3PL 0x01
52 #define NIC_HDS_SPLIT_L4PL 0x02
53
54 /* NIC WQ types */
55 #define NIC_WQ_TYPE_FORWARDING 0x01
56 #define NIC_WQ_TYPE_STANDARD 0x02
57 #define NIC_WQ_TYPE_LOW_LATENCY 0x04
58
59 #define INVALID_PMAC_ID 0xffffffff
60
61 #pragma pack(1)
62 enum {
63 OPCODE_CONFIG_NIC_RSS = 1,
64 OPCODE_CONFIG_NIC_ACPI = 2,
65 OPCODE_CONFIG_NIC_PROMISCUOUS = 3,
66 OPCODE_GET_NIC_STATS = 4,
67 OPCODE_CREATE_NIC_WQ = 7,
68 OPCODE_CREATE_NIC_RQ = 8,
69 OPCODE_DELETE_NIC_WQ = 9,
70 OPCODE_DELETE_NIC_RQ = 10,
71 OPCODE_CREATE_NIC_RSS_CQ = 11,
72 OPCODE_DELETE_NIC_RSS_CQ = 12,
73 OPCODE_SET_RSS_EQ_MSI = 13,
74 OPCODE_CREATE_NIC_HDS_RQ = 14,
75 OPCODE_DELETE_NIC_HDS_RQ = 15,
76 OPCODE_CONFIG_NIC_RSS_ADVANCED = 16,
77 OPCODE_NIC_GET_PPORT_STATS = 18
78 };
79
80 enum {
81 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
82 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
83 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
84 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
85 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */
86
87 };
88 /* NIC header WQE */
89 struct oce_nic_hdr_wqe {
90 union {
91 struct {
92 #ifdef _BIG_ENDIAN
93 /* dw0 */
94 uint32_t rsvd0;
95
96 /* dw1 */
97 uint32_t last_seg_udp_len:14;
224 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
225
226 /* Receive Queue Entry (RQE) */
227 struct oce_nic_rqe {
228 union {
229 struct {
230 uint32_t frag_pa_hi;
231 uint32_t frag_pa_lo;
232 }s;
233 uint32_t dw[2];
234 }u0;
235 };
236
237 /* NIC Receive CQE */
238 struct oce_nic_rx_cqe {
239 union {
240 struct {
241 #ifdef _BIG_ENDIAN
242 /* dw 0 */
243 uint32_t ip_options:1;
244 uint32_t vlan_tag_present:1;
245 uint32_t pkt_size:14;
246 uint32_t vlan_tag:16;
247
248 /* dw 1 */
249 uint32_t num_fragments:3;
250 uint32_t switched:1;
251 uint32_t ct:2;
252 uint32_t frag_index:10;
253 uint32_t rsvd0:1;
254 uint32_t mac_dst:7;
255 uint32_t ip_ver:1;
256 uint32_t l4_cksum_pass:1;
257 uint32_t ip_cksum_pass:1;
258 uint32_t udpframe:1;
259 uint32_t tcpframe:1;
260 uint32_t ipframe:1;
261 uint32_t rss_hp:1;
262 uint32_t error:1;
263
264 /* dw 2 */
265 uint32_t valid:1;
266 uint32_t rsvd2:13;
267 uint32_t hds_type:2;
268 uint32_t hds_hdr_size:8;
269 uint32_t vntagp:1;
270 uint32_t port:2;
271 uint32_t rss_bank:1;
272 uint32_t qnq:1;
273 uint32_t pkt_type:2;
274 uint32_t rss_flush:1;
275
276 /* dw 3 */
277 uint32_t rss_hash_value;
278 #else
279 /* dw 0 */
280 uint32_t vlan_tag:16;
281 uint32_t pkt_size:14;
282 uint32_t vlan_tag_present:1;
283 uint32_t ip_options:1;
284 /* dw 1 */
285 uint32_t error:1;
286 uint32_t rss_hp:1;
287 uint32_t ipframe:1;
288 uint32_t tcpframe:1;
289 uint32_t udpframe:1;
290 uint32_t ip_cksum_pass:1;
291 uint32_t l4_cksum_pass:1;
292 uint32_t ip_ver:1;
293 uint32_t mac_dst:7;
294 uint32_t rsvd0:1;
295 uint32_t frag_index:10;
296 uint32_t ct:2;
297 uint32_t switched:1;
298 uint32_t num_fragments:3;
299
300 /* dw 2 */
301 uint32_t rss_flush:1;
302 uint32_t pkt_type:2;
303 uint32_t qnq:1;
304 uint32_t rss_bank:1;
305 uint32_t port:2;
306 uint32_t vntagp:1;
307 uint32_t hds_hdr_size:8;
308 uint32_t hds_type:2;
309 uint32_t rsvd2:13;
310 uint32_t valid:1;
311
312 /* dw 3 */
313 uint32_t rss_hash_value;
314 #endif
315 }s; /* native mode(BE3) */
316 struct {
317 #ifdef _BIG_ENDIAN
318 /* dw 0 */
319 uint32_t ip_options:1;
320 uint32_t port:1;
321 uint32_t pkt_size:14;
322 uint32_t vlan_tag:16;
323
324 /* dw 1 */
325 uint32_t num_fragments:3;
326 uint32_t switched:1;
327 uint32_t ct:2;
328 uint32_t frag_index:10;
329 uint32_t rsvd0:1;
330 uint32_t vlan_tag_present:1;
331 uint32_t mac_dst:6;
332 uint32_t ip_ver:1;
333 uint32_t l4_cksum_pass:1;
334 uint32_t ip_cksum_pass:1;
335 uint32_t udpframe:1;
336 uint32_t tcpframe:1;
337 uint32_t ipframe:1;
338 uint32_t rss_hp:1;
339 uint32_t error:1;
340
341 /* dw 2 */
342 uint32_t valid:1;
343 uint32_t rsvd2:2;
344 uint32_t lro_pkt:1;
345 uint32_t rsvd1:23;
346 uint32_t rss_bank:1;
347 uint32_t qnq:1;
348 uint32_t pkt_type:2;
349 uint32_t rss_flush:1;
350
351 /* dw 3 */
352 uint32_t rss_hash_value;
353 #else
354 /* dw 0 */
355 uint32_t vlan_tag:16;
356 uint32_t pkt_size:14;
357 uint32_t port:1;
358 uint32_t ip_options:1;
359 /* dw 1 */
360 uint32_t error:1;
361 uint32_t rss_hp:1;
362 uint32_t ipframe:1;
363 uint32_t tcpframe:1;
364 uint32_t udpframe:1;
365 uint32_t ip_cksum_pass:1;
366 uint32_t l4_cksum_pass:1;
367 uint32_t ip_ver:1;
368 uint32_t mac_dst:6;
369 uint32_t vlan_tag_present:1;
370 uint32_t rsvd0:1;
371 uint32_t frag_index:10;
372 uint32_t ct:2;
373 uint32_t switched:1;
374 uint32_t num_fragments:3;
375
376 /* dw 2 */
377 uint32_t rss_flush:1;
378 uint32_t pkt_type:2;
379 uint32_t qnq:1;
380 uint32_t rss_bank:1;
381 uint32_t rsvd1:23;
382 uint32_t lro_pkt:1;
383 uint32_t rsvd2:2;
384 uint32_t valid:1;
385 /* dw 3 */
386 uint32_t rss_hash_value;
387 #endif
388 }v0; /* Legacy(BE2) */
389 uint32_t dw[4];
390 }u0;
391 };
392 #define RQ_CQE_VALID_MASK 0x80
393 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
394 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
395
396 struct mbx_config_nic_promiscuous {
397 struct mbx_hdr hdr;
398 union {
399 struct {
400 #ifdef _BIG_ENDIAN
401 uint16_t rsvd0;
402 uint8_t port1_promisc;
403 uint8_t port0_promisc;
404 #else
405 uint8_t port0_promisc;
406 uint8_t port1_promisc;
407 uint16_t rsvd0;
408 #endif
409 }req;
410
411 struct {
412 uint32_t rsvd0;
413 }rsp;
414 }params;
415 };
416
417 struct oce_tx_ctx {
418 #ifdef _BIG_ENDIAN
419 /* dw0 */
420 uint32_t rsvd0:12;
421 uint32_t wq_size:4;
422 uint32_t if_id:16;
423 /* dw1 */
424 uint32_t valid:1;
425 uint32_t pd_id:9;
426 uint32_t pci_function_id:8;
427 uint32_t rsvd1:14;
428 /* dw2 */
429 uint32_t rsvd2_1:1;
430 uint32_t no_rem_allowed:1;
431 uint32_t rsvd2:14;
432 uint32_t cq_id:16;
433 /* dw3 */
434 uint32_t rsvd3;
435 /* dw4 */
436 uint32_t rsvd4_1:10;
437 uint32_t cofe:1;
438 uint32_t rsvd4:21;
439 #else
440 /* dw0 */
441 uint32_t if_id:16;
442 uint32_t wq_size:4;
443 uint32_t rsvd0:12;
444 /* dw1 */
445 uint32_t rsvd1:14;
446 uint32_t pci_function_id:8;
447 uint32_t pd_id:9;
448 uint32_t valid:1;
449 /* dw2 */
450 uint32_t cq_id:16;
451 uint32_t rsvd2:14;
452 uint32_t no_rem_allowed:1;
453 uint32_t rsvd2_1:1;
454 /* dw3 */
455 uint32_t rsvd3;
456 /* dw4 */
457 uint32_t rsvd4:21;
458 uint32_t cofe:1;
459 uint32_t rsvd4_1:10;
460 #endif
461 /* dw5 - dw15 */
462 uint32_t rsvd5[11];
463 };
464
465 /* [07] OPCODE_CREATE_NIC_WQ */
466 struct mbx_create_nic_wq {
467
468 /* dw0 - dw3 */
469 struct mbx_hdr hdr;
470 union {
471 struct {
472 #ifdef _BIG_ENDIAN
473 /* dw4 */
474 uint8_t port;
475 uint8_t type;
476 uint8_t ulp_num;
477 uint8_t num_pages;
478 #else
479 /* dw4 */
480 uint8_t num_pages;
481 uint8_t ulp_num;
482 uint8_t type;
483 uint8_t port;
484 #endif
485 /* dw5 - dw20 */
486 struct oce_tx_ctx ctx;
487 /* dw21 - dw36 */
488 struct phys_addr pages[8];
489 }req;
490
491 struct {
492 uint16_t wq_id;
493 uint16_t rsvd0;
494 }rsp;
495 }params;
496 };
497
498 /* [09] OPCODE_DELETE_NIC_WQ */
499 struct mbx_delete_nic_wq {
500 /* dw0 - dw3 */
501 struct mbx_hdr hdr;
502 union {
503 struct {
504 #ifdef _BIG_ENDIAN
505 /* dw4 */
506 uint16_t rsvd0;
572 union {
573 struct {
574 #ifdef _BIG_ENDIAN
575 /* dw4 */
576 uint16_t bypass_flush;
577 uint16_t rq_id;
578 #else
579 /* dw4 */
580 uint16_t rq_id;
581 uint16_t bypass_flush;
582 #endif
583 }req;
584
585 struct {
586 /* dw4 */
587 uint32_t rsvd0;
588 }rsp;
589 }params;
590 };
591
592 struct rx_port_stats_v0 {
593 uint32_t rx_bytes_lsd;
594 uint32_t rx_bytes_msd;
595 uint32_t rx_total_frames;
596 uint32_t rx_unicast_frames;
597 uint32_t rx_multicast_frames;
598 uint32_t rx_broadcast_frames;
599 uint32_t rx_crc_errors;
600 uint32_t rx_alignment_symbol_errors;
601 uint32_t rx_pause_frames;
602 uint32_t rx_control_frames;
603 uint32_t rx_in_range_errors;
604 uint32_t rx_out_range_errors;
605 uint32_t rx_frame_too_long;
606 uint32_t rx_address_match_errors;
607 uint32_t rx_vlan_mismatch;
608 uint32_t rx_dropped_too_small;
609 uint32_t rx_dropped_too_short;
610 uint32_t rx_dropped_header_too_small;
611 uint32_t rx_dropped_tcp_length;
612 uint32_t rx_dropped_runt;
641 uint32_t tx_bytes_msd;
642 uint32_t tx_unicast_frames;
643 uint32_t tx_multicast_frames;
644 uint32_t tx_broadcast_frames;
645 uint32_t tx_pause_frames;
646 uint32_t tx_control_frames;
647 uint32_t tx_64_byte_packets;
648 uint32_t tx_65_127_byte_packets;
649 uint32_t tx_128_256_byte_packets;
650 uint32_t tx_256_511_byte_packets;
651 uint32_t tx_512_1023_byte_packets;
652 uint32_t tx_1024_1518_byte_packets;
653 uint32_t tx_1519_2047_byte_packets;
654 uint32_t tx_2048_4095_byte_packets;
655 uint32_t tx_4096_8191_byte_packets;
656 uint32_t tx_8192_9216_byte_packets;
657 uint32_t rx_fifo_overflow;
658 uint32_t rx_input_fifo_overflow;
659 };
660
661
662 struct rx_port_stats_v1 {
663 uint32_t rx_bytes_lsd;
664 uint32_t rx_bytes_msd;
665 uint32_t rx_ipv4_bytes_lsd;
666 uint32_t rx_ipv4_bytes_msd;
667 uint32_t rx_ipv6_bytes_lsd;
668 uint32_t rx_ipv6_bytes_msd;
669 uint32_t tx_bytes_lsd;
670 uint32_t tx_bytes_msd;
671 uint32_t rx_total_frames;
672 uint32_t rx_non_switched_unicast_frames;
673 uint32_t rx_non_switched_multicast_frames;
674 uint32_t rx_non_switched_broadcast_frames;
675 uint32_t rx_crc_errors;
676 uint32_t rx_alignment_symbol_errors;
677 uint32_t rx_pause_frames;
678 uint32_t rx_priority_pause_frames;
679 uint32_t rx_control_frames;
680 uint32_t rx_in_range_errors;
681 uint32_t rx_out_range_errors;
682 uint32_t rx_frame_too_long;
683 uint32_t rx_address_match_errors;
684 uint32_t rx_dropped_too_small;
685 uint32_t rx_dropped_too_short;
686 uint32_t rx_dropped_header_too_small;
687 uint32_t rx_dropped_tcp_length;
688 uint32_t rx_dropped_runt;
689 uint32_t rx_64_byte_packets;
690 uint32_t rx_65_127_byte_packets;
691 uint32_t rx_128_256_byte_packets;
692 uint32_t rx_256_511_byte_packets;
693 uint32_t rx_512_1023_byte_packets;
694 uint32_t rx_1024_1518_byte_packets;
695 uint32_t rx_1519_2047_byte_packets;
696 uint32_t rx_2048_4095_byte_packets;
697 uint32_t rx_4096_8191_byte_packets;
698 uint32_t rx_8192_9216_byte_packets;
699 uint32_t rx_ip_checksum_errs;
700 uint32_t rx_tcp_checksum_errs;
701 uint32_t rx_udp_checksum_errs;
702 uint32_t rx_non_rss_packets;
703 uint32_t rx_ipv4_packets;
704 uint32_t rx_ipv6_packets;
705 uint32_t rx_chute1_packets;
706 uint32_t rx_chute2_packets;
707 uint32_t rx_chute3_packets;
708 uint32_t rx_management_packets;
709 uint32_t rx_switched_unicast_packets;
710 uint32_t rx_switched_multicast_packets;
711 uint32_t rx_switched_broadcast_packets;
712 uint32_t tx_unicast_frames;
713 uint32_t tx_multicast_frames;
714 uint32_t tx_broadcast_frames;
715 uint32_t tx_pause_frames;
716 uint32_t tx_priority_pause_frames;
717 uint32_t tx_control_frames;
718 uint32_t tx_64_byte_packets;
719 uint32_t tx_65_127_byte_packets;
720 uint32_t tx_128_256_byte_packets;
721 uint32_t tx_256_511_byte_packets;
722 uint32_t tx_512_1023_byte_packets;
723 uint32_t tx_1024_1518_byte_packets;
724 uint32_t tx_1519_2047_byte_packets;
725 uint32_t tx_2048_4095_byte_packets;
726 uint32_t tx_4096_8191_byte_packets;
727 uint32_t tx_8192_9216_byte_packets;
728 uint32_t rxpp_fifo_overflow_drop;
729 uint32_t rx_input_fifo_overflow_drop;
730 uint32_t pmem_fifo_overflow_drop;
731 uint32_t jabber_events;
732 uint32_t rsvd2[3];
733 };
734
735
736 struct rx_stats_v0 {
737 struct rx_port_stats_v0 port[2];
738 uint32_t rx_drops_no_pbuf;
739 uint32_t rx_drops_no_txpb;
740 uint32_t rx_drops_no_erx_descr;
741 uint32_t rx_drops_no_tpre_descr;
742 uint32_t management_rx_port_packets;
743 uint32_t management_rx_port_bytes;
744 uint32_t management_rx_port_pause_frames;
745 uint32_t management_rx_port_errors;
746 uint32_t management_tx_port_packets;
747 uint32_t management_tx_port_bytes;
748 uint32_t management_tx_port_pause;
749 uint32_t management_rx_port_rxfifo_overflow;
750 uint32_t rx_drops_too_many_frags;
751 uint32_t rx_drops_invalid_ring;
752 uint32_t forwarded_packets;
753 uint32_t rx_drops_mtu;
754 uint32_t rsvd0[7]; /* fcoe is not relevent */
755 uint32_t port0_jabber_events;
756 uint32_t port1_jabber_events;
757 uint32_t rsvd1[6];
758 };
759
760 struct rx_stats_v1 {
761 struct rx_port_stats_v1 port[4];
762 uint32_t rsvd0[2];
763 uint32_t rx_drops_no_pbuf;
764 uint32_t rx_drops_no_txpb;
765 uint32_t rx_drops_no_erx_descr;
766 uint32_t rx_drops_no_tpre_descr;
767 uint32_t management_rx_port_packets;
768 uint32_t management_rx_port_pause_frames;
769 uint32_t management_rx_port_errors;
770 uint32_t management_tx_port_packets;
771 uint32_t management_tx_port_pause;
772 uint32_t management_rx_port_rxfifo_overflow;
773 uint32_t rx_drops_too_many_frags;
774 uint32_t rx_drops_invalid_ring;
775 uint32_t forwarded_packets;
776 uint32_t rx_drops_mtu;
777 uint32_t rsvd1[14]; /* fcoe is not relevent */
778 };
779
780 struct tx_counter {
781 uint32_t pkts;
782 uint32_t lsd;
783 uint32_t msd;
784 };
785
786 struct tx_stats {
787 struct tx_counter ct1pt0_xmt_ipv4_ctrs;
788 struct tx_counter ct1pt0_xmt_ipv6_ctrs;
789 struct tx_counter ct1pt0_rexmt_ipv4_ctrs;
790 struct tx_counter ct1pt0_rexmt_ipv6_ctrs;
791 struct tx_counter ct1pt1_xmt_ipv4_ctrs;
792 struct tx_counter ct1pt1_xmt_ipv6_ctrs;
793 struct tx_counter ct1pt1_rexmt_ipv4_ctrs;
794 struct tx_counter ct1pt1_rexmt_ipv6_ctrs;
795 struct tx_counter ct2pt0_xmt_ipv4_ctrs;
796 struct tx_counter ct2pt0_xmt_ipv6_ctrs;
797 struct tx_counter ct2pt0_rexmt_ipv4_ctrs;
798 struct tx_counter ct2pt0_rexmt_ipv6_ctrs;
799 struct tx_counter ct2pt1_xmt_ipv4_ctrs;
800 struct tx_counter ct2pt1_xmt_ipv6_ctrs;
801 struct tx_counter ct2pt1_rexmt_ipv4_ctrs;
802 struct tx_counter ct2pt1_rexmt_ipv6_ctrs;
803 };
804
805 struct rx_err_stats_v0 {
806 uint32_t rx_drops_no_fragments[44];
807 uint32_t debug_wdma_sent_hold;
808 uint32_t debug_wdma_pbfree_sent_hold;
809 uint32_t debug_wdma_zerobyte_pbfree_sent_hold;
810 uint32_t debug_pmem_pbuf_dealloc;
811 };
812
813 struct rx_err_stats_v1 {
814 uint32_t rx_drops_no_fragments[68];
815 uint32_t debug_wdma_sent_hold;
816 uint32_t debug_wdma_pbfree_sent_hold;
817 uint32_t debug_wdma_zerobyte_pbfree_sent_hold;
818 uint32_t debug_pmem_pbuf_dealloc;
819 };
820
821 struct mem_stats {
822 uint32_t eth_red_drops;
823 uint32_t lro_red_drops;
824 uint32_t ulp0_red_drops;
825 uint32_t ulp1_red_drops;
826 uint32_t rsvd;
827 uint32_t global_red_drops;
828 };
829
830
831 struct be_hw_stats_v0 {
832 struct rx_stats_v0 rx;
833 struct tx_stats tx;
834 struct rx_err_stats_v0 err_rx;
835 struct mem_stats mem;
836 };
837
838 struct be_hw_stats_v1 {
839 struct rx_stats_v1 rx;
840 struct tx_stats tx;
841 struct rx_err_stats_v1 err_rx;
842 struct mem_stats mem;
843 uint32_t rsvd1[18];
844 };
845
846
847 /* [04] OPCODE_GET_NIC_STATS */
848 struct mbx_get_nic_stats {
849 /* dw0 - dw3 */
850 struct mbx_hdr hdr;
851 union {
852 struct {
853 uint32_t rsvd0;
854 }req;
855
856 union {
857 struct be_hw_stats_v0 v0;
858 struct be_hw_stats_v1 v1;
859 }rsp;
860 }params;
861 };
862
863 /* Lancer Stats */
864 struct lancer_cmd_pport_stats {
865 uint32_t tx_packets_lo;
866 uint32_t tx_packets_hi;
867 uint32_t tx_unicast_packets_lo;
868 uint32_t tx_unicast_packets_hi;
869 uint32_t tx_multicast_packets_lo;
870 uint32_t tx_multicast_packets_hi;
871 uint32_t tx_broadcast_packets_lo;
872 uint32_t tx_broadcast_packets_hi;
873 uint32_t tx_bytes_lo;
874 uint32_t tx_bytes_hi;
875 uint32_t tx_unicast_bytes_lo;
876 uint32_t tx_unicast_bytes_hi;
877 uint32_t tx_multicast_bytes_lo;
878 uint32_t tx_multicast_bytes_hi;
879 uint32_t tx_broadcast_bytes_lo;
880 uint32_t tx_broadcast_bytes_hi;
881 uint32_t tx_discards_lo;
882 uint32_t tx_discards_hi;
883 uint32_t tx_errors_lo;
884 uint32_t tx_errors_hi;
885 uint32_t tx_pause_frames_lo;
886 uint32_t tx_pause_frames_hi;
887 uint32_t tx_pause_on_frames_lo;
888 uint32_t tx_pause_on_frames_hi;
889 uint32_t tx_pause_off_frames_lo;
890 uint32_t tx_pause_off_frames_hi;
891 uint32_t tx_internal_mac_errors_lo;
892 uint32_t tx_internal_mac_errors_hi;
893 uint32_t tx_control_frames_lo;
894 uint32_t tx_control_frames_hi;
895 uint32_t tx_packets_64_bytes_lo;
896 uint32_t tx_packets_64_bytes_hi;
897 uint32_t tx_packets_65_to_127_bytes_lo;
898 uint32_t tx_packets_65_to_127_bytes_hi;
899 uint32_t tx_packets_128_to_255_bytes_lo;
900 uint32_t tx_packets_128_to_255_bytes_hi;
901 uint32_t tx_packets_256_to_511_bytes_lo;
902 uint32_t tx_packets_256_to_511_bytes_hi;
903 uint32_t tx_packets_512_to_1023_bytes_lo;
904 uint32_t tx_packets_512_to_1023_bytes_hi;
905 uint32_t tx_packets_1024_to_1518_bytes_lo;
906 uint32_t tx_packets_1024_to_1518_bytes_hi;
907 uint32_t tx_packets_1519_to_2047_bytes_lo;
908 uint32_t tx_packets_1519_to_2047_bytes_hi;
909 uint32_t tx_packets_2048_to_4095_bytes_lo;
910 uint32_t tx_packets_2048_to_4095_bytes_hi;
911 uint32_t tx_packets_4096_to_8191_bytes_lo;
912 uint32_t tx_packets_4096_to_8191_bytes_hi;
913 uint32_t tx_packets_8192_to_9216_bytes_lo;
914 uint32_t tx_packets_8192_to_9216_bytes_hi;
915 uint32_t tx_lso_packets_lo;
916 uint32_t tx_lso_packets_hi;
917 uint32_t rx_packets_lo;
918 uint32_t rx_packets_hi;
919 uint32_t rx_unicast_packets_lo;
920 uint32_t rx_unicast_packets_hi;
921 uint32_t rx_multicast_packets_lo;
922 uint32_t rx_multicast_packets_hi;
923 uint32_t rx_broadcast_packets_lo;
924 uint32_t rx_broadcast_packets_hi;
925 uint32_t rx_bytes_lo;
926 uint32_t rx_bytes_hi;
927 uint32_t rx_unicast_bytes_lo;
928 uint32_t rx_unicast_bytes_hi;
929 uint32_t rx_multicast_bytes_lo;
930 uint32_t rx_multicast_bytes_hi;
931 uint32_t rx_broadcast_bytes_lo;
932 uint32_t rx_broadcast_bytes_hi;
933 uint32_t rx_unknown_protos;
934 uint32_t rsvd_69;
935 uint32_t rx_discards_lo;
936 uint32_t rx_discards_hi;
937 uint32_t rx_errors_lo;
938 uint32_t rx_errors_hi;
939 uint32_t rx_crc_errors_lo;
940 uint32_t rx_crc_errors_hi;
941 uint32_t rx_alignment_errors_lo;
942 uint32_t rx_alignment_errors_hi;
943 uint32_t rx_symbol_errors_lo;
944 uint32_t rx_symbol_errors_hi;
945 uint32_t rx_pause_frames_lo;
946 uint32_t rx_pause_frames_hi;
947 uint32_t rx_pause_on_frames_lo;
948 uint32_t rx_pause_on_frames_hi;
949 uint32_t rx_pause_off_frames_lo;
950 uint32_t rx_pause_off_frames_hi;
951 uint32_t rx_frames_too_long_lo;
952 uint32_t rx_frames_too_long_hi;
953 uint32_t rx_internal_mac_errors_lo;
954 uint32_t rx_internal_mac_errors_hi;
955 uint32_t rx_undersize_packets;
956 uint32_t rx_oversize_packets;
957 uint32_t rx_fragment_packets;
958 uint32_t rx_jabbers;
959 uint32_t rx_control_frames_lo;
960 uint32_t rx_control_frames_hi;
961 uint32_t rx_control_frames_unknown_opcode_lo;
962 uint32_t rx_control_frames_unknown_opcode_hi;
963 uint32_t rx_in_range_errors;
964 uint32_t rx_out_of_range_errors;
965 uint32_t rx_address_match_errors;
966 uint32_t rx_vlan_mismatch_errors;
967 uint32_t rx_dropped_too_small;
968 uint32_t rx_dropped_too_short;
969 uint32_t rx_dropped_header_too_small;
970 uint32_t rx_dropped_invalid_tcp_length;
971 uint32_t rx_dropped_runt;
972 uint32_t rx_ip_checksum_errors;
973 uint32_t rx_tcp_checksum_errors;
974 uint32_t rx_udp_checksum_errors;
975 uint32_t rx_non_rss_packets;
976 uint32_t rsvd_111;
977 uint32_t rx_ipv4_packets_lo;
978 uint32_t rx_ipv4_packets_hi;
979 uint32_t rx_ipv6_packets_lo;
980 uint32_t rx_ipv6_packets_hi;
981 uint32_t rx_ipv4_bytes_lo;
982 uint32_t rx_ipv4_bytes_hi;
983 uint32_t rx_ipv6_bytes_lo;
984 uint32_t rx_ipv6_bytes_hi;
985 uint32_t rx_nic_packets_lo;
986 uint32_t rx_nic_packets_hi;
987 uint32_t rx_tcp_packets_lo;
988 uint32_t rx_tcp_packets_hi;
989 uint32_t rx_iscsi_packets_lo;
990 uint32_t rx_iscsi_packets_hi;
991 uint32_t rx_management_packets_lo;
992 uint32_t rx_management_packets_hi;
993 uint32_t rx_switched_unicast_packets_lo;
994 uint32_t rx_switched_unicast_packets_hi;
995 uint32_t rx_switched_multicast_packets_lo;
996 uint32_t rx_switched_multicast_packets_hi;
997 uint32_t rx_switched_broadcast_packets_lo;
998 uint32_t rx_switched_broadcast_packets_hi;
999 uint32_t num_forwards_lo;
1000 uint32_t num_forwards_hi;
1001 uint32_t rx_fifo_overflow;
1002 uint32_t rx_input_fifo_overflow;
1003 uint32_t rx_drops_too_many_frags_lo;
1004 uint32_t rx_drops_too_many_frags_hi;
1005 uint32_t rx_drops_invalid_queue;
1006 uint32_t rsvd_141;
1007 uint32_t rx_drops_mtu_lo;
1008 uint32_t rx_drops_mtu_hi;
1009 uint32_t rx_packets_64_bytes_lo;
1010 uint32_t rx_packets_64_bytes_hi;
1011 uint32_t rx_packets_65_to_127_bytes_lo;
1012 uint32_t rx_packets_65_to_127_bytes_hi;
1013 uint32_t rx_packets_128_to_255_bytes_lo;
1014 uint32_t rx_packets_128_to_255_bytes_hi;
1015 uint32_t rx_packets_256_to_511_bytes_lo;
1016 uint32_t rx_packets_256_to_511_bytes_hi;
1017 uint32_t rx_packets_512_to_1023_bytes_lo;
1018 uint32_t rx_packets_512_to_1023_bytes_hi;
1019 uint32_t rx_packets_1024_to_1518_bytes_lo;
1020 uint32_t rx_packets_1024_to_1518_bytes_hi;
1021 uint32_t rx_packets_1519_to_2047_bytes_lo;
1022 uint32_t rx_packets_1519_to_2047_bytes_hi;
1023 uint32_t rx_packets_2048_to_4095_bytes_lo;
1024 uint32_t rx_packets_2048_to_4095_bytes_hi;
1025 uint32_t rx_packets_4096_to_8191_bytes_lo;
1026 uint32_t rx_packets_4096_to_8191_bytes_hi;
1027 uint32_t rx_packets_8192_to_9216_bytes_lo;
1028 uint32_t rx_packets_8192_to_9216_bytes_hi;
1029 };
1030
1031 struct pport_stats_params {
1032 uint16_t pport_num;
1033 uint8_t rsvd;
1034 uint8_t reset_stats;
1035 };
1036
1037 /* [18] OPCODE_NIC_GET_PPORT_STATS */
1038 struct mbx_get_pport_stats {
1039 /* dw0 - dw3 */
1040 struct mbx_hdr hdr;
1041 union {
1042 struct {
1043 struct pport_stats_params arg;
1044 }req;
1045
1046 struct {
1047 struct lancer_cmd_pport_stats pport_stats;
1048 }rsp;
1049 }params;
1050 };
1051
1052 /* [01] OPCODE_CONFIG_NIC_RSS */
1053 struct mbx_config_nic_rss {
1054 struct mbx_hdr hdr;
1055 union {
1056 struct {
1057 #ifdef _BIG_ENDIAN
1058 uint32_t if_id;
1059 uint16_t cpu_tbl_sz_log2;
1060 uint16_t enable_rss;
1061 uint32_t hash[10];
1062 uint8_t cputable[128];
1063 uint8_t rsvd[3];
1064 uint8_t flush;
1065 #else
1066 uint32_t if_id;
1067 uint16_t enable_rss;
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