1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright © 2003-2011 Emulex. All rights reserved. */
23
24 /*
25 * header file containing the data structure definitions for the NIC
26 * subsystetm
27 */
28
29 #ifndef _OCE_HW_ETH_H_
30 #define _OCE_HW_ETH_H_
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 #include <oce_hw.h>
37
38 #define NIC_WQE_SIZE 16
39 /* NIC packet type */
40 #define NIC_UNICAST 0x00
41 #define NIC_MULTICAST 0x01
42 #define NIC_BROADCAST 0x02
43
44 /* HDS type */
45 #define NIC_HDS_NO_SPLIT 0x00
46 #define NIC_HDS_SPLIT_L3PL 0x01
47 #define NIC_HDS_SPLIT_L4PL 0x02
48
49 /* NIC WQ types */
50 #define NIC_WQ_TYPE_FORWARDING 0x01
51 #define NIC_WQ_TYPE_STANDARD 0x02
52 #define NIC_WQ_TYPE_LOW_LATENCY 0x04
53
54 #pragma pack(1)
55 enum {
56 OPCODE_CONFIG_NIC_RSS = 1,
57 OPCODE_CONFIG_NIC_ACPI = 2,
58 OPCODE_CONFIG_NIC_PROMISCUOUS = 3,
59 OPCODE_GET_NIC_STATS = 4,
60 OPCODE_CREATE_NIC_WQ = 7,
61 OPCODE_CREATE_NIC_RQ = 8,
62 OPCODE_DELETE_NIC_WQ = 9,
63 OPCODE_DELETE_NIC_RQ = 10,
64 OPCODE_CREATE_NIC_RSS_CQ = 11,
65 OPCODE_DELETE_NIC_RSS_CQ = 12,
66 OPCODE_SET_RSS_EQ_MSI = 13,
67 OPCODE_CREATE_NIC_HDS_RQ = 14,
68 OPCODE_DELETE_NIC_HDS_RQ = 15,
69 OPCODE_CONFIG_NIC_RSS_ADVANCED = 16
70 };
71
72 enum {
73 RSS_ENABLE_NONE = 0x0, /* (No RSS) */
74 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */
75 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */
76 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */
77 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */
78
79 };
80 /* NIC header WQE */
81 struct oce_nic_hdr_wqe {
82 union {
83 struct {
84 #ifdef _BIG_ENDIAN
85 /* dw0 */
86 uint32_t rsvd0;
87
88 /* dw1 */
89 uint32_t last_seg_udp_len:14;
90 uint32_t rsvd1:18;
91
92 /* dw2 */
93 uint32_t lso_mss:14;
94 uint32_t num_wqe:5;
95 uint32_t rsvd4:2;
96 uint32_t vlan:1;
97 uint32_t lso:1;
98 uint32_t tcpcs:1;
99 uint32_t udpcs:1;
100 uint32_t ipcs:1;
101 uint32_t rsvd3:1;
102 uint32_t rsvd2:1;
103 uint32_t forward:1;
104 uint32_t crc:1;
105 uint32_t event:1;
106 uint32_t complete:1;
107
108 /* dw3 */
109 uint32_t vlan_tag:16;
110 uint32_t total_length:16;
111 #else
112 /* dw0 */
113 uint32_t rsvd0;
114
115 /* dw1 */
116 uint32_t rsvd1:18;
117 uint32_t last_seg_udp_len:14;
118
119 /* dw2 */
120 uint32_t complete:1;
121 uint32_t event:1;
122 uint32_t crc:1;
123 uint32_t forward:1;
124 uint32_t rsvd2:1;
125 uint32_t rsvd3:1;
126 uint32_t ipcs:1;
127 uint32_t udpcs:1;
128 uint32_t tcpcs:1;
129 uint32_t lso:1;
130 uint32_t vlan:1;
131 uint32_t rsvd4:2;
132 uint32_t num_wqe:5;
133 uint32_t lso_mss:14;
134
135 /* dw3 */
136 uint32_t total_length:16;
137 uint32_t vlan_tag:16;
138 #endif
139 }s;
140 uint32_t dw[4];
141 }u0;
142 };
143
144 /* NIC fragment WQE */
145 struct oce_nic_frag_wqe {
146 union {
147 struct {
148 /* dw0 */
149 uint32_t frag_pa_hi;
150 /* dw1 */
151 uint32_t frag_pa_lo;
152 /* dw2 */
153 uint32_t rsvd0;
154 uint32_t frag_len;
155 }s;
156 uint32_t dw[4];
157 }u0;
158 };
159
160 /* Ethernet Tx Completion Descriptor */
161 struct oce_nic_tx_cqe {
162 union {
163 struct {
164 #ifdef _BIG_ENDIAN
165 /* dw 0 */
166 uint32_t status:4;
167 uint32_t rsvd0:8;
168 uint32_t port:2;
169 uint32_t ct:2;
170 uint32_t wqe_index:16;
171
172 /* dw 1 */
173 uint32_t rsvd1:5;
174 uint32_t cast_enc:2;
175 uint32_t lso:1;
176 uint32_t nwh_bytes:8;
177 uint32_t user_bytes:16;
178
179 /* dw 2 */
180 uint32_t rsvd2;
181
182
183 /* dw 3 */
184 uint32_t valid:1;
185 uint32_t rsvd3:4;
186 uint32_t wq_id:11;
187 uint32_t num_pkts:16;
188 #else
189 /* dw 0 */
190 uint32_t wqe_index:16;
191 uint32_t ct:2;
192 uint32_t port:2;
193 uint32_t rsvd0:8;
194 uint32_t status:4;
195
196 /* dw 1 */
197 uint32_t user_bytes:16;
198 uint32_t nwh_bytes:8;
199 uint32_t lso:1;
200 uint32_t cast_enc:2;
201 uint32_t rsvd1:5;
202 /* dw 2 */
203 uint32_t rsvd2;
204
205 /* dw 3 */
206 uint32_t num_pkts:16;
207 uint32_t wq_id:11;
208 uint32_t rsvd3:4;
209 uint32_t valid:1;
210 #endif
211 }s;
212 uint32_t dw[4];
213 }u0;
214 };
215 #define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3])
216 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
217
218 /* Receive Queue Entry (RQE) */
219 struct oce_nic_rqe {
220 union {
221 struct {
222 uint32_t frag_pa_hi;
223 uint32_t frag_pa_lo;
224 }s;
225 uint32_t dw[2];
226 }u0;
227 };
228
229 /* NIC Receive CQE */
230 struct oce_nic_rx_cqe {
231 union {
232 struct {
233 #ifdef _BIG_ENDIAN
234 /* dw 0 */
235 uint32_t ip_options:1;
236 uint32_t port:1;
237 uint32_t pkt_size:14;
238 uint32_t vlan_tag:16;
239
240 /* dw 1 */
241 uint32_t num_fragments:3;
242 uint32_t switched:1;
243 uint32_t ct:2;
244 uint32_t frag_index:10;
245 uint32_t rsvd0:1;
246 uint32_t vlan_tag_present:1;
247 uint32_t mac_dst:6;
248 uint32_t ip_ver:1;
249 uint32_t l4_cksum_pass:1;
250 uint32_t ip_cksum_pass:1;
251 uint32_t udpframe:1;
252 uint32_t tcpframe:1;
253 uint32_t ipframe:1;
254 uint32_t rss_hp:1;
255 uint32_t error:1;
256
257 /* dw 2 */
258 uint32_t valid:1;
259 uint32_t hds_type:2;
260 uint32_t lro_pkt:1;
261 uint32_t rsvd4:1;
262 uint32_t hds_hdr_size:12;
263 uint32_t hds_hdr_frag_index:10;
264 uint32_t rss_bank:1;
265 uint32_t qnq:1;
266 uint32_t pkt_type:2;
267 uint32_t rss_flush:1;
268
269 /* dw 3 */
270 uint32_t rss_hash_value;
271 #else
272 /* dw 0 */
273 uint32_t vlan_tag:16;
274 uint32_t pkt_size:14;
275 uint32_t port:1;
276 uint32_t ip_options:1;
277 /* dw 1 */
278 uint32_t error:1;
279 uint32_t rss_hp:1;
280 uint32_t ipframe:1;
281 uint32_t tcpframe:1;
282 uint32_t udpframe:1;
283 uint32_t ip_cksum_pass:1;
284 uint32_t l4_cksum_pass:1;
285 uint32_t ip_ver:1;
286 uint32_t mac_dst:6;
287 uint32_t vlan_tag_present:1;
288 uint32_t rsvd0:1;
289 uint32_t frag_index:10;
290 uint32_t ct:2;
291 uint32_t switched:1;
292 uint32_t num_fragments:3;
293
294 /* dw 2 */
295 uint32_t rss_flush:1;
296 uint32_t pkt_type:2;
297 uint32_t qnq:1;
298 uint32_t rss_bank:1;
299 uint32_t hds_hdr_frag_index:10;
300 uint32_t hds_hdr_size:12;
301 uint32_t rsvd4:1;
302 uint32_t lro_pkt:1;
303 uint32_t hds_type:2;
304 uint32_t valid:1;
305 /* dw 3 */
306 uint32_t rss_hash_value;
307 #endif
308 }s;
309 uint32_t dw[4];
310 }u0;
311 };
312 #define RQ_CQE_VALID_MASK 0x80
313 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
314 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
315
316 struct mbx_config_nic_promiscuous {
317 struct mbx_hdr hdr;
318 union {
319 struct {
320 #ifdef _BIG_ENDIAN
321 uint16_t rsvd0;
322 uint8_t port1_promisc;
323 uint8_t port0_promisc;
324 #else
325 uint8_t port0_promisc;
326 uint8_t port1_promisc;
327 uint16_t rsvd0;
328 #endif
329 }req;
330
331 struct {
332 uint32_t rsvd0;
333 }rsp;
334 }params;
335 };
336
337 /* [07] OPCODE_CREATE_NIC_WQ */
338 struct mbx_create_nic_wq {
339
340 /* dw0 - dw3 */
341 struct mbx_hdr hdr;
342 union {
343 struct {
344 #ifdef _BIG_ENDIAN
345 /* dw4 */
346 uint8_t rsvd1;
347 uint8_t nic_wq_type;
348 uint8_t rsvd0;
349 uint8_t num_pages;
350
351 /* dw5 */
352 uint32_t rsvd3:12;
353 uint32_t wq_size:4;
354 uint32_t rsvd2:16;
355
356 /* dw6 */
357 uint32_t valid:1;
358 uint32_t pd_id:9;
359 uint32_t pci_function_id:8;
360 uint32_t rsvd4:14;
361
362 /* dw7 */
363 uint32_t rsvd5:16;
364 uint32_t cq_id:16;
365 #else
366 /* dw4 */
367 uint8_t num_pages;
368 uint8_t rsvd0;
369 uint8_t nic_wq_type;
370 uint8_t rsvd1;
371
372 /* dw5 */
373 uint32_t rsvd2:16;
374 uint32_t wq_size:4;
375 uint32_t rsvd3:12;
376
377 /* dw6 */
378 uint32_t rsvd4:14;
379 uint32_t pci_function_id:8;
380 uint32_t pd_id:9;
381 uint32_t valid:1;
382
383 /* dw7 */
384 uint32_t cq_id:16;
385 uint32_t rsvd5:16;
386 #endif
387 /* dw8 - dw20 */
388 uint32_t rsvd6[13];
389 /* dw21 - dw36 */
390 struct phys_addr pages[8];
391 }req;
392
393 struct {
394 uint16_t wq_id;
395 uint16_t rsvd0;
396 }rsp;
397 }params;
398 };
399
400 /* [09] OPCODE_DELETE_NIC_WQ */
401 struct mbx_delete_nic_wq {
402 /* dw0 - dw3 */
403 struct mbx_hdr hdr;
404 union {
405 struct {
406 #ifdef _BIG_ENDIAN
407 /* dw4 */
408 uint16_t rsvd0;
409 uint16_t wq_id;
410 #else
411 /* dw4 */
412 uint16_t wq_id;
413 uint16_t rsvd0;
414 #endif
415 }req;
416 struct {
417 uint32_t rsvd0;
418 }rsp;
419 }params;
420 };
421
422 /* [08] OPCODE_CREATE_NIC_RQ */
423 struct mbx_create_nic_rq {
424 /* dw0 - dw3 */
425 struct mbx_hdr hdr;
426 union {
427 struct {
428 #ifdef _BIG_ENDIAN
429 /* dw4 */
430 uint8_t num_pages;
431 uint8_t frag_size;
432 uint16_t cq_id;
433 #else
434 /* dw4 */
435 uint16_t cq_id;
436 uint8_t frag_size;
437 uint8_t num_pages;
438 #endif
439 /* dw5 - dw8 */
440 struct phys_addr pages[2];
441 /* dw9 */
442 uint32_t if_id;
443 #ifdef _BIG_ENDIAN
444 /* dw10 */
445 uint16_t rsvd0;
446 uint16_t max_frame_size;
447 #else
448 /* dw10 */
449 uint16_t max_frame_size;
450 uint16_t rsvd0;
451 #endif
452 /* dw11 */
453 uint32_t is_rss_queue;
454 }req;
455
456 struct {
457 /* dw4 */
458 union {
459 struct {
460 uint16_t rq_id;
461 uint8_t rss_cpuid;
462 uint8_t rsvd0;
463 } s;
464 uint32_t dw4;
465 }u0;
466 }rsp;
467 }params;
468 };
469
470 /* [10] OPCODE_DELETE_NIC_RQ */
471 struct mbx_delete_nic_rq {
472 /* dw0 - dw3 */
473 struct mbx_hdr hdr;
474 union {
475 struct {
476 #ifdef _BIG_ENDIAN
477 /* dw4 */
478 uint16_t bypass_flush;
479 uint16_t rq_id;
480 #else
481 /* dw4 */
482 uint16_t rq_id;
483 uint16_t bypass_flush;
484 #endif
485 }req;
486
487 struct {
488 /* dw4 */
489 uint32_t rsvd0;
490 }rsp;
491 }params;
492 };
493
494 struct rx_port_stats {
495 uint32_t rx_bytes_lsd;
496 uint32_t rx_bytes_msd;
497 uint32_t rx_total_frames;
498 uint32_t rx_unicast_frames;
499 uint32_t rx_multicast_frames;
500 uint32_t rx_broadcast_frames;
501 uint32_t rx_crc_errors;
502 uint32_t rx_alignment_symbol_errors;
503 uint32_t rx_pause_frames;
504 uint32_t rx_control_frames;
505 uint32_t rx_in_range_errors;
506 uint32_t rx_out_range_errors;
507 uint32_t rx_frame_too_long;
508 uint32_t rx_address_match_errors;
509 uint32_t rx_vlan_mismatch;
510 uint32_t rx_dropped_too_small;
511 uint32_t rx_dropped_too_short;
512 uint32_t rx_dropped_header_too_small;
513 uint32_t rx_dropped_tcp_length;
514 uint32_t rx_dropped_runt;
515 uint32_t rx_64_byte_packets;
516 uint32_t rx_65_127_byte_packets;
517 uint32_t rx_128_256_byte_packets;
518 uint32_t rx_256_511_byte_packets;
519 uint32_t rx_512_1023_byte_packets;
520 uint32_t rx_1024_1518_byte_packets;
521 uint32_t rx_1519_2047_byte_packets;
522 uint32_t rx_2048_4095_byte_packets;
523 uint32_t rx_4096_8191_byte_packets;
524 uint32_t rx_8192_9216_byte_packets;
525 uint32_t rx_ip_checksum_errs;
526 uint32_t rx_tcp_checksum_errs;
527 uint32_t rx_udp_checksum_errs;
528 uint32_t rx_non_rss_packets;
529 uint32_t rx_ipv4_packets;
530 uint32_t rx_ipv6_packets;
531 uint32_t rx_ipv4_bytes_lsd;
532 uint32_t rx_ipv4_bytes_msd;
533 uint32_t rx_ipv6_bytes_lsd;
534 uint32_t rx_ipv6_bytes_msd;
535 uint32_t rx_chute1_packets;
536 uint32_t rx_chute2_packets;
537 uint32_t rx_chute3_packets;
538 uint32_t rx_management_packets;
539 uint32_t rx_switched_unicast_packets;
540 uint32_t rx_switched_multicast_packets;
541 uint32_t rx_switched_broadcast_packets;
542 uint32_t tx_bytes_lsd;
543 uint32_t tx_bytes_msd;
544 uint32_t tx_unicast_frames;
545 uint32_t tx_multicast_frames;
546 uint32_t tx_broadcast_frames;
547 uint32_t tx_pause_frames;
548 uint32_t tx_control_frames;
549 uint32_t tx_64_byte_packets;
550 uint32_t tx_65_127_byte_packets;
551 uint32_t tx_128_256_byte_packets;
552 uint32_t tx_256_511_byte_packets;
553 uint32_t tx_512_1023_byte_packets;
554 uint32_t tx_1024_1518_byte_packets;
555 uint32_t tx_1519_2047_byte_packets;
556 uint32_t tx_2048_4095_byte_packets;
557 uint32_t tx_4096_8191_byte_packets;
558 uint32_t tx_8192_9216_byte_packets;
559 uint32_t rx_fifo_overflow;
560 uint32_t rx_input_fifo_overflow;
561 };
562
563 struct rx_stats {
564 /* dw 0-131 --2 X 66 */
565 struct rx_port_stats port[2];
566 /* dw 132-147 --16 */
567 uint32_t rx_drops_no_pbuf;
568 uint32_t rx_drops_no_txpb;
569 uint32_t rx_drops_no_erx_descr;
570 uint32_t rx_drops_no_tpre_descr;
571 uint32_t management_rx_port_packets;
572 uint32_t management_rx_port_bytes;
573 uint32_t management_rx_port_pause_frames;
574 uint32_t management_rx_port_errors;
575 uint32_t management_tx_port_packets;
576 uint32_t management_tx_port_bytes;
577 uint32_t management_tx_port_pause;
578 uint32_t management_rx_port_rxfifo_overflow;
579 uint32_t rx_drops_too_many_frags;
580 uint32_t rx_drops_invalid_ring;
581 uint32_t forwarded_packets;
582 uint32_t rx_drops_mtu;
583 /* fcoe is not relevent */
584 uint32_t rsvd[15];
585 };
586
587 struct tx_counter {
588 uint32_t pkts;
589 uint32_t lsd;
590 uint32_t msd;
591 };
592
593 struct tx_stats {
594 struct tx_counter ct1pt0_xmt_ipv4_ctrs;
595 struct tx_counter ct1pt0_xmt_ipv6_ctrs;
596 struct tx_counter ct1pt0_rexmt_ipv4_ctrs;
597 struct tx_counter ct1pt0_rexmt_ipv6_ctrs;
598 struct tx_counter ct1pt1_xmt_ipv4_ctrs;
599 struct tx_counter ct1pt1_xmt_ipv6_ctrs;
600 struct tx_counter ct1pt1_rexmt_ipv4_ctrs;
601 struct tx_counter ct1pt1_rexmt_ipv6_ctrs;
602 struct tx_counter ct2pt0_xmt_ipv4_ctrs;
603 struct tx_counter ct2pt0_xmt_ipv6_ctrs;
604 struct tx_counter ct2pt0_rexmt_ipv4_ctrs;
605 struct tx_counter ct2pt0_rexmt_ipv6_ctrs;
606 struct tx_counter ct2pt1_xmt_ipv4_ctrs;
607 struct tx_counter ct2pt1_xmt_ipv6_ctrs;
608 struct tx_counter ct2pt1_rexmt_ipv4_ctrs;
609 struct tx_counter ct2pt1_rexmt_ipv6_ctrs;
610 };
611
612 struct rx_err_stats {
613 uint32_t rx_drops_no_fragments[44];
614 uint32_t debug_wdma_sent_hold;
615 uint32_t debug_wdma_pbfree_sent_hold;
616 uint32_t debug_wdma_zerobyte_pbfree_sent_hold;
617 uint32_t debug_pmem_pbuf_dealloc;
618 };
619
620 struct mem_stats {
621 uint32_t eth_red_drops;
622 uint32_t lro_red_drops;
623 uint32_t ulp0_red_drops;
624 uint32_t ulp1_red_drops;
625 };
626
627 /* [04] OPCODE_GET_NIC_STATS */
628 struct mbx_get_nic_stats {
629 /* dw0 - dw3 */
630 struct mbx_hdr hdr;
631 union {
632 struct {
633 uint32_t rsvd0;
634 }req;
635
636 struct {
637 struct rx_stats rx;
638 struct tx_stats tx;
639 struct rx_err_stats err_rx;
640 struct mem_stats mem;
641 }rsp;
642 }params;
643 };
644
645 /* [01] OPCODE_CONFIG_NIC_RSS */
646 struct mbx_config_nic_rss {
647 struct mbx_hdr hdr;
648 union {
649 struct {
650 #ifdef _BIG_ENDIAN
651 uint32_t if_id;
652 uint16_t cpu_tbl_sz_log2;
653 uint16_t enable_rss;
654 uint32_t hash[10];
655 uint8_t cputable[128];
656 uint8_t rsvd[3];
657 uint8_t flush;
658 #else
659 uint32_t if_id;
660 uint16_t enable_rss;
661 uint16_t cpu_tbl_sz_log2;
662 uint32_t hash[10];
663 uint8_t cputable[128];
664 uint8_t flush;
665 uint8_t rsvd[3];
666 #endif
667 }req;
668 struct {
669 uint8_t rsvd[3];
670 uint8_t rss_bank;
671 }rsp;
672 }params;
673 };
674
675 #pragma pack()
676
677 #ifdef __cplusplus
678 }
679 #endif
680
681 #endif /* _OCE_HW_ETH_H_ */