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NEX-1890 update oce from source provided by Emulex
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--- old/usr/src/uts/common/sys/fibre-channel/fca/oce/oce_hw.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/oce/oce_hw.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
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12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 -/* Copyright © 2003-2011 Emulex. All rights reserved. */
22 +/*
23 + * Copyright (c) 2009-2012 Emulex. All rights reserved.
24 + * Use is subject to license terms.
25 + */
23 26
27 +
28 +
24 29 /*
25 30 * Header file containing the command structures for Hardware
26 31 */
27 32
28 33 #ifndef _OCE_HW_H_
29 34 #define _OCE_HW_H_
30 35
31 36 #ifdef __cplusplus
32 37 extern "C" {
33 38 #endif
34 39
35 40 #include <sys/types.h>
41 +#include "oce_sli4.h"
36 42
37 43 #pragma pack(1)
38 44
39 45 #define OC_CNA_GEN2 0x2
40 46 #define OC_CNA_GEN3 0x3
47 +enum {
48 + ASIC_REV_A0 = 0x0,
49 + ASIC_REV_A1 = 0x1,
50 + ASIC_REV_A2 = 0x2
51 +};
52 +#define BE3_ASIC_REV_A0 ((OC_CNA_GEN3<<8)| ASIC_REV_A0)
53 +#define BE3_ASIC_REV_A1 ((OC_CNA_GEN3<<8)| ASIC_REV_A1)
54 +#define BE3_ASIC_REV_A2 ((OC_CNA_GEN3<<8)| ASIC_REV_A2)
55 +
56 +#define BE3_A1(dev) (dev->asic_revision == BE3_ASIC_REV_A0 ||\
57 + dev->asic_revision == BE3_ASIC_REV_A1)
58 +
41 59 #define DEVID_TIGERSHARK 0x700
42 60 #define DEVID_TOMCAT 0x710
61 +#define DEVID_LANCER 0xe220
43 62
63 +#define LANCER_CHIP(device) (device->device_id == DEVID_LANCER)
64 +
65 +
44 66 /* PCI CSR offsets */
45 -#define PCICFG_F1_CSR 0x0 /* F1 for NIC */
46 -#define PCICFG_SEMAPHORE 0xbc
47 -#define PCICFG_SOFT_RESET 0x5c
48 -#define PCICFG_UE_STATUS_HI_MASK 0xac
49 -#define PCICFG_UE_STATUS_LO_MASK 0xa8
50 -#define PCICFG_ONLINE0 0xb0
51 -#define PCICFG_ONLINE1 0xb4
67 +#define PCICFG_F1_CSR 0x0 /* F1 for NIC */
68 +#define PCICFG_SEMAPHORE 0xbc
69 +#define PCICFG_SOFT_RESET 0x5c
70 +#define PCICFG_UE_STATUS_LO 0xA0 /* UE status low offset */
71 +#define PCICFG_UE_STATUS_HI 0xA4 /* UE status high offset */
72 +#define PCICFG_UE_STATUS_LO_MASK 0xa8 /* Error mask - low */
73 +#define PCICFG_UE_STATUS_HI_MASK 0xac /* Error mask - high */
74 +#define PCICFG_ONLINE0 0xb0
75 +#define PCICFG_ONLINE1 0xb4
52 76 #define INTR_EN 0x20000000
53 77 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */
54 78
55 79 /* CSR register offsets */
56 80 #define MPU_EP_CONTROL 0
57 81 #define MPU_EP_SEMAPHORE 0xac
58 82 #define PCICFG_INTR_CTRL 0xfc
59 83 #define HOSTINTR_MASK (1 << 29)
60 84 #define HOSTINTR_PFUNC_SHIFT 26
61 85 #define HOSTINTR_PFUNC_MASK 7
62 86
87 +/* Link Status CSR */
88 +#define PCICFG_PCIE_LINK_STATUS_OFFSET 0xd0
89 +#define PCIE_LINK_STATUS_SPEED_MASK 0xFF
90 +#define PCIE_LINK_STATUS_SPEED_SHIFT 16
91 +#define PCIE_LINK_STATUS_NEG_WIDTH_MASK 0x3F
92 +#define PCIE_LINK_STATUS_NEG_WIDTH_SHIFT 20
93 +
94 +/* Link Capability CSR */
95 +#define PCICFG_PCIE_LINK_CAP_OFFSET 0xcc
96 +#define PCIE_LINK_CAP_MAX_SPEED_MASK 0xFF
97 +#define PCIE_LINK_CAP_MAX_SPEED_SHIFT 0
98 +#define PCIE_LINK_CAP_MAX_WIDTH_MASK 0x3F
99 +#define PCIE_LINK_CAP_MAX_WIDTH_SHIFT 4
100 +
63 101 /* POST status reg struct */
64 102 #define POST_STAGE_POWER_ON_RESET 0x00
65 103 #define POST_STAGE_AWAITING_HOST_RDY 0x01
66 104 #define POST_STAGE_HOST_RDY 0x02
67 105 #define POST_STAGE_CHIP_RESET 0x03
68 106 #define POST_STAGE_ARMFW_READY 0xc000
69 107 #define POST_STAGE_ARMFW_UE 0xf000
70 108
71 109 /* DOORBELL registers */
72 110 #define PD_RXULP_DB 0x0100
73 111 #define PD_TXULP_DB 0x0060
74 112 #define DB_RQ_ID_MASK 0x3FF
75 113
76 114 #define PD_CQ_DB 0x0120
77 115 #define PD_EQ_DB PD_CQ_DB
78 116 #define PD_MPU_MBOX_DB 0x0160
79 117 #define PD_MQ_DB 0x0140
80 118
81 119 /* EQE completion types */
82 120 #define EQ_MINOR_CODE_COMPLETION 0x00
83 121 #define EQ_MINOR_CODE_OTHER 0x01
84 122 #define EQ_MAJOR_CODE_COMPLETION 0x00
85 123
86 124 /* Link Status field values */
87 125 #define PHY_LINK_FAULT_NONE 0x0
88 126 #define PHY_LINK_FAULT_LOCAL 0x01
89 127 #define PHY_LINK_FAULT_REMOTE 0x02
90 128
91 129 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */
92 130 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
93 131 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
94 132 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
95 133 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
96 134
97 135 #define PHY_LINK_DUPLEX_NONE 0x0
98 136 #define PHY_LINK_DUPLEX_HALF 0x1
99 137 #define PHY_LINK_DUPLEX_FULL 0x2
100 138
101 139 #define NTWK_PORT_A 0x0 /* (Port A) */
102 140 #define NTWK_PORT_B 0x1 /* (Port B) */
103 141
104 142 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */
105 143 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
106 144 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
107 145 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
108 146 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
109 147
110 148 /* Hardware Address types */
111 149 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */
112 150 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */
113 151 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */
114 152 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */
115 153 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */
116 154
117 155 /* CREATE_IFACE capability and cap_en flags */
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118 156 #define MBX_RX_IFACE_FLAGS_RSS 0x4
119 157 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
120 158 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
121 159 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
122 160 #define MBX_RX_IFACE_FLAGS_ULP 0x40
123 161 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
124 162 #define MBX_RX_IFACE_FLAGS_VLAN 0x100
125 163 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
126 164 #define MBX_RX_IFACE_FLAGS_PASS_L2 0x400
127 165 #define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800
166 +#define MBX_RX_IFACE_FLAGS_MCAST 0x1000
128 167
129 168 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */
130 169 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */
131 170 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
132 171 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
133 172
134 173
135 174 #define MBX_DB_READY_BIT 0x1
136 175 #define MBX_DB_HI_BIT 0x2
137 -#define ASYNC_EVENT_CODE_LINK_STATE 0x1
138 -#define ASYNC_EVENT_LINK_UP 0x1
139 -#define ASYNC_EVENT_LINK_DOWN 0x0
176 +/* Event bit map registered with mq */
177 +enum {
178 + ASYNC_EVENT_CODE_LINK_STATE = 0x1,
179 + ASYNC_EVENT_CODE_FCOE_FIP = 0x2,
180 + ASYNC_EVENT_CODE_DCBX = 0x3,
181 + ASYNC_EVENT_CODE_ISCSI = 0x4,
182 + ASYNC_EVENT_CODE_GRP_5 = 0x5,
183 + ASYNC_EVENT_CODE_DEBUG = 0x6
184 +};
140 185
141 -/* port link_status */
142 -#define ASYNC_EVENT_LOGICAL 0x02
186 +/* Link events */
187 +enum {
188 + ASYNC_EVENT_LINK_DOWN = 0x0,
189 + ASYNC_EVENT_LINK_UP = 0x1,
190 + ASYNC_EVENT_LOGICAL = 0x02
191 +};
143 192
193 +/* GRP5 Events */
194 +enum {
195 + ASYNC_EVENT_QOS_SPEED = 0x1,
196 + ASYNC_EVENT_COS_PRIORITY = 0x2,
197 + ASYNC_EVENT_PVID_STATE = 0x3
198 +};
199 +
200 +/* Event Mask */
201 +#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8
202 +#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
203 +#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
204 +#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
205 +
144 206 /* Logical Link Status */
145 207 #define NTWK_LOGICAL_LINK_DOWN 0
146 208 #define NTWK_LOGICAL_LINK_UP 1
147 209
148 210 /* Rx filter bits */
149 211 #define NTWK_RX_FILTER_IP_CKSUM 0x1
150 212 #define NTWK_RX_FILTER_TCP_CKSUM 0x2
151 213 #define NTWK_RX_FILTER_UDP_CKSUM 0x4
152 214 #define NTWK_RX_FILTER_STRIP_CRC 0x8
153 215
216 +/* driver_function_capabilities */
217 +#define DRVFN_CAPAB_SW_TIMESTAMPS 0x2
218 +#define DRVFN_CAPAB_BE3_NATIVE 0x4
219 +
220 +/* Function Capabilities */
221 +#define BE_FUNCTION_CAPS_UNCLASSIFIED_STATS 0x1
222 +#define BE_FUNCTION_CAPS_RSS 0x2
223 +#define BE_FUNCTION_CAPS_PROMISCUOUS 0x4
224 +#define BE_FUNCTION_CAPS_LEGACY_MODE 0x8
225 +
154 226 /* max SGE per mbx */
155 227 #define MAX_MBX_SGE 19
156 228
229 +/* max RSS rings */
230 +#define MAX_RING_PER_GROUP_LEGACY 5
231 +#define MAX_RING_PER_GROUP_NATIVE 16
232 +
233 +/* MCCQ LEN */
234 +#define MCC_Q_LEN 128
235 +#define MCC_CQ_LEN 256
236 +
237 +/* RSS PARAMETERS */
238 +#define MAX_TBL_SIZE 64
239 +#define MAX_HKEY_SIZE 40
240 +
241 +/* ULP */
242 +#define BE_ULP1_NUM 1
243 +
157 244 /* physical address structure to be used in MBX */
158 245 struct phys_addr {
159 246 /* dw0 */
160 247 uint32_t lo;
161 248 /* dw1 */
162 249 uint32_t hi;
163 250 };
164 251
165 252 typedef union pcicfg_intr_ctl_u {
166 253 uint32_t dw0;
167 254 struct {
168 255 #ifdef _BIG_ENDIAN
169 256 uint32_t winselect:2;
170 257 uint32_t hostintr:1;
171 258 uint32_t pfnum:3;
172 259 uint32_t vf_cev_int_line_en:1;
173 260 uint32_t winaddr:23;
174 261 uint32_t membarwinen:1;
175 262 #else
176 263 uint32_t membarwinen:1;
177 264 uint32_t winaddr:23;
178 265 uint32_t vf_cev_int_line_en:1;
179 266 uint32_t pfnum:3;
180 267 uint32_t hostintr:1;
181 268 uint32_t winselect:2;
182 269 #endif
183 270 } bits;
184 271 }pcicfg_intr_ctl_t;
185 272
186 273 typedef union pcicfg_semaphore_u {
187 274 uint32_t dw0;
188 275 struct {
189 276 #ifdef _BIG_ENDIAN
190 277 uint32_t rsvd:31;
191 278 uint32_t lock:1;
192 279 #else
193 280 uint32_t lock:1;
194 281 uint32_t rsvd:31;
195 282 #endif
196 283 }bits;
197 284 }pcicfg_semaphore_t;
198 285
199 286 typedef union pcicfg_soft_reset_u {
200 287 uint32_t dw0;
201 288 struct {
202 289 #ifdef _BIG_ENDIAN
203 290 uint32_t nec_ll_rcvdetect:8;
204 291 uint32_t dbg_all_reqs_62_49:14;
205 292 uint32_t scratchpad0:1;
206 293 uint32_t exception_oe:1;
207 294 uint32_t soft_reset:1;
208 295 uint32_t rsvd0:7;
209 296 #else
210 297 uint32_t rsvd0:7;
211 298 uint32_t soft_reset:1;
212 299 uint32_t exception_oe:1;
213 300 uint32_t scratchpad0:1;
214 301 uint32_t dbg_all_reqs_62_49:14;
215 302 uint32_t nec_ll_rcvdetect:8;
216 303 #endif
217 304 }bits;
218 305 }pcicfg_soft_reset_t;
219 306
220 307 typedef union pcicfg_online1_u {
221 308 uint32_t dw0;
222 309 struct {
223 310 #ifdef _BIG_ENDIAN
224 311 uint32_t host8_online:1;
225 312 uint32_t host7_online:1;
226 313 uint32_t host6_online:1;
227 314 uint32_t host5_online:1;
228 315 uint32_t host4_online:1;
229 316 uint32_t host3_online:1;
230 317 uint32_t host2_online:1;
231 318 uint32_t ipc_online:1;
232 319 uint32_t arm_online:1;
233 320 uint32_t txp_online:1;
234 321 uint32_t xaui_online:1;
235 322 uint32_t rxpp_online:1;
236 323 uint32_t txpb_online:1;
237 324 uint32_t rr_online:1;
238 325 uint32_t pmem_online:1;
239 326 uint32_t pctl1_online:1;
240 327 uint32_t pctl0_online:1;
241 328 uint32_t pcs1online_online:1;
242 329 uint32_t mpu_iram_online:1;
243 330 uint32_t pcs0online_online:1;
244 331 uint32_t mgmt_mac_online:1;
245 332 uint32_t lpcmemhost_online:1;
246 333 #else
247 334 uint32_t lpcmemhost_online:1;
248 335 uint32_t mgmt_mac_online:1;
249 336 uint32_t pcs0online_online:1;
250 337 uint32_t mpu_iram_online:1;
251 338 uint32_t pcs1online_online:1;
252 339 uint32_t pctl0_online:1;
253 340 uint32_t pctl1_online:1;
254 341 uint32_t pmem_online:1;
255 342 uint32_t rr_online:1;
256 343 uint32_t txpb_online:1;
257 344 uint32_t rxpp_online:1;
258 345 uint32_t xaui_online:1;
259 346 uint32_t txp_online:1;
260 347 uint32_t arm_online:1;
261 348 uint32_t ipc_online:1;
262 349 uint32_t host2_online:1;
263 350 uint32_t host3_online:1;
264 351 uint32_t host4_online:1;
265 352 uint32_t host5_online:1;
266 353 uint32_t host6_online:1;
267 354 uint32_t host7_online:1;
268 355 uint32_t host8_online:1;
269 356 #endif
270 357 }bits;
271 358 }pcicfg_online1_t;
272 359
273 360 typedef union mpu_ep_semaphore_u {
274 361 uint32_t dw0;
275 362 struct {
276 363 #ifdef _BIG_ENDIAN
277 364 uint32_t error:1;
278 365 uint32_t backup_fw:1;
279 366 uint32_t iscsi_no_ip:1;
280 367 uint32_t iscsi_ip_conflict:1;
281 368 uint32_t option_rom_installed:1;
282 369 uint32_t iscsi_drv_loaded:1;
283 370 uint32_t rsvd0:10;
284 371 uint32_t stage:16;
285 372 #else
286 373 uint32_t stage:16;
287 374 uint32_t rsvd0:10;
288 375 uint32_t iscsi_drv_loaded:1;
289 376 uint32_t option_rom_installed:1;
290 377 uint32_t iscsi_ip_conflict:1;
291 378 uint32_t iscsi_no_ip:1;
292 379 uint32_t backup_fw:1;
293 380 uint32_t error:1;
294 381 #endif
295 382 }bits;
296 383 }mpu_ep_semaphore_t;
297 384
298 385 typedef union mpu_ep_control_u {
299 386 uint32_t dw0;
300 387 struct {
301 388 #ifdef _BIG_ENDIAN
302 389 uint32_t cpu_reset:1;
303 390 uint32_t rsvd1:15;
304 391 uint32_t ep_ram_init_status:1;
305 392 uint32_t rsvd0:12;
306 393 uint32_t m2_rxpbuf:1;
307 394 uint32_t m1_rxpbuf:1;
308 395 uint32_t m0_rxpbuf:1;
309 396 #else
310 397 uint32_t m0_rxpbuf:1;
311 398 uint32_t m1_rxpbuf:1;
312 399 uint32_t m2_rxpbuf:1;
313 400 uint32_t rsvd0:12;
314 401 uint32_t ep_ram_init_status:1;
315 402 uint32_t rsvd1:15;
316 403 uint32_t cpu_reset:1;
317 404 #endif
318 405 }bits;
319 406 }mpu_ep_control_t;
320 407
321 408 /* RX doorbell */
322 409 typedef union pd_rxulp_db_u {
323 410 uint32_t dw0;
324 411 struct {
325 412 #ifdef _BIG_ENDIAN
326 413 uint32_t num_posted:8;
327 414 uint32_t invalidate:1;
328 415 uint32_t rsvd1:13;
329 416 uint32_t qid:10;
330 417 #else
331 418 uint32_t qid:10;
332 419 uint32_t rsvd1:13;
333 420 uint32_t invalidate:1;
334 421 uint32_t num_posted:8;
335 422 #endif
336 423 }bits;
337 424 }pd_rxulp_db_t;
338 425
339 426 /* TX doorbell */
340 427 typedef union pd_txulp_db_u {
341 428 uint32_t dw0;
342 429 struct {
343 430 #ifdef _BIG_ENDIAN
344 431 uint32_t rsvd1:2;
345 432 uint32_t num_posted:14;
346 433 uint32_t rsvd0:6;
347 434 uint32_t qid:10;
348 435 #else
349 436 uint32_t qid:10;
350 437 uint32_t rsvd0:6;
351 438 uint32_t num_posted:14;
352 439 uint32_t rsvd1:2;
353 440 #endif
354 441 }bits;
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355 442 }pd_txulp_db_t;
356 443
357 444 /* CQ doorbell */
358 445 typedef union cq_db_u {
359 446 uint32_t dw0;
360 447 struct {
361 448 #ifdef _BIG_ENDIAN
362 449 uint32_t rsvd1:2;
363 450 uint32_t rearm:1;
364 451 uint32_t num_popped:13;
365 - uint32_t rsvd0:5;
452 + uint32_t eq_cq_extid:5;
366 453 uint32_t event:1;
367 454 uint32_t qid:10;
368 455 #else
369 456 uint32_t qid:10;
370 457 uint32_t event:1;
371 - uint32_t rsvd0:5;
458 + uint32_t eq_cq_extid:5;
372 459 uint32_t num_popped:13;
373 460 uint32_t rearm:1;
374 461 uint32_t rsvd1:2;
375 462 #endif
376 463 }bits;
377 464 }cq_db_t;
378 465
379 466 /* EQ doorbell */
380 467 typedef union eq_db_u {
381 468 uint32_t dw0;
382 469 struct {
383 470 #ifdef _BIG_ENDIAN
384 471 uint32_t rsvd1:2;
385 472 uint32_t rearm:1;
386 473 uint32_t num_popped:13;
387 - uint32_t rsvd0:5;
474 + uint32_t eq_cq_extid:5;
388 475 uint32_t event:1;
389 476 uint32_t clrint:1;
390 477 uint32_t qid:9;
391 478 #else
392 479 uint32_t qid:9;
393 480 uint32_t clrint:1;
394 481 uint32_t event:1;
395 - uint32_t rsvd0:5;
482 + uint32_t eq_cq_extid:5;
396 483 uint32_t num_popped:13;
397 484 uint32_t rearm:1;
398 485 uint32_t rsvd1:2;
399 486 #endif
400 487 }bits;
401 488 }eq_db_t;
402 489
403 490 /* bootstrap mbox doorbell */
404 491 typedef union pd_mpu_mbox_db_u {
405 492 uint32_t dw0;
406 493 struct {
407 494 #ifdef _BIG_ENDIAN
408 495 uint32_t address:30;
409 496 uint32_t hi:1;
410 497 uint32_t ready:1;
411 498 #else
412 499 uint32_t ready:1;
413 500 uint32_t hi:1;
414 501 uint32_t address:30;
415 502 #endif
416 503 }bits;
417 504 }pd_mpu_mbox_db_t;
418 505
419 506
420 507 /* MQ ring doorbell */
421 508 typedef union pd_mq_db_u {
422 509 uint32_t dw0;
423 510 struct {
424 511 #ifdef _BIG_ENDIAN
425 512 uint32_t rsvd1:2;
426 513 uint32_t num_posted:14;
427 514 uint32_t rsvd0:5;
428 515 uint32_t mq_id:11;
429 516 #else
430 517 uint32_t mq_id:11;
431 518 uint32_t rsvd0:5;
432 519 uint32_t num_posted:14;
433 520 uint32_t rsvd1:2;
434 521 #endif
435 522 }bits;
436 523 }pd_mq_db_t;
437 524
438 525 /*
439 526 * Event Queue Entry
440 527 */
441 528 struct oce_eqe {
442 529 union {
443 530 struct {
444 531 #ifdef _BIG_ENDIAN
445 532 uint32_t resource_id:16;
446 533 uint32_t minor_code:12;
447 534 uint32_t major_code:3;
448 535 uint32_t valid:1;
449 536 #else
450 537 uint32_t valid:1;
451 538 uint32_t major_code:3;
452 539 uint32_t minor_code:12;
453 540 uint32_t resource_id:16;
454 541 #endif
455 542 }s;
456 543 uint32_t dw0;
457 544 }u0;
458 545 };
459 546
460 547 /* MQ scatter gather entry. Array of these make an SGL */
461 548 struct oce_mq_sge {
462 549 uint32_t pa_lo;
463 550 uint32_t pa_hi;
464 551 uint32_t length;
465 552 };
466 553
467 554 /*
468 555 * payload can contain an SGL or an embedded array of upto 59 dwords
469 556 */
470 557 struct oce_mbx_payload {
471 558 union {
472 559 union {
473 560 struct oce_mq_sge sgl[MAX_MBX_SGE];
474 561 uint32_t embedded[59];
475 562 }u1;
476 563 uint32_t dw[59];
477 564 }u0;
478 565 };
479 566
480 567 /*
481 568 * MQ MBX structure
482 569 */
483 570 struct oce_mbx {
484 571 union {
485 572 struct {
486 573 #ifdef _BIG_ENDIAN
487 574 uint32_t special : 8;
488 575 uint32_t rsvd1 : 16;
489 576 uint32_t sge_count : 5;
490 577 uint32_t rsvd0 : 2;
491 578 uint32_t embedded : 1;
492 579 #else
493 580 uint32_t embedded:1;
494 581 uint32_t rsvd0:2;
495 582 uint32_t sge_count:5;
496 583 uint32_t rsvd1:16;
497 584 uint32_t special:8;
498 585 #endif
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499 586 }s;
500 587 uint32_t dw0;
501 588 }u0;
502 589
503 590 uint32_t payload_length;
504 591 uint32_t tag[2];
505 592 uint32_t rsvd2[1];
506 593 struct oce_mbx_payload payload;
507 594 };
508 595
596 +#define MQ_CQE_VALID_MASK (1 << 31)
597 +#define MQ_CQE_ASYNC_MASK (1 << 30)
598 +#define MQ_CQE_COMPLETED_MASK (1 << 28)
599 +#define MQ_CQE_CONSUMED_MASK (1 << 27)
600 +#define MQ_CQE_VALID(_cqe) (_cqe->u0.dw[3])
601 +#define MQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
602 +
603 +/* Macros for handling extra bytes in EQ-CQ IDs */
604 +#define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
605 +#define DB_CQ_RING_ID_EXT_MASK_SHIFT (1)
606 + /*
607 + * qid bits 10-14
608 + * placing at 11-15
609 + */
610 +#define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
611 +#define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
612 +
509 613 /* completion queue entry for MQ */
510 614 struct oce_mq_cqe {
511 615 union {
512 616 struct {
513 617 #ifdef _BIG_ENDIAN
514 618 /* dw0 */
515 619 uint32_t extended_status:16;
516 620 uint32_t completion_status:16;
517 621 /* dw1 dw2 */
518 622 uint32_t mq_tag[2];
519 623 /* dw3 */
520 624 uint32_t valid:1;
521 625 uint32_t async_event:1;
522 - uint32_t hpi_buffer_cmpl:1;
626 + uint32_t rsvd:1;
523 627 uint32_t completed:1;
524 628 uint32_t consumed:1;
525 629 uint32_t rsvd0:27;
526 630 #else
527 631 /* dw0 */
528 632 uint32_t completion_status:16;
529 633 uint32_t extended_status:16;
530 634 /* dw1 dw2 */
531 635 uint32_t mq_tag[2];
532 636 /* dw3 */
533 637 uint32_t rsvd0:27;
534 638 uint32_t consumed:1;
535 639 uint32_t completed:1;
536 - uint32_t hpi_buffer_cmpl:1;
640 + uint32_t rsvd:1;
537 641 uint32_t async_event:1;
538 642 uint32_t valid:1;
539 643 #endif
540 644 }s;
541 645 uint32_t dw[4];
542 646 }u0;
543 647 };
544 648
545 -struct oce_async_cqe_link_state {
649 +struct oce_async_event_trailer {
546 650 union {
547 651 struct {
548 652 #ifdef _BIG_ENDIAN
549 - /* dw0 */
550 - uint8_t speed;
551 - uint8_t duplex;
552 - uint8_t link_status;
553 - uint8_t phy_port;
554 - /* dw1 */
555 - uint8_t rsvd0[3];
556 - uint8_t fault;
557 - /* dw2 */
558 - uint32_t event_tag;
559 - /* dw3 */
560 653 uint32_t valid:1;
561 654 uint32_t async_event:1;
562 655 uint32_t rsvd2:6;
563 656 uint32_t event_type:8;
564 657 uint32_t event_code:8;
565 658 uint32_t rsvd1:8;
566 659 #else
567 - /* dw0 */
568 - uint8_t phy_port;
569 - uint8_t link_status;
570 - uint8_t duplex;
571 - uint8_t speed;
572 - /* dw1 */
573 - uint8_t fault;
574 - uint8_t rsvd0[3];
575 - /* dw2 */
576 - uint32_t event_tag;
577 - /* dw3 */
578 660 uint32_t rsvd1:8;
579 661 uint32_t event_code:8;
580 662 uint32_t event_type:8;
581 663 uint32_t rsvd2:6;
582 664 uint32_t async_event:1;
583 665 uint32_t valid:1;
584 666 #endif
585 - }s;
586 - uint32_t dw[4];
587 - }u0;
667 + } bits;
668 + uint32_t code;
669 + } u0;
588 670 };
589 671
672 +
673 +/* Async Debug Event Types */
674 +#define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
675 +
676 +struct async_event_qnq {
677 + uint8_t enabled;
678 + uint8_t rsvd0;
679 + uint16_t vlan_tag;
680 + uint32_t event_tag;
681 + uint32_t rsvd1[1];
682 + struct oce_async_event_trailer trailer;
683 +};
684 +
685 +
686 +struct oce_async_cqe_link_state {
687 + uint8_t phy_port;
688 + uint8_t link_status;
689 + uint8_t duplex;
690 + uint8_t speed;
691 + uint8_t fault;
692 + uint8_t reason;
693 + uint16_t qos_link_speed;
694 + uint32_t event_tag;
695 + struct oce_async_event_trailer trailer;
696 +};
697 +
698 +struct oce_async_event_grp5_qos_link_speed {
699 + uint8_t physical_port;
700 + uint8_t rsvd[5];
701 + uint16_t qos_link_speed;
702 + uint32_t event_tag;
703 + struct oce_async_event_trailer trailer;
704 +};
705 +
706 +
707 +struct oce_async_event_grp5_cos_priority {
708 + uint8_t physical_port;
709 + uint8_t available_priority_bmap;
710 + uint8_t reco_default_priority;
711 + uint8_t valid;
712 + uint8_t rsvd0;
713 + uint32_t event_tag;
714 + struct oce_async_event_trailer trailer;
715 +};
716 +
717 +struct oce_async_event_grp5_pvid_state {
718 + uint8_t enabled;
719 + uint8_t rsvd0;
720 + uint16_t tag;
721 + uint32_t event_tag;
722 + uint32_t rsvd1;
723 + struct oce_async_event_trailer trailer;
724 +};
725 +
726 +struct oce_event_grp_5_priority_class_queue_map {
727 + uint8_t priority0_classq;
728 + uint8_t priority1_classq;
729 + uint8_t priority2_classq;
730 + uint8_t priority3_classq;
731 + uint8_t priority4_classq;
732 + uint8_t priority5_classq;
733 + uint8_t priority6_classq;
734 + uint8_t priority7_classq;
735 + uint32_t event_tag;
736 + struct oce_async_event_trailer trailer;
737 +};
738 +
739 +
590 740 /* MQ mailbox structure */
591 741 struct oce_bmbx {
592 742 struct oce_mbx mbx;
593 743 struct oce_mq_cqe cqe;
594 744 };
595 745
596 746 /* ---[ MBXs start here ]---------------------------------------------- */
597 747 /* MBXs sub system codes */
598 748 enum {
599 749 MBX_SUBSYSTEM_RSVD = 0,
600 750 MBX_SUBSYSTEM_COMMON = 1,
601 751 MBX_SUBSYSTEM_COMMON_ISCSI = 2,
602 752 MBX_SUBSYSTEM_NIC = 3,
603 753 MBX_SUBSYSTEM_TOE = 4,
604 754 MBX_SUBSYSTEM_PXE_UNDI = 5,
605 755 MBX_SUBSYSTEM_ISCSI_INI = 6,
606 756 MBX_SUBSYSTEM_ISCSI_TGT = 7,
607 757 MBX_SUBSYSTEM_MILI_PTL = 8,
608 758 MBX_SUBSYSTEM_MILI_TMD = 9,
609 759 MBX_SUBSYSTEM_RDMA = 10,
610 760 MBX_SUBSYSTEM_LOWLEVEL = 11,
611 761 MBX_SUBSYSTEM_LRO = 13,
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612 762 IOCBMBX_SUBSYSTEM_DCBX = 15,
613 763 IOCBMBX_SUBSYSTEM_DIAG = 16,
614 764 IOCBMBX_SUBSYSTEM_VENDOR = 17
615 765 };
616 766
617 767 /* common ioctl opcodes */
618 768 enum {
619 769 OPCODE_QUERY_COMMON_IFACE_MAC = 1,
620 770 OPCODE_SET_COMMON_IFACE_MAC = 2,
621 771 OPCODE_SET_COMMON_IFACE_MULTICAST = 3,
622 - OPCODE_CONFIG_COMMON_IFACE_VLAN = 4,
772 + OPCODE_COMMON_NTWK_VLAN_CONFIG = 4,
623 773 OPCODE_QUERY_COMMON_LINK_STATUS = 5,
624 774 OPCODE_READ_COMMON_FLASHROM = 6,
625 775 OPCODE_WRITE_COMMON_FLASHROM = 7,
626 776 OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8,
627 777 OPCODE_ADD_COMMON_PAGE_TABLES = 9,
628 778 OPCODE_REMOVE_COMMON_PAGE_TABLES = 10,
629 779 OPCODE_CREATE_COMMON_CQ = 12,
630 780 OPCODE_CREATE_COMMON_EQ = 13,
631 781 OPCODE_CREATE_COMMON_MQ = 21,
632 782 OPCODE_COMMON_JELL_CONFIG = 22,
633 783 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24,
634 784 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25,
635 785 OPCODE_COMMON_POST_ZERO_BUFFER = 26,
636 786 OPCODE_COMMON_GET_QOS = 27,
637 787 OPCODE_COMMON_SET_QOS = 28,
638 788 OPCODE_COMMON_TCP_GET_STATISTICS = 29,
639 789 OPCODE_READ_COMMON_SEEPROM = 30,
640 790 OPCODE_COMMON_TCP_STATE_QUERY = 31,
641 791 OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32,
642 792 OPCODE_COMMON_NOP = 33,
643 793 OPCODE_COMMON_NTWK_RX_FILTER = 34,
644 794 OPCODE_GET_COMMON_FW_VERSION = 35,
645 795 OPCODE_SET_COMMON_FLOW_CONTROL = 36,
646 796 OPCODE_GET_COMMON_FLOW_CONTROL = 37,
647 797 OPCODE_COMMON_SET_TCP_PARAMETERS = 38,
648 798 OPCODE_SET_COMMON_FRAME_SIZE = 39,
649 799 OPCODE_COMMON_GET_FAT = 40,
650 800 OPCODE_MODIFY_COMMON_EQ_DELAY = 41,
651 801 OPCODE_COMMON_FIRMWARE_CONFIG = 42,
652 802 OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43,
653 803 OPCODE_COMMON_GET_DOMAIN_CONFIG = 44,
654 804 OPCODE_COMMON_GET_PORT_EQUALIZATION = 47,
655 805 OPCODE_COMMON_SET_PORT_EQUALIZATION = 48,
656 806 OPCODE_COMMON_RED_CONFIG = 49,
657 807 OPCODE_CREATE_COMMON_IFACE = 50,
658 808 OPCODE_DESTROY_COMMON_IFACE = 51,
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659 809 OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52,
660 810 OPCODE_DESTROY_COMMON_MQ = 53,
661 811 OPCODE_DESTROY_COMMON_CQ = 54,
662 812 OPCODE_DESTROY_COMMON_EQ = 55,
663 813 OPCODE_COMMON_TCP_UPL_OAD = 56,
664 814 OPCODE_SET_COMMON_LINK_SPEED = 57,
665 815 OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58,
666 816 OPCODE_ADD_COMMON_IFACE_MAC = 59,
667 817 OPCODE_DEL_COMMON_IFACE_MAC = 60,
668 818 OPCODE_COMMON_FUNCTION_RESET = 61,
669 - OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80
819 + OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80,
820 + OPCODE_CREATE_COMMON_MQ_EXT = 90,
821 + OPCODE_COMMON_SET_DRIVER_FUNCTION_CAPABILITIES = 103
670 822 };
671 823
824 +/* Management status error code in Response header */
825 +enum {
826 + MGMT_STATUS_SUCCESS = 0, /* The IOCTL completed without errors. */
827 + MGMT_STATUS_FAILED = 1, /* Generic error status */
828 + MGMT_STATUS_ILLEGAL_REQUEST = 2, /* Invalid IOCTL opcode. */
829 + MGMT_STATUS_ILLEGAL_FIELD = 3, /* Invalid param in IOCTL pyld */
830 + MGMT_STATUS_INSUFFICIENT_BUFFER = 4, /* Insufficient buf for response */
831 + MGMT_STATUS_UNAUTHORIZED_REQUEST = 5 /* Domain invalid access rights */
832 +};
833 +
834 +/* Additional status error codes */
835 +enum {
836 + MGMT_ADDI_STATUS_NO_STATUS = 0, /* IOCTL completed successfully */
837 + MGMT_ADDI_STATUS_INVALID_SUBSYSTEM = 29, /* Invalid subsystem id */
838 + MGMT_ADDI_STATUS_INVALID_OPCODE = 30, /* Opcode Invalid */
839 + MGMT_ADDI_STATUS_INVALID_DOMAIN = 35, /* Invalid domain id */
840 + MGMT_ADDI_STATUS_INVALID_EXTENDED_TIMEOUT = 64 /* Invalid timeout */
841 +};
842 +
672 843 /* common ioctl header */
673 844 struct mbx_hdr {
674 845 union {
675 846 struct {
676 847 #ifdef _BIG_ENDIAN
677 848 uint8_t domain;
678 849 uint8_t port_number;
679 850 uint8_t subsystem;
680 851 uint8_t opcode;
852 + uint32_t timeout;
853 + uint32_t request_length;
854 + uint8_t rsvd0[3];
855 + uint8_t version;
681 856 #else
682 857 uint8_t opcode;
683 858 uint8_t subsystem;
684 859 uint8_t port_number;
685 860 uint8_t domain;
686 -#endif
687 861 uint32_t timeout;
688 862 uint32_t request_length;
689 - uint32_t rsvd0;
863 + uint8_t version;
864 + uint8_t rsvd0[3];
865 +#endif
690 866 }req;
691 867
692 868 struct {
693 869 /* dw 0 */
694 870 uint8_t opcode;
695 871 uint8_t subsystem;
696 872 uint8_t rsvd0;
697 873 uint8_t domain;
698 874 /* dw 1 */
699 875 uint8_t status;
700 876 uint8_t additional_status;
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701 877 uint16_t rsvd1;
702 878
703 879 uint32_t rsp_length;
704 880 uint32_t actual_rsp_length;
705 881 }rsp;
706 882 uint32_t dw[4];
707 883 }u0;
708 884 };
709 885 #define OCE_BMBX_RHDR_SZ 20
710 886 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
711 -#define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
712 -#define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
887 +#define OCE_MBX_ADDL_STATUS(_MHDR) \
888 + (((struct mbx_hdr *)_MHDR)->u0.rsp.additional_status)
889 +#define OCE_MBX_STATUS(_MHDR) (((struct mbx_hdr *)_MHDR)->u0.rsp.status)
713 890
714 891 /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */
715 892 struct mbx_query_common_link_status {
716 893 struct mbx_hdr hdr;
717 894 union {
718 895 struct {
719 896 uint32_t rsvd0;
720 897 }req;
721 898
722 899 struct {
723 900 /* dw 0 */
724 901 uint8_t physical_port;
725 902 uint8_t mac_duplex;
726 903 uint8_t mac_speed;
727 904 uint8_t mac_fault;
728 905 /* dw 1 */
729 906 uint8_t mgmt_mac_duplex;
730 907 uint8_t mgmt_mac_speed;
731 908 uint16_t qos_link_speed;
732 909 uint32_t logical_link_status;
733 910 }rsp;
734 911 }params;
735 912 };
736 913
737 914 /* [57] OPCODE_SET_COMMON_LINK_SPEED */
738 915 struct mbx_set_common_link_speed {
739 916 struct mbx_hdr hdr;
740 917 union {
741 918 struct {
742 919 #ifdef _BIG_ENDIAN
743 920 uint8_t rsvd0;
744 921 uint8_t mac_speed;
745 922 uint8_t virtual_port;
746 923 uint8_t physical_port;
747 924 #else
748 925 uint8_t physical_port;
749 926 uint8_t virtual_port;
750 927 uint8_t mac_speed;
751 928 uint8_t rsvd0;
752 929 #endif
753 930 }req;
754 931
755 932 struct {
756 933 uint32_t rsvd0;
757 934 }rsp;
758 935
759 936 uint32_t dw;
760 937 }params;
761 938 };
762 939
763 940 struct mac_address_format {
764 941 uint16_t size_of_struct;
765 942 uint8_t mac_addr[6];
766 943 };
767 944
768 945 /* [01] OPCODE_QUERY_COMMON_IFACE_MAC */
769 946 struct mbx_query_common_iface_mac {
770 947 struct mbx_hdr hdr;
771 948 union {
772 949 struct {
773 950 #ifdef _BIG_ENDIAN
774 951 uint16_t if_id;
775 952 uint8_t permanent;
776 953 uint8_t type;
777 954 #else
778 955 uint8_t type;
779 956 uint8_t permanent;
780 957 uint16_t if_id;
781 958 #endif
782 959
783 960 }req;
784 961
785 962 struct {
786 963 struct mac_address_format mac;
787 964 }rsp;
788 965 }params;
789 966 };
790 967
791 968 /* [02] OPCODE_SET_COMMON_IFACE_MAC */
792 969 struct mbx_set_common_iface_mac {
793 970 struct mbx_hdr hdr;
794 971 union {
795 972 struct {
796 973 #ifdef _BIG_ENDIAN
797 974 /* dw 0 */
798 975 uint16_t if_id;
799 976 uint8_t invalidate;
800 977 uint8_t type;
801 978 #else
802 979 /* dw 0 */
803 980 uint8_t type;
804 981 uint8_t invalidate;
805 982 uint16_t if_id;
806 983 #endif
807 984 /* dw 1 */
808 985 struct mac_address_format mac;
809 986 }req;
810 987
811 988 struct {
812 989 uint32_t rsvd0;
813 990 }rsp;
814 991
815 992 uint32_t dw[2];
816 993 }params;
817 994 };
818 995
819 996 /* [03] OPCODE_SET_COMMON_IFACE_MULTICAST */
820 997 struct mbx_set_common_iface_multicast {
821 998 struct mbx_hdr hdr;
822 999 union {
823 1000 struct {
824 1001 /* dw 0 */
825 1002 uint16_t num_mac;
826 1003 uint8_t promiscuous;
827 1004 uint8_t if_id;
828 1005 /* dw 1-48 */
829 1006 struct {
830 1007 uint8_t byte[6];
831 1008 } mac[32];
832 1009
833 1010 }req;
834 1011
835 1012 struct {
836 1013 uint32_t rsvd0;
837 1014 }rsp;
838 1015
839 1016 uint32_t dw[49];
840 1017 }params;
841 1018 };
842 1019
843 1020 struct qinq_vlan {
844 1021 #ifdef _BIG_ENDIAN
845 1022 uint16_t inner;
846 1023 uint16_t outer;
847 1024 #else
848 1025 uint16_t outer;
849 1026 uint16_t inner;
850 1027 #endif
851 1028 };
852 1029
853 1030 struct normal_vlan {
854 1031 uint16_t vtag;
855 1032 };
856 1033
857 1034 struct ntwk_if_vlan_tag {
858 1035 union {
859 1036 struct normal_vlan normal;
860 1037 struct qinq_vlan qinq;
861 1038 }u0;
862 1039 };
863 1040
864 1041 /* [50] OPCODE_CREATE_COMMON_IFACE */
865 1042 struct mbx_create_common_iface {
866 1043 struct mbx_hdr hdr;
867 1044 union {
868 1045 struct {
869 1046 uint32_t version;
870 1047 uint32_t cap_flags;
871 1048 uint32_t enable_flags;
872 1049 uint8_t mac_addr[6];
873 1050 uint8_t rsvd0;
874 1051 uint8_t mac_invalid;
875 1052 struct ntwk_if_vlan_tag vlan_tag;
876 1053 }req;
877 1054
878 1055 struct {
879 1056 uint32_t if_id;
880 1057 uint32_t pmac_id;
881 1058 }rsp;
882 1059 uint32_t dw[4];
883 1060 }params;
884 1061 };
885 1062
886 1063 /* [51] OPCODE_DESTROY_COMMON_IFACE */
887 1064 struct mbx_destroy_common_iface {
888 1065 struct mbx_hdr hdr;
889 1066 union {
890 1067 struct {
891 1068 uint32_t if_id;
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892 1069 }req;
893 1070
894 1071 struct {
895 1072 uint32_t rsvd0;
896 1073 }rsp;
897 1074
898 1075 uint32_t dw;
899 1076 }params;
900 1077 };
901 1078
1079 +struct mbx_set_common_iface_rx_filter {
1080 + struct mbx_hdr hdr;
1081 + union {
1082 + struct {
1083 + uint32_t gflags_mask;
1084 + uint32_t gflags;
1085 + uint32_t if_flags_mask;
1086 + uint32_t if_flags;
1087 + uint32_t if_id;
1088 + uint32_t multicast_num;
1089 + struct ether_addr mac[32];
1090 + }req;
1091 + struct {
1092 + uint32_t gflags_mask;
1093 + uint32_t gflags;
1094 + uint32_t if_flags_mask;
1095 + uint32_t if_flags;
1096 + uint32_t if_id;
1097 + uint32_t multicast_num;
1098 + struct ether_addr mac[32];
1099 + }rsp;
1100 + }params;
1101 +};
1102 +
902 1103 /* event queue context structure */
903 1104 struct oce_eq_ctx {
904 1105 #ifdef _BIG_ENDIAN
905 1106 /* dw0 */
906 1107 uint32_t size:1;
907 1108 uint32_t rsvd1:1;
908 1109 uint32_t valid:1;
909 1110 uint32_t epidx:13;
910 1111 uint32_t rsvd0:3;
911 1112 uint32_t cidx:13;
912 1113
913 1114 /* dw1 */
914 1115 uint32_t armed:1;
915 1116 uint32_t stalled:1;
916 1117 uint32_t sol_event:1;
917 1118 uint32_t count:3;
918 1119 uint32_t pd:10;
919 1120 uint32_t rsvd2:3;
920 1121 uint32_t pidx:13;
921 1122
922 1123 /* dw2 */
923 1124 uint32_t rsvd6:4;
924 1125 uint32_t nodelay:1;
925 1126 uint32_t phase:2;
926 1127 uint32_t rsvd5:2;
927 1128 uint32_t delay_mult:10;
928 1129 uint32_t rsvd4:1;
929 1130 uint32_t function:8;
930 1131 uint32_t rsvd3:4;
931 1132
932 1133 /* dw 3 */
933 1134 uint32_t rsvd7;
934 1135 #else
935 1136 /* dw0 */
936 1137 uint32_t cidx:13;
937 1138 uint32_t rsvd0:3;
938 1139 uint32_t epidx:13;
939 1140 uint32_t valid:1;
940 1141 uint32_t rsvd1:1;
941 1142 uint32_t size:1;
942 1143
943 1144 /* dw1 */
944 1145 uint32_t pidx:13;
945 1146 uint32_t rsvd2:3;
946 1147 uint32_t pd:10;
947 1148 uint32_t count:3;
948 1149 uint32_t sol_event:1;
949 1150 uint32_t stalled:1;
950 1151 uint32_t armed:1;
951 1152
952 1153 /* dw2 */
953 1154 uint32_t rsvd3:4;
954 1155 uint32_t function:8;
955 1156 uint32_t rsvd4:1;
956 1157 uint32_t delay_mult:10;
957 1158 uint32_t rsvd5:2;
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958 1159 uint32_t phase:2;
959 1160 uint32_t nodelay:1;
960 1161 uint32_t rsvd6:4;
961 1162
962 1163 /* dw3 */
963 1164 uint32_t rsvd7;
964 1165 #endif
965 1166 };
966 1167
967 1168 /* [13] OPCODE_CREATE_COMMON_EQ */
968 - struct mbx_create_common_eq {
1169 +struct mbx_create_common_eq {
969 1170 struct mbx_hdr hdr;
970 1171 union {
971 1172 struct {
972 1173 #ifdef _BIG_ENDIAN
973 1174 uint16_t rsvd0;
974 1175 uint16_t num_pages;
975 1176 #else
976 1177 uint16_t num_pages;
977 1178 uint16_t rsvd0;
978 1179 #endif
979 1180 struct oce_eq_ctx eq_ctx;
980 1181 struct phys_addr pages[8];
981 1182 }req;
982 1183
983 1184 struct {
984 1185 uint16_t eq_id;
985 1186 uint16_t rsvd0;
986 1187 }rsp;
987 1188 }params;
988 1189 };
989 1190
990 1191 /* [55] OPCODE_DESTROY_COMMON_EQ */
991 1192 struct mbx_destroy_common_eq {
992 1193 struct mbx_hdr hdr;
993 1194 union {
994 1195 struct {
995 1196 #ifdef _BIG_ENDIAN
996 1197 uint16_t rsvd0;
997 1198 uint16_t id;
998 1199 #else
999 1200 uint16_t id;
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1000 1201 uint16_t rsvd0;
1001 1202 #endif
1002 1203 }req;
1003 1204
1004 1205 struct {
1005 1206 uint32_t rsvd0;
1006 1207 }rsp;
1007 1208 }params;
1008 1209 };
1009 1210
1010 -struct oce_cq_ctx {
1211 +struct oce_cq_ctx_v0 {
1011 1212 #ifdef _BIG_ENDIAN
1012 1213 /* dw0 */
1013 1214 uint32_t eventable:1;
1014 1215 uint32_t sol_event:1;
1015 1216 uint32_t valid:1;
1016 1217 uint32_t count:2;
1017 1218 uint32_t rsvd1:1;
1018 1219 uint32_t epidx:11;
1019 1220 uint32_t nodelay:1;
1020 1221 uint32_t coalesce_wm:2;
1021 1222 uint32_t rsvd0:1;
1022 1223 uint32_t cidx:11;
1023 1224
1024 1225 /* dw1 */
1025 1226 uint32_t armed:1;
1026 1227 uint32_t stalled:1;
1027 1228 uint32_t eq_id:8;
1028 1229 uint32_t pd:10;
1029 1230 uint32_t rsvd2:1;
1030 1231 uint32_t pidx:11;
1031 1232
1032 1233 /* dw2 */
1033 1234 uint32_t rsvd4:20;
1034 1235 uint32_t function:8;
1035 1236 uint32_t rsvd3:4;
1036 1237 #else
1037 1238 /* dw0 */
1038 1239 uint32_t cidx:11;
1039 1240 uint32_t rsvd0:1;
1040 1241 uint32_t coalesce_wm:2;
1041 1242 uint32_t nodelay:1;
1042 1243 uint32_t epidx:11;
1043 1244 uint32_t rsvd1:1;
1044 1245 uint32_t count:2;
1045 1246 uint32_t valid:1;
1046 1247 uint32_t sol_event:1;
1047 1248 uint32_t eventable:1;
1048 1249
1049 1250 /* dw1 */
1050 1251 uint32_t pidx:11;
1051 1252 uint32_t rsvd2:1;
1052 1253 uint32_t pd:10;
1053 1254 uint32_t eq_id:8;
1054 1255 uint32_t stalled:1;
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1055 1256 uint32_t armed:1;
1056 1257
1057 1258 /* dw2 */
1058 1259 uint32_t rsvd3:4;
1059 1260 uint32_t function:8;
1060 1261 uint32_t rsvd4:20;
1061 1262 #endif
1062 1263 uint32_t rsvd5;
1063 1264 };
1064 1265
1065 -/* [12] OPCODE_CREATE_COMMON_CQ */
1066 -struct mbx_create_common_cq {
1266 +/* [12] OPCODE_CREATE_COMMON_CQ V0 */
1267 +struct mbx_create_common_cq_v0 {
1067 1268 struct mbx_hdr hdr;
1068 1269 union {
1069 1270 struct {
1070 1271 #ifdef _BIG_ENDIAN
1071 1272 uint16_t rsvd0;
1072 1273 uint16_t num_pages;
1073 1274 #else
1074 1275 uint16_t num_pages;
1075 1276 uint16_t rsvd0;
1076 1277 #endif
1077 - struct oce_cq_ctx cq_ctx;
1278 + struct oce_cq_ctx_v0 cq_ctx;
1078 1279 struct phys_addr pages[4];
1079 1280 }req;
1080 1281
1081 1282 struct {
1082 1283 uint16_t cq_id;
1083 1284 uint16_t rsvd0;
1084 1285 }rsp;
1085 1286 }params;
1086 1287 };
1087 1288
1289 +struct oce_cq_ctx_v2 {
1290 +#ifdef _BIG_ENDIAN
1291 + /* dw0 */
1292 + uint32_t eventable:1;
1293 + uint32_t rsvd2:1;
1294 + uint32_t valid:1;
1295 + uint32_t count:2;
1296 + uint32_t rsvd1:11;
1297 + uint32_t auto_valid:1;
1298 + uint32_t nodelay:1;
1299 + uint32_t coalesce_wm:2;
1300 + uint32_t rsvd0:12;
1301 +
1302 + /* dw1 */
1303 + uint32_t armed:1;
1304 + uint32_t rsvd3:15;
1305 + uint32_t eq_id:16;
1306 +
1307 + /* dw2 */
1308 + uint32_t rsvd4:16;
1309 + uint32_t cqe_count:16;
1310 +#else
1311 + /* dw0 */
1312 + uint32_t rsvd0:12;
1313 + uint32_t coalesce_wm:2;
1314 + uint32_t nodelay:1;
1315 + uint32_t auto_valid:1;
1316 + uint32_t rsvd1:11;
1317 + uint32_t count:2;
1318 + uint32_t valid:1;
1319 + uint32_t rsvd2:1;
1320 + uint32_t eventable:1;
1321 +
1322 + /* dw1 */
1323 + uint32_t eq_id:16;
1324 + uint32_t rsvd3:15;
1325 + uint32_t armed:1;
1326 +
1327 + /* dw2 */
1328 + uint32_t cqe_count:16;
1329 + uint32_t rsvd4:16;
1330 +#endif
1331 + uint32_t rsvd5;
1332 +};
1333 +
1334 +/* [12] OPCODE_CREATE_COMMON_CQ V2 */
1335 +struct mbx_create_common_cq_v2 {
1336 + struct mbx_hdr hdr;
1337 + union {
1338 + struct {
1339 +#ifdef _BIG_ENDIAN
1340 + uint8_t rsvd0;
1341 + uint8_t page_size;
1342 + uint16_t num_pages;
1343 +#else
1344 + uint16_t num_pages;
1345 + uint8_t page_size;
1346 + uint8_t rsvd0;
1347 +#endif
1348 + struct oce_cq_ctx_v2 cq_ctx;
1349 + struct phys_addr pages[8];
1350 + }req;
1351 +
1352 + struct {
1353 + uint16_t cq_id;
1354 + uint16_t rsvd0;
1355 + }rsp;
1356 + }params;
1357 +};
1358 +
1088 1359 /* [54] OPCODE_DESTROY_COMMON_CQ */
1089 1360 struct mbx_destroy_common_cq {
1090 1361 struct mbx_hdr hdr;
1091 1362 union {
1092 1363 struct {
1093 1364 #ifdef _BIG_ENDIAN
1094 1365 uint16_t rsvd0;
1095 1366 uint16_t id;
1096 1367 #else
1097 1368 uint16_t id;
1098 1369 uint16_t rsvd0;
1099 1370 #endif
1100 1371 }req;
1101 1372
1102 1373 struct {
1103 1374 uint32_t rsvd0;
1104 1375 }rsp;
1105 1376 }params;
1106 1377 };
1107 1378
1108 -struct mq_ring_ctx {
1379 +struct mq_ring_ctx_v0 {
1109 1380 union {
1110 1381 struct {
1111 1382 #ifdef _BIG_ENDIAN
1112 1383 /* dw 0 */
1113 1384 uint32_t cq_id:10;
1114 1385 uint32_t fetch_r2t:1;
1115 1386 uint32_t fetch_wrb:1;
1116 1387 uint32_t ring_size:4;
1117 1388 uint32_t rsvd0:2;
1118 1389 uint32_t con_index:14;
1119 1390
1120 1391 /* dw1 */
1121 1392 uint32_t valid:1;
1122 1393 uint32_t pdid:9;
1123 1394 uint32_t fid:8;
1124 1395 uint32_t prod_index:14;
1125 1396
1126 1397 /* dw 2 */
1127 1398 uint32_t rsvd1:21;
1128 1399 uint32_t async_cq_id:10;
1129 1400 uint32_t async_cq_valid:1;
1130 1401 #else
1131 1402 /* dw 0 */
1132 1403 uint32_t con_index:14;
1133 1404 uint32_t rsvd0:2;
1134 1405 uint32_t ring_size:4;
1135 1406 uint32_t fetch_wrb:1;
1136 1407 uint32_t fetch_r2t:1;
1137 1408 uint32_t cq_id:10;
1138 1409
1139 1410 /* dw1 */
1140 1411 uint32_t prod_index:14;
1141 1412 uint32_t fid:8;
1142 1413 uint32_t pdid:9;
1143 1414 uint32_t valid:1;
1144 1415
1145 1416 /* dw 2 */
1146 1417 uint32_t async_cq_valid:1;
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1147 1418 uint32_t async_cq_id:10;
1148 1419 uint32_t rsvd1:21;
1149 1420 #endif
1150 1421 /* dw3 */
1151 1422 uint32_t rsvd3;
1152 1423 }s;
1153 1424 uint32_t dw[4];
1154 1425 }u0;
1155 1426 };
1156 1427
1157 -/* [21] OPCODE_CREATE_COMMON_MQ */
1428 +/* [21] OPCODE_CREATE_COMMON_MQ V0 */
1158 1429 struct mbx_create_common_mq {
1159 1430 struct mbx_hdr hdr;
1160 1431 union {
1161 1432 struct {
1162 1433 #ifdef _BIG_ENDIAN
1163 1434 uint16_t rsvd0;
1164 1435 uint16_t num_pages;
1165 1436 #else
1166 1437 uint16_t num_pages;
1167 1438 uint16_t rsvd0;
1168 1439 #endif
1169 - struct mq_ring_ctx context;
1440 + struct mq_ring_ctx_v0 context;
1170 1441 struct phys_addr pages[8];
1171 1442 }req;
1172 1443
1173 1444 struct {
1174 1445 uint32_t mq_id:16;
1175 1446 uint32_t rsvd0:16;
1176 1447 }rsp;
1177 1448 }params;
1178 1449 };
1179 1450
1451 +/* [90] OPCODE_COMMON_MCC_CREATE_EXT V0 */
1452 +struct mbx_create_common_mq_ext_v0 {
1453 + struct mbx_hdr hdr;
1454 + union {
1455 + struct {
1456 +#ifdef _BIG_ENDIAN
1457 + uint16_t rsvd0;
1458 + uint16_t num_pages;
1459 +#else
1460 + uint16_t num_pages;
1461 + uint16_t rsvd0;
1462 +#endif
1463 + uint32_t async_event_bitmap[1];
1464 + struct mq_ring_ctx_v0 context;
1465 + struct phys_addr pages[8];
1466 + }req;
1467 +
1468 + struct {
1469 + uint32_t mq_id:16;
1470 + uint32_t rsvd0:16;
1471 + }rsp;
1472 + }params;
1473 +};
1474 +
1475 +struct mq_ring_ctx_v1 {
1476 + union {
1477 + struct {
1478 +#ifdef _BIG_ENDIAN
1479 + /* dw 0 */
1480 + uint32_t rsrvd0:12;
1481 + uint32_t ring_size:4;
1482 + uint32_t async_cq_id:16;
1483 +
1484 + /* dw1 */
1485 + uint32_t valid:1;
1486 + uint32_t rsrvd1:31;
1487 +
1488 + /* dw 2 */
1489 + uint32_t rsvd2:31;
1490 + uint32_t async_cq_valid:1;
1491 +#else
1492 + /* dw 0 */
1493 + uint32_t async_cq_id:16;
1494 + uint32_t ring_size:4;
1495 + uint32_t rsrvd0:12;
1496 +
1497 + /* dw1 */
1498 + uint32_t rsrvd1:31;
1499 + uint32_t valid:1;
1500 +
1501 + /* dw 2 */
1502 + uint32_t async_cq_valid:1;
1503 + uint32_t rsvd2:31;
1504 +#endif
1505 + /* dw3 */
1506 + uint32_t rsvd3;
1507 + }s;
1508 + uint32_t dw[4];
1509 + }u0;
1510 +};
1511 +
1512 +/* [90] OPCODE_COMMON_MCC_CREATE_EXT V1 */
1513 +struct mbx_create_common_mq_ext_v1 {
1514 + struct mbx_hdr hdr;
1515 + union {
1516 + struct {
1517 +#ifdef _BIG_ENDIAN
1518 + uint16_t cq_id;
1519 + uint16_t num_pages;
1520 +#else
1521 + uint16_t num_pages;
1522 + uint16_t cq_id;
1523 +#endif
1524 + uint32_t async_event_bitmap[1];
1525 + struct mq_ring_ctx_v1 context;
1526 + struct phys_addr pages[8];
1527 + }req;
1528 +
1529 + struct {
1530 + uint32_t mq_id:16;
1531 + uint32_t rsvd0:16;
1532 + }rsp;
1533 + }params;
1534 +};
1535 +
1180 1536 /* [53] OPCODE_DESTROY_COMMON_MQ */
1181 1537 struct mbx_destroy_common_mq {
1182 1538 struct mbx_hdr hdr;
1183 1539 union {
1184 1540 struct {
1185 1541 #ifdef _BIG_ENDIAN
1186 1542 uint16_t rsvd0;
1187 1543 uint16_t id;
1188 1544 #else
1189 1545 uint16_t id;
1190 1546 uint16_t rsvd0;
1191 1547 #endif
1192 1548 }req;
1193 1549
1194 1550 struct {
1195 1551 uint32_t rsvd0;
1196 1552 }rsp;
1197 1553 }params;
1198 1554 };
1199 1555
1200 1556 /* [35] OPCODE_GET_COMMON_ FW_VERSION */
1201 1557 struct mbx_get_common_fw_version {
1202 1558 struct mbx_hdr hdr;
1203 1559 union {
1204 1560 struct {
1205 1561 uint32_t rsvd0;
1206 1562 }req;
1207 1563
1208 1564 struct {
1209 1565 uint8_t fw_ver_str[32];
1210 1566 uint8_t fw_on_flash_ver_str[32];
1211 1567 }rsp;
1212 1568 }params;
1213 1569 };
1214 1570
1215 1571 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1216 1572 struct mbx_common_cev_modify_msi_messages {
1217 1573 struct mbx_hdr hdr;
1218 1574 union {
1219 1575 struct {
1220 1576 uint32_t num_msi_msgs;
1221 1577 }req;
1222 1578
1223 1579 struct {
1224 1580 uint32_t rsvd0;
1225 1581 }rsp;
1226 1582 }params;
1227 1583 };
1228 1584
1229 1585 /* [36] OPCODE_SET_COMMON_FLOW_CONTROL */
1230 1586 /* [37] OPCODE_GET_COMMON_FLOW_CONTROL */
1231 1587 struct mbx_common_get_set_flow_control {
1232 1588 struct mbx_hdr hdr;
1233 1589 #ifdef _BIG_ENDIAN
1234 1590 uint16_t tx_flow_control;
1235 1591 uint16_t rx_flow_control;
1236 1592 #else
1237 1593 uint16_t rx_flow_control;
1238 1594 uint16_t tx_flow_control;
1239 1595 #endif
1240 1596 };
1241 1597
1242 1598 enum e_flash_opcode {
1243 1599 MGMT_FLASHROM_OPCODE_FLASH = 1,
1244 1600 MGMT_FLASHROM_OPCODE_SAVE = 2
1245 1601 };
1246 1602
1247 1603 /* [06] OPCODE_READ_COMMON_FLASHROM */
1248 1604 /* [07] OPCODE_WRITE_COMMON_FLASHROM */
1249 1605
1250 1606 struct mbx_common_read_write_flashrom {
1251 1607 struct mbx_hdr hdr;
1252 1608 uint32_t flash_op_code;
1253 1609 uint32_t flash_op_type;
1254 1610 uint32_t data_buffer_size;
1255 1611 uint32_t data_offset;
1256 1612 uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */
1257 1613 };
1258 1614
1259 1615 /* ULP MODE SUPPORTED */
1260 1616 enum {
1261 1617 ULP_TOE_MODE = 0x1,
1262 1618 ULP_NIC_MODE = 0x2,
1263 1619 ULP_RDMA_MODE = 0x4,
1264 1620 ULP_ISCSI_INI_MODE = 0x10,
1265 1621 ULP_ISCSI_TGT_MODE = 0x20,
1266 1622 ULP_FCOE_INI_MODE = 0x40,
1267 1623 ULP_FCOE_TGT_MODE = 0x80,
1268 1624 ULP_DAL_MODE = 0x100,
1269 1625 ULP_LRO_MODE = 0x200
1270 1626 };
1271 1627
1272 1628 /* Function Mode Supported */
1273 1629 enum {
1274 1630 TOE_MODE = 0x1, /* TCP offload */
1275 1631 NIC_MODE = 0x2, /* Raw Ethernet */
1276 1632 RDMA_MODE = 0x4, /* RDMA */
1277 1633 VM_MODE = 0x8, /* VM */
1278 1634 ISCSI_INI_MODE = 0x10, /* iSCSI initiator */
1279 1635 ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */
1280 1636 FCOE_INI_MODE = 0x40, /* FCoE Initiator */
1281 1637 FCOE_TGT_MODE = 0x80, /* FCoE target */
1282 1638 DAL_MODE = 0x100, /* DAL */
1283 1639 LRO_MODE = 0x200, /* LRO */
1284 1640 FLEX10_MODE = 0x400, /* FLEX-10 or VNIC */
1285 1641 NCSI_MODE = 0x800, /* NCSI */
1286 1642 INVALID_MODE = 0x8000 /* Invalid */
1287 1643 };
1288 1644
1289 1645 struct mbx_common_query_fw_config {
1290 1646 struct mbx_hdr hdr;
1291 1647 union {
1292 1648 struct {
1293 1649 uint32_t rsvd0[30];
1294 1650 }req;
1295 1651
1296 1652 struct {
1297 1653 uint32_t config_number;
1298 1654 uint32_t asic_revision;
1299 1655 uint32_t port_id; /* used for stats retrieval */
1300 1656 uint32_t function_mode;
1301 1657 struct {
1302 1658
1303 1659 uint32_t mode;
1304 1660 uint32_t wq_base;
1305 1661 uint32_t wq_count;
1306 1662 uint32_t sq_base;
1307 1663 uint32_t sq_count;
1308 1664 uint32_t rq_base;
1309 1665 uint32_t rq_count;
1310 1666 uint32_t dq_base;
1311 1667 uint32_t dq_count;
1312 1668 uint32_t lro_base;
1313 1669 uint32_t lro_count;
1314 1670 uint32_t icd_base;
1315 1671 uint32_t icd_count;
1316 1672 } ulp[2];
1317 1673 uint32_t function_caps;
1318 1674 }rsp;
1319 1675 }params;
1320 1676 };
1321 1677
1322 1678 struct mbx_common_config_vlan {
1323 1679 struct mbx_hdr hdr;
1324 1680 union {
1325 1681 struct {
1326 1682 #ifdef _BIG_ENDIAN
1327 1683 uint8_t num_vlans;
1328 1684 uint8_t untagged;
1329 1685 uint8_t promisc;
1330 1686 uint8_t if_id;
1331 1687 #else
1332 1688 uint8_t if_id;
1333 1689 uint8_t promisc;
1334 1690 uint8_t untagged;
1335 1691 uint8_t num_vlans;
1336 1692 #endif
1337 1693 union {
1338 1694 struct normal_vlan normal_vlans[64];
1339 1695 struct qinq_vlan qinq_vlans[32];
1340 1696 }tags;
1341 1697 }req;
1342 1698
1343 1699 struct {
1344 1700 uint32_t rsvd;
1345 1701 }rsp;
1346 1702 }params;
1347 1703 };
1348 1704
1349 1705 /* [34] OPCODE_COMMON_NTWK_RX_FILTER */
1350 1706 struct mbx_set_common_ntwk_rx_filter {
1351 1707 struct mbx_hdr hdr;
1352 1708 uint32_t global_flags_mask;
1353 1709 uint32_t global_flags;
1354 1710 uint32_t iface_flags_mask;
1355 1711 uint32_t iface_flags;
1356 1712 uint32_t if_id;
1357 1713 uint32_t num_mcast;
1358 1714 struct {
1359 1715 uint8_t byte[6];
1360 1716 }mac[32];
1361 1717 };
1362 1718 /* [41] OPCODE_MODIFY_COMMON_EQ_DELAY */
1363 1719 struct mbx_modify_common_eq_delay {
1364 1720 struct mbx_hdr hdr;
1365 1721 union {
1366 1722 struct {
1367 1723 uint32_t num_eq;
1368 1724 struct {
1369 1725 uint32_t eq_id;
1370 1726 uint32_t phase;
1371 1727 uint32_t dm;
1372 1728 }delay[8];
1373 1729 }req;
1374 1730
1375 1731 struct {
1376 1732 uint32_t rsvd0;
1377 1733 }rsp;
1378 1734 }params;
1379 1735 };
1380 1736 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1381 1737 struct mbx_add_common_iface_mac {
1382 1738 struct mbx_hdr hdr;
1383 1739 union {
1384 1740 struct {
1385 1741 uint32_t if_id;
1386 1742 uint8_t mac_address[6];
1387 1743 uint8_t rsvd0[2];
1388 1744 }req;
1389 1745 struct {
1390 1746 uint32_t pmac_id;
1391 1747 }rsp;
1392 1748 } params;
1393 1749 };
1394 1750
1395 1751 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1396 1752 struct mbx_del_common_iface_mac {
1397 1753 struct mbx_hdr hdr;
1398 1754 union {
1399 1755 struct {
1400 1756 uint32_t if_id;
1401 1757 uint32_t pmac_id;
1402 1758 }req;
1403 1759 struct {
1404 1760 uint32_t rsvd0;
1405 1761 }rsp;
1406 1762 } params;
1407 1763 };
1408 1764
1409 1765 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1410 1766 struct mbx_query_common_max_mbx_buffer_size {
1411 1767 struct mbx_hdr hdr;
1412 1768 struct {
1413 1769 uint32_t max_ioctl_bufsz;
1414 1770 } rsp;
1415 1771 };
1416 1772
1417 1773 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1418 1774 struct ioctl_common_function_reset {
1419 1775 struct mbx_hdr hdr;
1420 1776 };
1421 1777
1422 1778 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1423 1779 struct mbx_common_func_link_cfg {
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1424 1780 struct mbx_hdr hdr;
1425 1781 union {
1426 1782 struct {
1427 1783 uint32_t enable;
1428 1784 }req;
1429 1785 struct {
1430 1786 uint32_t rsvd0;
1431 1787 }rsp;
1432 1788 } params;
1433 1789 };
1790 +
1791 +/* [103] OPCODE_COMMON_SET_DRIVER_FUNCTION_CAPABILITIES */
1792 +struct mbx_common_set_drvfn_capab {
1793 + struct mbx_hdr hdr;
1794 + union {
1795 + struct {
1796 + uint32_t valid_capability_flags;
1797 + uint32_t capability_flags;
1798 + uint8_t sbz[212];
1799 + } request;
1800 + struct {
1801 + uint32_t valid_capability_flags;
1802 + uint32_t capability_flags;
1803 + uint8_t sbz[212];
1804 + } response;
1805 + } params;
1806 +};
1434 1807
1435 1808 #pragma pack()
1436 1809
1437 1810 #ifdef __cplusplus
1438 1811 }
1439 1812 #endif
1440 1813
1441 1814 #endif /* _OCE_HW_H_ */
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