2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright © 2003-2011 Emulex. All rights reserved. */
23
24 /*
25 * Header file containing the command structures for Hardware
26 */
27
28 #ifndef _OCE_HW_H_
29 #define _OCE_HW_H_
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 #include <sys/types.h>
36
37 #pragma pack(1)
38
39 #define OC_CNA_GEN2 0x2
40 #define OC_CNA_GEN3 0x3
41 #define DEVID_TIGERSHARK 0x700
42 #define DEVID_TOMCAT 0x710
43
44 /* PCI CSR offsets */
45 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */
46 #define PCICFG_SEMAPHORE 0xbc
47 #define PCICFG_SOFT_RESET 0x5c
48 #define PCICFG_UE_STATUS_HI_MASK 0xac
49 #define PCICFG_UE_STATUS_LO_MASK 0xa8
50 #define PCICFG_ONLINE0 0xb0
51 #define PCICFG_ONLINE1 0xb4
52 #define INTR_EN 0x20000000
53 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */
54
55 /* CSR register offsets */
56 #define MPU_EP_CONTROL 0
57 #define MPU_EP_SEMAPHORE 0xac
58 #define PCICFG_INTR_CTRL 0xfc
59 #define HOSTINTR_MASK (1 << 29)
60 #define HOSTINTR_PFUNC_SHIFT 26
61 #define HOSTINTR_PFUNC_MASK 7
62
63 /* POST status reg struct */
64 #define POST_STAGE_POWER_ON_RESET 0x00
65 #define POST_STAGE_AWAITING_HOST_RDY 0x01
66 #define POST_STAGE_HOST_RDY 0x02
67 #define POST_STAGE_CHIP_RESET 0x03
68 #define POST_STAGE_ARMFW_READY 0xc000
69 #define POST_STAGE_ARMFW_UE 0xf000
70
71 /* DOORBELL registers */
72 #define PD_RXULP_DB 0x0100
73 #define PD_TXULP_DB 0x0060
74 #define DB_RQ_ID_MASK 0x3FF
75
76 #define PD_CQ_DB 0x0120
77 #define PD_EQ_DB PD_CQ_DB
78 #define PD_MPU_MBOX_DB 0x0160
79 #define PD_MQ_DB 0x0140
80
81 /* EQE completion types */
82 #define EQ_MINOR_CODE_COMPLETION 0x00
108 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
109
110 /* Hardware Address types */
111 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */
112 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */
113 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */
114 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */
115 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */
116
117 /* CREATE_IFACE capability and cap_en flags */
118 #define MBX_RX_IFACE_FLAGS_RSS 0x4
119 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
120 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
121 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
122 #define MBX_RX_IFACE_FLAGS_ULP 0x40
123 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
124 #define MBX_RX_IFACE_FLAGS_VLAN 0x100
125 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
126 #define MBX_RX_IFACE_FLAGS_PASS_L2 0x400
127 #define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800
128
129 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */
130 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */
131 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
132 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
133
134
135 #define MBX_DB_READY_BIT 0x1
136 #define MBX_DB_HI_BIT 0x2
137 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
138 #define ASYNC_EVENT_LINK_UP 0x1
139 #define ASYNC_EVENT_LINK_DOWN 0x0
140
141 /* port link_status */
142 #define ASYNC_EVENT_LOGICAL 0x02
143
144 /* Logical Link Status */
145 #define NTWK_LOGICAL_LINK_DOWN 0
146 #define NTWK_LOGICAL_LINK_UP 1
147
148 /* Rx filter bits */
149 #define NTWK_RX_FILTER_IP_CKSUM 0x1
150 #define NTWK_RX_FILTER_TCP_CKSUM 0x2
151 #define NTWK_RX_FILTER_UDP_CKSUM 0x4
152 #define NTWK_RX_FILTER_STRIP_CRC 0x8
153
154 /* max SGE per mbx */
155 #define MAX_MBX_SGE 19
156
157 /* physical address structure to be used in MBX */
158 struct phys_addr {
159 /* dw0 */
160 uint32_t lo;
161 /* dw1 */
162 uint32_t hi;
163 };
164
165 typedef union pcicfg_intr_ctl_u {
166 uint32_t dw0;
167 struct {
168 #ifdef _BIG_ENDIAN
169 uint32_t winselect:2;
170 uint32_t hostintr:1;
171 uint32_t pfnum:3;
172 uint32_t vf_cev_int_line_en:1;
173 uint32_t winaddr:23;
174 uint32_t membarwinen:1;
175 #else
176 uint32_t membarwinen:1;
345 uint32_t num_posted:14;
346 uint32_t rsvd0:6;
347 uint32_t qid:10;
348 #else
349 uint32_t qid:10;
350 uint32_t rsvd0:6;
351 uint32_t num_posted:14;
352 uint32_t rsvd1:2;
353 #endif
354 }bits;
355 }pd_txulp_db_t;
356
357 /* CQ doorbell */
358 typedef union cq_db_u {
359 uint32_t dw0;
360 struct {
361 #ifdef _BIG_ENDIAN
362 uint32_t rsvd1:2;
363 uint32_t rearm:1;
364 uint32_t num_popped:13;
365 uint32_t rsvd0:5;
366 uint32_t event:1;
367 uint32_t qid:10;
368 #else
369 uint32_t qid:10;
370 uint32_t event:1;
371 uint32_t rsvd0:5;
372 uint32_t num_popped:13;
373 uint32_t rearm:1;
374 uint32_t rsvd1:2;
375 #endif
376 }bits;
377 }cq_db_t;
378
379 /* EQ doorbell */
380 typedef union eq_db_u {
381 uint32_t dw0;
382 struct {
383 #ifdef _BIG_ENDIAN
384 uint32_t rsvd1:2;
385 uint32_t rearm:1;
386 uint32_t num_popped:13;
387 uint32_t rsvd0:5;
388 uint32_t event:1;
389 uint32_t clrint:1;
390 uint32_t qid:9;
391 #else
392 uint32_t qid:9;
393 uint32_t clrint:1;
394 uint32_t event:1;
395 uint32_t rsvd0:5;
396 uint32_t num_popped:13;
397 uint32_t rearm:1;
398 uint32_t rsvd1:2;
399 #endif
400 }bits;
401 }eq_db_t;
402
403 /* bootstrap mbox doorbell */
404 typedef union pd_mpu_mbox_db_u {
405 uint32_t dw0;
406 struct {
407 #ifdef _BIG_ENDIAN
408 uint32_t address:30;
409 uint32_t hi:1;
410 uint32_t ready:1;
411 #else
412 uint32_t ready:1;
413 uint32_t hi:1;
414 uint32_t address:30;
415 #endif
489 uint32_t sge_count : 5;
490 uint32_t rsvd0 : 2;
491 uint32_t embedded : 1;
492 #else
493 uint32_t embedded:1;
494 uint32_t rsvd0:2;
495 uint32_t sge_count:5;
496 uint32_t rsvd1:16;
497 uint32_t special:8;
498 #endif
499 }s;
500 uint32_t dw0;
501 }u0;
502
503 uint32_t payload_length;
504 uint32_t tag[2];
505 uint32_t rsvd2[1];
506 struct oce_mbx_payload payload;
507 };
508
509 /* completion queue entry for MQ */
510 struct oce_mq_cqe {
511 union {
512 struct {
513 #ifdef _BIG_ENDIAN
514 /* dw0 */
515 uint32_t extended_status:16;
516 uint32_t completion_status:16;
517 /* dw1 dw2 */
518 uint32_t mq_tag[2];
519 /* dw3 */
520 uint32_t valid:1;
521 uint32_t async_event:1;
522 uint32_t hpi_buffer_cmpl:1;
523 uint32_t completed:1;
524 uint32_t consumed:1;
525 uint32_t rsvd0:27;
526 #else
527 /* dw0 */
528 uint32_t completion_status:16;
529 uint32_t extended_status:16;
530 /* dw1 dw2 */
531 uint32_t mq_tag[2];
532 /* dw3 */
533 uint32_t rsvd0:27;
534 uint32_t consumed:1;
535 uint32_t completed:1;
536 uint32_t hpi_buffer_cmpl:1;
537 uint32_t async_event:1;
538 uint32_t valid:1;
539 #endif
540 }s;
541 uint32_t dw[4];
542 }u0;
543 };
544
545 struct oce_async_cqe_link_state {
546 union {
547 struct {
548 #ifdef _BIG_ENDIAN
549 /* dw0 */
550 uint8_t speed;
551 uint8_t duplex;
552 uint8_t link_status;
553 uint8_t phy_port;
554 /* dw1 */
555 uint8_t rsvd0[3];
556 uint8_t fault;
557 /* dw2 */
558 uint32_t event_tag;
559 /* dw3 */
560 uint32_t valid:1;
561 uint32_t async_event:1;
562 uint32_t rsvd2:6;
563 uint32_t event_type:8;
564 uint32_t event_code:8;
565 uint32_t rsvd1:8;
566 #else
567 /* dw0 */
568 uint8_t phy_port;
569 uint8_t link_status;
570 uint8_t duplex;
571 uint8_t speed;
572 /* dw1 */
573 uint8_t fault;
574 uint8_t rsvd0[3];
575 /* dw2 */
576 uint32_t event_tag;
577 /* dw3 */
578 uint32_t rsvd1:8;
579 uint32_t event_code:8;
580 uint32_t event_type:8;
581 uint32_t rsvd2:6;
582 uint32_t async_event:1;
583 uint32_t valid:1;
584 #endif
585 }s;
586 uint32_t dw[4];
587 }u0;
588 };
589
590 /* MQ mailbox structure */
591 struct oce_bmbx {
592 struct oce_mbx mbx;
593 struct oce_mq_cqe cqe;
594 };
595
596 /* ---[ MBXs start here ]---------------------------------------------- */
597 /* MBXs sub system codes */
598 enum {
599 MBX_SUBSYSTEM_RSVD = 0,
600 MBX_SUBSYSTEM_COMMON = 1,
601 MBX_SUBSYSTEM_COMMON_ISCSI = 2,
602 MBX_SUBSYSTEM_NIC = 3,
603 MBX_SUBSYSTEM_TOE = 4,
604 MBX_SUBSYSTEM_PXE_UNDI = 5,
605 MBX_SUBSYSTEM_ISCSI_INI = 6,
606 MBX_SUBSYSTEM_ISCSI_TGT = 7,
607 MBX_SUBSYSTEM_MILI_PTL = 8,
608 MBX_SUBSYSTEM_MILI_TMD = 9,
609 MBX_SUBSYSTEM_RDMA = 10,
610 MBX_SUBSYSTEM_LOWLEVEL = 11,
611 MBX_SUBSYSTEM_LRO = 13,
612 IOCBMBX_SUBSYSTEM_DCBX = 15,
613 IOCBMBX_SUBSYSTEM_DIAG = 16,
614 IOCBMBX_SUBSYSTEM_VENDOR = 17
615 };
616
617 /* common ioctl opcodes */
618 enum {
619 OPCODE_QUERY_COMMON_IFACE_MAC = 1,
620 OPCODE_SET_COMMON_IFACE_MAC = 2,
621 OPCODE_SET_COMMON_IFACE_MULTICAST = 3,
622 OPCODE_CONFIG_COMMON_IFACE_VLAN = 4,
623 OPCODE_QUERY_COMMON_LINK_STATUS = 5,
624 OPCODE_READ_COMMON_FLASHROM = 6,
625 OPCODE_WRITE_COMMON_FLASHROM = 7,
626 OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8,
627 OPCODE_ADD_COMMON_PAGE_TABLES = 9,
628 OPCODE_REMOVE_COMMON_PAGE_TABLES = 10,
629 OPCODE_CREATE_COMMON_CQ = 12,
630 OPCODE_CREATE_COMMON_EQ = 13,
631 OPCODE_CREATE_COMMON_MQ = 21,
632 OPCODE_COMMON_JELL_CONFIG = 22,
633 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24,
634 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25,
635 OPCODE_COMMON_POST_ZERO_BUFFER = 26,
636 OPCODE_COMMON_GET_QOS = 27,
637 OPCODE_COMMON_SET_QOS = 28,
638 OPCODE_COMMON_TCP_GET_STATISTICS = 29,
639 OPCODE_READ_COMMON_SEEPROM = 30,
640 OPCODE_COMMON_TCP_STATE_QUERY = 31,
641 OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32,
642 OPCODE_COMMON_NOP = 33,
649 OPCODE_COMMON_GET_FAT = 40,
650 OPCODE_MODIFY_COMMON_EQ_DELAY = 41,
651 OPCODE_COMMON_FIRMWARE_CONFIG = 42,
652 OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43,
653 OPCODE_COMMON_GET_DOMAIN_CONFIG = 44,
654 OPCODE_COMMON_GET_PORT_EQUALIZATION = 47,
655 OPCODE_COMMON_SET_PORT_EQUALIZATION = 48,
656 OPCODE_COMMON_RED_CONFIG = 49,
657 OPCODE_CREATE_COMMON_IFACE = 50,
658 OPCODE_DESTROY_COMMON_IFACE = 51,
659 OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52,
660 OPCODE_DESTROY_COMMON_MQ = 53,
661 OPCODE_DESTROY_COMMON_CQ = 54,
662 OPCODE_DESTROY_COMMON_EQ = 55,
663 OPCODE_COMMON_TCP_UPL_OAD = 56,
664 OPCODE_SET_COMMON_LINK_SPEED = 57,
665 OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58,
666 OPCODE_ADD_COMMON_IFACE_MAC = 59,
667 OPCODE_DEL_COMMON_IFACE_MAC = 60,
668 OPCODE_COMMON_FUNCTION_RESET = 61,
669 OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80
670 };
671
672 /* common ioctl header */
673 struct mbx_hdr {
674 union {
675 struct {
676 #ifdef _BIG_ENDIAN
677 uint8_t domain;
678 uint8_t port_number;
679 uint8_t subsystem;
680 uint8_t opcode;
681 #else
682 uint8_t opcode;
683 uint8_t subsystem;
684 uint8_t port_number;
685 uint8_t domain;
686 #endif
687 uint32_t timeout;
688 uint32_t request_length;
689 uint32_t rsvd0;
690 }req;
691
692 struct {
693 /* dw 0 */
694 uint8_t opcode;
695 uint8_t subsystem;
696 uint8_t rsvd0;
697 uint8_t domain;
698 /* dw 1 */
699 uint8_t status;
700 uint8_t additional_status;
701 uint16_t rsvd1;
702
703 uint32_t rsp_length;
704 uint32_t actual_rsp_length;
705 }rsp;
706 uint32_t dw[4];
707 }u0;
708 };
709 #define OCE_BMBX_RHDR_SZ 20
710 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
711 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
712 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
713
714 /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */
715 struct mbx_query_common_link_status {
716 struct mbx_hdr hdr;
717 union {
718 struct {
719 uint32_t rsvd0;
720 }req;
721
722 struct {
723 /* dw 0 */
724 uint8_t physical_port;
725 uint8_t mac_duplex;
726 uint8_t mac_speed;
727 uint8_t mac_fault;
728 /* dw 1 */
729 uint8_t mgmt_mac_duplex;
730 uint8_t mgmt_mac_speed;
731 uint16_t qos_link_speed;
732 uint32_t logical_link_status;
882 uint32_t dw[4];
883 }params;
884 };
885
886 /* [51] OPCODE_DESTROY_COMMON_IFACE */
887 struct mbx_destroy_common_iface {
888 struct mbx_hdr hdr;
889 union {
890 struct {
891 uint32_t if_id;
892 }req;
893
894 struct {
895 uint32_t rsvd0;
896 }rsp;
897
898 uint32_t dw;
899 }params;
900 };
901
902 /* event queue context structure */
903 struct oce_eq_ctx {
904 #ifdef _BIG_ENDIAN
905 /* dw0 */
906 uint32_t size:1;
907 uint32_t rsvd1:1;
908 uint32_t valid:1;
909 uint32_t epidx:13;
910 uint32_t rsvd0:3;
911 uint32_t cidx:13;
912
913 /* dw1 */
914 uint32_t armed:1;
915 uint32_t stalled:1;
916 uint32_t sol_event:1;
917 uint32_t count:3;
918 uint32_t pd:10;
919 uint32_t rsvd2:3;
920 uint32_t pidx:13;
921
948 uint32_t sol_event:1;
949 uint32_t stalled:1;
950 uint32_t armed:1;
951
952 /* dw2 */
953 uint32_t rsvd3:4;
954 uint32_t function:8;
955 uint32_t rsvd4:1;
956 uint32_t delay_mult:10;
957 uint32_t rsvd5:2;
958 uint32_t phase:2;
959 uint32_t nodelay:1;
960 uint32_t rsvd6:4;
961
962 /* dw3 */
963 uint32_t rsvd7;
964 #endif
965 };
966
967 /* [13] OPCODE_CREATE_COMMON_EQ */
968 struct mbx_create_common_eq {
969 struct mbx_hdr hdr;
970 union {
971 struct {
972 #ifdef _BIG_ENDIAN
973 uint16_t rsvd0;
974 uint16_t num_pages;
975 #else
976 uint16_t num_pages;
977 uint16_t rsvd0;
978 #endif
979 struct oce_eq_ctx eq_ctx;
980 struct phys_addr pages[8];
981 }req;
982
983 struct {
984 uint16_t eq_id;
985 uint16_t rsvd0;
986 }rsp;
987 }params;
988 };
990 /* [55] OPCODE_DESTROY_COMMON_EQ */
991 struct mbx_destroy_common_eq {
992 struct mbx_hdr hdr;
993 union {
994 struct {
995 #ifdef _BIG_ENDIAN
996 uint16_t rsvd0;
997 uint16_t id;
998 #else
999 uint16_t id;
1000 uint16_t rsvd0;
1001 #endif
1002 }req;
1003
1004 struct {
1005 uint32_t rsvd0;
1006 }rsp;
1007 }params;
1008 };
1009
1010 struct oce_cq_ctx {
1011 #ifdef _BIG_ENDIAN
1012 /* dw0 */
1013 uint32_t eventable:1;
1014 uint32_t sol_event:1;
1015 uint32_t valid:1;
1016 uint32_t count:2;
1017 uint32_t rsvd1:1;
1018 uint32_t epidx:11;
1019 uint32_t nodelay:1;
1020 uint32_t coalesce_wm:2;
1021 uint32_t rsvd0:1;
1022 uint32_t cidx:11;
1023
1024 /* dw1 */
1025 uint32_t armed:1;
1026 uint32_t stalled:1;
1027 uint32_t eq_id:8;
1028 uint32_t pd:10;
1029 uint32_t rsvd2:1;
1030 uint32_t pidx:11;
1045 uint32_t valid:1;
1046 uint32_t sol_event:1;
1047 uint32_t eventable:1;
1048
1049 /* dw1 */
1050 uint32_t pidx:11;
1051 uint32_t rsvd2:1;
1052 uint32_t pd:10;
1053 uint32_t eq_id:8;
1054 uint32_t stalled:1;
1055 uint32_t armed:1;
1056
1057 /* dw2 */
1058 uint32_t rsvd3:4;
1059 uint32_t function:8;
1060 uint32_t rsvd4:20;
1061 #endif
1062 uint32_t rsvd5;
1063 };
1064
1065 /* [12] OPCODE_CREATE_COMMON_CQ */
1066 struct mbx_create_common_cq {
1067 struct mbx_hdr hdr;
1068 union {
1069 struct {
1070 #ifdef _BIG_ENDIAN
1071 uint16_t rsvd0;
1072 uint16_t num_pages;
1073 #else
1074 uint16_t num_pages;
1075 uint16_t rsvd0;
1076 #endif
1077 struct oce_cq_ctx cq_ctx;
1078 struct phys_addr pages[4];
1079 }req;
1080
1081 struct {
1082 uint16_t cq_id;
1083 uint16_t rsvd0;
1084 }rsp;
1085 }params;
1086 };
1087
1088 /* [54] OPCODE_DESTROY_COMMON_CQ */
1089 struct mbx_destroy_common_cq {
1090 struct mbx_hdr hdr;
1091 union {
1092 struct {
1093 #ifdef _BIG_ENDIAN
1094 uint16_t rsvd0;
1095 uint16_t id;
1096 #else
1097 uint16_t id;
1098 uint16_t rsvd0;
1099 #endif
1100 }req;
1101
1102 struct {
1103 uint32_t rsvd0;
1104 }rsp;
1105 }params;
1106 };
1107
1108 struct mq_ring_ctx {
1109 union {
1110 struct {
1111 #ifdef _BIG_ENDIAN
1112 /* dw 0 */
1113 uint32_t cq_id:10;
1114 uint32_t fetch_r2t:1;
1115 uint32_t fetch_wrb:1;
1116 uint32_t ring_size:4;
1117 uint32_t rsvd0:2;
1118 uint32_t con_index:14;
1119
1120 /* dw1 */
1121 uint32_t valid:1;
1122 uint32_t pdid:9;
1123 uint32_t fid:8;
1124 uint32_t prod_index:14;
1125
1126 /* dw 2 */
1127 uint32_t rsvd1:21;
1128 uint32_t async_cq_id:10;
1137 uint32_t cq_id:10;
1138
1139 /* dw1 */
1140 uint32_t prod_index:14;
1141 uint32_t fid:8;
1142 uint32_t pdid:9;
1143 uint32_t valid:1;
1144
1145 /* dw 2 */
1146 uint32_t async_cq_valid:1;
1147 uint32_t async_cq_id:10;
1148 uint32_t rsvd1:21;
1149 #endif
1150 /* dw3 */
1151 uint32_t rsvd3;
1152 }s;
1153 uint32_t dw[4];
1154 }u0;
1155 };
1156
1157 /* [21] OPCODE_CREATE_COMMON_MQ */
1158 struct mbx_create_common_mq {
1159 struct mbx_hdr hdr;
1160 union {
1161 struct {
1162 #ifdef _BIG_ENDIAN
1163 uint16_t rsvd0;
1164 uint16_t num_pages;
1165 #else
1166 uint16_t num_pages;
1167 uint16_t rsvd0;
1168 #endif
1169 struct mq_ring_ctx context;
1170 struct phys_addr pages[8];
1171 }req;
1172
1173 struct {
1174 uint32_t mq_id:16;
1175 uint32_t rsvd0:16;
1176 }rsp;
1177 }params;
1178 };
1179
1180 /* [53] OPCODE_DESTROY_COMMON_MQ */
1181 struct mbx_destroy_common_mq {
1182 struct mbx_hdr hdr;
1183 union {
1184 struct {
1185 #ifdef _BIG_ENDIAN
1186 uint16_t rsvd0;
1187 uint16_t id;
1188 #else
1189 uint16_t id;
1190 uint16_t rsvd0;
1191 #endif
1192 }req;
1193
1194 struct {
1195 uint32_t rsvd0;
1196 }rsp;
1197 }params;
1198 };
1199
1414 } rsp;
1415 };
1416
1417 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1418 struct ioctl_common_function_reset {
1419 struct mbx_hdr hdr;
1420 };
1421
1422 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1423 struct mbx_common_func_link_cfg {
1424 struct mbx_hdr hdr;
1425 union {
1426 struct {
1427 uint32_t enable;
1428 }req;
1429 struct {
1430 uint32_t rsvd0;
1431 }rsp;
1432 } params;
1433 };
1434
1435 #pragma pack()
1436
1437 #ifdef __cplusplus
1438 }
1439 #endif
1440
1441 #endif /* _OCE_HW_H_ */
|
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27
28
29 /*
30 * Header file containing the command structures for Hardware
31 */
32
33 #ifndef _OCE_HW_H_
34 #define _OCE_HW_H_
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #include <sys/types.h>
41 #include "oce_sli4.h"
42
43 #pragma pack(1)
44
45 #define OC_CNA_GEN2 0x2
46 #define OC_CNA_GEN3 0x3
47 enum {
48 ASIC_REV_A0 = 0x0,
49 ASIC_REV_A1 = 0x1,
50 ASIC_REV_A2 = 0x2
51 };
52 #define BE3_ASIC_REV_A0 ((OC_CNA_GEN3<<8)| ASIC_REV_A0)
53 #define BE3_ASIC_REV_A1 ((OC_CNA_GEN3<<8)| ASIC_REV_A1)
54 #define BE3_ASIC_REV_A2 ((OC_CNA_GEN3<<8)| ASIC_REV_A2)
55
56 #define BE3_A1(dev) (dev->asic_revision == BE3_ASIC_REV_A0 ||\
57 dev->asic_revision == BE3_ASIC_REV_A1)
58
59 #define DEVID_TIGERSHARK 0x700
60 #define DEVID_TOMCAT 0x710
61 #define DEVID_LANCER 0xe220
62
63 #define LANCER_CHIP(device) (device->device_id == DEVID_LANCER)
64
65
66 /* PCI CSR offsets */
67 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */
68 #define PCICFG_SEMAPHORE 0xbc
69 #define PCICFG_SOFT_RESET 0x5c
70 #define PCICFG_UE_STATUS_LO 0xA0 /* UE status low offset */
71 #define PCICFG_UE_STATUS_HI 0xA4 /* UE status high offset */
72 #define PCICFG_UE_STATUS_LO_MASK 0xa8 /* Error mask - low */
73 #define PCICFG_UE_STATUS_HI_MASK 0xac /* Error mask - high */
74 #define PCICFG_ONLINE0 0xb0
75 #define PCICFG_ONLINE1 0xb4
76 #define INTR_EN 0x20000000
77 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */
78
79 /* CSR register offsets */
80 #define MPU_EP_CONTROL 0
81 #define MPU_EP_SEMAPHORE 0xac
82 #define PCICFG_INTR_CTRL 0xfc
83 #define HOSTINTR_MASK (1 << 29)
84 #define HOSTINTR_PFUNC_SHIFT 26
85 #define HOSTINTR_PFUNC_MASK 7
86
87 /* Link Status CSR */
88 #define PCICFG_PCIE_LINK_STATUS_OFFSET 0xd0
89 #define PCIE_LINK_STATUS_SPEED_MASK 0xFF
90 #define PCIE_LINK_STATUS_SPEED_SHIFT 16
91 #define PCIE_LINK_STATUS_NEG_WIDTH_MASK 0x3F
92 #define PCIE_LINK_STATUS_NEG_WIDTH_SHIFT 20
93
94 /* Link Capability CSR */
95 #define PCICFG_PCIE_LINK_CAP_OFFSET 0xcc
96 #define PCIE_LINK_CAP_MAX_SPEED_MASK 0xFF
97 #define PCIE_LINK_CAP_MAX_SPEED_SHIFT 0
98 #define PCIE_LINK_CAP_MAX_WIDTH_MASK 0x3F
99 #define PCIE_LINK_CAP_MAX_WIDTH_SHIFT 4
100
101 /* POST status reg struct */
102 #define POST_STAGE_POWER_ON_RESET 0x00
103 #define POST_STAGE_AWAITING_HOST_RDY 0x01
104 #define POST_STAGE_HOST_RDY 0x02
105 #define POST_STAGE_CHIP_RESET 0x03
106 #define POST_STAGE_ARMFW_READY 0xc000
107 #define POST_STAGE_ARMFW_UE 0xf000
108
109 /* DOORBELL registers */
110 #define PD_RXULP_DB 0x0100
111 #define PD_TXULP_DB 0x0060
112 #define DB_RQ_ID_MASK 0x3FF
113
114 #define PD_CQ_DB 0x0120
115 #define PD_EQ_DB PD_CQ_DB
116 #define PD_MPU_MBOX_DB 0x0160
117 #define PD_MQ_DB 0x0140
118
119 /* EQE completion types */
120 #define EQ_MINOR_CODE_COMPLETION 0x00
146 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
147
148 /* Hardware Address types */
149 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */
150 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */
151 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */
152 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */
153 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */
154
155 /* CREATE_IFACE capability and cap_en flags */
156 #define MBX_RX_IFACE_FLAGS_RSS 0x4
157 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
158 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
159 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
160 #define MBX_RX_IFACE_FLAGS_ULP 0x40
161 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
162 #define MBX_RX_IFACE_FLAGS_VLAN 0x100
163 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
164 #define MBX_RX_IFACE_FLAGS_PASS_L2 0x400
165 #define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800
166 #define MBX_RX_IFACE_FLAGS_MCAST 0x1000
167
168 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */
169 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */
170 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
171 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
172
173
174 #define MBX_DB_READY_BIT 0x1
175 #define MBX_DB_HI_BIT 0x2
176 /* Event bit map registered with mq */
177 enum {
178 ASYNC_EVENT_CODE_LINK_STATE = 0x1,
179 ASYNC_EVENT_CODE_FCOE_FIP = 0x2,
180 ASYNC_EVENT_CODE_DCBX = 0x3,
181 ASYNC_EVENT_CODE_ISCSI = 0x4,
182 ASYNC_EVENT_CODE_GRP_5 = 0x5,
183 ASYNC_EVENT_CODE_DEBUG = 0x6
184 };
185
186 /* Link events */
187 enum {
188 ASYNC_EVENT_LINK_DOWN = 0x0,
189 ASYNC_EVENT_LINK_UP = 0x1,
190 ASYNC_EVENT_LOGICAL = 0x02
191 };
192
193 /* GRP5 Events */
194 enum {
195 ASYNC_EVENT_QOS_SPEED = 0x1,
196 ASYNC_EVENT_COS_PRIORITY = 0x2,
197 ASYNC_EVENT_PVID_STATE = 0x3
198 };
199
200 /* Event Mask */
201 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8
202 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
203 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
204 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
205
206 /* Logical Link Status */
207 #define NTWK_LOGICAL_LINK_DOWN 0
208 #define NTWK_LOGICAL_LINK_UP 1
209
210 /* Rx filter bits */
211 #define NTWK_RX_FILTER_IP_CKSUM 0x1
212 #define NTWK_RX_FILTER_TCP_CKSUM 0x2
213 #define NTWK_RX_FILTER_UDP_CKSUM 0x4
214 #define NTWK_RX_FILTER_STRIP_CRC 0x8
215
216 /* driver_function_capabilities */
217 #define DRVFN_CAPAB_SW_TIMESTAMPS 0x2
218 #define DRVFN_CAPAB_BE3_NATIVE 0x4
219
220 /* Function Capabilities */
221 #define BE_FUNCTION_CAPS_UNCLASSIFIED_STATS 0x1
222 #define BE_FUNCTION_CAPS_RSS 0x2
223 #define BE_FUNCTION_CAPS_PROMISCUOUS 0x4
224 #define BE_FUNCTION_CAPS_LEGACY_MODE 0x8
225
226 /* max SGE per mbx */
227 #define MAX_MBX_SGE 19
228
229 /* max RSS rings */
230 #define MAX_RING_PER_GROUP_LEGACY 5
231 #define MAX_RING_PER_GROUP_NATIVE 16
232
233 /* MCCQ LEN */
234 #define MCC_Q_LEN 128
235 #define MCC_CQ_LEN 256
236
237 /* RSS PARAMETERS */
238 #define MAX_TBL_SIZE 64
239 #define MAX_HKEY_SIZE 40
240
241 /* ULP */
242 #define BE_ULP1_NUM 1
243
244 /* physical address structure to be used in MBX */
245 struct phys_addr {
246 /* dw0 */
247 uint32_t lo;
248 /* dw1 */
249 uint32_t hi;
250 };
251
252 typedef union pcicfg_intr_ctl_u {
253 uint32_t dw0;
254 struct {
255 #ifdef _BIG_ENDIAN
256 uint32_t winselect:2;
257 uint32_t hostintr:1;
258 uint32_t pfnum:3;
259 uint32_t vf_cev_int_line_en:1;
260 uint32_t winaddr:23;
261 uint32_t membarwinen:1;
262 #else
263 uint32_t membarwinen:1;
432 uint32_t num_posted:14;
433 uint32_t rsvd0:6;
434 uint32_t qid:10;
435 #else
436 uint32_t qid:10;
437 uint32_t rsvd0:6;
438 uint32_t num_posted:14;
439 uint32_t rsvd1:2;
440 #endif
441 }bits;
442 }pd_txulp_db_t;
443
444 /* CQ doorbell */
445 typedef union cq_db_u {
446 uint32_t dw0;
447 struct {
448 #ifdef _BIG_ENDIAN
449 uint32_t rsvd1:2;
450 uint32_t rearm:1;
451 uint32_t num_popped:13;
452 uint32_t eq_cq_extid:5;
453 uint32_t event:1;
454 uint32_t qid:10;
455 #else
456 uint32_t qid:10;
457 uint32_t event:1;
458 uint32_t eq_cq_extid:5;
459 uint32_t num_popped:13;
460 uint32_t rearm:1;
461 uint32_t rsvd1:2;
462 #endif
463 }bits;
464 }cq_db_t;
465
466 /* EQ doorbell */
467 typedef union eq_db_u {
468 uint32_t dw0;
469 struct {
470 #ifdef _BIG_ENDIAN
471 uint32_t rsvd1:2;
472 uint32_t rearm:1;
473 uint32_t num_popped:13;
474 uint32_t eq_cq_extid:5;
475 uint32_t event:1;
476 uint32_t clrint:1;
477 uint32_t qid:9;
478 #else
479 uint32_t qid:9;
480 uint32_t clrint:1;
481 uint32_t event:1;
482 uint32_t eq_cq_extid:5;
483 uint32_t num_popped:13;
484 uint32_t rearm:1;
485 uint32_t rsvd1:2;
486 #endif
487 }bits;
488 }eq_db_t;
489
490 /* bootstrap mbox doorbell */
491 typedef union pd_mpu_mbox_db_u {
492 uint32_t dw0;
493 struct {
494 #ifdef _BIG_ENDIAN
495 uint32_t address:30;
496 uint32_t hi:1;
497 uint32_t ready:1;
498 #else
499 uint32_t ready:1;
500 uint32_t hi:1;
501 uint32_t address:30;
502 #endif
576 uint32_t sge_count : 5;
577 uint32_t rsvd0 : 2;
578 uint32_t embedded : 1;
579 #else
580 uint32_t embedded:1;
581 uint32_t rsvd0:2;
582 uint32_t sge_count:5;
583 uint32_t rsvd1:16;
584 uint32_t special:8;
585 #endif
586 }s;
587 uint32_t dw0;
588 }u0;
589
590 uint32_t payload_length;
591 uint32_t tag[2];
592 uint32_t rsvd2[1];
593 struct oce_mbx_payload payload;
594 };
595
596 #define MQ_CQE_VALID_MASK (1 << 31)
597 #define MQ_CQE_ASYNC_MASK (1 << 30)
598 #define MQ_CQE_COMPLETED_MASK (1 << 28)
599 #define MQ_CQE_CONSUMED_MASK (1 << 27)
600 #define MQ_CQE_VALID(_cqe) (_cqe->u0.dw[3])
601 #define MQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0)
602
603 /* Macros for handling extra bytes in EQ-CQ IDs */
604 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
605 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1)
606 /*
607 * qid bits 10-14
608 * placing at 11-15
609 */
610 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
611 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
612
613 /* completion queue entry for MQ */
614 struct oce_mq_cqe {
615 union {
616 struct {
617 #ifdef _BIG_ENDIAN
618 /* dw0 */
619 uint32_t extended_status:16;
620 uint32_t completion_status:16;
621 /* dw1 dw2 */
622 uint32_t mq_tag[2];
623 /* dw3 */
624 uint32_t valid:1;
625 uint32_t async_event:1;
626 uint32_t rsvd:1;
627 uint32_t completed:1;
628 uint32_t consumed:1;
629 uint32_t rsvd0:27;
630 #else
631 /* dw0 */
632 uint32_t completion_status:16;
633 uint32_t extended_status:16;
634 /* dw1 dw2 */
635 uint32_t mq_tag[2];
636 /* dw3 */
637 uint32_t rsvd0:27;
638 uint32_t consumed:1;
639 uint32_t completed:1;
640 uint32_t rsvd:1;
641 uint32_t async_event:1;
642 uint32_t valid:1;
643 #endif
644 }s;
645 uint32_t dw[4];
646 }u0;
647 };
648
649 struct oce_async_event_trailer {
650 union {
651 struct {
652 #ifdef _BIG_ENDIAN
653 uint32_t valid:1;
654 uint32_t async_event:1;
655 uint32_t rsvd2:6;
656 uint32_t event_type:8;
657 uint32_t event_code:8;
658 uint32_t rsvd1:8;
659 #else
660 uint32_t rsvd1:8;
661 uint32_t event_code:8;
662 uint32_t event_type:8;
663 uint32_t rsvd2:6;
664 uint32_t async_event:1;
665 uint32_t valid:1;
666 #endif
667 } bits;
668 uint32_t code;
669 } u0;
670 };
671
672
673 /* Async Debug Event Types */
674 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
675
676 struct async_event_qnq {
677 uint8_t enabled;
678 uint8_t rsvd0;
679 uint16_t vlan_tag;
680 uint32_t event_tag;
681 uint32_t rsvd1[1];
682 struct oce_async_event_trailer trailer;
683 };
684
685
686 struct oce_async_cqe_link_state {
687 uint8_t phy_port;
688 uint8_t link_status;
689 uint8_t duplex;
690 uint8_t speed;
691 uint8_t fault;
692 uint8_t reason;
693 uint16_t qos_link_speed;
694 uint32_t event_tag;
695 struct oce_async_event_trailer trailer;
696 };
697
698 struct oce_async_event_grp5_qos_link_speed {
699 uint8_t physical_port;
700 uint8_t rsvd[5];
701 uint16_t qos_link_speed;
702 uint32_t event_tag;
703 struct oce_async_event_trailer trailer;
704 };
705
706
707 struct oce_async_event_grp5_cos_priority {
708 uint8_t physical_port;
709 uint8_t available_priority_bmap;
710 uint8_t reco_default_priority;
711 uint8_t valid;
712 uint8_t rsvd0;
713 uint32_t event_tag;
714 struct oce_async_event_trailer trailer;
715 };
716
717 struct oce_async_event_grp5_pvid_state {
718 uint8_t enabled;
719 uint8_t rsvd0;
720 uint16_t tag;
721 uint32_t event_tag;
722 uint32_t rsvd1;
723 struct oce_async_event_trailer trailer;
724 };
725
726 struct oce_event_grp_5_priority_class_queue_map {
727 uint8_t priority0_classq;
728 uint8_t priority1_classq;
729 uint8_t priority2_classq;
730 uint8_t priority3_classq;
731 uint8_t priority4_classq;
732 uint8_t priority5_classq;
733 uint8_t priority6_classq;
734 uint8_t priority7_classq;
735 uint32_t event_tag;
736 struct oce_async_event_trailer trailer;
737 };
738
739
740 /* MQ mailbox structure */
741 struct oce_bmbx {
742 struct oce_mbx mbx;
743 struct oce_mq_cqe cqe;
744 };
745
746 /* ---[ MBXs start here ]---------------------------------------------- */
747 /* MBXs sub system codes */
748 enum {
749 MBX_SUBSYSTEM_RSVD = 0,
750 MBX_SUBSYSTEM_COMMON = 1,
751 MBX_SUBSYSTEM_COMMON_ISCSI = 2,
752 MBX_SUBSYSTEM_NIC = 3,
753 MBX_SUBSYSTEM_TOE = 4,
754 MBX_SUBSYSTEM_PXE_UNDI = 5,
755 MBX_SUBSYSTEM_ISCSI_INI = 6,
756 MBX_SUBSYSTEM_ISCSI_TGT = 7,
757 MBX_SUBSYSTEM_MILI_PTL = 8,
758 MBX_SUBSYSTEM_MILI_TMD = 9,
759 MBX_SUBSYSTEM_RDMA = 10,
760 MBX_SUBSYSTEM_LOWLEVEL = 11,
761 MBX_SUBSYSTEM_LRO = 13,
762 IOCBMBX_SUBSYSTEM_DCBX = 15,
763 IOCBMBX_SUBSYSTEM_DIAG = 16,
764 IOCBMBX_SUBSYSTEM_VENDOR = 17
765 };
766
767 /* common ioctl opcodes */
768 enum {
769 OPCODE_QUERY_COMMON_IFACE_MAC = 1,
770 OPCODE_SET_COMMON_IFACE_MAC = 2,
771 OPCODE_SET_COMMON_IFACE_MULTICAST = 3,
772 OPCODE_COMMON_NTWK_VLAN_CONFIG = 4,
773 OPCODE_QUERY_COMMON_LINK_STATUS = 5,
774 OPCODE_READ_COMMON_FLASHROM = 6,
775 OPCODE_WRITE_COMMON_FLASHROM = 7,
776 OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8,
777 OPCODE_ADD_COMMON_PAGE_TABLES = 9,
778 OPCODE_REMOVE_COMMON_PAGE_TABLES = 10,
779 OPCODE_CREATE_COMMON_CQ = 12,
780 OPCODE_CREATE_COMMON_EQ = 13,
781 OPCODE_CREATE_COMMON_MQ = 21,
782 OPCODE_COMMON_JELL_CONFIG = 22,
783 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24,
784 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25,
785 OPCODE_COMMON_POST_ZERO_BUFFER = 26,
786 OPCODE_COMMON_GET_QOS = 27,
787 OPCODE_COMMON_SET_QOS = 28,
788 OPCODE_COMMON_TCP_GET_STATISTICS = 29,
789 OPCODE_READ_COMMON_SEEPROM = 30,
790 OPCODE_COMMON_TCP_STATE_QUERY = 31,
791 OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32,
792 OPCODE_COMMON_NOP = 33,
799 OPCODE_COMMON_GET_FAT = 40,
800 OPCODE_MODIFY_COMMON_EQ_DELAY = 41,
801 OPCODE_COMMON_FIRMWARE_CONFIG = 42,
802 OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43,
803 OPCODE_COMMON_GET_DOMAIN_CONFIG = 44,
804 OPCODE_COMMON_GET_PORT_EQUALIZATION = 47,
805 OPCODE_COMMON_SET_PORT_EQUALIZATION = 48,
806 OPCODE_COMMON_RED_CONFIG = 49,
807 OPCODE_CREATE_COMMON_IFACE = 50,
808 OPCODE_DESTROY_COMMON_IFACE = 51,
809 OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52,
810 OPCODE_DESTROY_COMMON_MQ = 53,
811 OPCODE_DESTROY_COMMON_CQ = 54,
812 OPCODE_DESTROY_COMMON_EQ = 55,
813 OPCODE_COMMON_TCP_UPL_OAD = 56,
814 OPCODE_SET_COMMON_LINK_SPEED = 57,
815 OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58,
816 OPCODE_ADD_COMMON_IFACE_MAC = 59,
817 OPCODE_DEL_COMMON_IFACE_MAC = 60,
818 OPCODE_COMMON_FUNCTION_RESET = 61,
819 OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80,
820 OPCODE_CREATE_COMMON_MQ_EXT = 90,
821 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAPABILITIES = 103
822 };
823
824 /* Management status error code in Response header */
825 enum {
826 MGMT_STATUS_SUCCESS = 0, /* The IOCTL completed without errors. */
827 MGMT_STATUS_FAILED = 1, /* Generic error status */
828 MGMT_STATUS_ILLEGAL_REQUEST = 2, /* Invalid IOCTL opcode. */
829 MGMT_STATUS_ILLEGAL_FIELD = 3, /* Invalid param in IOCTL pyld */
830 MGMT_STATUS_INSUFFICIENT_BUFFER = 4, /* Insufficient buf for response */
831 MGMT_STATUS_UNAUTHORIZED_REQUEST = 5 /* Domain invalid access rights */
832 };
833
834 /* Additional status error codes */
835 enum {
836 MGMT_ADDI_STATUS_NO_STATUS = 0, /* IOCTL completed successfully */
837 MGMT_ADDI_STATUS_INVALID_SUBSYSTEM = 29, /* Invalid subsystem id */
838 MGMT_ADDI_STATUS_INVALID_OPCODE = 30, /* Opcode Invalid */
839 MGMT_ADDI_STATUS_INVALID_DOMAIN = 35, /* Invalid domain id */
840 MGMT_ADDI_STATUS_INVALID_EXTENDED_TIMEOUT = 64 /* Invalid timeout */
841 };
842
843 /* common ioctl header */
844 struct mbx_hdr {
845 union {
846 struct {
847 #ifdef _BIG_ENDIAN
848 uint8_t domain;
849 uint8_t port_number;
850 uint8_t subsystem;
851 uint8_t opcode;
852 uint32_t timeout;
853 uint32_t request_length;
854 uint8_t rsvd0[3];
855 uint8_t version;
856 #else
857 uint8_t opcode;
858 uint8_t subsystem;
859 uint8_t port_number;
860 uint8_t domain;
861 uint32_t timeout;
862 uint32_t request_length;
863 uint8_t version;
864 uint8_t rsvd0[3];
865 #endif
866 }req;
867
868 struct {
869 /* dw 0 */
870 uint8_t opcode;
871 uint8_t subsystem;
872 uint8_t rsvd0;
873 uint8_t domain;
874 /* dw 1 */
875 uint8_t status;
876 uint8_t additional_status;
877 uint16_t rsvd1;
878
879 uint32_t rsp_length;
880 uint32_t actual_rsp_length;
881 }rsp;
882 uint32_t dw[4];
883 }u0;
884 };
885 #define OCE_BMBX_RHDR_SZ 20
886 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
887 #define OCE_MBX_ADDL_STATUS(_MHDR) \
888 (((struct mbx_hdr *)_MHDR)->u0.rsp.additional_status)
889 #define OCE_MBX_STATUS(_MHDR) (((struct mbx_hdr *)_MHDR)->u0.rsp.status)
890
891 /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */
892 struct mbx_query_common_link_status {
893 struct mbx_hdr hdr;
894 union {
895 struct {
896 uint32_t rsvd0;
897 }req;
898
899 struct {
900 /* dw 0 */
901 uint8_t physical_port;
902 uint8_t mac_duplex;
903 uint8_t mac_speed;
904 uint8_t mac_fault;
905 /* dw 1 */
906 uint8_t mgmt_mac_duplex;
907 uint8_t mgmt_mac_speed;
908 uint16_t qos_link_speed;
909 uint32_t logical_link_status;
1059 uint32_t dw[4];
1060 }params;
1061 };
1062
1063 /* [51] OPCODE_DESTROY_COMMON_IFACE */
1064 struct mbx_destroy_common_iface {
1065 struct mbx_hdr hdr;
1066 union {
1067 struct {
1068 uint32_t if_id;
1069 }req;
1070
1071 struct {
1072 uint32_t rsvd0;
1073 }rsp;
1074
1075 uint32_t dw;
1076 }params;
1077 };
1078
1079 struct mbx_set_common_iface_rx_filter {
1080 struct mbx_hdr hdr;
1081 union {
1082 struct {
1083 uint32_t gflags_mask;
1084 uint32_t gflags;
1085 uint32_t if_flags_mask;
1086 uint32_t if_flags;
1087 uint32_t if_id;
1088 uint32_t multicast_num;
1089 struct ether_addr mac[32];
1090 }req;
1091 struct {
1092 uint32_t gflags_mask;
1093 uint32_t gflags;
1094 uint32_t if_flags_mask;
1095 uint32_t if_flags;
1096 uint32_t if_id;
1097 uint32_t multicast_num;
1098 struct ether_addr mac[32];
1099 }rsp;
1100 }params;
1101 };
1102
1103 /* event queue context structure */
1104 struct oce_eq_ctx {
1105 #ifdef _BIG_ENDIAN
1106 /* dw0 */
1107 uint32_t size:1;
1108 uint32_t rsvd1:1;
1109 uint32_t valid:1;
1110 uint32_t epidx:13;
1111 uint32_t rsvd0:3;
1112 uint32_t cidx:13;
1113
1114 /* dw1 */
1115 uint32_t armed:1;
1116 uint32_t stalled:1;
1117 uint32_t sol_event:1;
1118 uint32_t count:3;
1119 uint32_t pd:10;
1120 uint32_t rsvd2:3;
1121 uint32_t pidx:13;
1122
1149 uint32_t sol_event:1;
1150 uint32_t stalled:1;
1151 uint32_t armed:1;
1152
1153 /* dw2 */
1154 uint32_t rsvd3:4;
1155 uint32_t function:8;
1156 uint32_t rsvd4:1;
1157 uint32_t delay_mult:10;
1158 uint32_t rsvd5:2;
1159 uint32_t phase:2;
1160 uint32_t nodelay:1;
1161 uint32_t rsvd6:4;
1162
1163 /* dw3 */
1164 uint32_t rsvd7;
1165 #endif
1166 };
1167
1168 /* [13] OPCODE_CREATE_COMMON_EQ */
1169 struct mbx_create_common_eq {
1170 struct mbx_hdr hdr;
1171 union {
1172 struct {
1173 #ifdef _BIG_ENDIAN
1174 uint16_t rsvd0;
1175 uint16_t num_pages;
1176 #else
1177 uint16_t num_pages;
1178 uint16_t rsvd0;
1179 #endif
1180 struct oce_eq_ctx eq_ctx;
1181 struct phys_addr pages[8];
1182 }req;
1183
1184 struct {
1185 uint16_t eq_id;
1186 uint16_t rsvd0;
1187 }rsp;
1188 }params;
1189 };
1191 /* [55] OPCODE_DESTROY_COMMON_EQ */
1192 struct mbx_destroy_common_eq {
1193 struct mbx_hdr hdr;
1194 union {
1195 struct {
1196 #ifdef _BIG_ENDIAN
1197 uint16_t rsvd0;
1198 uint16_t id;
1199 #else
1200 uint16_t id;
1201 uint16_t rsvd0;
1202 #endif
1203 }req;
1204
1205 struct {
1206 uint32_t rsvd0;
1207 }rsp;
1208 }params;
1209 };
1210
1211 struct oce_cq_ctx_v0 {
1212 #ifdef _BIG_ENDIAN
1213 /* dw0 */
1214 uint32_t eventable:1;
1215 uint32_t sol_event:1;
1216 uint32_t valid:1;
1217 uint32_t count:2;
1218 uint32_t rsvd1:1;
1219 uint32_t epidx:11;
1220 uint32_t nodelay:1;
1221 uint32_t coalesce_wm:2;
1222 uint32_t rsvd0:1;
1223 uint32_t cidx:11;
1224
1225 /* dw1 */
1226 uint32_t armed:1;
1227 uint32_t stalled:1;
1228 uint32_t eq_id:8;
1229 uint32_t pd:10;
1230 uint32_t rsvd2:1;
1231 uint32_t pidx:11;
1246 uint32_t valid:1;
1247 uint32_t sol_event:1;
1248 uint32_t eventable:1;
1249
1250 /* dw1 */
1251 uint32_t pidx:11;
1252 uint32_t rsvd2:1;
1253 uint32_t pd:10;
1254 uint32_t eq_id:8;
1255 uint32_t stalled:1;
1256 uint32_t armed:1;
1257
1258 /* dw2 */
1259 uint32_t rsvd3:4;
1260 uint32_t function:8;
1261 uint32_t rsvd4:20;
1262 #endif
1263 uint32_t rsvd5;
1264 };
1265
1266 /* [12] OPCODE_CREATE_COMMON_CQ V0 */
1267 struct mbx_create_common_cq_v0 {
1268 struct mbx_hdr hdr;
1269 union {
1270 struct {
1271 #ifdef _BIG_ENDIAN
1272 uint16_t rsvd0;
1273 uint16_t num_pages;
1274 #else
1275 uint16_t num_pages;
1276 uint16_t rsvd0;
1277 #endif
1278 struct oce_cq_ctx_v0 cq_ctx;
1279 struct phys_addr pages[4];
1280 }req;
1281
1282 struct {
1283 uint16_t cq_id;
1284 uint16_t rsvd0;
1285 }rsp;
1286 }params;
1287 };
1288
1289 struct oce_cq_ctx_v2 {
1290 #ifdef _BIG_ENDIAN
1291 /* dw0 */
1292 uint32_t eventable:1;
1293 uint32_t rsvd2:1;
1294 uint32_t valid:1;
1295 uint32_t count:2;
1296 uint32_t rsvd1:11;
1297 uint32_t auto_valid:1;
1298 uint32_t nodelay:1;
1299 uint32_t coalesce_wm:2;
1300 uint32_t rsvd0:12;
1301
1302 /* dw1 */
1303 uint32_t armed:1;
1304 uint32_t rsvd3:15;
1305 uint32_t eq_id:16;
1306
1307 /* dw2 */
1308 uint32_t rsvd4:16;
1309 uint32_t cqe_count:16;
1310 #else
1311 /* dw0 */
1312 uint32_t rsvd0:12;
1313 uint32_t coalesce_wm:2;
1314 uint32_t nodelay:1;
1315 uint32_t auto_valid:1;
1316 uint32_t rsvd1:11;
1317 uint32_t count:2;
1318 uint32_t valid:1;
1319 uint32_t rsvd2:1;
1320 uint32_t eventable:1;
1321
1322 /* dw1 */
1323 uint32_t eq_id:16;
1324 uint32_t rsvd3:15;
1325 uint32_t armed:1;
1326
1327 /* dw2 */
1328 uint32_t cqe_count:16;
1329 uint32_t rsvd4:16;
1330 #endif
1331 uint32_t rsvd5;
1332 };
1333
1334 /* [12] OPCODE_CREATE_COMMON_CQ V2 */
1335 struct mbx_create_common_cq_v2 {
1336 struct mbx_hdr hdr;
1337 union {
1338 struct {
1339 #ifdef _BIG_ENDIAN
1340 uint8_t rsvd0;
1341 uint8_t page_size;
1342 uint16_t num_pages;
1343 #else
1344 uint16_t num_pages;
1345 uint8_t page_size;
1346 uint8_t rsvd0;
1347 #endif
1348 struct oce_cq_ctx_v2 cq_ctx;
1349 struct phys_addr pages[8];
1350 }req;
1351
1352 struct {
1353 uint16_t cq_id;
1354 uint16_t rsvd0;
1355 }rsp;
1356 }params;
1357 };
1358
1359 /* [54] OPCODE_DESTROY_COMMON_CQ */
1360 struct mbx_destroy_common_cq {
1361 struct mbx_hdr hdr;
1362 union {
1363 struct {
1364 #ifdef _BIG_ENDIAN
1365 uint16_t rsvd0;
1366 uint16_t id;
1367 #else
1368 uint16_t id;
1369 uint16_t rsvd0;
1370 #endif
1371 }req;
1372
1373 struct {
1374 uint32_t rsvd0;
1375 }rsp;
1376 }params;
1377 };
1378
1379 struct mq_ring_ctx_v0 {
1380 union {
1381 struct {
1382 #ifdef _BIG_ENDIAN
1383 /* dw 0 */
1384 uint32_t cq_id:10;
1385 uint32_t fetch_r2t:1;
1386 uint32_t fetch_wrb:1;
1387 uint32_t ring_size:4;
1388 uint32_t rsvd0:2;
1389 uint32_t con_index:14;
1390
1391 /* dw1 */
1392 uint32_t valid:1;
1393 uint32_t pdid:9;
1394 uint32_t fid:8;
1395 uint32_t prod_index:14;
1396
1397 /* dw 2 */
1398 uint32_t rsvd1:21;
1399 uint32_t async_cq_id:10;
1408 uint32_t cq_id:10;
1409
1410 /* dw1 */
1411 uint32_t prod_index:14;
1412 uint32_t fid:8;
1413 uint32_t pdid:9;
1414 uint32_t valid:1;
1415
1416 /* dw 2 */
1417 uint32_t async_cq_valid:1;
1418 uint32_t async_cq_id:10;
1419 uint32_t rsvd1:21;
1420 #endif
1421 /* dw3 */
1422 uint32_t rsvd3;
1423 }s;
1424 uint32_t dw[4];
1425 }u0;
1426 };
1427
1428 /* [21] OPCODE_CREATE_COMMON_MQ V0 */
1429 struct mbx_create_common_mq {
1430 struct mbx_hdr hdr;
1431 union {
1432 struct {
1433 #ifdef _BIG_ENDIAN
1434 uint16_t rsvd0;
1435 uint16_t num_pages;
1436 #else
1437 uint16_t num_pages;
1438 uint16_t rsvd0;
1439 #endif
1440 struct mq_ring_ctx_v0 context;
1441 struct phys_addr pages[8];
1442 }req;
1443
1444 struct {
1445 uint32_t mq_id:16;
1446 uint32_t rsvd0:16;
1447 }rsp;
1448 }params;
1449 };
1450
1451 /* [90] OPCODE_COMMON_MCC_CREATE_EXT V0 */
1452 struct mbx_create_common_mq_ext_v0 {
1453 struct mbx_hdr hdr;
1454 union {
1455 struct {
1456 #ifdef _BIG_ENDIAN
1457 uint16_t rsvd0;
1458 uint16_t num_pages;
1459 #else
1460 uint16_t num_pages;
1461 uint16_t rsvd0;
1462 #endif
1463 uint32_t async_event_bitmap[1];
1464 struct mq_ring_ctx_v0 context;
1465 struct phys_addr pages[8];
1466 }req;
1467
1468 struct {
1469 uint32_t mq_id:16;
1470 uint32_t rsvd0:16;
1471 }rsp;
1472 }params;
1473 };
1474
1475 struct mq_ring_ctx_v1 {
1476 union {
1477 struct {
1478 #ifdef _BIG_ENDIAN
1479 /* dw 0 */
1480 uint32_t rsrvd0:12;
1481 uint32_t ring_size:4;
1482 uint32_t async_cq_id:16;
1483
1484 /* dw1 */
1485 uint32_t valid:1;
1486 uint32_t rsrvd1:31;
1487
1488 /* dw 2 */
1489 uint32_t rsvd2:31;
1490 uint32_t async_cq_valid:1;
1491 #else
1492 /* dw 0 */
1493 uint32_t async_cq_id:16;
1494 uint32_t ring_size:4;
1495 uint32_t rsrvd0:12;
1496
1497 /* dw1 */
1498 uint32_t rsrvd1:31;
1499 uint32_t valid:1;
1500
1501 /* dw 2 */
1502 uint32_t async_cq_valid:1;
1503 uint32_t rsvd2:31;
1504 #endif
1505 /* dw3 */
1506 uint32_t rsvd3;
1507 }s;
1508 uint32_t dw[4];
1509 }u0;
1510 };
1511
1512 /* [90] OPCODE_COMMON_MCC_CREATE_EXT V1 */
1513 struct mbx_create_common_mq_ext_v1 {
1514 struct mbx_hdr hdr;
1515 union {
1516 struct {
1517 #ifdef _BIG_ENDIAN
1518 uint16_t cq_id;
1519 uint16_t num_pages;
1520 #else
1521 uint16_t num_pages;
1522 uint16_t cq_id;
1523 #endif
1524 uint32_t async_event_bitmap[1];
1525 struct mq_ring_ctx_v1 context;
1526 struct phys_addr pages[8];
1527 }req;
1528
1529 struct {
1530 uint32_t mq_id:16;
1531 uint32_t rsvd0:16;
1532 }rsp;
1533 }params;
1534 };
1535
1536 /* [53] OPCODE_DESTROY_COMMON_MQ */
1537 struct mbx_destroy_common_mq {
1538 struct mbx_hdr hdr;
1539 union {
1540 struct {
1541 #ifdef _BIG_ENDIAN
1542 uint16_t rsvd0;
1543 uint16_t id;
1544 #else
1545 uint16_t id;
1546 uint16_t rsvd0;
1547 #endif
1548 }req;
1549
1550 struct {
1551 uint32_t rsvd0;
1552 }rsp;
1553 }params;
1554 };
1555
1770 } rsp;
1771 };
1772
1773 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1774 struct ioctl_common_function_reset {
1775 struct mbx_hdr hdr;
1776 };
1777
1778 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1779 struct mbx_common_func_link_cfg {
1780 struct mbx_hdr hdr;
1781 union {
1782 struct {
1783 uint32_t enable;
1784 }req;
1785 struct {
1786 uint32_t rsvd0;
1787 }rsp;
1788 } params;
1789 };
1790
1791 /* [103] OPCODE_COMMON_SET_DRIVER_FUNCTION_CAPABILITIES */
1792 struct mbx_common_set_drvfn_capab {
1793 struct mbx_hdr hdr;
1794 union {
1795 struct {
1796 uint32_t valid_capability_flags;
1797 uint32_t capability_flags;
1798 uint8_t sbz[212];
1799 } request;
1800 struct {
1801 uint32_t valid_capability_flags;
1802 uint32_t capability_flags;
1803 uint8_t sbz[212];
1804 } response;
1805 } params;
1806 };
1807
1808 #pragma pack()
1809
1810 #ifdef __cplusplus
1811 }
1812 #endif
1813
1814 #endif /* _OCE_HW_H_ */
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