1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /* Copyright © 2003-2011 Emulex. All rights reserved. */
23
24 /*
25 * Header file containing the command structures for Hardware
26 */
27
28 #ifndef _OCE_HW_H_
29 #define _OCE_HW_H_
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 #include <sys/types.h>
36
37 #pragma pack(1)
38
39 #define OC_CNA_GEN2 0x2
40 #define OC_CNA_GEN3 0x3
41 #define DEVID_TIGERSHARK 0x700
42 #define DEVID_TOMCAT 0x710
43
44 /* PCI CSR offsets */
45 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */
46 #define PCICFG_SEMAPHORE 0xbc
47 #define PCICFG_SOFT_RESET 0x5c
48 #define PCICFG_UE_STATUS_HI_MASK 0xac
49 #define PCICFG_UE_STATUS_LO_MASK 0xa8
50 #define PCICFG_ONLINE0 0xb0
51 #define PCICFG_ONLINE1 0xb4
52 #define INTR_EN 0x20000000
53 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */
54
55 /* CSR register offsets */
56 #define MPU_EP_CONTROL 0
57 #define MPU_EP_SEMAPHORE 0xac
58 #define PCICFG_INTR_CTRL 0xfc
59 #define HOSTINTR_MASK (1 << 29)
60 #define HOSTINTR_PFUNC_SHIFT 26
61 #define HOSTINTR_PFUNC_MASK 7
62
63 /* POST status reg struct */
64 #define POST_STAGE_POWER_ON_RESET 0x00
65 #define POST_STAGE_AWAITING_HOST_RDY 0x01
66 #define POST_STAGE_HOST_RDY 0x02
67 #define POST_STAGE_CHIP_RESET 0x03
68 #define POST_STAGE_ARMFW_READY 0xc000
69 #define POST_STAGE_ARMFW_UE 0xf000
70
71 /* DOORBELL registers */
72 #define PD_RXULP_DB 0x0100
73 #define PD_TXULP_DB 0x0060
74 #define DB_RQ_ID_MASK 0x3FF
75
76 #define PD_CQ_DB 0x0120
77 #define PD_EQ_DB PD_CQ_DB
78 #define PD_MPU_MBOX_DB 0x0160
79 #define PD_MQ_DB 0x0140
80
81 /* EQE completion types */
82 #define EQ_MINOR_CODE_COMPLETION 0x00
83 #define EQ_MINOR_CODE_OTHER 0x01
84 #define EQ_MAJOR_CODE_COMPLETION 0x00
85
86 /* Link Status field values */
87 #define PHY_LINK_FAULT_NONE 0x0
88 #define PHY_LINK_FAULT_LOCAL 0x01
89 #define PHY_LINK_FAULT_REMOTE 0x02
90
91 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */
92 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
93 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
94 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
95 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
96
97 #define PHY_LINK_DUPLEX_NONE 0x0
98 #define PHY_LINK_DUPLEX_HALF 0x1
99 #define PHY_LINK_DUPLEX_FULL 0x2
100
101 #define NTWK_PORT_A 0x0 /* (Port A) */
102 #define NTWK_PORT_B 0x1 /* (Port B) */
103
104 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */
105 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */
106 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */
107 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */
108 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */
109
110 /* Hardware Address types */
111 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */
112 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */
113 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */
114 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */
115 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */
116
117 /* CREATE_IFACE capability and cap_en flags */
118 #define MBX_RX_IFACE_FLAGS_RSS 0x4
119 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
120 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
121 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
122 #define MBX_RX_IFACE_FLAGS_ULP 0x40
123 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
124 #define MBX_RX_IFACE_FLAGS_VLAN 0x100
125 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
126 #define MBX_RX_IFACE_FLAGS_PASS_L2 0x400
127 #define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800
128
129 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */
130 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */
131 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
132 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
133
134
135 #define MBX_DB_READY_BIT 0x1
136 #define MBX_DB_HI_BIT 0x2
137 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
138 #define ASYNC_EVENT_LINK_UP 0x1
139 #define ASYNC_EVENT_LINK_DOWN 0x0
140
141 /* port link_status */
142 #define ASYNC_EVENT_LOGICAL 0x02
143
144 /* Logical Link Status */
145 #define NTWK_LOGICAL_LINK_DOWN 0
146 #define NTWK_LOGICAL_LINK_UP 1
147
148 /* Rx filter bits */
149 #define NTWK_RX_FILTER_IP_CKSUM 0x1
150 #define NTWK_RX_FILTER_TCP_CKSUM 0x2
151 #define NTWK_RX_FILTER_UDP_CKSUM 0x4
152 #define NTWK_RX_FILTER_STRIP_CRC 0x8
153
154 /* max SGE per mbx */
155 #define MAX_MBX_SGE 19
156
157 /* physical address structure to be used in MBX */
158 struct phys_addr {
159 /* dw0 */
160 uint32_t lo;
161 /* dw1 */
162 uint32_t hi;
163 };
164
165 typedef union pcicfg_intr_ctl_u {
166 uint32_t dw0;
167 struct {
168 #ifdef _BIG_ENDIAN
169 uint32_t winselect:2;
170 uint32_t hostintr:1;
171 uint32_t pfnum:3;
172 uint32_t vf_cev_int_line_en:1;
173 uint32_t winaddr:23;
174 uint32_t membarwinen:1;
175 #else
176 uint32_t membarwinen:1;
177 uint32_t winaddr:23;
178 uint32_t vf_cev_int_line_en:1;
179 uint32_t pfnum:3;
180 uint32_t hostintr:1;
181 uint32_t winselect:2;
182 #endif
183 } bits;
184 }pcicfg_intr_ctl_t;
185
186 typedef union pcicfg_semaphore_u {
187 uint32_t dw0;
188 struct {
189 #ifdef _BIG_ENDIAN
190 uint32_t rsvd:31;
191 uint32_t lock:1;
192 #else
193 uint32_t lock:1;
194 uint32_t rsvd:31;
195 #endif
196 }bits;
197 }pcicfg_semaphore_t;
198
199 typedef union pcicfg_soft_reset_u {
200 uint32_t dw0;
201 struct {
202 #ifdef _BIG_ENDIAN
203 uint32_t nec_ll_rcvdetect:8;
204 uint32_t dbg_all_reqs_62_49:14;
205 uint32_t scratchpad0:1;
206 uint32_t exception_oe:1;
207 uint32_t soft_reset:1;
208 uint32_t rsvd0:7;
209 #else
210 uint32_t rsvd0:7;
211 uint32_t soft_reset:1;
212 uint32_t exception_oe:1;
213 uint32_t scratchpad0:1;
214 uint32_t dbg_all_reqs_62_49:14;
215 uint32_t nec_ll_rcvdetect:8;
216 #endif
217 }bits;
218 }pcicfg_soft_reset_t;
219
220 typedef union pcicfg_online1_u {
221 uint32_t dw0;
222 struct {
223 #ifdef _BIG_ENDIAN
224 uint32_t host8_online:1;
225 uint32_t host7_online:1;
226 uint32_t host6_online:1;
227 uint32_t host5_online:1;
228 uint32_t host4_online:1;
229 uint32_t host3_online:1;
230 uint32_t host2_online:1;
231 uint32_t ipc_online:1;
232 uint32_t arm_online:1;
233 uint32_t txp_online:1;
234 uint32_t xaui_online:1;
235 uint32_t rxpp_online:1;
236 uint32_t txpb_online:1;
237 uint32_t rr_online:1;
238 uint32_t pmem_online:1;
239 uint32_t pctl1_online:1;
240 uint32_t pctl0_online:1;
241 uint32_t pcs1online_online:1;
242 uint32_t mpu_iram_online:1;
243 uint32_t pcs0online_online:1;
244 uint32_t mgmt_mac_online:1;
245 uint32_t lpcmemhost_online:1;
246 #else
247 uint32_t lpcmemhost_online:1;
248 uint32_t mgmt_mac_online:1;
249 uint32_t pcs0online_online:1;
250 uint32_t mpu_iram_online:1;
251 uint32_t pcs1online_online:1;
252 uint32_t pctl0_online:1;
253 uint32_t pctl1_online:1;
254 uint32_t pmem_online:1;
255 uint32_t rr_online:1;
256 uint32_t txpb_online:1;
257 uint32_t rxpp_online:1;
258 uint32_t xaui_online:1;
259 uint32_t txp_online:1;
260 uint32_t arm_online:1;
261 uint32_t ipc_online:1;
262 uint32_t host2_online:1;
263 uint32_t host3_online:1;
264 uint32_t host4_online:1;
265 uint32_t host5_online:1;
266 uint32_t host6_online:1;
267 uint32_t host7_online:1;
268 uint32_t host8_online:1;
269 #endif
270 }bits;
271 }pcicfg_online1_t;
272
273 typedef union mpu_ep_semaphore_u {
274 uint32_t dw0;
275 struct {
276 #ifdef _BIG_ENDIAN
277 uint32_t error:1;
278 uint32_t backup_fw:1;
279 uint32_t iscsi_no_ip:1;
280 uint32_t iscsi_ip_conflict:1;
281 uint32_t option_rom_installed:1;
282 uint32_t iscsi_drv_loaded:1;
283 uint32_t rsvd0:10;
284 uint32_t stage:16;
285 #else
286 uint32_t stage:16;
287 uint32_t rsvd0:10;
288 uint32_t iscsi_drv_loaded:1;
289 uint32_t option_rom_installed:1;
290 uint32_t iscsi_ip_conflict:1;
291 uint32_t iscsi_no_ip:1;
292 uint32_t backup_fw:1;
293 uint32_t error:1;
294 #endif
295 }bits;
296 }mpu_ep_semaphore_t;
297
298 typedef union mpu_ep_control_u {
299 uint32_t dw0;
300 struct {
301 #ifdef _BIG_ENDIAN
302 uint32_t cpu_reset:1;
303 uint32_t rsvd1:15;
304 uint32_t ep_ram_init_status:1;
305 uint32_t rsvd0:12;
306 uint32_t m2_rxpbuf:1;
307 uint32_t m1_rxpbuf:1;
308 uint32_t m0_rxpbuf:1;
309 #else
310 uint32_t m0_rxpbuf:1;
311 uint32_t m1_rxpbuf:1;
312 uint32_t m2_rxpbuf:1;
313 uint32_t rsvd0:12;
314 uint32_t ep_ram_init_status:1;
315 uint32_t rsvd1:15;
316 uint32_t cpu_reset:1;
317 #endif
318 }bits;
319 }mpu_ep_control_t;
320
321 /* RX doorbell */
322 typedef union pd_rxulp_db_u {
323 uint32_t dw0;
324 struct {
325 #ifdef _BIG_ENDIAN
326 uint32_t num_posted:8;
327 uint32_t invalidate:1;
328 uint32_t rsvd1:13;
329 uint32_t qid:10;
330 #else
331 uint32_t qid:10;
332 uint32_t rsvd1:13;
333 uint32_t invalidate:1;
334 uint32_t num_posted:8;
335 #endif
336 }bits;
337 }pd_rxulp_db_t;
338
339 /* TX doorbell */
340 typedef union pd_txulp_db_u {
341 uint32_t dw0;
342 struct {
343 #ifdef _BIG_ENDIAN
344 uint32_t rsvd1:2;
345 uint32_t num_posted:14;
346 uint32_t rsvd0:6;
347 uint32_t qid:10;
348 #else
349 uint32_t qid:10;
350 uint32_t rsvd0:6;
351 uint32_t num_posted:14;
352 uint32_t rsvd1:2;
353 #endif
354 }bits;
355 }pd_txulp_db_t;
356
357 /* CQ doorbell */
358 typedef union cq_db_u {
359 uint32_t dw0;
360 struct {
361 #ifdef _BIG_ENDIAN
362 uint32_t rsvd1:2;
363 uint32_t rearm:1;
364 uint32_t num_popped:13;
365 uint32_t rsvd0:5;
366 uint32_t event:1;
367 uint32_t qid:10;
368 #else
369 uint32_t qid:10;
370 uint32_t event:1;
371 uint32_t rsvd0:5;
372 uint32_t num_popped:13;
373 uint32_t rearm:1;
374 uint32_t rsvd1:2;
375 #endif
376 }bits;
377 }cq_db_t;
378
379 /* EQ doorbell */
380 typedef union eq_db_u {
381 uint32_t dw0;
382 struct {
383 #ifdef _BIG_ENDIAN
384 uint32_t rsvd1:2;
385 uint32_t rearm:1;
386 uint32_t num_popped:13;
387 uint32_t rsvd0:5;
388 uint32_t event:1;
389 uint32_t clrint:1;
390 uint32_t qid:9;
391 #else
392 uint32_t qid:9;
393 uint32_t clrint:1;
394 uint32_t event:1;
395 uint32_t rsvd0:5;
396 uint32_t num_popped:13;
397 uint32_t rearm:1;
398 uint32_t rsvd1:2;
399 #endif
400 }bits;
401 }eq_db_t;
402
403 /* bootstrap mbox doorbell */
404 typedef union pd_mpu_mbox_db_u {
405 uint32_t dw0;
406 struct {
407 #ifdef _BIG_ENDIAN
408 uint32_t address:30;
409 uint32_t hi:1;
410 uint32_t ready:1;
411 #else
412 uint32_t ready:1;
413 uint32_t hi:1;
414 uint32_t address:30;
415 #endif
416 }bits;
417 }pd_mpu_mbox_db_t;
418
419
420 /* MQ ring doorbell */
421 typedef union pd_mq_db_u {
422 uint32_t dw0;
423 struct {
424 #ifdef _BIG_ENDIAN
425 uint32_t rsvd1:2;
426 uint32_t num_posted:14;
427 uint32_t rsvd0:5;
428 uint32_t mq_id:11;
429 #else
430 uint32_t mq_id:11;
431 uint32_t rsvd0:5;
432 uint32_t num_posted:14;
433 uint32_t rsvd1:2;
434 #endif
435 }bits;
436 }pd_mq_db_t;
437
438 /*
439 * Event Queue Entry
440 */
441 struct oce_eqe {
442 union {
443 struct {
444 #ifdef _BIG_ENDIAN
445 uint32_t resource_id:16;
446 uint32_t minor_code:12;
447 uint32_t major_code:3;
448 uint32_t valid:1;
449 #else
450 uint32_t valid:1;
451 uint32_t major_code:3;
452 uint32_t minor_code:12;
453 uint32_t resource_id:16;
454 #endif
455 }s;
456 uint32_t dw0;
457 }u0;
458 };
459
460 /* MQ scatter gather entry. Array of these make an SGL */
461 struct oce_mq_sge {
462 uint32_t pa_lo;
463 uint32_t pa_hi;
464 uint32_t length;
465 };
466
467 /*
468 * payload can contain an SGL or an embedded array of upto 59 dwords
469 */
470 struct oce_mbx_payload {
471 union {
472 union {
473 struct oce_mq_sge sgl[MAX_MBX_SGE];
474 uint32_t embedded[59];
475 }u1;
476 uint32_t dw[59];
477 }u0;
478 };
479
480 /*
481 * MQ MBX structure
482 */
483 struct oce_mbx {
484 union {
485 struct {
486 #ifdef _BIG_ENDIAN
487 uint32_t special : 8;
488 uint32_t rsvd1 : 16;
489 uint32_t sge_count : 5;
490 uint32_t rsvd0 : 2;
491 uint32_t embedded : 1;
492 #else
493 uint32_t embedded:1;
494 uint32_t rsvd0:2;
495 uint32_t sge_count:5;
496 uint32_t rsvd1:16;
497 uint32_t special:8;
498 #endif
499 }s;
500 uint32_t dw0;
501 }u0;
502
503 uint32_t payload_length;
504 uint32_t tag[2];
505 uint32_t rsvd2[1];
506 struct oce_mbx_payload payload;
507 };
508
509 /* completion queue entry for MQ */
510 struct oce_mq_cqe {
511 union {
512 struct {
513 #ifdef _BIG_ENDIAN
514 /* dw0 */
515 uint32_t extended_status:16;
516 uint32_t completion_status:16;
517 /* dw1 dw2 */
518 uint32_t mq_tag[2];
519 /* dw3 */
520 uint32_t valid:1;
521 uint32_t async_event:1;
522 uint32_t hpi_buffer_cmpl:1;
523 uint32_t completed:1;
524 uint32_t consumed:1;
525 uint32_t rsvd0:27;
526 #else
527 /* dw0 */
528 uint32_t completion_status:16;
529 uint32_t extended_status:16;
530 /* dw1 dw2 */
531 uint32_t mq_tag[2];
532 /* dw3 */
533 uint32_t rsvd0:27;
534 uint32_t consumed:1;
535 uint32_t completed:1;
536 uint32_t hpi_buffer_cmpl:1;
537 uint32_t async_event:1;
538 uint32_t valid:1;
539 #endif
540 }s;
541 uint32_t dw[4];
542 }u0;
543 };
544
545 struct oce_async_cqe_link_state {
546 union {
547 struct {
548 #ifdef _BIG_ENDIAN
549 /* dw0 */
550 uint8_t speed;
551 uint8_t duplex;
552 uint8_t link_status;
553 uint8_t phy_port;
554 /* dw1 */
555 uint8_t rsvd0[3];
556 uint8_t fault;
557 /* dw2 */
558 uint32_t event_tag;
559 /* dw3 */
560 uint32_t valid:1;
561 uint32_t async_event:1;
562 uint32_t rsvd2:6;
563 uint32_t event_type:8;
564 uint32_t event_code:8;
565 uint32_t rsvd1:8;
566 #else
567 /* dw0 */
568 uint8_t phy_port;
569 uint8_t link_status;
570 uint8_t duplex;
571 uint8_t speed;
572 /* dw1 */
573 uint8_t fault;
574 uint8_t rsvd0[3];
575 /* dw2 */
576 uint32_t event_tag;
577 /* dw3 */
578 uint32_t rsvd1:8;
579 uint32_t event_code:8;
580 uint32_t event_type:8;
581 uint32_t rsvd2:6;
582 uint32_t async_event:1;
583 uint32_t valid:1;
584 #endif
585 }s;
586 uint32_t dw[4];
587 }u0;
588 };
589
590 /* MQ mailbox structure */
591 struct oce_bmbx {
592 struct oce_mbx mbx;
593 struct oce_mq_cqe cqe;
594 };
595
596 /* ---[ MBXs start here ]---------------------------------------------- */
597 /* MBXs sub system codes */
598 enum {
599 MBX_SUBSYSTEM_RSVD = 0,
600 MBX_SUBSYSTEM_COMMON = 1,
601 MBX_SUBSYSTEM_COMMON_ISCSI = 2,
602 MBX_SUBSYSTEM_NIC = 3,
603 MBX_SUBSYSTEM_TOE = 4,
604 MBX_SUBSYSTEM_PXE_UNDI = 5,
605 MBX_SUBSYSTEM_ISCSI_INI = 6,
606 MBX_SUBSYSTEM_ISCSI_TGT = 7,
607 MBX_SUBSYSTEM_MILI_PTL = 8,
608 MBX_SUBSYSTEM_MILI_TMD = 9,
609 MBX_SUBSYSTEM_RDMA = 10,
610 MBX_SUBSYSTEM_LOWLEVEL = 11,
611 MBX_SUBSYSTEM_LRO = 13,
612 IOCBMBX_SUBSYSTEM_DCBX = 15,
613 IOCBMBX_SUBSYSTEM_DIAG = 16,
614 IOCBMBX_SUBSYSTEM_VENDOR = 17
615 };
616
617 /* common ioctl opcodes */
618 enum {
619 OPCODE_QUERY_COMMON_IFACE_MAC = 1,
620 OPCODE_SET_COMMON_IFACE_MAC = 2,
621 OPCODE_SET_COMMON_IFACE_MULTICAST = 3,
622 OPCODE_CONFIG_COMMON_IFACE_VLAN = 4,
623 OPCODE_QUERY_COMMON_LINK_STATUS = 5,
624 OPCODE_READ_COMMON_FLASHROM = 6,
625 OPCODE_WRITE_COMMON_FLASHROM = 7,
626 OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8,
627 OPCODE_ADD_COMMON_PAGE_TABLES = 9,
628 OPCODE_REMOVE_COMMON_PAGE_TABLES = 10,
629 OPCODE_CREATE_COMMON_CQ = 12,
630 OPCODE_CREATE_COMMON_EQ = 13,
631 OPCODE_CREATE_COMMON_MQ = 21,
632 OPCODE_COMMON_JELL_CONFIG = 22,
633 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24,
634 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25,
635 OPCODE_COMMON_POST_ZERO_BUFFER = 26,
636 OPCODE_COMMON_GET_QOS = 27,
637 OPCODE_COMMON_SET_QOS = 28,
638 OPCODE_COMMON_TCP_GET_STATISTICS = 29,
639 OPCODE_READ_COMMON_SEEPROM = 30,
640 OPCODE_COMMON_TCP_STATE_QUERY = 31,
641 OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32,
642 OPCODE_COMMON_NOP = 33,
643 OPCODE_COMMON_NTWK_RX_FILTER = 34,
644 OPCODE_GET_COMMON_FW_VERSION = 35,
645 OPCODE_SET_COMMON_FLOW_CONTROL = 36,
646 OPCODE_GET_COMMON_FLOW_CONTROL = 37,
647 OPCODE_COMMON_SET_TCP_PARAMETERS = 38,
648 OPCODE_SET_COMMON_FRAME_SIZE = 39,
649 OPCODE_COMMON_GET_FAT = 40,
650 OPCODE_MODIFY_COMMON_EQ_DELAY = 41,
651 OPCODE_COMMON_FIRMWARE_CONFIG = 42,
652 OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43,
653 OPCODE_COMMON_GET_DOMAIN_CONFIG = 44,
654 OPCODE_COMMON_GET_PORT_EQUALIZATION = 47,
655 OPCODE_COMMON_SET_PORT_EQUALIZATION = 48,
656 OPCODE_COMMON_RED_CONFIG = 49,
657 OPCODE_CREATE_COMMON_IFACE = 50,
658 OPCODE_DESTROY_COMMON_IFACE = 51,
659 OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52,
660 OPCODE_DESTROY_COMMON_MQ = 53,
661 OPCODE_DESTROY_COMMON_CQ = 54,
662 OPCODE_DESTROY_COMMON_EQ = 55,
663 OPCODE_COMMON_TCP_UPL_OAD = 56,
664 OPCODE_SET_COMMON_LINK_SPEED = 57,
665 OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58,
666 OPCODE_ADD_COMMON_IFACE_MAC = 59,
667 OPCODE_DEL_COMMON_IFACE_MAC = 60,
668 OPCODE_COMMON_FUNCTION_RESET = 61,
669 OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80
670 };
671
672 /* common ioctl header */
673 struct mbx_hdr {
674 union {
675 struct {
676 #ifdef _BIG_ENDIAN
677 uint8_t domain;
678 uint8_t port_number;
679 uint8_t subsystem;
680 uint8_t opcode;
681 #else
682 uint8_t opcode;
683 uint8_t subsystem;
684 uint8_t port_number;
685 uint8_t domain;
686 #endif
687 uint32_t timeout;
688 uint32_t request_length;
689 uint32_t rsvd0;
690 }req;
691
692 struct {
693 /* dw 0 */
694 uint8_t opcode;
695 uint8_t subsystem;
696 uint8_t rsvd0;
697 uint8_t domain;
698 /* dw 1 */
699 uint8_t status;
700 uint8_t additional_status;
701 uint16_t rsvd1;
702
703 uint32_t rsp_length;
704 uint32_t actual_rsp_length;
705 }rsp;
706 uint32_t dw[4];
707 }u0;
708 };
709 #define OCE_BMBX_RHDR_SZ 20
710 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
711 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
712 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
713
714 /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */
715 struct mbx_query_common_link_status {
716 struct mbx_hdr hdr;
717 union {
718 struct {
719 uint32_t rsvd0;
720 }req;
721
722 struct {
723 /* dw 0 */
724 uint8_t physical_port;
725 uint8_t mac_duplex;
726 uint8_t mac_speed;
727 uint8_t mac_fault;
728 /* dw 1 */
729 uint8_t mgmt_mac_duplex;
730 uint8_t mgmt_mac_speed;
731 uint16_t qos_link_speed;
732 uint32_t logical_link_status;
733 }rsp;
734 }params;
735 };
736
737 /* [57] OPCODE_SET_COMMON_LINK_SPEED */
738 struct mbx_set_common_link_speed {
739 struct mbx_hdr hdr;
740 union {
741 struct {
742 #ifdef _BIG_ENDIAN
743 uint8_t rsvd0;
744 uint8_t mac_speed;
745 uint8_t virtual_port;
746 uint8_t physical_port;
747 #else
748 uint8_t physical_port;
749 uint8_t virtual_port;
750 uint8_t mac_speed;
751 uint8_t rsvd0;
752 #endif
753 }req;
754
755 struct {
756 uint32_t rsvd0;
757 }rsp;
758
759 uint32_t dw;
760 }params;
761 };
762
763 struct mac_address_format {
764 uint16_t size_of_struct;
765 uint8_t mac_addr[6];
766 };
767
768 /* [01] OPCODE_QUERY_COMMON_IFACE_MAC */
769 struct mbx_query_common_iface_mac {
770 struct mbx_hdr hdr;
771 union {
772 struct {
773 #ifdef _BIG_ENDIAN
774 uint16_t if_id;
775 uint8_t permanent;
776 uint8_t type;
777 #else
778 uint8_t type;
779 uint8_t permanent;
780 uint16_t if_id;
781 #endif
782
783 }req;
784
785 struct {
786 struct mac_address_format mac;
787 }rsp;
788 }params;
789 };
790
791 /* [02] OPCODE_SET_COMMON_IFACE_MAC */
792 struct mbx_set_common_iface_mac {
793 struct mbx_hdr hdr;
794 union {
795 struct {
796 #ifdef _BIG_ENDIAN
797 /* dw 0 */
798 uint16_t if_id;
799 uint8_t invalidate;
800 uint8_t type;
801 #else
802 /* dw 0 */
803 uint8_t type;
804 uint8_t invalidate;
805 uint16_t if_id;
806 #endif
807 /* dw 1 */
808 struct mac_address_format mac;
809 }req;
810
811 struct {
812 uint32_t rsvd0;
813 }rsp;
814
815 uint32_t dw[2];
816 }params;
817 };
818
819 /* [03] OPCODE_SET_COMMON_IFACE_MULTICAST */
820 struct mbx_set_common_iface_multicast {
821 struct mbx_hdr hdr;
822 union {
823 struct {
824 /* dw 0 */
825 uint16_t num_mac;
826 uint8_t promiscuous;
827 uint8_t if_id;
828 /* dw 1-48 */
829 struct {
830 uint8_t byte[6];
831 } mac[32];
832
833 }req;
834
835 struct {
836 uint32_t rsvd0;
837 }rsp;
838
839 uint32_t dw[49];
840 }params;
841 };
842
843 struct qinq_vlan {
844 #ifdef _BIG_ENDIAN
845 uint16_t inner;
846 uint16_t outer;
847 #else
848 uint16_t outer;
849 uint16_t inner;
850 #endif
851 };
852
853 struct normal_vlan {
854 uint16_t vtag;
855 };
856
857 struct ntwk_if_vlan_tag {
858 union {
859 struct normal_vlan normal;
860 struct qinq_vlan qinq;
861 }u0;
862 };
863
864 /* [50] OPCODE_CREATE_COMMON_IFACE */
865 struct mbx_create_common_iface {
866 struct mbx_hdr hdr;
867 union {
868 struct {
869 uint32_t version;
870 uint32_t cap_flags;
871 uint32_t enable_flags;
872 uint8_t mac_addr[6];
873 uint8_t rsvd0;
874 uint8_t mac_invalid;
875 struct ntwk_if_vlan_tag vlan_tag;
876 }req;
877
878 struct {
879 uint32_t if_id;
880 uint32_t pmac_id;
881 }rsp;
882 uint32_t dw[4];
883 }params;
884 };
885
886 /* [51] OPCODE_DESTROY_COMMON_IFACE */
887 struct mbx_destroy_common_iface {
888 struct mbx_hdr hdr;
889 union {
890 struct {
891 uint32_t if_id;
892 }req;
893
894 struct {
895 uint32_t rsvd0;
896 }rsp;
897
898 uint32_t dw;
899 }params;
900 };
901
902 /* event queue context structure */
903 struct oce_eq_ctx {
904 #ifdef _BIG_ENDIAN
905 /* dw0 */
906 uint32_t size:1;
907 uint32_t rsvd1:1;
908 uint32_t valid:1;
909 uint32_t epidx:13;
910 uint32_t rsvd0:3;
911 uint32_t cidx:13;
912
913 /* dw1 */
914 uint32_t armed:1;
915 uint32_t stalled:1;
916 uint32_t sol_event:1;
917 uint32_t count:3;
918 uint32_t pd:10;
919 uint32_t rsvd2:3;
920 uint32_t pidx:13;
921
922 /* dw2 */
923 uint32_t rsvd6:4;
924 uint32_t nodelay:1;
925 uint32_t phase:2;
926 uint32_t rsvd5:2;
927 uint32_t delay_mult:10;
928 uint32_t rsvd4:1;
929 uint32_t function:8;
930 uint32_t rsvd3:4;
931
932 /* dw 3 */
933 uint32_t rsvd7;
934 #else
935 /* dw0 */
936 uint32_t cidx:13;
937 uint32_t rsvd0:3;
938 uint32_t epidx:13;
939 uint32_t valid:1;
940 uint32_t rsvd1:1;
941 uint32_t size:1;
942
943 /* dw1 */
944 uint32_t pidx:13;
945 uint32_t rsvd2:3;
946 uint32_t pd:10;
947 uint32_t count:3;
948 uint32_t sol_event:1;
949 uint32_t stalled:1;
950 uint32_t armed:1;
951
952 /* dw2 */
953 uint32_t rsvd3:4;
954 uint32_t function:8;
955 uint32_t rsvd4:1;
956 uint32_t delay_mult:10;
957 uint32_t rsvd5:2;
958 uint32_t phase:2;
959 uint32_t nodelay:1;
960 uint32_t rsvd6:4;
961
962 /* dw3 */
963 uint32_t rsvd7;
964 #endif
965 };
966
967 /* [13] OPCODE_CREATE_COMMON_EQ */
968 struct mbx_create_common_eq {
969 struct mbx_hdr hdr;
970 union {
971 struct {
972 #ifdef _BIG_ENDIAN
973 uint16_t rsvd0;
974 uint16_t num_pages;
975 #else
976 uint16_t num_pages;
977 uint16_t rsvd0;
978 #endif
979 struct oce_eq_ctx eq_ctx;
980 struct phys_addr pages[8];
981 }req;
982
983 struct {
984 uint16_t eq_id;
985 uint16_t rsvd0;
986 }rsp;
987 }params;
988 };
989
990 /* [55] OPCODE_DESTROY_COMMON_EQ */
991 struct mbx_destroy_common_eq {
992 struct mbx_hdr hdr;
993 union {
994 struct {
995 #ifdef _BIG_ENDIAN
996 uint16_t rsvd0;
997 uint16_t id;
998 #else
999 uint16_t id;
1000 uint16_t rsvd0;
1001 #endif
1002 }req;
1003
1004 struct {
1005 uint32_t rsvd0;
1006 }rsp;
1007 }params;
1008 };
1009
1010 struct oce_cq_ctx {
1011 #ifdef _BIG_ENDIAN
1012 /* dw0 */
1013 uint32_t eventable:1;
1014 uint32_t sol_event:1;
1015 uint32_t valid:1;
1016 uint32_t count:2;
1017 uint32_t rsvd1:1;
1018 uint32_t epidx:11;
1019 uint32_t nodelay:1;
1020 uint32_t coalesce_wm:2;
1021 uint32_t rsvd0:1;
1022 uint32_t cidx:11;
1023
1024 /* dw1 */
1025 uint32_t armed:1;
1026 uint32_t stalled:1;
1027 uint32_t eq_id:8;
1028 uint32_t pd:10;
1029 uint32_t rsvd2:1;
1030 uint32_t pidx:11;
1031
1032 /* dw2 */
1033 uint32_t rsvd4:20;
1034 uint32_t function:8;
1035 uint32_t rsvd3:4;
1036 #else
1037 /* dw0 */
1038 uint32_t cidx:11;
1039 uint32_t rsvd0:1;
1040 uint32_t coalesce_wm:2;
1041 uint32_t nodelay:1;
1042 uint32_t epidx:11;
1043 uint32_t rsvd1:1;
1044 uint32_t count:2;
1045 uint32_t valid:1;
1046 uint32_t sol_event:1;
1047 uint32_t eventable:1;
1048
1049 /* dw1 */
1050 uint32_t pidx:11;
1051 uint32_t rsvd2:1;
1052 uint32_t pd:10;
1053 uint32_t eq_id:8;
1054 uint32_t stalled:1;
1055 uint32_t armed:1;
1056
1057 /* dw2 */
1058 uint32_t rsvd3:4;
1059 uint32_t function:8;
1060 uint32_t rsvd4:20;
1061 #endif
1062 uint32_t rsvd5;
1063 };
1064
1065 /* [12] OPCODE_CREATE_COMMON_CQ */
1066 struct mbx_create_common_cq {
1067 struct mbx_hdr hdr;
1068 union {
1069 struct {
1070 #ifdef _BIG_ENDIAN
1071 uint16_t rsvd0;
1072 uint16_t num_pages;
1073 #else
1074 uint16_t num_pages;
1075 uint16_t rsvd0;
1076 #endif
1077 struct oce_cq_ctx cq_ctx;
1078 struct phys_addr pages[4];
1079 }req;
1080
1081 struct {
1082 uint16_t cq_id;
1083 uint16_t rsvd0;
1084 }rsp;
1085 }params;
1086 };
1087
1088 /* [54] OPCODE_DESTROY_COMMON_CQ */
1089 struct mbx_destroy_common_cq {
1090 struct mbx_hdr hdr;
1091 union {
1092 struct {
1093 #ifdef _BIG_ENDIAN
1094 uint16_t rsvd0;
1095 uint16_t id;
1096 #else
1097 uint16_t id;
1098 uint16_t rsvd0;
1099 #endif
1100 }req;
1101
1102 struct {
1103 uint32_t rsvd0;
1104 }rsp;
1105 }params;
1106 };
1107
1108 struct mq_ring_ctx {
1109 union {
1110 struct {
1111 #ifdef _BIG_ENDIAN
1112 /* dw 0 */
1113 uint32_t cq_id:10;
1114 uint32_t fetch_r2t:1;
1115 uint32_t fetch_wrb:1;
1116 uint32_t ring_size:4;
1117 uint32_t rsvd0:2;
1118 uint32_t con_index:14;
1119
1120 /* dw1 */
1121 uint32_t valid:1;
1122 uint32_t pdid:9;
1123 uint32_t fid:8;
1124 uint32_t prod_index:14;
1125
1126 /* dw 2 */
1127 uint32_t rsvd1:21;
1128 uint32_t async_cq_id:10;
1129 uint32_t async_cq_valid:1;
1130 #else
1131 /* dw 0 */
1132 uint32_t con_index:14;
1133 uint32_t rsvd0:2;
1134 uint32_t ring_size:4;
1135 uint32_t fetch_wrb:1;
1136 uint32_t fetch_r2t:1;
1137 uint32_t cq_id:10;
1138
1139 /* dw1 */
1140 uint32_t prod_index:14;
1141 uint32_t fid:8;
1142 uint32_t pdid:9;
1143 uint32_t valid:1;
1144
1145 /* dw 2 */
1146 uint32_t async_cq_valid:1;
1147 uint32_t async_cq_id:10;
1148 uint32_t rsvd1:21;
1149 #endif
1150 /* dw3 */
1151 uint32_t rsvd3;
1152 }s;
1153 uint32_t dw[4];
1154 }u0;
1155 };
1156
1157 /* [21] OPCODE_CREATE_COMMON_MQ */
1158 struct mbx_create_common_mq {
1159 struct mbx_hdr hdr;
1160 union {
1161 struct {
1162 #ifdef _BIG_ENDIAN
1163 uint16_t rsvd0;
1164 uint16_t num_pages;
1165 #else
1166 uint16_t num_pages;
1167 uint16_t rsvd0;
1168 #endif
1169 struct mq_ring_ctx context;
1170 struct phys_addr pages[8];
1171 }req;
1172
1173 struct {
1174 uint32_t mq_id:16;
1175 uint32_t rsvd0:16;
1176 }rsp;
1177 }params;
1178 };
1179
1180 /* [53] OPCODE_DESTROY_COMMON_MQ */
1181 struct mbx_destroy_common_mq {
1182 struct mbx_hdr hdr;
1183 union {
1184 struct {
1185 #ifdef _BIG_ENDIAN
1186 uint16_t rsvd0;
1187 uint16_t id;
1188 #else
1189 uint16_t id;
1190 uint16_t rsvd0;
1191 #endif
1192 }req;
1193
1194 struct {
1195 uint32_t rsvd0;
1196 }rsp;
1197 }params;
1198 };
1199
1200 /* [35] OPCODE_GET_COMMON_ FW_VERSION */
1201 struct mbx_get_common_fw_version {
1202 struct mbx_hdr hdr;
1203 union {
1204 struct {
1205 uint32_t rsvd0;
1206 }req;
1207
1208 struct {
1209 uint8_t fw_ver_str[32];
1210 uint8_t fw_on_flash_ver_str[32];
1211 }rsp;
1212 }params;
1213 };
1214
1215 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1216 struct mbx_common_cev_modify_msi_messages {
1217 struct mbx_hdr hdr;
1218 union {
1219 struct {
1220 uint32_t num_msi_msgs;
1221 }req;
1222
1223 struct {
1224 uint32_t rsvd0;
1225 }rsp;
1226 }params;
1227 };
1228
1229 /* [36] OPCODE_SET_COMMON_FLOW_CONTROL */
1230 /* [37] OPCODE_GET_COMMON_FLOW_CONTROL */
1231 struct mbx_common_get_set_flow_control {
1232 struct mbx_hdr hdr;
1233 #ifdef _BIG_ENDIAN
1234 uint16_t tx_flow_control;
1235 uint16_t rx_flow_control;
1236 #else
1237 uint16_t rx_flow_control;
1238 uint16_t tx_flow_control;
1239 #endif
1240 };
1241
1242 enum e_flash_opcode {
1243 MGMT_FLASHROM_OPCODE_FLASH = 1,
1244 MGMT_FLASHROM_OPCODE_SAVE = 2
1245 };
1246
1247 /* [06] OPCODE_READ_COMMON_FLASHROM */
1248 /* [07] OPCODE_WRITE_COMMON_FLASHROM */
1249
1250 struct mbx_common_read_write_flashrom {
1251 struct mbx_hdr hdr;
1252 uint32_t flash_op_code;
1253 uint32_t flash_op_type;
1254 uint32_t data_buffer_size;
1255 uint32_t data_offset;
1256 uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */
1257 };
1258
1259 /* ULP MODE SUPPORTED */
1260 enum {
1261 ULP_TOE_MODE = 0x1,
1262 ULP_NIC_MODE = 0x2,
1263 ULP_RDMA_MODE = 0x4,
1264 ULP_ISCSI_INI_MODE = 0x10,
1265 ULP_ISCSI_TGT_MODE = 0x20,
1266 ULP_FCOE_INI_MODE = 0x40,
1267 ULP_FCOE_TGT_MODE = 0x80,
1268 ULP_DAL_MODE = 0x100,
1269 ULP_LRO_MODE = 0x200
1270 };
1271
1272 /* Function Mode Supported */
1273 enum {
1274 TOE_MODE = 0x1, /* TCP offload */
1275 NIC_MODE = 0x2, /* Raw Ethernet */
1276 RDMA_MODE = 0x4, /* RDMA */
1277 VM_MODE = 0x8, /* VM */
1278 ISCSI_INI_MODE = 0x10, /* iSCSI initiator */
1279 ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */
1280 FCOE_INI_MODE = 0x40, /* FCoE Initiator */
1281 FCOE_TGT_MODE = 0x80, /* FCoE target */
1282 DAL_MODE = 0x100, /* DAL */
1283 LRO_MODE = 0x200, /* LRO */
1284 FLEX10_MODE = 0x400, /* FLEX-10 or VNIC */
1285 NCSI_MODE = 0x800, /* NCSI */
1286 INVALID_MODE = 0x8000 /* Invalid */
1287 };
1288
1289 struct mbx_common_query_fw_config {
1290 struct mbx_hdr hdr;
1291 union {
1292 struct {
1293 uint32_t rsvd0[30];
1294 }req;
1295
1296 struct {
1297 uint32_t config_number;
1298 uint32_t asic_revision;
1299 uint32_t port_id; /* used for stats retrieval */
1300 uint32_t function_mode;
1301 struct {
1302
1303 uint32_t mode;
1304 uint32_t wq_base;
1305 uint32_t wq_count;
1306 uint32_t sq_base;
1307 uint32_t sq_count;
1308 uint32_t rq_base;
1309 uint32_t rq_count;
1310 uint32_t dq_base;
1311 uint32_t dq_count;
1312 uint32_t lro_base;
1313 uint32_t lro_count;
1314 uint32_t icd_base;
1315 uint32_t icd_count;
1316 } ulp[2];
1317 uint32_t function_caps;
1318 }rsp;
1319 }params;
1320 };
1321
1322 struct mbx_common_config_vlan {
1323 struct mbx_hdr hdr;
1324 union {
1325 struct {
1326 #ifdef _BIG_ENDIAN
1327 uint8_t num_vlans;
1328 uint8_t untagged;
1329 uint8_t promisc;
1330 uint8_t if_id;
1331 #else
1332 uint8_t if_id;
1333 uint8_t promisc;
1334 uint8_t untagged;
1335 uint8_t num_vlans;
1336 #endif
1337 union {
1338 struct normal_vlan normal_vlans[64];
1339 struct qinq_vlan qinq_vlans[32];
1340 }tags;
1341 }req;
1342
1343 struct {
1344 uint32_t rsvd;
1345 }rsp;
1346 }params;
1347 };
1348
1349 /* [34] OPCODE_COMMON_NTWK_RX_FILTER */
1350 struct mbx_set_common_ntwk_rx_filter {
1351 struct mbx_hdr hdr;
1352 uint32_t global_flags_mask;
1353 uint32_t global_flags;
1354 uint32_t iface_flags_mask;
1355 uint32_t iface_flags;
1356 uint32_t if_id;
1357 uint32_t num_mcast;
1358 struct {
1359 uint8_t byte[6];
1360 }mac[32];
1361 };
1362 /* [41] OPCODE_MODIFY_COMMON_EQ_DELAY */
1363 struct mbx_modify_common_eq_delay {
1364 struct mbx_hdr hdr;
1365 union {
1366 struct {
1367 uint32_t num_eq;
1368 struct {
1369 uint32_t eq_id;
1370 uint32_t phase;
1371 uint32_t dm;
1372 }delay[8];
1373 }req;
1374
1375 struct {
1376 uint32_t rsvd0;
1377 }rsp;
1378 }params;
1379 };
1380 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1381 struct mbx_add_common_iface_mac {
1382 struct mbx_hdr hdr;
1383 union {
1384 struct {
1385 uint32_t if_id;
1386 uint8_t mac_address[6];
1387 uint8_t rsvd0[2];
1388 }req;
1389 struct {
1390 uint32_t pmac_id;
1391 }rsp;
1392 } params;
1393 };
1394
1395 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1396 struct mbx_del_common_iface_mac {
1397 struct mbx_hdr hdr;
1398 union {
1399 struct {
1400 uint32_t if_id;
1401 uint32_t pmac_id;
1402 }req;
1403 struct {
1404 uint32_t rsvd0;
1405 }rsp;
1406 } params;
1407 };
1408
1409 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1410 struct mbx_query_common_max_mbx_buffer_size {
1411 struct mbx_hdr hdr;
1412 struct {
1413 uint32_t max_ioctl_bufsz;
1414 } rsp;
1415 };
1416
1417 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1418 struct ioctl_common_function_reset {
1419 struct mbx_hdr hdr;
1420 };
1421
1422 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1423 struct mbx_common_func_link_cfg {
1424 struct mbx_hdr hdr;
1425 union {
1426 struct {
1427 uint32_t enable;
1428 }req;
1429 struct {
1430 uint32_t rsvd0;
1431 }rsp;
1432 } params;
1433 };
1434
1435 #pragma pack()
1436
1437 #ifdef __cplusplus
1438 }
1439 #endif
1440
1441 #endif /* _OCE_HW_H_ */