NEX-1890 update oce from source provided by Emulex

@@ -17,12 +17,16 @@
  * information: Portions Copyright [yyyy] [name of copyright owner]
  *
  * CDDL HEADER END
  */
 
-/* Copyright © 2003-2011 Emulex. All rights reserved.  */
+/*
+ * Copyright (c) 2009-2012 Emulex. All rights reserved.
+ * Use is subject to license terms.
+ */
 
+
 /*
  * Header file defining the driver buffer management interface
  */
 
 #ifndef _OCE_BUF_H_

@@ -67,45 +71,45 @@
         /* size of the memory */
         size_t          size;
         size_t          off;
         size_t          len;
         uint32_t        num_pages;
+        uint32_t        ncookies;
+        ddi_dma_cookie_t cookie;
 }oce_dma_buf_t;
 
-#define DBUF_PA(obj) (((oce_dma_buf_t *)(obj))->addr)
-#define DBUF_VA(obj) (((oce_dma_buf_t *)(obj))->base)
-#define DBUF_DHDL(obj) (((oce_dma_buf_t *)(obj))->dma_handle)
-#define DBUF_AHDL(obj) (((oce_dma_buf_t *)obj))->acc_handle)
-#define DBUF_SYNC(obj, flags)   (void) ddi_dma_sync(DBUF_DHDL(obj), 0,\
-                        0, (flags))
+#define DBUF_PA(obj) ((obj).addr)
+#define DBUF_VA(obj) ((obj).base)
+#define DBUF_DHDL(obj) ((obj).dma_handle)
+#define DBUF_AHDL(obj) ((obj).acc_handle)
+#define DBUF_SYNC(obj, off, len, flags)         \
+        (void) ddi_dma_sync(DBUF_DHDL(obj), off, len, (flags))
 
 typedef struct oce_ring_buffer_s {
         uint16_t    cidx;       /* Get ptr */
         uint16_t    pidx;       /* Put Ptr */
         size_t  item_size;      /* Size */
         size_t  num_items;      /* count */
         uint32_t  num_used;
-        oce_dma_buf_t   *dbuf;  /* dma buffer */
+        oce_dma_buf_t   dbuf;   /* dma buffer */
 }oce_ring_buffer_t;
 
 typedef struct oce_rq_bdesc_s {
-        oce_dma_buf_t   *rqb;
+        oce_dma_buf_t   rqb;
         struct oce_rq   *rq;
         oce_addr64_t    frag_addr;
         mblk_t          *mp;
         frtn_t          fr_rtn;
     uint32_t    ref_cnt;
 }oce_rq_bdesc_t;
 
 typedef struct oce_wq_bdesc_s {
-        OCE_LIST_NODE_T  link;
-        oce_dma_buf_t   *wqb;
+        oce_dma_buf_t   wqb;
         oce_addr64_t    frag_addr;
 } oce_wq_bdesc_t;
 
 typedef struct oce_wq_mdesc_s {
-        OCE_LIST_NODE_T         link;
         ddi_dma_handle_t        dma_handle;
 } oce_wq_mdesc_t;
 
 enum entry_type {
         HEADER_WQE = 0x1, /* arbitrary value */

@@ -118,11 +122,11 @@
     enum entry_type     type;
         void            *hdl; /* opaque handle */
 }oce_handle_t;
 
 typedef struct _oce_wqe_desc_s {
-        OCE_LIST_NODE_T  link;
+        list_node_t     link;
         oce_handle_t    hdesc[OCE_MAX_TX_HDL];
         struct oce_nic_frag_wqe frag[OCE_TX_MAX_FRAGS];
         struct oce_wq  *wq;
         mblk_t          *mp;
         uint16_t        wqe_cnt;

@@ -138,11 +142,12 @@
         uint8_t pad[18];
         /* ether_vlan_header_t vhdr; */
 } oce_rq_buf_hdr_t;
 #pragma pack()
 
-#define OCE_RQE_BUF_HEADROOM    18
+#define OCE_RQE_BUF_HEADROOM    10      /* always 2 mod  4 */
+#define OCE_IP_ALIGN            2       /* Align the IP header */
 #define MAX_POOL_NAME           32
 
 #define RING_NUM_PENDING(ring)  ring->num_used
 
 #define RING_NUM_FREE(ring)     \