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NEX-8705 Drivers for ATTO Celerity FC-162E Gen 5 and Celerity FC-162P Gen 6 16GB FC cards support
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-1878 update emlxs from source provided by Emulex
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--- old/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_queue.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_queue.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at
9 9 * http://www.opensource.org/licenses/cddl1.txt.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 #ifndef _EMLXS_QUEUE_H
28 28 #define _EMLXS_QUEUE_H
29 29
30 30 #ifdef __cplusplus
31 31 extern "C" {
32 32 #endif
33 33
34 34
35 35 /* Queue entry defines */
36 36
37 37 /* EQ entries */
38 38 typedef struct EQE
39 39 {
40 40 #ifdef EMLXS_BIG_ENDIAN
41 41 uint32_t CQId: 16;
42 42 uint32_t MinorCode: 12;
43 43 uint32_t MajorCode: 3;
44 44 uint32_t Valid: 1;
45 45 #endif
46 46 #ifdef EMLXS_LITTLE_ENDIAN
47 47 uint32_t Valid: 1;
48 48 uint32_t MajorCode: 3;
49 49 uint32_t MinorCode: 12;
50 50 uint32_t CQId: 16;
51 51 #endif
52 52
53 53 } EQE_t;
54 54
55 55 typedef union
56 56 {
57 57 uint32_t word;
58 58 EQE_t entry;
59 59
60 60 } EQE_u;
61 61
62 62 #define EQE_VALID 0x00000001 /* Mask for EQE valid */
63 63 #define EQE_CQID 0xFFFF0000 /* Mask for EQE CQID */
64 64
65 65 /* CQ entries */
66 66 typedef struct CQE_CmplWQ
67 67 {
68 68 #ifdef EMLXS_BIG_ENDIAN
69 69 uint16_t RequestTag; /* Word 0 */
70 70 uint8_t Status;
71 71 uint8_t hw_status;
72 72
73 73 uint32_t CmdSpecific; /* Word 1 */
74 74 uint32_t Parameter; /* Word 2 */
75 75
76 76 uint32_t Valid: 1; /* Word 3 */
77 77 uint32_t Rsvd1: 2;
78 78 uint32_t XB: 1;
79 79 uint32_t PV: 1;
80 80 uint32_t Priority: 3;
81 81 uint32_t Code: 8;
82 82 uint32_t Rsvd2: 16;
83 83 #endif
84 84 #ifdef EMLXS_LITTLE_ENDIAN
85 85 uint8_t hw_status;
86 86 uint8_t Status;
87 87 uint16_t RequestTag; /* Word 0 */
88 88
89 89 uint32_t CmdSpecific; /* Word 1 */
90 90 uint32_t Parameter; /* Word 2 */
91 91
92 92 uint32_t Rsvd2: 16;
93 93 uint32_t Code: 8;
94 94 uint32_t Priority: 3;
95 95 uint32_t PV: 1;
96 96 uint32_t XB: 1;
97 97 uint32_t Rsvd1: 2;
98 98 uint32_t Valid: 1; /* Word 3 */
99 99 #endif
100 100 } CQE_CmplWQ_t;
101 101
102 102 typedef struct CQE_RelWQ
103 103 {
104 104 #ifdef EMLXS_BIG_ENDIAN
105 105 uint32_t Reserved1; /* Word 0 */
106 106 uint32_t Reserved2; /* Word 1 */
107 107
108 108 uint16_t WQid; /* Word 2 */
109 109 uint16_t WQindex;
110 110
111 111 uint32_t Valid: 1; /* Word 3 */
112 112 uint32_t Rsvd1: 7;
113 113 uint32_t Code: 8;
114 114 uint32_t Rsvd2: 16;
115 115 #endif
116 116 #ifdef EMLXS_LITTLE_ENDIAN
117 117 uint32_t Reserved1; /* Word 0 */
118 118 uint32_t Reserved2; /* Word 1 */
119 119
120 120 uint16_t WQindex;
121 121 uint16_t WQid; /* Word 2 */
122 122
123 123 uint32_t Rsvd2: 16;
124 124 uint32_t Code: 8;
125 125 uint32_t Rsvd1: 7;
126 126 uint32_t Valid: 1; /* Word 3 */
127 127 #endif
128 128 } CQE_RelWQ_t;
129 129
130 130 typedef struct CQE_UnsolRcv
131 131 {
132 132 #ifdef EMLXS_BIG_ENDIAN
133 133 uint16_t RQindex; /* Word 0 */
134 134 uint8_t Status;
135 135 uint8_t Rsvd1;
136 136
137 137 uint32_t Rsvd2; /* Word 1 */
138 138
139 139 uint32_t data_size: 16; /* Word 2 */
140 140 uint32_t RQid: 10;
141 141 uint32_t FCFId: 6;
142 142
143 143 uint32_t Valid: 1; /* Word 3 */
144 144 uint32_t Rsvd3: 1;
145 145 uint32_t hdr_size: 6;
146 146 uint32_t Code: 8;
147 147 uint32_t eof: 8;
148 148 uint32_t sof: 8;
149 149 #endif
150 150 #ifdef EMLXS_LITTLE_ENDIAN
151 151 uint8_t Rsvd1;
152 152 uint8_t Status;
153 153 uint16_t RQindex; /* Word 0 */
154 154
155 155 uint32_t Rsvd2; /* Word 1 */
156 156
157 157 uint32_t FCFId: 6;
158 158 uint32_t RQid: 10;
159 159 uint32_t data_size: 16; /* Word 2 */
160 160
161 161 uint32_t sof: 8;
162 162 uint32_t eof: 8;
163 163 uint32_t Code: 8;
164 164 uint32_t hdr_size: 6;
165 165 uint32_t Rsvd3: 1;
166 166 uint32_t Valid: 1; /* Word 3 */
167 167 #endif
168 168 } CQE_UnsolRcv_t;
169 169
170 170
171 171 typedef struct CQE_UnsolRcvV1
172 172 {
173 173 #ifdef EMLXS_BIG_ENDIAN
174 174 uint16_t RQindex; /* Word 0 */
175 175 uint8_t Status;
176 176 uint8_t Rsvd1;
177 177
178 178 uint32_t Rsvd2: 26; /* Word 1 */
179 179 uint32_t FCFId: 6;
180 180
181 181 uint16_t data_size; /* Word 2 */
182 182 uint16_t RQid;
183 183
184 184 uint32_t Valid: 1; /* Word 3 */
185 185 uint32_t Rsvd3: 1;
186 186 uint32_t hdr_size: 6;
187 187 uint32_t Code: 8;
188 188 uint32_t eof: 8;
189 189 uint32_t sof: 8;
190 190 #endif
191 191 #ifdef EMLXS_LITTLE_ENDIAN
192 192 uint8_t Rsvd1;
193 193 uint8_t Status;
194 194 uint16_t RQindex; /* Word 0 */
195 195
196 196 uint32_t FCFId: 6;
197 197 uint32_t Rsvd2: 26; /* Word 1 */
198 198
199 199 uint16_t RQid;
200 200 uint16_t data_size; /* Word 2 */
201 201
202 202 uint32_t sof: 8;
203 203 uint32_t eof: 8;
204 204 uint32_t Code: 8;
205 205 uint32_t hdr_size: 6;
206 206 uint32_t Rsvd3: 1;
207 207 uint32_t Valid: 1; /* Word 3 */
208 208 #endif
209 209 } CQE_UnsolRcvV1_t;
210 210
211 211 /* Status defines */
212 212 #define RQ_STATUS_SUCCESS 0x10
213 213 #define RQ_STATUS_BUFLEN_EXCEEDED 0x11
214 214 #define RQ_STATUS_NEED_BUFFER 0x12
215 215 #define RQ_STATUS_FRAME_DISCARDED 0x13
216 216
217 217
218 218 typedef struct CQE_XRI_Abort
219 219 {
220 220 #ifdef EMLXS_BIG_ENDIAN
221 221 uint16_t Rsvd1; /* Word 0 */
222 222 uint8_t Status;
223 223 uint8_t Rsvd2;
224 224
225 225 uint32_t rjtStatus; /* Word 1 */
226 226
227 227 uint16_t RemoteXID; /* Word 2 */
228 228 uint16_t XRI;
229 229
230 230 uint32_t Valid: 1; /* Word 3 */
231 231 uint32_t IA: 1;
232 232 uint32_t BR: 1;
233 233 uint32_t EO: 1;
234 234 uint32_t Rsvd3: 4;
235 235 uint32_t Code: 8;
236 236 uint32_t Rsvd4: 16;
237 237 #endif
238 238 #ifdef EMLXS_LITTLE_ENDIAN
239 239 uint8_t Rsvd2;
240 240 uint8_t Status;
241 241 uint16_t Rsvd1; /* Word 0 */
242 242
243 243 uint32_t rjtStatus; /* Word 1 */
244 244
245 245 uint16_t XRI;
246 246 uint16_t RemoteXID; /* Word 2 */
247 247
248 248 uint32_t Rsvd4: 16;
249 249 uint32_t Code: 8;
250 250 uint32_t Rsvd3: 4;
251 251 uint32_t EO: 1;
252 252 uint32_t BR: 1;
253 253 uint32_t IA: 1;
254 254 uint32_t Valid: 1; /* Word 3 */
255 255 #endif
256 256 } CQE_XRI_Abort_t;
257 257
258 258
259 259
260 260 #define CQE_VALID 0x80000000 /* Mask for CQE valid */
261 261
262 262 /* Defines for CQE Codes */
263 263 #define CQE_TYPE_WQ_COMPLETION 1
264 264 #define CQE_TYPE_RELEASE_WQE 2
265 265 #define CQE_TYPE_UNSOL_RCV 4
266 266 #define CQE_TYPE_XRI_ABORTED 5
267 267 #define CQE_TYPE_UNSOL_RCV_V1 9
268 268
269 269
270 270 typedef struct CQE_ASYNC_FCOE
271 271 {
272 272 #ifdef EMLXS_BIG_ENDIAN
273 273 uint32_t ref_index; /* Word 0 */
274 274
275 275 uint16_t evt_type; /* Word 1 */
276 276 uint16_t fcf_count;
277 277
278 278 uint32_t event_tag; /* Word 2 */
279 279 #endif
280 280 #ifdef EMLXS_LITTLE_ENDIAN
281 281 uint32_t ref_index; /* Word 0 */
282 282
283 283 uint16_t fcf_count;
284 284 uint16_t evt_type; /* Word 1 */
285 285
286 286 uint32_t event_tag; /* Word 2 */
287 287 #endif
288 288 } CQE_ASYNC_FCOE_t;
289 289
290 290 typedef struct CQE_ASYNC_LINK_STATE
291 291 {
292 292 #ifdef EMLXS_BIG_ENDIAN
293 293 uint8_t port_speed; /* Word 0 */
294 294 uint8_t port_duplex;
295 295 uint8_t link_status;
296 296 uint8_t phys_port;
297 297
298 298 uint16_t qos_link_speed; /* Word 1 */
299 299 uint8_t Rsvd1;
300 300 uint8_t port_fault;
301 301
302 302 uint32_t event_tag; /* Word 2 */
303 303 #endif
304 304 #ifdef EMLXS_LITTLE_ENDIAN
305 305 uint8_t phys_port;
306 306 uint8_t link_status;
307 307 uint8_t port_duplex;
308 308 uint8_t port_speed; /* Word 0 */
309 309
310 310 uint8_t port_fault; /* Word 1 */
311 311 uint8_t Rsvd1;
312 312 uint16_t qos_link_speed;
313 313
314 314 uint32_t event_tag; /* Word 2 */
315 315 #endif
316 316 } CQE_ASYNC_LINK_STATE_t;
317 317
318 318 typedef struct CQE_ASYNC_GRP_5_QOS
319 319 {
320 320 #ifdef EMLXS_BIG_ENDIAN
321 321 uint8_t Rsvd2;
322 322 uint8_t Rsvd1;
323 323 uint8_t Rsvd0;
324 324 uint8_t phys_port; /* Word 0 */
325 325
326 326 uint16_t qos_link_speed;
327 327 uint8_t Rsvd4;
328 328 uint8_t Rsvd3; /* Word 1 */
329 329
330 330 uint32_t event_tag; /* Word 2 */
331 331 #endif
332 332 #ifdef EMLXS_LITTLE_ENDIAN
333 333 uint8_t phys_port;
334 334 uint8_t Rsvd0;
335 335 uint8_t Rsvd1;
336 336 uint8_t Rsvd2; /* Word 0 */
337 337
338 338 uint8_t Rsvd3;
339 339 uint8_t Rsvd4;
340 340 uint16_t qos_link_speed; /* Word 1 */
341 341
342 342 uint32_t event_tag; /* Word 2 */
343 343 #endif
344 344 } CQE_ASYNC_GRP_5_QOS_t;
345 345
346 346
347 347 typedef struct CQE_ASYNC_FC_LINK_ATT
348 348 {
349 349 #ifdef EMLXS_BIG_ENDIAN
350 350 uint8_t port_speed; /* Word 0 */
351 351 uint8_t topology;
352 352 uint8_t att_type;
353 353 uint8_t link_number;
354 354
355 355 uint16_t link_speed; /* Word 1 */
356 356 uint8_t shared_link_status;
357 357 uint8_t port_fault;
358 358
359 359 uint32_t event_tag; /* Word 2 */
360 360 #endif
361 361 #ifdef EMLXS_LITTLE_ENDIAN
362 362 uint8_t link_number;
363 363 uint8_t att_type;
364 364 uint8_t topology;
365 365 uint8_t port_speed; /* Word 0 */
366 366
367 367 uint8_t port_fault;
368 368 uint8_t shared_link_status;
369 369 uint16_t link_speed; /* Word 1 */
370 370
371 371 uint32_t event_tag; /* Word 2 */
372 372 #endif
373 373 } CQE_ASYNC_FC_LINK_ATT_t;
374 374
375 375 typedef struct CQE_ASYNC_PORT
376 376 {
377 377 uint8_t link_status[4];
378 378 uint32_t data_word2;
379 379 uint32_t Rsvd;
380 380 } CQE_ASYNC_PORT_t;
381 381
382 382 /* topology */
383 383 #define TOPOLOGY_UNKNOWN 0
384 384 #define TOPOLOGY_NPORT 1
385 385 #define TOPOLOGY_LPORT 2
386 386 #define TOPOLOGY_INTERNAL_LB 3
387 387 #define TOPOLOGY_SERDES_LB 4
388 388
389 389 /* att_type */
390 390 #define ATT_TYPE_LINK_UP 1
391 391 #define ATT_TYPE_LINK_DOWN 2
392 392 #define ATT_TYPE_NO_HARD_ALPA 3
393 393
394 394 /* shared_link_status */
395 395 #define SHARED_STATUS_NONE 0
396 396 #define SHARED_STATUS_LD_UNUSABLE 1
397 397 #define SHARED_STATUS_LD_TRAN_FAULT 2
398 398 #define SHARED_STATUS_LD_NO_SIGNAL 3
399 399 #define SHARED_STATUS_LD_MGMT_DISABLED 4
400 400 #define SHARED_STATUS_LU_FAILED_P2P 5
401 401 #define SHARED_STATUS_LU_FAILED_FLOGI_TMO 6
402 402 #define SHARED_STATUS_LU_FAILED_NO_FPORT 7
403 403 #define SHARED_STATUS_LU_FAILED_NO_NPIV 8
404 404 #define SHARED_STATUS_LU_FAILED_FLOGO 9
405 405 #define SHARED_STATUS_LU_LOOPBACK 20
406 406 #define SHARED_STATUS_LU_NORMAL 40
407 407
408 408 /* port_fault */
409 409 #define PORT_FAULT_NONE 0
410 410 #define PORT_FAULT_LOCAL 1
411 411 #define PORT_FAULT_REMOTE 2
412 412
413 413 typedef struct CQE_ASYNC
414 414 {
415 415 /* Words 0-2 */
416 416 union
417 417 {
418 418 CQE_ASYNC_LINK_STATE_t link;
419 419 CQE_ASYNC_FCOE_t fcoe;
420 420 CQE_ASYNC_GRP_5_QOS_t qos;
421 421 CQE_ASYNC_FC_LINK_ATT_t fc;
422 422 CQE_ASYNC_PORT_t port;
423 423 } un;
424 424
425 425 #ifdef EMLXS_BIG_ENDIAN
426 426 uint32_t valid: 1;
427 427 uint32_t async_evt: 1;
428 428 uint32_t Rsvd2: 6;
429 429 uint32_t event_type: 8;
430 430 uint32_t event_code: 8;
431 431 uint32_t Rsvd3: 8; /* Word 3 */
432 432 #endif
433 433 #ifdef EMLXS_LITTLE_ENDIAN
434 434 uint32_t Rsvd3: 8;
435 435 uint32_t event_code: 8;
436 436 uint32_t event_type: 8;
437 437 uint32_t Rsvd2: 6;
438 438 uint32_t async_evt: 1;
439 439 uint32_t valid: 1; /* Word 3 */
440 440 #endif
441 441 } CQE_ASYNC_t;
442 442
443 443 /* port_speed defines */
444 444 #define PHY_1GHZ_LINK 3
445 445 #define PHY_10GHZ_LINK 4
446 446
447 447 /* event_code defines */
448 448 #define ASYNC_EVENT_CODE_FCOE_LINK_STATE 0x01
449 449 #define ASYNC_EVENT_CODE_FCOE_FIP 0x02
450 450 #define ASYNC_EVENT_CODE_DCBX 0x03
451 451 #define ASYNC_EVENT_CODE_ISCSI 0x04
452 452 #define ASYNC_EVENT_CODE_GRP_5 0x05
453 453 #define ASYNC_EVENT_CODE_FC_EVENT 0x10
454 454 #define ASYNC_EVENT_CODE_PORT 0x11
455 455 #define ASYNC_EVENT_CODE_VF 0x12
456 456 #define ASYNC_EVENT_CODE_MR 0x13
457 457
458 458 /* FC Event */
459 459 #define ASYNC_EVENT_FC_LINK_ATT 1
460 460 #define ASYNC_EVENT_FC_SHARED_LINK_ATT 2
461 461
462 462 /* LINK_STATE - link_status defines */
463 463 #define ASYNC_EVENT_PHYS_LINK_DOWN 0
464 464 #define ASYNC_EVENT_PHYS_LINK_UP 1
465 465 #define ASYNC_EVENT_LOGICAL_LINK_DOWN 2
466 466 #define ASYNC_EVENT_LOGICAL_LINK_UP 3
467 467
468 468 /* FCOE_FIP - evt_type defines */
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469 469 #define ASYNC_EVENT_NEW_FCF_DISC 1
470 470 #define ASYNC_EVENT_FCF_TABLE_FULL 2
471 471 #define ASYNC_EVENT_FCF_DEAD 3
472 472 #define ASYNC_EVENT_VIRT_LINK_CLEAR 4
473 473 #define ASYNC_EVENT_FCF_MODIFIED 5
474 474
475 475 /* GRP_5 - evt_type defines */
476 476 #define ASYNC_EVENT_QOS_SPEED 1
477 477
478 478 /* PORT - evt_type defines */
479 +#define ASYNC_EVENT_PORT_OTEMP 2
480 +#define ASYNC_EVENT_PORT_NTEMP 3
479 481 #define ASYNC_EVENT_MISCONFIG_PORT 9
480 482
481 483 typedef struct CQE_MBOX
482 484 {
483 485 #ifdef EMLXS_BIG_ENDIAN
484 486 uint16_t extend_status; /* Word 0 */
485 487 uint16_t cmpl_status;
486 488
487 489 uint32_t tag_low; /* Word 1 */
488 490 uint32_t tag_high; /* Word 2 */
489 491
490 492 uint32_t valid: 1; /* Word 3 */
491 493 uint32_t async_evt: 1;
492 494 uint32_t hpi: 1;
493 495 uint32_t completed: 1;
494 496 uint32_t consumed: 1;
495 497 uint32_t Rsvd1: 27;
496 498 #endif
497 499 #ifdef EMLXS_LITTLE_ENDIAN
498 500 uint16_t cmpl_status;
499 501 uint16_t extend_status; /* Word 0 */
500 502
501 503 uint32_t tag_low; /* Word 1 */
502 504 uint32_t tag_high; /* Word 2 */
503 505
504 506 uint32_t Rsvd1: 27;
505 507 uint32_t consumed: 1;
506 508 uint32_t completed: 1;
507 509 uint32_t hpi: 1;
508 510 uint32_t async_evt: 1;
509 511 uint32_t valid: 1; /* Word 3 */
510 512 #endif
511 513 } CQE_MBOX_t;
512 514
513 515 typedef union
514 516 {
515 517 uint32_t word[4];
516 518
517 519 /* Group 1 types */
518 520 CQE_ASYNC_t cqAsyncEntry;
519 521 CQE_ASYNC_FCOE_t cqAsyncFCOEEntry;
520 522 CQE_MBOX_t cqMboxEntry;
521 523
522 524 /* Group 2 types */
523 525 CQE_CmplWQ_t cqCmplEntry;
524 526 CQE_RelWQ_t cqRelEntry;
525 527 CQE_UnsolRcv_t cqUnsolRcvEntry;
526 528 CQE_UnsolRcvV1_t cqUnsolRcvEntryV1;
527 529 CQE_XRI_Abort_t cqXRIEntry;
528 530 } CQE_u;
529 531
530 532 /* RQ entries */
531 533 typedef struct RQE
532 534 {
533 535 uint32_t AddrHi;
534 536 uint32_t AddrLo;
535 537
536 538 } RQE_t;
537 539
538 540
539 541 /* Definitions for WQEs */
540 542 typedef struct
541 543 {
542 544 /* Word 0 - 2 */
543 545 ULP_BDE64 Payload;
544 546
545 547 /* Word 3 */
546 548 uint32_t PayloadLength;
547 549
548 550 #ifdef EMLXS_BIG_ENDIAN
549 551 /* Word 4 */
550 552 uint32_t Rsvd1: 6;
551 553 uint32_t VF: 1;
552 554 uint32_t SP: 1;
553 555 uint32_t LocalId: 24;
554 556
555 557 /* Word 5 */
556 558 uint32_t Rsvd2: 8;
557 559 uint32_t RemoteId: 24;
558 560 #endif
559 561 #ifdef EMLXS_LITTLE_ENDIAN
560 562 /* Word 4 */
561 563 uint32_t LocalId: 24;
562 564 uint32_t SP: 1;
563 565 uint32_t VF: 1;
564 566 uint32_t Rsvd1: 6;
565 567
566 568 /* Word 5 */
567 569 uint32_t RemoteId: 24;
568 570 uint32_t Rsvd2: 8;
569 571 #endif
570 572
571 573 } ELS_REQ_WQE;
572 574
573 575 typedef struct
574 576 {
575 577 /* Word 0 - 2 */
576 578 ULP_BDE64 Payload;
577 579
578 580 /* Word 3 */
579 581 uint32_t PayloadLength;
580 582
581 583 /* Word 4 */
582 584 uint32_t Rsvd1;
583 585
584 586 #ifdef EMLXS_BIG_ENDIAN
585 587 /* Word 5 */
586 588 uint32_t Rsvd2: 8;
587 589 uint32_t RemoteId: 24;
588 590 #endif
589 591 #ifdef EMLXS_LITTLE_ENDIAN
590 592 /* Word 5 */
591 593 uint32_t RemoteId: 24;
592 594 uint32_t Rsvd2: 8;
593 595 #endif
594 596
595 597 } ELS_RSP_WQE;
596 598
597 599 typedef struct
598 600 {
599 601 /* Word 0 - 2 */
600 602 ULP_BDE64 Payload;
601 603
602 604 /* Word 3 */
603 605 uint32_t PayloadLength;
604 606
605 607 /* Word 4 */
606 608 uint32_t Parameter;
607 609
608 610 #ifdef EMLXS_BIG_ENDIAN
609 611 /* Word 5 */
610 612 uint32_t Rctl: 8;
611 613 uint32_t Type: 8;
612 614 uint32_t DFctl: 8;
613 615 uint32_t Rsvd1: 4;
614 616 uint32_t la: 1;
615 617 uint32_t Rsvd2: 3;
616 618 #endif
617 619 #ifdef EMLXS_LITTLE_ENDIAN
618 620 /* Word 5 */
619 621 uint32_t Rsvd2: 3;
620 622 uint32_t la: 1;
621 623 uint32_t Rsvd1: 4;
622 624 uint32_t DFctl: 8;
623 625 uint32_t Type: 8;
624 626 uint32_t Rctl: 8;
625 627 #endif
626 628
627 629 } GEN_REQ_WQE;
628 630
629 631 typedef struct
630 632 {
631 633 /* Word 0 - 2 */
632 634 ULP_BDE64 Payload;
633 635
634 636 /* Word 3 */
635 637 uint32_t Rsvd0;
636 638
637 639 /* Word 4 */
638 640 uint32_t Parameter;
639 641
640 642 #ifdef EMLXS_BIG_ENDIAN
641 643 /* Word 5 */
642 644 uint32_t Rctl: 8;
643 645 uint32_t Type: 8;
644 646 uint32_t DFctl: 8;
645 647 uint32_t ls: 1;
646 648 uint32_t xo: 1;
647 649 uint32_t Rsvd1: 2;
648 650 uint32_t ft: 1;
649 651 uint32_t si: 1;
650 652 uint32_t Rsvd2: 2;
651 653 #endif
652 654 #ifdef EMLXS_LITTLE_ENDIAN
653 655 /* Word 5 */
654 656 uint32_t Rsvd2: 2;
655 657 uint32_t si: 1;
656 658 uint32_t ft: 1;
657 659 uint32_t Rsvd1: 2;
658 660 uint32_t xo: 1;
659 661 uint32_t ls: 1;
660 662 uint32_t DFctl: 8;
661 663 uint32_t Type: 8;
662 664 uint32_t Rctl: 8;
663 665 #endif
664 666
665 667 } XMIT_SEQ_WQE;
666 668
667 669 typedef struct
668 670 {
669 671 /* Word 0 - 2 */
670 672 ULP_BDE64 Payload;
671 673
672 674 /* Word 3 */
673 675 uint32_t PayloadLength;
674 676
675 677 /* Word 4 */
676 678 uint32_t TotalTransferCount;
677 679
678 680 /* Word 5 */
679 681 uint32_t Rsvd1;
680 682
681 683 } FCP_WQE;
682 684
683 685
684 686 typedef struct
685 687 {
686 688 /* Word 0 - 2 */
687 689 uint32_t Rsvd1[3];
688 690
689 691 #ifdef EMLXS_BIG_ENDIAN
690 692 /* Word 3 */
691 693 uint32_t Rsvd2: 16;
692 694 uint32_t Criteria: 8;
693 695 uint32_t Rsvd3: 7;
694 696 uint32_t IA: 1;
695 697 #endif
696 698 #ifdef EMLXS_LITTLE_ENDIAN
697 699 /* Word 3 */
698 700 uint32_t IA: 1;
699 701 uint32_t Rsvd3: 7;
700 702 uint32_t Criteria: 8;
701 703 uint32_t Rsvd2: 16;
702 704 #endif
703 705
704 706 /* Word 4 - 5 */
705 707 uint32_t Rsvd4[2];
706 708
707 709 } ABORT_WQE;
708 710
709 711 #define ABORT_XRI_TAG 1 /* Abort tag is a XRITag */
710 712 #define ABORT_ABT_TAG 2 /* Abort tag is a AbortTag */
711 713 #define ABORT_REQ_TAG 3 /* Abort tag is a RequestTag */
712 714
713 715 typedef struct
714 716 {
715 717 #ifdef EMLXS_BIG_ENDIAN
716 718 /* Word 0 */
717 719 uint8_t Payload0;
718 720 uint8_t Payload1;
719 721 uint8_t Payload2;
720 722 uint8_t Payload3;
721 723
722 724 /* Word 1 */
723 725 uint32_t OXId: 16;
724 726 uint32_t RXId: 16;
725 727
726 728 /* Word 2 */
727 729 uint32_t SeqCntLow: 16;
728 730 uint32_t SeqCntHigh: 16;
729 731
730 732 /* Word 3 */
731 733 uint32_t Rsvd1;
732 734
733 735 /* Word 4 */
734 736 uint32_t Rsvd2: 8;
735 737 uint32_t LocalId: 24;
736 738
737 739 /* Word 5 */
738 740 uint32_t XO: 1;
739 741 uint32_t AR: 1;
740 742 uint32_t Rsvd3: 6;
741 743 uint32_t RemoteId: 24;
742 744 #endif
743 745 #ifdef EMLXS_LITTLE_ENDIAN
744 746 /* Word 0 */
745 747 uint8_t Payload3;
746 748 uint8_t Payload2;
747 749 uint8_t Payload1;
748 750 uint8_t Payload0;
749 751
750 752 /* Word 1 */
751 753 uint32_t RXId: 16;
752 754 uint32_t OXId: 16;
753 755
754 756 /* Word 2 */
755 757 uint32_t SeqCntHigh: 16;
756 758 uint32_t SeqCntLow: 16;
757 759
758 760 /* Word 3 */
759 761 uint32_t Rsvd1;
760 762
761 763 /* Word 4 */
762 764 uint32_t LocalId: 24;
763 765 uint32_t Rsvd2: 8;
764 766
765 767 /* Word 5 */
766 768 uint32_t RemoteId: 24;
767 769 uint32_t Rsvd3: 6;
768 770 uint32_t AR: 1;
769 771 uint32_t XO: 1;
770 772 #endif
771 773
772 774 } BLS_WQE;
773 775
774 776
775 777 typedef struct
776 778 {
777 779 /* Word 0 - 4 */
778 780 uint32_t Rsvd1[5];
779 781
780 782 #ifdef EMLXS_BIG_ENDIAN
781 783 /* Word 5 */
782 784 uint32_t XO: 1;
783 785 uint32_t Rsvd2: 31;
784 786 #endif
785 787 #ifdef EMLXS_LITTLE_ENDIAN
786 788 /* Word 5 */
787 789 uint32_t Rsvd2: 31;
788 790 uint32_t XO: 1;
789 791 #endif
790 792
791 793 } CREATE_XRI_WQE;
792 794
793 795 typedef struct emlxs_wqe
794 796 {
795 797 /* Words 0-5 */
796 798 union
797 799 {
798 800 uint32_t word[6]; /* Words 0-5: cmd specific */
799 801 ELS_REQ_WQE ElsCmd; /* ELS command overlay */
800 802 GEN_REQ_WQE GenReq; /* CT command overlay */
801 803 FCP_WQE FcpCmd; /* FCP command overlay */
802 804 ELS_RSP_WQE ElsRsp; /* ELS response overlay */
803 805 ABORT_WQE Abort; /* Abort overlay */
804 806 BLS_WQE BlsRsp; /* BLS overlay */
805 807 CREATE_XRI_WQE CreateXri; /* Create XRI */
806 808 XMIT_SEQ_WQE XmitSeq; /* Xmit Sequence */
807 809 } un;
808 810
809 811 #ifdef EMLXS_BIG_ENDIAN
810 812 /* Word 6 */
811 813 uint16_t ContextTag; /* Context Tag */
812 814 uint16_t XRITag; /* XRItag */
813 815 /* Word 7 */
814 816 uint32_t Timer: 8; /* TOV */
815 817 uint32_t Rsvd1: 1;
816 818 uint32_t ERP: 1; /* ERP */
817 819 uint32_t PU: 2; /* PU */
818 820 uint32_t AR: 1; /* Auto Response */
819 821 uint32_t Class: 3; /* COS */
820 822 uint32_t Command: 8; /* Command Code */
821 823 uint32_t Rsvd0: 1;
822 824 uint32_t BsType: 3; /* DIF Block Size type */
823 825 uint32_t ContextType: 2; /* Context Type */
824 826 uint32_t DIF: 2;
825 827 /* Word 8 */
826 828 uint32_t AbortTag; /* Abort Tag */
827 829 /* Word 9 */
828 830 uint16_t OXId; /* OXId on xmitted rsp */
829 831 uint16_t RequestTag; /* Request Tag */
830 832 /* Word 10 */
831 833 uint32_t CCP: 8; /* CCP */
832 834 uint32_t CCPE: 1; /* CCPEnabled */
833 835 uint32_t CMD: 1;
834 836 uint32_t XC: 1; /* Exchange Create */
835 837 uint32_t Rsvd5: 1;
836 838 uint32_t PV: 1; /* PRIValid */
837 839 uint32_t PRI: 3; /* PRI */
838 840 /* The following 16 bits may be */
839 841 /* overwritten by PHWQ */
840 842 uint32_t WQES: 1; /* WQE specify XBL */
841 843 uint32_t DBDE: 1; /* Data type for BDE 0 */
842 844 uint32_t IOd: 1; /* IO direction */
843 845 uint32_t Rsvd4: 1;
844 846 uint32_t XBL: 1; /* Explicit Buffer List */
845 847 uint32_t Rsvd3: 1;
846 848 uint32_t QOSd: 1; /* QOS disable */
847 849 uint32_t LenLoc: 2; /* Length Location */
848 850 uint32_t Rsvd2: 3;
849 851 uint32_t EBDEcnt: 4; /* Extended BDE cnt */
850 852 /* Word 11 */
851 853 uint32_t CQId: 16; /* CompletionQueueID */
852 854 uint32_t Rsvd8: 8;
853 855 uint32_t WQEC: 1; /* Request WQE consumed CQE */
854 856 uint32_t ELSId: 3;
855 857 uint32_t CmdType: 4; /* Command Type */
856 858 #endif
857 859 #ifdef EMLXS_LITTLE_ENDIAN
858 860 /* Word 6 */
859 861 uint16_t XRITag; /* XRItag */
860 862 uint16_t ContextTag; /* Context Tag */
861 863 /* Word 7 */
862 864 uint32_t DIF: 2;
863 865 uint32_t ContextType: 2; /* Context Type */
864 866 uint32_t BsType: 3; /* DIF Block Size type */
865 867 uint32_t Rsvd0: 1;
866 868 uint32_t Command: 8; /* Command Code */
867 869 uint32_t Class: 3; /* COS */
868 870 uint32_t AR: 1; /* Auto Response */
869 871 uint32_t PU: 2; /* PU */
870 872 uint32_t ERP: 1; /* ERP */
871 873 uint32_t Rsvd1: 1;
872 874 uint32_t Timer: 8; /* TOV */
873 875 /* Word 8 */
874 876 uint32_t AbortTag; /* Abort Tag */
875 877 /* Word 9 */
876 878 uint16_t RequestTag; /* Request Tag */
877 879 uint16_t OXId; /* OXId on xmitted rsp */
878 880 /* Word 10 */
879 881 /* The following 16 bits may be */
880 882 /* overwritten by PHWQ */
881 883 uint32_t EBDEcnt: 4; /* Extended BDE cnt */
882 884 uint32_t Rsvd2: 3;
883 885 uint32_t LenLoc: 2; /* Length Location */
884 886 uint32_t QOSd: 1; /* QOS disable */
885 887 uint32_t Rsvd3: 1;
886 888 uint32_t XBL: 1; /* Explicit Buffer List */
887 889 uint32_t Rsvd4: 1;
888 890 uint32_t IOd: 1; /* IO direction */
889 891 uint32_t DBDE: 1; /* Data type for BDE 0 */
890 892 uint32_t WQES: 1; /* WQE specify XBL */
891 893 uint32_t PRI: 3; /* PRI */
892 894 uint32_t PV: 1; /* PRIValid */
893 895 uint32_t Rsvd5: 1;
894 896 uint32_t XC: 1; /* Exchange Create */
895 897 uint32_t CMD: 1;
896 898 uint32_t CCPE: 1; /* CCPEnabled */
897 899 uint32_t CCP: 8; /* CCP */
898 900 /* Word 11 */
899 901 uint32_t CmdType: 4; /* Command Type */
900 902 uint32_t ELSId: 3;
901 903 uint32_t WQEC: 1; /* Request WQE consumed CQE */
902 904 uint32_t Rsvd8: 8;
903 905 uint32_t CQId: 16; /* CompletionQueueID */
904 906 #endif
905 907
906 908 /* Words 12 */
907 909 uint32_t CmdSpecific; /* Command specific information */
908 910
909 911 /* Words 13-15 */
910 912 ULP_BDE64 FirstData;
911 913 } emlxs_wqe_t;
912 914
913 915 /* Used if PHWQ is enabled */
914 916 #ifdef EMLXS_BIG_ENDIAN
915 917 #define WQE_PHWQ_WQID(wqe, qid) *(((uint16_t *)(wqe)) + 21) = \
916 918 ((qid << 1) & 0xfffe);
917 919 #endif
918 920 #ifdef EMLXS_LITTLE_ENDIAN
919 921 #define WQE_PHWQ_WQID(wqe, qid) *(((uint16_t *)(wqe)) + 20) = \
920 922 ((qid << 1) & 0xfffe);
921 923 #endif
922 924
923 925 /* Defines for ContextType */
924 926 #define WQE_RPI_CONTEXT 0
925 927 #define WQE_VPI_CONTEXT 1
926 928 #define WQE_VFI_CONTEXT 2
927 929 #define WQE_FCFI_CONTEXT 3
928 930
929 931 /* Defines for CmdType */
930 932 #define WQE_TYPE_FCP_DATA_IN 0x00
931 933 #define WQE_TYPE_FCP_DATA_OUT 0x01
932 934 #define WQE_TYPE_TRECEIVE 0x02
933 935 #define WQE_TYPE_TRSP 0x03
934 936 #define WQE_TYPE_SRR_RSP 0x06
935 937 #define WQE_TYPE_TSEND 0x07
936 938 #define WQE_TYPE_GEN 0x08
937 939 #define WQE_TYPE_ABORT 0x08
938 940 #define WQE_TYPE_ELS 0x0C
939 941 #define WQE_TYPE_MASK_FIP 0x01
940 942
941 943 /* Defines for ELSId */
942 944 #define WQE_ELSID_PLOGI 0x04
943 945 #define WQE_ELSID_FLOGI 0x03
944 946 #define WQE_ELSID_FDISC 0x02
945 947 #define WQE_ELSID_LOGO 0x01
946 948 #define WQE_ELSID_CMD 0x00
947 949
948 950 /* RQB */
949 951 #define RQB_HEADER_SIZE 32
950 952 #define RQB_DATA_SIZE 2048
951 953 #define RQB_COUNT 256
952 954
953 955 #define EMLXS_NUM_WQ_PAGES 4
954 956 #define WQE_SIZE 64
955 957
956 958 #define EMLXS_NUM_CQ_PAGES_V2 4
957 959 #define CQE_SIZE 16
958 960
959 961 #define EQ_DEPTH 1024
960 962 #define CQ_DEPTH 256
961 963 #define CQ_DEPTH_V2 ((4096/CQE_SIZE) * EMLXS_NUM_CQ_PAGES_V2) /* 1024 */
962 964 #define WQ_DEPTH ((4096/WQE_SIZE) * EMLXS_NUM_WQ_PAGES) /* 256 */
963 965 #define MQ_DEPTH 16
964 966 #define RQ_DEPTH 512 /* Multiple of RQB_COUNT */
965 967 #define RQ_DEPTH_EXPONENT 9
966 968
967 969 #define EMLXS_MAX_WQS_PER_EQ 4
968 970
969 971
970 972 /* Principal doorbell register layouts */
971 973 typedef struct emlxs_rqdb
972 974 {
973 975 #ifdef EMLXS_BIG_ENDIAN
974 976 uint32_t Rsvd2:2;
975 977 uint32_t NumPosted:14; /* Number of entries posted */
976 978 uint32_t Rsvd1:6;
977 979 uint32_t Qid:10; /* RQ id for posted RQE */
978 980 #endif /* EMLXS_BIG_ENDIAN */
979 981
980 982 #ifdef EMLXS_LITTLE_ENDIAN
981 983 uint32_t Qid:10; /* RQ id for posted RQE */
982 984 uint32_t Rsvd1:6;
983 985 uint32_t NumPosted:14; /* Number of entries posted */
984 986 uint32_t Rsvd2:2;
985 987 #endif /* EMLXS_LITTLE_ENDIAN */
986 988
987 989 } emlxs_rqdb_t;
988 990
989 991
990 992 typedef union emlxs_rqdbu
991 993 {
992 994 uint32_t word;
993 995 emlxs_rqdb_t db;
994 996
995 997 } emlxs_rqdbu_t;
996 998
997 999
998 1000 typedef struct emlxs_wqdb
999 1001 {
1000 1002 #ifdef EMLXS_BIG_ENDIAN
1001 1003 uint32_t NumPosted:8; /* Number of entries posted */
1002 1004 uint32_t Index:8; /* Queue index for posted command */
1003 1005 uint32_t Rsvd1:6;
1004 1006 uint32_t Qid:10; /* WQ id for posted WQE */
1005 1007 #endif /* EMLXS_BIG_ENDIAN */
1006 1008
1007 1009 #ifdef EMLXS_LITTLE_ENDIAN
1008 1010 uint32_t Qid:10; /* WQ id for posted WQE */
1009 1011 uint32_t Rsvd1:6;
1010 1012 uint32_t Index:8; /* Queue index for posted command */
1011 1013 uint32_t NumPosted:8; /* Number of entries posted */
1012 1014 #endif /* EMLXS_LITTLE_ENDIAN */
1013 1015
1014 1016 } emlxs_wqdb_t;
1015 1017
1016 1018
1017 1019 typedef union emlxs_wqdbu
1018 1020 {
1019 1021 uint32_t word;
1020 1022 emlxs_wqdb_t db;
1021 1023
1022 1024 } emlxs_wqdbu_t;
1023 1025
1024 1026
1025 1027 typedef struct emlxs_cqdb
1026 1028 {
1027 1029 #ifdef EMLXS_BIG_ENDIAN
1028 1030 uint32_t NumPosted:2; /* Number of entries posted */
1029 1031 uint32_t Rearm:1; /* Rearm CQ */
1030 1032 uint32_t NumPopped:13; /* Number of CQ entries processed */
1031 1033 uint32_t Rsvd1:5;
1032 1034 uint32_t Event:1; /* 1 if processed entry is EQE */
1033 1035 /* 0 if processed entry is CQE */
1034 1036 uint32_t Qid:10; /* CQ id for posted CQE */
1035 1037 #endif /* EMLXS_BIG_ENDIAN */
1036 1038
1037 1039 #ifdef EMLXS_LITTLE_ENDIAN
1038 1040 uint32_t Qid:10; /* CQ id for posted CQE */
1039 1041 uint32_t Event:1; /* 1 if processed entry is EQE */
1040 1042 /* 0 if processed entry is CQE */
1041 1043 uint32_t Rsvd1:5;
1042 1044 uint32_t NumPopped:13; /* Number of CQ entries processed */
1043 1045 uint32_t Rearm:1; /* Rearm CQ */
1044 1046 uint32_t NumPosted:2; /* Number of entries posted */
1045 1047 #endif /* EMLXS_LITTLE_ENDIAN */
1046 1048
1047 1049 } emlxs_cqdb_t;
1048 1050
1049 1051
1050 1052 typedef union emlxs_cqdbu
1051 1053 {
1052 1054 uint32_t word;
1053 1055 emlxs_cqdb_t db;
1054 1056
1055 1057 } emlxs_cqdbu_t;
1056 1058
1057 1059 typedef struct emlxs_eqdb
1058 1060 {
1059 1061 #ifdef EMLXS_BIG_ENDIAN
1060 1062 uint32_t Rsvd2:2;
1061 1063 uint32_t Rearm:1; /* Rearm EQ */
1062 1064 uint32_t NumPopped:13; /* Number of CQ entries processed */
1063 1065 uint32_t Rsvd1:5;
1064 1066 uint32_t Event:1; /* True iff processed entry is EQE */
1065 1067 uint32_t Clear:1; /* clears EQ interrupt when set */
1066 1068 uint32_t Qid:9; /* EQ id for posted EQE */
1067 1069 #endif /* EMLXS_BIG_ENDIAN */
1068 1070
1069 1071 #ifdef EMLXS_LITTLE_ENDIAN
1070 1072 uint32_t Qid:9; /* EQ id for posted EQE */
1071 1073 uint32_t Clear:1; /* clears EQ interrupt when set */
1072 1074 uint32_t Event:1; /* True iff processed entry is EQE */
1073 1075 uint32_t Rsvd1:5;
1074 1076 uint32_t NumPopped:13; /* Number of CQ entries processed */
1075 1077 uint32_t Rearm:1; /* Rearm EQ */
1076 1078 uint32_t Rsvd2:2;
1077 1079 #endif /* EMLXS_LITTLE_ENDIAN */
1078 1080
1079 1081 } emlxs_eqdb_t;
1080 1082
1081 1083
1082 1084 typedef union emlxs_eqdbu
1083 1085 {
1084 1086 uint32_t word;
1085 1087 emlxs_eqdb_t db;
1086 1088
1087 1089 } emlxs_eqdbu_t;
1088 1090
1089 1091
1090 1092 typedef struct emlxs_mqdb
1091 1093 {
1092 1094 #ifdef EMLXS_BIG_ENDIAN
1093 1095 uint32_t Rsvd2:2;
1094 1096 uint32_t NumPosted:14; /* Number of entries posted */
1095 1097 uint32_t Rsvd1:5;
1096 1098 uint32_t Qid:11; /* MQ id for posted MQE */
1097 1099 #endif /* EMLXS_BIG_ENDIAN */
1098 1100
1099 1101 #ifdef EMLXS_LITTLE_ENDIAN
1100 1102 uint32_t Qid:11; /* MQ id for posted MQE */
1101 1103 uint32_t Rsvd1:5;
1102 1104 uint32_t NumPosted:14; /* Number of entries posted */
1103 1105 uint32_t Rsvd2:2;
1104 1106 #endif /* EMLXS_LITTLE_ENDIAN */
1105 1107
1106 1108 } emlxs_mqdb_t;
1107 1109
1108 1110
1109 1111 typedef union emlxs_mqdbu
1110 1112 {
1111 1113 uint32_t word;
1112 1114 emlxs_mqdb_t db;
1113 1115
1114 1116 } emlxs_mqdbu_t;
1115 1117
1116 1118
1117 1119 #ifdef __cplusplus
1118 1120 }
1119 1121 #endif
1120 1122
1121 1123 #endif /* _EMLXS_QUEUE_H */
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