1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _EMLXS_QUEUE_H
28 #define _EMLXS_QUEUE_H
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34
35 /* Queue entry defines */
36
37 /* EQ entries */
38 typedef struct EQE
39 {
40 #ifdef EMLXS_BIG_ENDIAN
41 uint32_t CQId: 16;
42 uint32_t MinorCode: 12;
43 uint32_t MajorCode: 3;
44 uint32_t Valid: 1;
45 #endif
46 #ifdef EMLXS_LITTLE_ENDIAN
47 uint32_t Valid: 1;
48 uint32_t MajorCode: 3;
49 uint32_t MinorCode: 12;
50 uint32_t CQId: 16;
51 #endif
52
53 } EQE_t;
54
55 typedef union
56 {
57 uint32_t word;
58 EQE_t entry;
59
60 } EQE_u;
61
62 #define EQE_VALID 0x00000001 /* Mask for EQE valid */
63 #define EQE_CQID 0xFFFF0000 /* Mask for EQE CQID */
64
65 /* CQ entries */
66 typedef struct CQE_CmplWQ
67 {
68 #ifdef EMLXS_BIG_ENDIAN
69 uint16_t RequestTag; /* Word 0 */
70 uint8_t Status;
71 uint8_t hw_status;
72
73 uint32_t CmdSpecific; /* Word 1 */
74 uint32_t Parameter; /* Word 2 */
75
76 uint32_t Valid: 1; /* Word 3 */
77 uint32_t Rsvd1: 2;
78 uint32_t XB: 1;
79 uint32_t PV: 1;
80 uint32_t Priority: 3;
81 uint32_t Code: 8;
82 uint32_t Rsvd2: 16;
83 #endif
84 #ifdef EMLXS_LITTLE_ENDIAN
85 uint8_t hw_status;
86 uint8_t Status;
87 uint16_t RequestTag; /* Word 0 */
88
89 uint32_t CmdSpecific; /* Word 1 */
90 uint32_t Parameter; /* Word 2 */
91
92 uint32_t Rsvd2: 16;
93 uint32_t Code: 8;
94 uint32_t Priority: 3;
95 uint32_t PV: 1;
96 uint32_t XB: 1;
97 uint32_t Rsvd1: 2;
98 uint32_t Valid: 1; /* Word 3 */
99 #endif
100 } CQE_CmplWQ_t;
101
102 typedef struct CQE_RelWQ
103 {
104 #ifdef EMLXS_BIG_ENDIAN
105 uint32_t Reserved1; /* Word 0 */
106 uint32_t Reserved2; /* Word 1 */
107
108 uint16_t WQid; /* Word 2 */
109 uint16_t WQindex;
110
111 uint32_t Valid: 1; /* Word 3 */
112 uint32_t Rsvd1: 7;
113 uint32_t Code: 8;
114 uint32_t Rsvd2: 16;
115 #endif
116 #ifdef EMLXS_LITTLE_ENDIAN
117 uint32_t Reserved1; /* Word 0 */
118 uint32_t Reserved2; /* Word 1 */
119
120 uint16_t WQindex;
121 uint16_t WQid; /* Word 2 */
122
123 uint32_t Rsvd2: 16;
124 uint32_t Code: 8;
125 uint32_t Rsvd1: 7;
126 uint32_t Valid: 1; /* Word 3 */
127 #endif
128 } CQE_RelWQ_t;
129
130 typedef struct CQE_UnsolRcv
131 {
132 #ifdef EMLXS_BIG_ENDIAN
133 uint16_t RQindex; /* Word 0 */
134 uint8_t Status;
135 uint8_t Rsvd1;
136
137 uint32_t Rsvd2; /* Word 1 */
138
139 uint32_t data_size: 16; /* Word 2 */
140 uint32_t RQid: 10;
141 uint32_t FCFId: 6;
142
143 uint32_t Valid: 1; /* Word 3 */
144 uint32_t Rsvd3: 1;
145 uint32_t hdr_size: 6;
146 uint32_t Code: 8;
147 uint32_t eof: 8;
148 uint32_t sof: 8;
149 #endif
150 #ifdef EMLXS_LITTLE_ENDIAN
151 uint8_t Rsvd1;
152 uint8_t Status;
153 uint16_t RQindex; /* Word 0 */
154
155 uint32_t Rsvd2; /* Word 1 */
156
157 uint32_t FCFId: 6;
158 uint32_t RQid: 10;
159 uint32_t data_size: 16; /* Word 2 */
160
161 uint32_t sof: 8;
162 uint32_t eof: 8;
163 uint32_t Code: 8;
164 uint32_t hdr_size: 6;
165 uint32_t Rsvd3: 1;
166 uint32_t Valid: 1; /* Word 3 */
167 #endif
168 } CQE_UnsolRcv_t;
169
170
171 typedef struct CQE_UnsolRcvV1
172 {
173 #ifdef EMLXS_BIG_ENDIAN
174 uint16_t RQindex; /* Word 0 */
175 uint8_t Status;
176 uint8_t Rsvd1;
177
178 uint32_t Rsvd2: 26; /* Word 1 */
179 uint32_t FCFId: 6;
180
181 uint16_t data_size; /* Word 2 */
182 uint16_t RQid;
183
184 uint32_t Valid: 1; /* Word 3 */
185 uint32_t Rsvd3: 1;
186 uint32_t hdr_size: 6;
187 uint32_t Code: 8;
188 uint32_t eof: 8;
189 uint32_t sof: 8;
190 #endif
191 #ifdef EMLXS_LITTLE_ENDIAN
192 uint8_t Rsvd1;
193 uint8_t Status;
194 uint16_t RQindex; /* Word 0 */
195
196 uint32_t FCFId: 6;
197 uint32_t Rsvd2: 26; /* Word 1 */
198
199 uint16_t RQid;
200 uint16_t data_size; /* Word 2 */
201
202 uint32_t sof: 8;
203 uint32_t eof: 8;
204 uint32_t Code: 8;
205 uint32_t hdr_size: 6;
206 uint32_t Rsvd3: 1;
207 uint32_t Valid: 1; /* Word 3 */
208 #endif
209 } CQE_UnsolRcvV1_t;
210
211 /* Status defines */
212 #define RQ_STATUS_SUCCESS 0x10
213 #define RQ_STATUS_BUFLEN_EXCEEDED 0x11
214 #define RQ_STATUS_NEED_BUFFER 0x12
215 #define RQ_STATUS_FRAME_DISCARDED 0x13
216
217
218 typedef struct CQE_XRI_Abort
219 {
220 #ifdef EMLXS_BIG_ENDIAN
221 uint16_t Rsvd1; /* Word 0 */
222 uint8_t Status;
223 uint8_t Rsvd2;
224
225 uint32_t rjtStatus; /* Word 1 */
226
227 uint16_t RemoteXID; /* Word 2 */
228 uint16_t XRI;
229
230 uint32_t Valid: 1; /* Word 3 */
231 uint32_t IA: 1;
232 uint32_t BR: 1;
233 uint32_t EO: 1;
234 uint32_t Rsvd3: 4;
235 uint32_t Code: 8;
236 uint32_t Rsvd4: 16;
237 #endif
238 #ifdef EMLXS_LITTLE_ENDIAN
239 uint8_t Rsvd2;
240 uint8_t Status;
241 uint16_t Rsvd1; /* Word 0 */
242
243 uint32_t rjtStatus; /* Word 1 */
244
245 uint16_t XRI;
246 uint16_t RemoteXID; /* Word 2 */
247
248 uint32_t Rsvd4: 16;
249 uint32_t Code: 8;
250 uint32_t Rsvd3: 4;
251 uint32_t EO: 1;
252 uint32_t BR: 1;
253 uint32_t IA: 1;
254 uint32_t Valid: 1; /* Word 3 */
255 #endif
256 } CQE_XRI_Abort_t;
257
258
259
260 #define CQE_VALID 0x80000000 /* Mask for CQE valid */
261
262 /* Defines for CQE Codes */
263 #define CQE_TYPE_WQ_COMPLETION 1
264 #define CQE_TYPE_RELEASE_WQE 2
265 #define CQE_TYPE_UNSOL_RCV 4
266 #define CQE_TYPE_XRI_ABORTED 5
267 #define CQE_TYPE_UNSOL_RCV_V1 9
268
269
270 typedef struct CQE_ASYNC_FCOE
271 {
272 #ifdef EMLXS_BIG_ENDIAN
273 uint32_t ref_index; /* Word 0 */
274
275 uint16_t evt_type; /* Word 1 */
276 uint16_t fcf_count;
277
278 uint32_t event_tag; /* Word 2 */
279 #endif
280 #ifdef EMLXS_LITTLE_ENDIAN
281 uint32_t ref_index; /* Word 0 */
282
283 uint16_t fcf_count;
284 uint16_t evt_type; /* Word 1 */
285
286 uint32_t event_tag; /* Word 2 */
287 #endif
288 } CQE_ASYNC_FCOE_t;
289
290 typedef struct CQE_ASYNC_LINK_STATE
291 {
292 #ifdef EMLXS_BIG_ENDIAN
293 uint8_t port_speed; /* Word 0 */
294 uint8_t port_duplex;
295 uint8_t link_status;
296 uint8_t phys_port;
297
298 uint16_t qos_link_speed; /* Word 1 */
299 uint8_t Rsvd1;
300 uint8_t port_fault;
301
302 uint32_t event_tag; /* Word 2 */
303 #endif
304 #ifdef EMLXS_LITTLE_ENDIAN
305 uint8_t phys_port;
306 uint8_t link_status;
307 uint8_t port_duplex;
308 uint8_t port_speed; /* Word 0 */
309
310 uint8_t port_fault; /* Word 1 */
311 uint8_t Rsvd1;
312 uint16_t qos_link_speed;
313
314 uint32_t event_tag; /* Word 2 */
315 #endif
316 } CQE_ASYNC_LINK_STATE_t;
317
318 typedef struct CQE_ASYNC_GRP_5_QOS
319 {
320 #ifdef EMLXS_BIG_ENDIAN
321 uint8_t Rsvd2;
322 uint8_t Rsvd1;
323 uint8_t Rsvd0;
324 uint8_t phys_port; /* Word 0 */
325
326 uint16_t qos_link_speed;
327 uint8_t Rsvd4;
328 uint8_t Rsvd3; /* Word 1 */
329
330 uint32_t event_tag; /* Word 2 */
331 #endif
332 #ifdef EMLXS_LITTLE_ENDIAN
333 uint8_t phys_port;
334 uint8_t Rsvd0;
335 uint8_t Rsvd1;
336 uint8_t Rsvd2; /* Word 0 */
337
338 uint8_t Rsvd3;
339 uint8_t Rsvd4;
340 uint16_t qos_link_speed; /* Word 1 */
341
342 uint32_t event_tag; /* Word 2 */
343 #endif
344 } CQE_ASYNC_GRP_5_QOS_t;
345
346
347 typedef struct CQE_ASYNC_FC_LINK_ATT
348 {
349 #ifdef EMLXS_BIG_ENDIAN
350 uint8_t port_speed; /* Word 0 */
351 uint8_t topology;
352 uint8_t att_type;
353 uint8_t link_number;
354
355 uint16_t link_speed; /* Word 1 */
356 uint8_t shared_link_status;
357 uint8_t port_fault;
358
359 uint32_t event_tag; /* Word 2 */
360 #endif
361 #ifdef EMLXS_LITTLE_ENDIAN
362 uint8_t link_number;
363 uint8_t att_type;
364 uint8_t topology;
365 uint8_t port_speed; /* Word 0 */
366
367 uint8_t port_fault;
368 uint8_t shared_link_status;
369 uint16_t link_speed; /* Word 1 */
370
371 uint32_t event_tag; /* Word 2 */
372 #endif
373 } CQE_ASYNC_FC_LINK_ATT_t;
374
375 typedef struct CQE_ASYNC_PORT
376 {
377 uint8_t link_status[4];
378 uint32_t data_word2;
379 uint32_t Rsvd;
380 } CQE_ASYNC_PORT_t;
381
382 /* topology */
383 #define TOPOLOGY_UNKNOWN 0
384 #define TOPOLOGY_NPORT 1
385 #define TOPOLOGY_LPORT 2
386 #define TOPOLOGY_INTERNAL_LB 3
387 #define TOPOLOGY_SERDES_LB 4
388
389 /* att_type */
390 #define ATT_TYPE_LINK_UP 1
391 #define ATT_TYPE_LINK_DOWN 2
392 #define ATT_TYPE_NO_HARD_ALPA 3
393
394 /* shared_link_status */
395 #define SHARED_STATUS_NONE 0
396 #define SHARED_STATUS_LD_UNUSABLE 1
397 #define SHARED_STATUS_LD_TRAN_FAULT 2
398 #define SHARED_STATUS_LD_NO_SIGNAL 3
399 #define SHARED_STATUS_LD_MGMT_DISABLED 4
400 #define SHARED_STATUS_LU_FAILED_P2P 5
401 #define SHARED_STATUS_LU_FAILED_FLOGI_TMO 6
402 #define SHARED_STATUS_LU_FAILED_NO_FPORT 7
403 #define SHARED_STATUS_LU_FAILED_NO_NPIV 8
404 #define SHARED_STATUS_LU_FAILED_FLOGO 9
405 #define SHARED_STATUS_LU_LOOPBACK 20
406 #define SHARED_STATUS_LU_NORMAL 40
407
408 /* port_fault */
409 #define PORT_FAULT_NONE 0
410 #define PORT_FAULT_LOCAL 1
411 #define PORT_FAULT_REMOTE 2
412
413 typedef struct CQE_ASYNC
414 {
415 /* Words 0-2 */
416 union
417 {
418 CQE_ASYNC_LINK_STATE_t link;
419 CQE_ASYNC_FCOE_t fcoe;
420 CQE_ASYNC_GRP_5_QOS_t qos;
421 CQE_ASYNC_FC_LINK_ATT_t fc;
422 CQE_ASYNC_PORT_t port;
423 } un;
424
425 #ifdef EMLXS_BIG_ENDIAN
426 uint32_t valid: 1;
427 uint32_t async_evt: 1;
428 uint32_t Rsvd2: 6;
429 uint32_t event_type: 8;
430 uint32_t event_code: 8;
431 uint32_t Rsvd3: 8; /* Word 3 */
432 #endif
433 #ifdef EMLXS_LITTLE_ENDIAN
434 uint32_t Rsvd3: 8;
435 uint32_t event_code: 8;
436 uint32_t event_type: 8;
437 uint32_t Rsvd2: 6;
438 uint32_t async_evt: 1;
439 uint32_t valid: 1; /* Word 3 */
440 #endif
441 } CQE_ASYNC_t;
442
443 /* port_speed defines */
444 #define PHY_1GHZ_LINK 3
445 #define PHY_10GHZ_LINK 4
446
447 /* event_code defines */
448 #define ASYNC_EVENT_CODE_FCOE_LINK_STATE 0x01
449 #define ASYNC_EVENT_CODE_FCOE_FIP 0x02
450 #define ASYNC_EVENT_CODE_DCBX 0x03
451 #define ASYNC_EVENT_CODE_ISCSI 0x04
452 #define ASYNC_EVENT_CODE_GRP_5 0x05
453 #define ASYNC_EVENT_CODE_FC_EVENT 0x10
454 #define ASYNC_EVENT_CODE_PORT 0x11
455 #define ASYNC_EVENT_CODE_VF 0x12
456 #define ASYNC_EVENT_CODE_MR 0x13
457
458 /* FC Event */
459 #define ASYNC_EVENT_FC_LINK_ATT 1
460 #define ASYNC_EVENT_FC_SHARED_LINK_ATT 2
461
462 /* LINK_STATE - link_status defines */
463 #define ASYNC_EVENT_PHYS_LINK_DOWN 0
464 #define ASYNC_EVENT_PHYS_LINK_UP 1
465 #define ASYNC_EVENT_LOGICAL_LINK_DOWN 2
466 #define ASYNC_EVENT_LOGICAL_LINK_UP 3
467
468 /* FCOE_FIP - evt_type defines */
469 #define ASYNC_EVENT_NEW_FCF_DISC 1
470 #define ASYNC_EVENT_FCF_TABLE_FULL 2
471 #define ASYNC_EVENT_FCF_DEAD 3
472 #define ASYNC_EVENT_VIRT_LINK_CLEAR 4
473 #define ASYNC_EVENT_FCF_MODIFIED 5
474
475 /* GRP_5 - evt_type defines */
476 #define ASYNC_EVENT_QOS_SPEED 1
477
478 /* PORT - evt_type defines */
479 #define ASYNC_EVENT_PORT_OTEMP 2
480 #define ASYNC_EVENT_PORT_NTEMP 3
481 #define ASYNC_EVENT_MISCONFIG_PORT 9
482
483 typedef struct CQE_MBOX
484 {
485 #ifdef EMLXS_BIG_ENDIAN
486 uint16_t extend_status; /* Word 0 */
487 uint16_t cmpl_status;
488
489 uint32_t tag_low; /* Word 1 */
490 uint32_t tag_high; /* Word 2 */
491
492 uint32_t valid: 1; /* Word 3 */
493 uint32_t async_evt: 1;
494 uint32_t hpi: 1;
495 uint32_t completed: 1;
496 uint32_t consumed: 1;
497 uint32_t Rsvd1: 27;
498 #endif
499 #ifdef EMLXS_LITTLE_ENDIAN
500 uint16_t cmpl_status;
501 uint16_t extend_status; /* Word 0 */
502
503 uint32_t tag_low; /* Word 1 */
504 uint32_t tag_high; /* Word 2 */
505
506 uint32_t Rsvd1: 27;
507 uint32_t consumed: 1;
508 uint32_t completed: 1;
509 uint32_t hpi: 1;
510 uint32_t async_evt: 1;
511 uint32_t valid: 1; /* Word 3 */
512 #endif
513 } CQE_MBOX_t;
514
515 typedef union
516 {
517 uint32_t word[4];
518
519 /* Group 1 types */
520 CQE_ASYNC_t cqAsyncEntry;
521 CQE_ASYNC_FCOE_t cqAsyncFCOEEntry;
522 CQE_MBOX_t cqMboxEntry;
523
524 /* Group 2 types */
525 CQE_CmplWQ_t cqCmplEntry;
526 CQE_RelWQ_t cqRelEntry;
527 CQE_UnsolRcv_t cqUnsolRcvEntry;
528 CQE_UnsolRcvV1_t cqUnsolRcvEntryV1;
529 CQE_XRI_Abort_t cqXRIEntry;
530 } CQE_u;
531
532 /* RQ entries */
533 typedef struct RQE
534 {
535 uint32_t AddrHi;
536 uint32_t AddrLo;
537
538 } RQE_t;
539
540
541 /* Definitions for WQEs */
542 typedef struct
543 {
544 /* Word 0 - 2 */
545 ULP_BDE64 Payload;
546
547 /* Word 3 */
548 uint32_t PayloadLength;
549
550 #ifdef EMLXS_BIG_ENDIAN
551 /* Word 4 */
552 uint32_t Rsvd1: 6;
553 uint32_t VF: 1;
554 uint32_t SP: 1;
555 uint32_t LocalId: 24;
556
557 /* Word 5 */
558 uint32_t Rsvd2: 8;
559 uint32_t RemoteId: 24;
560 #endif
561 #ifdef EMLXS_LITTLE_ENDIAN
562 /* Word 4 */
563 uint32_t LocalId: 24;
564 uint32_t SP: 1;
565 uint32_t VF: 1;
566 uint32_t Rsvd1: 6;
567
568 /* Word 5 */
569 uint32_t RemoteId: 24;
570 uint32_t Rsvd2: 8;
571 #endif
572
573 } ELS_REQ_WQE;
574
575 typedef struct
576 {
577 /* Word 0 - 2 */
578 ULP_BDE64 Payload;
579
580 /* Word 3 */
581 uint32_t PayloadLength;
582
583 /* Word 4 */
584 uint32_t Rsvd1;
585
586 #ifdef EMLXS_BIG_ENDIAN
587 /* Word 5 */
588 uint32_t Rsvd2: 8;
589 uint32_t RemoteId: 24;
590 #endif
591 #ifdef EMLXS_LITTLE_ENDIAN
592 /* Word 5 */
593 uint32_t RemoteId: 24;
594 uint32_t Rsvd2: 8;
595 #endif
596
597 } ELS_RSP_WQE;
598
599 typedef struct
600 {
601 /* Word 0 - 2 */
602 ULP_BDE64 Payload;
603
604 /* Word 3 */
605 uint32_t PayloadLength;
606
607 /* Word 4 */
608 uint32_t Parameter;
609
610 #ifdef EMLXS_BIG_ENDIAN
611 /* Word 5 */
612 uint32_t Rctl: 8;
613 uint32_t Type: 8;
614 uint32_t DFctl: 8;
615 uint32_t Rsvd1: 4;
616 uint32_t la: 1;
617 uint32_t Rsvd2: 3;
618 #endif
619 #ifdef EMLXS_LITTLE_ENDIAN
620 /* Word 5 */
621 uint32_t Rsvd2: 3;
622 uint32_t la: 1;
623 uint32_t Rsvd1: 4;
624 uint32_t DFctl: 8;
625 uint32_t Type: 8;
626 uint32_t Rctl: 8;
627 #endif
628
629 } GEN_REQ_WQE;
630
631 typedef struct
632 {
633 /* Word 0 - 2 */
634 ULP_BDE64 Payload;
635
636 /* Word 3 */
637 uint32_t Rsvd0;
638
639 /* Word 4 */
640 uint32_t Parameter;
641
642 #ifdef EMLXS_BIG_ENDIAN
643 /* Word 5 */
644 uint32_t Rctl: 8;
645 uint32_t Type: 8;
646 uint32_t DFctl: 8;
647 uint32_t ls: 1;
648 uint32_t xo: 1;
649 uint32_t Rsvd1: 2;
650 uint32_t ft: 1;
651 uint32_t si: 1;
652 uint32_t Rsvd2: 2;
653 #endif
654 #ifdef EMLXS_LITTLE_ENDIAN
655 /* Word 5 */
656 uint32_t Rsvd2: 2;
657 uint32_t si: 1;
658 uint32_t ft: 1;
659 uint32_t Rsvd1: 2;
660 uint32_t xo: 1;
661 uint32_t ls: 1;
662 uint32_t DFctl: 8;
663 uint32_t Type: 8;
664 uint32_t Rctl: 8;
665 #endif
666
667 } XMIT_SEQ_WQE;
668
669 typedef struct
670 {
671 /* Word 0 - 2 */
672 ULP_BDE64 Payload;
673
674 /* Word 3 */
675 uint32_t PayloadLength;
676
677 /* Word 4 */
678 uint32_t TotalTransferCount;
679
680 /* Word 5 */
681 uint32_t Rsvd1;
682
683 } FCP_WQE;
684
685
686 typedef struct
687 {
688 /* Word 0 - 2 */
689 uint32_t Rsvd1[3];
690
691 #ifdef EMLXS_BIG_ENDIAN
692 /* Word 3 */
693 uint32_t Rsvd2: 16;
694 uint32_t Criteria: 8;
695 uint32_t Rsvd3: 7;
696 uint32_t IA: 1;
697 #endif
698 #ifdef EMLXS_LITTLE_ENDIAN
699 /* Word 3 */
700 uint32_t IA: 1;
701 uint32_t Rsvd3: 7;
702 uint32_t Criteria: 8;
703 uint32_t Rsvd2: 16;
704 #endif
705
706 /* Word 4 - 5 */
707 uint32_t Rsvd4[2];
708
709 } ABORT_WQE;
710
711 #define ABORT_XRI_TAG 1 /* Abort tag is a XRITag */
712 #define ABORT_ABT_TAG 2 /* Abort tag is a AbortTag */
713 #define ABORT_REQ_TAG 3 /* Abort tag is a RequestTag */
714
715 typedef struct
716 {
717 #ifdef EMLXS_BIG_ENDIAN
718 /* Word 0 */
719 uint8_t Payload0;
720 uint8_t Payload1;
721 uint8_t Payload2;
722 uint8_t Payload3;
723
724 /* Word 1 */
725 uint32_t OXId: 16;
726 uint32_t RXId: 16;
727
728 /* Word 2 */
729 uint32_t SeqCntLow: 16;
730 uint32_t SeqCntHigh: 16;
731
732 /* Word 3 */
733 uint32_t Rsvd1;
734
735 /* Word 4 */
736 uint32_t Rsvd2: 8;
737 uint32_t LocalId: 24;
738
739 /* Word 5 */
740 uint32_t XO: 1;
741 uint32_t AR: 1;
742 uint32_t Rsvd3: 6;
743 uint32_t RemoteId: 24;
744 #endif
745 #ifdef EMLXS_LITTLE_ENDIAN
746 /* Word 0 */
747 uint8_t Payload3;
748 uint8_t Payload2;
749 uint8_t Payload1;
750 uint8_t Payload0;
751
752 /* Word 1 */
753 uint32_t RXId: 16;
754 uint32_t OXId: 16;
755
756 /* Word 2 */
757 uint32_t SeqCntHigh: 16;
758 uint32_t SeqCntLow: 16;
759
760 /* Word 3 */
761 uint32_t Rsvd1;
762
763 /* Word 4 */
764 uint32_t LocalId: 24;
765 uint32_t Rsvd2: 8;
766
767 /* Word 5 */
768 uint32_t RemoteId: 24;
769 uint32_t Rsvd3: 6;
770 uint32_t AR: 1;
771 uint32_t XO: 1;
772 #endif
773
774 } BLS_WQE;
775
776
777 typedef struct
778 {
779 /* Word 0 - 4 */
780 uint32_t Rsvd1[5];
781
782 #ifdef EMLXS_BIG_ENDIAN
783 /* Word 5 */
784 uint32_t XO: 1;
785 uint32_t Rsvd2: 31;
786 #endif
787 #ifdef EMLXS_LITTLE_ENDIAN
788 /* Word 5 */
789 uint32_t Rsvd2: 31;
790 uint32_t XO: 1;
791 #endif
792
793 } CREATE_XRI_WQE;
794
795 typedef struct emlxs_wqe
796 {
797 /* Words 0-5 */
798 union
799 {
800 uint32_t word[6]; /* Words 0-5: cmd specific */
801 ELS_REQ_WQE ElsCmd; /* ELS command overlay */
802 GEN_REQ_WQE GenReq; /* CT command overlay */
803 FCP_WQE FcpCmd; /* FCP command overlay */
804 ELS_RSP_WQE ElsRsp; /* ELS response overlay */
805 ABORT_WQE Abort; /* Abort overlay */
806 BLS_WQE BlsRsp; /* BLS overlay */
807 CREATE_XRI_WQE CreateXri; /* Create XRI */
808 XMIT_SEQ_WQE XmitSeq; /* Xmit Sequence */
809 } un;
810
811 #ifdef EMLXS_BIG_ENDIAN
812 /* Word 6 */
813 uint16_t ContextTag; /* Context Tag */
814 uint16_t XRITag; /* XRItag */
815 /* Word 7 */
816 uint32_t Timer: 8; /* TOV */
817 uint32_t Rsvd1: 1;
818 uint32_t ERP: 1; /* ERP */
819 uint32_t PU: 2; /* PU */
820 uint32_t AR: 1; /* Auto Response */
821 uint32_t Class: 3; /* COS */
822 uint32_t Command: 8; /* Command Code */
823 uint32_t Rsvd0: 1;
824 uint32_t BsType: 3; /* DIF Block Size type */
825 uint32_t ContextType: 2; /* Context Type */
826 uint32_t DIF: 2;
827 /* Word 8 */
828 uint32_t AbortTag; /* Abort Tag */
829 /* Word 9 */
830 uint16_t OXId; /* OXId on xmitted rsp */
831 uint16_t RequestTag; /* Request Tag */
832 /* Word 10 */
833 uint32_t CCP: 8; /* CCP */
834 uint32_t CCPE: 1; /* CCPEnabled */
835 uint32_t CMD: 1;
836 uint32_t XC: 1; /* Exchange Create */
837 uint32_t Rsvd5: 1;
838 uint32_t PV: 1; /* PRIValid */
839 uint32_t PRI: 3; /* PRI */
840 /* The following 16 bits may be */
841 /* overwritten by PHWQ */
842 uint32_t WQES: 1; /* WQE specify XBL */
843 uint32_t DBDE: 1; /* Data type for BDE 0 */
844 uint32_t IOd: 1; /* IO direction */
845 uint32_t Rsvd4: 1;
846 uint32_t XBL: 1; /* Explicit Buffer List */
847 uint32_t Rsvd3: 1;
848 uint32_t QOSd: 1; /* QOS disable */
849 uint32_t LenLoc: 2; /* Length Location */
850 uint32_t Rsvd2: 3;
851 uint32_t EBDEcnt: 4; /* Extended BDE cnt */
852 /* Word 11 */
853 uint32_t CQId: 16; /* CompletionQueueID */
854 uint32_t Rsvd8: 8;
855 uint32_t WQEC: 1; /* Request WQE consumed CQE */
856 uint32_t ELSId: 3;
857 uint32_t CmdType: 4; /* Command Type */
858 #endif
859 #ifdef EMLXS_LITTLE_ENDIAN
860 /* Word 6 */
861 uint16_t XRITag; /* XRItag */
862 uint16_t ContextTag; /* Context Tag */
863 /* Word 7 */
864 uint32_t DIF: 2;
865 uint32_t ContextType: 2; /* Context Type */
866 uint32_t BsType: 3; /* DIF Block Size type */
867 uint32_t Rsvd0: 1;
868 uint32_t Command: 8; /* Command Code */
869 uint32_t Class: 3; /* COS */
870 uint32_t AR: 1; /* Auto Response */
871 uint32_t PU: 2; /* PU */
872 uint32_t ERP: 1; /* ERP */
873 uint32_t Rsvd1: 1;
874 uint32_t Timer: 8; /* TOV */
875 /* Word 8 */
876 uint32_t AbortTag; /* Abort Tag */
877 /* Word 9 */
878 uint16_t RequestTag; /* Request Tag */
879 uint16_t OXId; /* OXId on xmitted rsp */
880 /* Word 10 */
881 /* The following 16 bits may be */
882 /* overwritten by PHWQ */
883 uint32_t EBDEcnt: 4; /* Extended BDE cnt */
884 uint32_t Rsvd2: 3;
885 uint32_t LenLoc: 2; /* Length Location */
886 uint32_t QOSd: 1; /* QOS disable */
887 uint32_t Rsvd3: 1;
888 uint32_t XBL: 1; /* Explicit Buffer List */
889 uint32_t Rsvd4: 1;
890 uint32_t IOd: 1; /* IO direction */
891 uint32_t DBDE: 1; /* Data type for BDE 0 */
892 uint32_t WQES: 1; /* WQE specify XBL */
893 uint32_t PRI: 3; /* PRI */
894 uint32_t PV: 1; /* PRIValid */
895 uint32_t Rsvd5: 1;
896 uint32_t XC: 1; /* Exchange Create */
897 uint32_t CMD: 1;
898 uint32_t CCPE: 1; /* CCPEnabled */
899 uint32_t CCP: 8; /* CCP */
900 /* Word 11 */
901 uint32_t CmdType: 4; /* Command Type */
902 uint32_t ELSId: 3;
903 uint32_t WQEC: 1; /* Request WQE consumed CQE */
904 uint32_t Rsvd8: 8;
905 uint32_t CQId: 16; /* CompletionQueueID */
906 #endif
907
908 /* Words 12 */
909 uint32_t CmdSpecific; /* Command specific information */
910
911 /* Words 13-15 */
912 ULP_BDE64 FirstData;
913 } emlxs_wqe_t;
914
915 /* Used if PHWQ is enabled */
916 #ifdef EMLXS_BIG_ENDIAN
917 #define WQE_PHWQ_WQID(wqe, qid) *(((uint16_t *)(wqe)) + 21) = \
918 ((qid << 1) & 0xfffe);
919 #endif
920 #ifdef EMLXS_LITTLE_ENDIAN
921 #define WQE_PHWQ_WQID(wqe, qid) *(((uint16_t *)(wqe)) + 20) = \
922 ((qid << 1) & 0xfffe);
923 #endif
924
925 /* Defines for ContextType */
926 #define WQE_RPI_CONTEXT 0
927 #define WQE_VPI_CONTEXT 1
928 #define WQE_VFI_CONTEXT 2
929 #define WQE_FCFI_CONTEXT 3
930
931 /* Defines for CmdType */
932 #define WQE_TYPE_FCP_DATA_IN 0x00
933 #define WQE_TYPE_FCP_DATA_OUT 0x01
934 #define WQE_TYPE_TRECEIVE 0x02
935 #define WQE_TYPE_TRSP 0x03
936 #define WQE_TYPE_SRR_RSP 0x06
937 #define WQE_TYPE_TSEND 0x07
938 #define WQE_TYPE_GEN 0x08
939 #define WQE_TYPE_ABORT 0x08
940 #define WQE_TYPE_ELS 0x0C
941 #define WQE_TYPE_MASK_FIP 0x01
942
943 /* Defines for ELSId */
944 #define WQE_ELSID_PLOGI 0x04
945 #define WQE_ELSID_FLOGI 0x03
946 #define WQE_ELSID_FDISC 0x02
947 #define WQE_ELSID_LOGO 0x01
948 #define WQE_ELSID_CMD 0x00
949
950 /* RQB */
951 #define RQB_HEADER_SIZE 32
952 #define RQB_DATA_SIZE 2048
953 #define RQB_COUNT 256
954
955 #define EMLXS_NUM_WQ_PAGES 4
956 #define WQE_SIZE 64
957
958 #define EMLXS_NUM_CQ_PAGES_V2 4
959 #define CQE_SIZE 16
960
961 #define EQ_DEPTH 1024
962 #define CQ_DEPTH 256
963 #define CQ_DEPTH_V2 ((4096/CQE_SIZE) * EMLXS_NUM_CQ_PAGES_V2) /* 1024 */
964 #define WQ_DEPTH ((4096/WQE_SIZE) * EMLXS_NUM_WQ_PAGES) /* 256 */
965 #define MQ_DEPTH 16
966 #define RQ_DEPTH 512 /* Multiple of RQB_COUNT */
967 #define RQ_DEPTH_EXPONENT 9
968
969 #define EMLXS_MAX_WQS_PER_EQ 4
970
971
972 /* Principal doorbell register layouts */
973 typedef struct emlxs_rqdb
974 {
975 #ifdef EMLXS_BIG_ENDIAN
976 uint32_t Rsvd2:2;
977 uint32_t NumPosted:14; /* Number of entries posted */
978 uint32_t Rsvd1:6;
979 uint32_t Qid:10; /* RQ id for posted RQE */
980 #endif /* EMLXS_BIG_ENDIAN */
981
982 #ifdef EMLXS_LITTLE_ENDIAN
983 uint32_t Qid:10; /* RQ id for posted RQE */
984 uint32_t Rsvd1:6;
985 uint32_t NumPosted:14; /* Number of entries posted */
986 uint32_t Rsvd2:2;
987 #endif /* EMLXS_LITTLE_ENDIAN */
988
989 } emlxs_rqdb_t;
990
991
992 typedef union emlxs_rqdbu
993 {
994 uint32_t word;
995 emlxs_rqdb_t db;
996
997 } emlxs_rqdbu_t;
998
999
1000 typedef struct emlxs_wqdb
1001 {
1002 #ifdef EMLXS_BIG_ENDIAN
1003 uint32_t NumPosted:8; /* Number of entries posted */
1004 uint32_t Index:8; /* Queue index for posted command */
1005 uint32_t Rsvd1:6;
1006 uint32_t Qid:10; /* WQ id for posted WQE */
1007 #endif /* EMLXS_BIG_ENDIAN */
1008
1009 #ifdef EMLXS_LITTLE_ENDIAN
1010 uint32_t Qid:10; /* WQ id for posted WQE */
1011 uint32_t Rsvd1:6;
1012 uint32_t Index:8; /* Queue index for posted command */
1013 uint32_t NumPosted:8; /* Number of entries posted */
1014 #endif /* EMLXS_LITTLE_ENDIAN */
1015
1016 } emlxs_wqdb_t;
1017
1018
1019 typedef union emlxs_wqdbu
1020 {
1021 uint32_t word;
1022 emlxs_wqdb_t db;
1023
1024 } emlxs_wqdbu_t;
1025
1026
1027 typedef struct emlxs_cqdb
1028 {
1029 #ifdef EMLXS_BIG_ENDIAN
1030 uint32_t NumPosted:2; /* Number of entries posted */
1031 uint32_t Rearm:1; /* Rearm CQ */
1032 uint32_t NumPopped:13; /* Number of CQ entries processed */
1033 uint32_t Rsvd1:5;
1034 uint32_t Event:1; /* 1 if processed entry is EQE */
1035 /* 0 if processed entry is CQE */
1036 uint32_t Qid:10; /* CQ id for posted CQE */
1037 #endif /* EMLXS_BIG_ENDIAN */
1038
1039 #ifdef EMLXS_LITTLE_ENDIAN
1040 uint32_t Qid:10; /* CQ id for posted CQE */
1041 uint32_t Event:1; /* 1 if processed entry is EQE */
1042 /* 0 if processed entry is CQE */
1043 uint32_t Rsvd1:5;
1044 uint32_t NumPopped:13; /* Number of CQ entries processed */
1045 uint32_t Rearm:1; /* Rearm CQ */
1046 uint32_t NumPosted:2; /* Number of entries posted */
1047 #endif /* EMLXS_LITTLE_ENDIAN */
1048
1049 } emlxs_cqdb_t;
1050
1051
1052 typedef union emlxs_cqdbu
1053 {
1054 uint32_t word;
1055 emlxs_cqdb_t db;
1056
1057 } emlxs_cqdbu_t;
1058
1059 typedef struct emlxs_eqdb
1060 {
1061 #ifdef EMLXS_BIG_ENDIAN
1062 uint32_t Rsvd2:2;
1063 uint32_t Rearm:1; /* Rearm EQ */
1064 uint32_t NumPopped:13; /* Number of CQ entries processed */
1065 uint32_t Rsvd1:5;
1066 uint32_t Event:1; /* True iff processed entry is EQE */
1067 uint32_t Clear:1; /* clears EQ interrupt when set */
1068 uint32_t Qid:9; /* EQ id for posted EQE */
1069 #endif /* EMLXS_BIG_ENDIAN */
1070
1071 #ifdef EMLXS_LITTLE_ENDIAN
1072 uint32_t Qid:9; /* EQ id for posted EQE */
1073 uint32_t Clear:1; /* clears EQ interrupt when set */
1074 uint32_t Event:1; /* True iff processed entry is EQE */
1075 uint32_t Rsvd1:5;
1076 uint32_t NumPopped:13; /* Number of CQ entries processed */
1077 uint32_t Rearm:1; /* Rearm EQ */
1078 uint32_t Rsvd2:2;
1079 #endif /* EMLXS_LITTLE_ENDIAN */
1080
1081 } emlxs_eqdb_t;
1082
1083
1084 typedef union emlxs_eqdbu
1085 {
1086 uint32_t word;
1087 emlxs_eqdb_t db;
1088
1089 } emlxs_eqdbu_t;
1090
1091
1092 typedef struct emlxs_mqdb
1093 {
1094 #ifdef EMLXS_BIG_ENDIAN
1095 uint32_t Rsvd2:2;
1096 uint32_t NumPosted:14; /* Number of entries posted */
1097 uint32_t Rsvd1:5;
1098 uint32_t Qid:11; /* MQ id for posted MQE */
1099 #endif /* EMLXS_BIG_ENDIAN */
1100
1101 #ifdef EMLXS_LITTLE_ENDIAN
1102 uint32_t Qid:11; /* MQ id for posted MQE */
1103 uint32_t Rsvd1:5;
1104 uint32_t NumPosted:14; /* Number of entries posted */
1105 uint32_t Rsvd2:2;
1106 #endif /* EMLXS_LITTLE_ENDIAN */
1107
1108 } emlxs_mqdb_t;
1109
1110
1111 typedef union emlxs_mqdbu
1112 {
1113 uint32_t word;
1114 emlxs_mqdb_t db;
1115
1116 } emlxs_mqdbu_t;
1117
1118
1119 #ifdef __cplusplus
1120 }
1121 #endif
1122
1123 #endif /* _EMLXS_QUEUE_H */