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NEX-8705 Drivers for ATTO Celerity FC-162E Gen 5 and Celerity FC-162P Gen 6 16GB FC cards support
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-1878 update emlxs from source provided by Emulex
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--- old/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at
9 9 * http://www.opensource.org/licenses/cddl1.txt.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 #ifndef _EMLXS_MBOX_H
28 28 #define _EMLXS_MBOX_H
29 29
30 30 #ifdef __cplusplus
31 31 extern "C" {
32 32 #endif
33 33
34 34 /* SLI 2/3 Mailbox defines */
35 35
36 36 #define MBOX_SIZE 256
37 37 #define MBOX_EXTENSION_OFFSET MBOX_SIZE
38 38
39 39 #ifdef MBOX_EXT_SUPPORT
40 40 #define MBOX_EXTENSION_SIZE 1024
41 41 #else
42 42 #define MBOX_EXTENSION_SIZE 0
43 43 #endif /* MBOX_EXT_SUPPORT */
44 44
45 45
46 46
47 47 /* ==== Mailbox Commands ==== */
48 48 #define MBX_SHUTDOWN 0x00 /* terminate testing */
49 49 #define MBX_LOAD_SM 0x01
50 50 #define MBX_READ_NV 0x02
51 51 #define MBX_WRITE_NV 0x03
52 52 #define MBX_RUN_BIU_DIAG 0x04
53 53 #define MBX_INIT_LINK 0x05
54 54 #define MBX_DOWN_LINK 0x06
55 55 #define MBX_CONFIG_LINK 0x07
56 56 #define MBX_PART_SLIM 0x08
57 57 #define MBX_CONFIG_RING 0x09
58 58 #define MBX_RESET_RING 0x0A
59 59 #define MBX_READ_CONFIG 0x0B
60 60 #define MBX_READ_RCONFIG 0x0C
61 61 #define MBX_READ_SPARM 0x0D
62 62 #define MBX_READ_STATUS 0x0E
63 63 #define MBX_READ_RPI 0x0F
64 64 #define MBX_READ_XRI 0x10
65 65 #define MBX_READ_REV 0x11
66 66 #define MBX_READ_LNK_STAT 0x12
67 67 #define MBX_REG_LOGIN 0x13
68 68 #define MBX_UNREG_LOGIN 0x14 /* SLI2/3 */
69 69 #define MBX_UNREG_RPI 0x14 /* SLI4 */
70 70 #define MBX_READ_LA 0x15
71 71 #define MBX_CLEAR_LA 0x16
72 72 #define MBX_DUMP_MEMORY 0x17
73 73 #define MBX_DUMP_CONTEXT 0x18
74 74 #define MBX_RUN_DIAGS 0x19
75 75 #define MBX_RESTART 0x1A
76 76 #define MBX_UPDATE_CFG 0x1B
77 77 #define MBX_DOWN_LOAD 0x1C
78 78 #define MBX_DEL_LD_ENTRY 0x1D
79 79 #define MBX_RUN_PROGRAM 0x1E
80 80 #define MBX_SET_MASK 0x20
81 81 #define MBX_SET_VARIABLE 0x21
82 82 #define MBX_UNREG_D_ID 0x23
83 83 #define MBX_KILL_BOARD 0x24
84 84 #define MBX_CONFIG_FARP 0x25
85 85 #define MBX_BEACON 0x2A
86 86 #define MBX_READ_VPI 0x2B
87 87 #define MBX_CONFIG_MSIX 0x30
88 88 #define MBX_HEARTBEAT 0x31
89 89 #define MBX_WRITE_VPARMS 0x32
90 90 #define MBX_ASYNC_EVENT 0x33
91 91
92 92 #define MBX_READ_EVENT_LOG_STATUS 0x37
93 93 #define MBX_READ_EVENT_LOG 0x38
94 94 #define MBX_WRITE_EVENT_LOG 0x39
95 95 #define MBX_NV_LOG 0x3A
96 96 #define MBX_PORT_CAPABILITIES 0x3B
97 97 #define MBX_IOV_CONTROL 0x3C
98 98 #define MBX_IOV_MBX 0x3D
99 99
100 100
101 101 #define MBX_CONFIG_HBQ 0x7C /* SLI3 */
102 102 #define MBX_LOAD_AREA 0x81
103 103 #define MBX_RUN_BIU_DIAG64 0x84
104 104 #define MBX_GET_DEBUG 0x86
105 105 #define MBX_CONFIG_PORT 0x88
106 106 #define MBX_READ_SPARM64 0x8D
107 107 #define MBX_READ_RPI64 0x8F
108 108 #define MBX_CONFIG_MSI 0x90
109 109 #define MBX_REG_LOGIN64 0x93 /* SLI2/3 */
110 110 #define MBX_REG_RPI 0x93 /* SLI4 */
111 111 #define MBX_READ_LA64 0x95 /* SLI2/3 */
112 112 #define MBX_READ_TOPOLOGY 0x95 /* SLI4 */
113 113 #define MBX_REG_VPI 0x96 /* NPIV */
114 114 #define MBX_UNREG_VPI 0x97 /* NPIV */
115 115 #define MBX_FLASH_WR_ULA 0x98
116 116 #define MBX_SET_DEBUG 0x99
117 117 #define MBX_SLI_CONFIG 0x9B
118 118 #define MBX_LOAD_EXP_ROM 0x9C
119 119 #define MBX_REQUEST_FEATURES 0x9D
120 120 #define MBX_RESUME_RPI 0x9E
121 121 #define MBX_REG_VFI 0x9F
122 122 #define MBX_REG_FCFI 0xA0
123 123 #define MBX_UNREG_VFI 0xA1
124 124 #define MBX_UNREG_FCFI 0xA2
125 125 #define MBX_INIT_VFI 0xA3
126 126 #define MBX_INIT_VPI 0xA4
127 127 #define MBX_ACCESS_VDATA 0xA5
128 128 #define MBX_MAX_CMDS 0xA6
129 129
130 130
131 131 /*
132 132 * Define Status
133 133 */
134 134 #define MBX_SUCCESS 0x0
135 135 #define MBX_FAILURE 0x1
136 136 #define MBXERR_NUM_IOCBS 0x2
137 137 #define MBXERR_IOCBS_EXCEEDED 0x3
138 138 #define MBXERR_BAD_RING_NUMBER 0x4
139 139 #define MBXERR_MASK_ENTRIES_RANGE 0x5
140 140 #define MBXERR_MASKS_EXCEEDED 0x6
141 141 #define MBXERR_BAD_PROFILE 0x7
142 142 #define MBXERR_BAD_DEF_CLASS 0x8
143 143 #define MBXERR_BAD_MAX_RESPONDER 0x9
144 144 #define MBXERR_BAD_MAX_ORIGINATOR 0xA
145 145 #define MBXERR_RPI_REGISTERED 0xB
146 146 #define MBXERR_RPI_FULL 0xC
147 147 #define MBXERR_NO_RESOURCES 0xD
148 148 #define MBXERR_BAD_RCV_LENGTH 0xE
149 149 #define MBXERR_DMA_ERROR 0xF
150 150 #define MBXERR_NOT_SUPPORTED 0x10
151 151 #define MBXERR_UNSUPPORTED_FEATURE 0x11
152 152 #define MBXERR_UNKNOWN_COMMAND 0x12
153 153 #define MBXERR_BAD_IP_BIT 0x13
154 154 #define MBXERR_BAD_PCB_ALIGN 0x14
155 155 #define MBXERR_BAD_HBQ_ID 0x15
156 156 #define MBXERR_BAD_HBQ_STATE 0x16
157 157 #define MBXERR_BAD_HBQ_MASK_NUM 0x17
158 158 #define MBXERR_BAD_HBQ_MASK_SUBSET 0x18
159 159 #define MBXERR_HBQ_CREATE_FAIL 0x19
160 160 #define MBXERR_HBQ_EXISTING 0x1A
161 161 #define MBXERR_HBQ_RSPRING_FULL 0x1B
162 162 #define MBXERR_HBQ_DUP_MASK 0x1C
163 163 #define MBXERR_HBQ_INVAL_GET_PTR 0x1D
164 164 #define MBXERR_BAD_HBQ_SIZE 0x1E
165 165 #define MBXERR_BAD_HBQ_ORDER 0x1F
166 166 #define MBXERR_INVALID_ID 0x20
167 167
168 168 #define MBXERR_INVALID_VFI 0x30
169 169
170 170 #define MBXERR_FLASH_WRITE_FAILED 0x100
171 171
172 172 #define MBXERR_INVALID_LINKSPEED 0x500
173 173
174 174 #define MBXERR_BAD_REDIRECT 0x900
175 175 #define MBXERR_RING_ALREADY_CONFIG 0x901
176 176
177 177 #define MBXERR_RING_INACTIVE 0xA00
178 178
179 179 #define MBXERR_RPI_INACTIVE 0xF00
180 180
181 181 #define MBXERR_NO_ACTIVE_XRI 0x1100
182 182 #define MBXERR_XRI_NOT_ACTIVE 0x1101
183 183
184 184 #define MBXERR_RPI_INUSE 0x1400
185 185
186 186 #define MBXERR_NO_LINK_ATTENTION 0x1500
187 187
188 188 #define MBXERR_INVALID_SLI_MODE 0x8800
189 189 #define MBXERR_INVALID_HOST_PTR 0x8801
190 190 #define MBXERR_CANT_CFG_SLI_MODE 0x8802
191 191 #define MBXERR_BAD_OVERLAY 0x8803
192 192 #define MBXERR_INVALID_FEAT_REQ 0x8804
193 193
194 194 #define MBXERR_CONFIG_CANT_COMPLETE 0x88FF
195 195
196 196 #define MBXERR_DID_ALREADY_REGISTERED 0x9600
197 197 #define MBXERR_DID_INCONSISTENT 0x9601
198 198 #define MBXERR_VPI_TOO_LARGE 0x9603
199 199
200 200 #define MBXERR_STILL_ASSOCIATED 0x9700
201 201
202 202 #define MBXERR_INVALID_VF_STATE 0x9F00
203 203 #define MBXERR_VFI_ALREADY_REGISTERED 0x9F02
204 204 #define MBXERR_VFI_TOO_LARGE 0x9F03
205 205
206 206 #define MBXERR_LOAD_FW_FAILED 0xFFFE
207 207 #define MBXERR_FIND_FW_FAILED 0xFFFF
208 208
209 209 /* Driver special codes */
210 210 #define MBX_DRIVER_RESERVED 0xF9 /* Set to lowest drv status */
211 211 #define MBX_NONEMBED_ERROR 0xF9
212 212 #define MBX_OVERTEMP_ERROR 0xFA
213 213 #define MBX_HARDWARE_ERROR 0xFB
214 214 #define MBX_DRVR_ERROR 0xFC
215 215 #define MBX_BUSY 0xFD
216 216 #define MBX_TIMEOUT 0xFE
217 217 #define MBX_NOT_FINISHED 0xFF
218 218
219 219 /*
220 220 * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
221 221 */
222 222 #define MBX_POLL 0x01 /* poll mailbox till command done, */
223 223 /* then return */
224 224 #define MBX_SLEEP 0x02 /* sleep till mailbox intr cmpl */
225 225 /* wakes thread up */
226 226 #define MBX_WAIT 0x03 /* wait for comand done, then return */
227 227 #define MBX_NOWAIT 0x04 /* issue command then return immediately */
228 228 #define MBX_BOOTSTRAP 0x80 /* issue a command on the bootstrap mbox */
229 229
230 230
231 231
232 232 /*
233 233 * Begin Structure Definitions for Mailbox Commands
234 234 */
235 235
236 236 typedef struct revcompat
237 237 {
238 238 #ifdef EMLXS_BIG_ENDIAN
239 239 uint32_t ldflag:1; /* Set in SRAM descriptor */
240 240 uint32_t ldcount:7; /* For use by program load */
241 241 uint32_t kernel:4; /* Kernel ID */
242 242 uint32_t kver:4; /* Kernel compatibility version */
243 243 uint32_t SMver:4; /* Sequence Manager version */
244 244 /* 0 if none */
245 245 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */
246 246 uint32_t BIUtype:4; /* PCI = 0 */
247 247 uint32_t BIUver:4; /* BIU version, 0 if none */
248 248 #endif
249 249 #ifdef EMLXS_LITTLE_ENDIAN
250 250 uint32_t BIUver:4; /* BIU version, 0 if none */
251 251 uint32_t BIUtype:4; /* PCI = 0 */
252 252 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */
253 253 uint32_t SMver:4; /* Sequence Manager version */
254 254 /* 0 if none */
255 255 uint32_t kver:4; /* Kernel compatibility version */
256 256 uint32_t kernel:4; /* Kernel ID */
257 257 uint32_t ldcount:7; /* For use by program load */
258 258 uint32_t ldflag:1; /* Set in SRAM descriptor */
259 259 #endif
260 260 } REVCOMPAT;
261 261
262 262 typedef struct id_word
263 263 {
264 264 #ifdef EMLXS_BIG_ENDIAN
265 265 uint8_t Type;
266 266 uint8_t Id;
267 267 uint8_t Ver;
268 268 uint8_t Rev;
269 269 #endif
270 270 #ifdef EMLXS_LITTLE_ENDIAN
271 271 uint8_t Rev;
272 272 uint8_t Ver;
273 273 uint8_t Id;
274 274 uint8_t Type;
275 275 #endif
276 276 union
277 277 {
278 278 REVCOMPAT cp;
279 279 uint32_t revcomp;
280 280 } un;
281 281 } PROG_ID;
282 282
283 283 typedef struct
284 284 {
285 285 #ifdef EMLXS_BIG_ENDIAN
286 286 uint8_t tval;
287 287 uint8_t tmask;
288 288 uint8_t rval;
289 289 uint8_t rmask;
290 290 #endif
291 291 #ifdef EMLXS_LITTLE_ENDIAN
292 292 uint8_t rmask;
293 293 uint8_t rval;
294 294 uint8_t tmask;
295 295 uint8_t tval;
296 296 #endif
297 297 } RR_REG;
298 298
299 299
300 300 /* Structure used for a HBQ entry */
301 301 typedef struct
302 302 {
303 303 ULP_BDE64 bde;
304 304 union UN_TAG
305 305 {
306 306 uint32_t w;
307 307 struct
308 308 {
309 309 #ifdef EMLXS_BIG_ENDIAN
310 310 uint32_t HBQ_tag:4;
311 311 uint32_t HBQE_tag:28;
312 312 #endif
313 313 #ifdef EMLXS_LITTLE_ENDIAN
314 314 uint32_t HBQE_tag:28;
315 315 uint32_t HBQ_tag:4;
316 316 #endif
317 317 } ext;
318 318 } unt;
319 319 } HBQE_t;
320 320
321 321 typedef struct
322 322 {
323 323 #ifdef EMLXS_BIG_ENDIAN
324 324 uint8_t tmatch;
325 325 uint8_t tmask;
326 326 uint8_t rctlmatch;
327 327 uint8_t rctlmask;
328 328 #endif
329 329 #ifdef EMLXS_LITTLE_ENDIAN
330 330 uint8_t rctlmask;
331 331 uint8_t rctlmatch;
332 332 uint8_t tmask;
333 333 uint8_t tmatch;
334 334 #endif
335 335 } HBQ_MASK;
336 336
337 337 #define EMLXS_MAX_HBQ_BUFFERS 4096
338 338
339 339 typedef struct
340 340 {
341 341 uint32_t HBQ_num_mask; /* number of mask entries in */
342 342 /* port array */
343 343 uint32_t HBQ_recvNotify; /* Rcv buffer notification */
344 344 uint32_t HBQ_numEntries; /* # of entries in HBQ */
345 345 uint32_t HBQ_headerLen; /* 0 if not profile 4 or 5 */
346 346 uint32_t HBQ_logEntry; /* Set to 1 if this HBQ used */
347 347 /* for LogEntry */
348 348 uint32_t HBQ_profile; /* Selection profile 0=all, */
349 349 /* 7=logentry */
350 350 uint32_t HBQ_ringMask; /* Binds HBQ to a ring e.g. */
351 351 /* Ring0=b0001, ring2=b0100 */
352 352 uint32_t HBQ_id; /* index of this hbq in ring */
353 353 /* of HBQs[] */
354 354 uint32_t HBQ_PutIdx_next; /* Index to next HBQ slot to */
355 355 /* use */
356 356 uint32_t HBQ_PutIdx; /* HBQ slot to use */
357 357 uint32_t HBQ_GetIdx; /* Local copy of Get index */
358 358 /* from Port */
359 359 uint16_t HBQ_PostBufCnt; /* Current number of entries */
360 360 /* in list */
361 361 MATCHMAP *HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
362 362 MATCHMAP HBQ_host_buf; /* HBQ host buffer for HBQEs */
363 363 HBQ_MASK HBQ_Masks[6];
364 364
365 365 union
366 366 {
367 367 uint32_t allprofiles[12];
368 368
369 369 struct
370 370 {
371 371 #ifdef EMLXS_BIG_ENDIAN
372 372 uint32_t seqlenoff:16;
373 373 uint32_t maxlen:16;
374 374 #endif
375 375 #ifdef EMLXS_LITTLE_ENDIAN
376 376 uint32_t maxlen:16;
377 377 uint32_t seqlenoff:16;
378 378 #endif
379 379 #ifdef EMLXS_BIG_ENDIAN
380 380 uint32_t rsvd1:28;
381 381 uint32_t seqlenbcnt:4;
382 382 #endif
383 383 #ifdef EMLXS_LITTLE_ENDIAN
384 384 uint32_t seqlenbcnt:4;
385 385 uint32_t rsvd1:28;
386 386 #endif
387 387 uint32_t rsvd[10];
388 388 } profile2;
389 389
390 390 struct
391 391 {
392 392 #ifdef EMLXS_BIG_ENDIAN
393 393 uint32_t seqlenoff:16;
394 394 uint32_t maxlen:16;
395 395 #endif
396 396 #ifdef EMLXS_LITTLE_ENDIAN
397 397 uint32_t maxlen:16;
398 398 uint32_t seqlenoff:16;
399 399 #endif
400 400 #ifdef EMLXS_BIG_ENDIAN
401 401 uint32_t cmdcodeoff:28;
402 402 uint32_t rsvd1:12;
403 403 uint32_t seqlenbcnt:4;
404 404 #endif
405 405 #ifdef EMLXS_LITTLE_ENDIAN
406 406 uint32_t seqlenbcnt:4;
407 407 uint32_t rsvd1:12;
408 408 uint32_t cmdcodeoff:28;
409 409 #endif
410 410 uint32_t cmdmatch[8];
411 411
412 412 uint32_t rsvd[2];
413 413 } profile3;
414 414
415 415 struct
416 416 {
417 417 #ifdef EMLXS_BIG_ENDIAN
418 418 uint32_t seqlenoff:16;
419 419 uint32_t maxlen:16;
420 420 #endif
421 421 #ifdef EMLXS_LITTLE_ENDIAN
422 422 uint32_t maxlen:16;
423 423 uint32_t seqlenoff:16;
424 424 #endif
425 425 #ifdef EMLXS_BIG_ENDIAN
426 426 uint32_t cmdcodeoff:28;
427 427 uint32_t rsvd1:12;
428 428 uint32_t seqlenbcnt:4;
429 429 #endif
430 430 #ifdef EMLXS_LITTLE_ENDIAN
431 431 uint32_t seqlenbcnt:4;
432 432 uint32_t rsvd1:12;
433 433 uint32_t cmdcodeoff:28;
434 434 #endif
435 435 uint32_t cmdmatch[8];
436 436
437 437 uint32_t rsvd[2];
438 438 } profile5;
439 439 } profiles;
440 440 } HBQ_INIT_t;
441 441
442 442
443 443
444 444 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
445 445
446 446
447 447 typedef struct
448 448 {
449 449 #ifdef EMLXS_BIG_ENDIAN
450 450 uint32_t rsvd2:24;
451 451 uint32_t keep:1;
452 452 uint32_t acknowledgment:1;
453 453 uint32_t version:1;
454 454 uint32_t erase_or_prog:1;
455 455 uint32_t update_flash:1;
456 456 uint32_t update_ram:1;
457 457 uint32_t method:1;
458 458 uint32_t load_cmplt:1;
459 459 #endif
460 460 #ifdef EMLXS_LITTLE_ENDIAN
461 461 uint32_t load_cmplt:1;
462 462 uint32_t method:1;
463 463 uint32_t update_ram:1;
464 464 uint32_t update_flash:1;
465 465 uint32_t erase_or_prog:1;
466 466 uint32_t version:1;
467 467 uint32_t acknowledgment:1;
468 468 uint32_t keep:1;
469 469 uint32_t rsvd2:24;
470 470 #endif
471 471
472 472 #define DL_FROM_BDE 0 /* method */
473 473 #define DL_FROM_SLIM 1
474 474
475 475 #define PROGRAM_FLASH 0 /* erase_or_prog */
476 476 #define ERASE_FLASH 1
477 477
478 478 uint32_t dl_to_adr;
479 479 uint32_t dl_len;
480 480 union
481 481 {
482 482 uint32_t dl_from_slim_offset;
483 483 ULP_BDE dl_from_bde;
484 484 ULP_BDE64 dl_from_bde64;
485 485 PROG_ID prog_id;
486 486 } un;
487 487 } LOAD_SM_VAR;
488 488
489 489
490 490 /* Structure for MB Command READ_NVPARM (02) */
491 491 /* Good for SLI2/3 and SLI4 */
492 492
493 493 typedef struct
494 494 {
495 495 uint32_t rsvd1[3]; /* Read as all one's */
496 496 uint32_t rsvd2; /* Read as all zero's */
497 497 uint32_t portname[2]; /* N_PORT name */
498 498 uint32_t nodename[2]; /* NODE name */
499 499 #ifdef EMLXS_BIG_ENDIAN
500 500 uint32_t pref_DID:24;
501 501 uint32_t hardAL_PA:8;
502 502 #endif
503 503 #ifdef EMLXS_LITTLE_ENDIAN
504 504 uint32_t hardAL_PA:8;
505 505 uint32_t pref_DID:24;
506 506 #endif
507 507 uint32_t rsvd3[21]; /* Read as all one's */
508 508 } READ_NV_VAR;
509 509
510 510
511 511 /* Structure for MB Command WRITE_NVPARMS (03) */
512 512 /* Good for SLI2/3 and SLI4 */
513 513
514 514 typedef struct
515 515 {
516 516 uint32_t rsvd1[3]; /* Must be all one's */
517 517 uint32_t rsvd2; /* Must be all zero's */
518 518 uint32_t portname[2]; /* N_PORT name */
519 519 uint32_t nodename[2]; /* NODE name */
520 520 #ifdef EMLXS_BIG_ENDIAN
521 521 uint32_t pref_DID:24;
522 522 uint32_t hardAL_PA:8;
523 523 #endif
524 524 #ifdef EMLXS_LITTLE_ENDIAN
525 525 uint32_t hardAL_PA:8;
526 526 uint32_t pref_DID:24;
527 527 #endif
528 528 uint32_t rsvd3[21]; /* Must be all one's */
529 529 } WRITE_NV_VAR;
530 530
531 531
532 532 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
533 533 /* Good for SLI2/3 and SLI4 */
534 534
535 535 typedef struct
536 536 {
537 537 uint32_t rsvd1;
538 538 union
539 539 {
540 540 struct
541 541 {
542 542 ULP_BDE64 xmit_bde64;
543 543 ULP_BDE64 rcv_bde64;
544 544 } s2;
545 545 } un;
546 546 } BIU_DIAG_VAR;
547 547
548 548
549 549 /* Structure for MB Command INIT_LINK (05) */
550 550 /* Good for SLI2/3 and SLI4 */
551 551
552 552 typedef struct
553 553 {
554 554 #ifdef EMLXS_BIG_ENDIAN
555 555 uint32_t rsvd1:24;
556 556 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */
557 557 /* Reset to */
558 558 #endif
559 559 #ifdef EMLXS_LITTLE_ENDIAN
560 560 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */
561 561 /* Reset to */
562 562 uint32_t rsvd1:24;
563 563 #endif
564 564
565 565 #ifdef EMLXS_BIG_ENDIAN
566 566 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
567 567 uint8_t rsvd2;
568 568 uint16_t link_flags;
569 569 #endif
570 570 #ifdef EMLXS_LITTLE_ENDIAN
571 571 uint16_t link_flags;
572 572 uint8_t rsvd2;
573 573 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
574 574 #endif
575 575 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) */
576 576 /* ENDEC loopback */
577 577 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
578 578 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
579 579 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
580 580 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
581 581 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
582 582
583 583 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
584 584 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
585 585 #define FLAGS_PREABORT_RETURN 0x4000 /* Bit 14 */
586 586
587 587 uint32_t link_speed; /* NEW_FEATURE */
588 588 #define LINK_SPEED_AUTO 0 /* Auto selection */
589 589 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
590 590 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
591 591 } INIT_LINK_VAR;
592 592
593 593
594 594 /* Structure for MB Command DOWN_LINK (06) */
595 595 /* Good for SLI2/3 and SLI4 */
596 596
597 597 typedef struct
598 598 {
599 599 uint32_t rsvd1;
600 600 } DOWN_LINK_VAR;
601 601
602 602
603 603 /* Structure for MB Command CONFIG_LINK (07) */
604 604
605 605 typedef struct
606 606 {
607 607 #ifdef EMLXS_BIG_ENDIAN
608 608 uint32_t cr:1;
609 609 uint32_t ci:1;
610 610 uint32_t cr_delay:6;
611 611 uint32_t cr_count:8;
612 612 uint32_t rsvd1:8;
613 613 uint32_t MaxBBC:8;
614 614 #endif
615 615 #ifdef EMLXS_LITTLE_ENDIAN
616 616 uint32_t MaxBBC:8;
617 617 uint32_t rsvd1:8;
618 618 uint32_t cr_count:8;
619 619 uint32_t cr_delay:6;
620 620 uint32_t ci:1;
621 621 uint32_t cr:1;
622 622 #endif
623 623 uint32_t myId;
624 624 uint32_t rsvd2;
625 625 uint32_t edtov;
626 626 uint32_t arbtov;
627 627 uint32_t ratov;
628 628 uint32_t rttov;
629 629 uint32_t altov;
630 630 uint32_t crtov;
631 631 uint32_t citov;
632 632 #ifdef EMLXS_BIG_ENDIAN
633 633 uint32_t rrq_enable:1;
634 634 uint32_t rrq_immed:1;
635 635 uint32_t rsvd4:29;
636 636 uint32_t ack0_enable:1;
637 637 #endif
638 638 #ifdef EMLXS_LITTLE_ENDIAN
639 639 uint32_t ack0_enable:1;
640 640 uint32_t rsvd4:29;
641 641 uint32_t rrq_immed:1;
642 642 uint32_t rrq_enable:1;
643 643 #endif
644 644 } CONFIG_LINK;
645 645
646 646
647 647 /* Structure for MB Command PART_SLIM (08) */
648 648
649 649 typedef struct
650 650 {
651 651 #ifdef EMLXS_BIG_ENDIAN
652 652 uint32_t unused1:24;
653 653 uint32_t numRing:8;
654 654 #endif
655 655 #ifdef EMLXS_LITTLE_ENDIAN
656 656 uint32_t numRing:8;
657 657 uint32_t unused1:24;
658 658 #endif
659 659 emlxs_ring_def_t ringdef[4];
660 660 uint32_t hbainit;
661 661 } PART_SLIM_VAR;
662 662
663 663
664 664 /* Structure for MB Command CONFIG_RING (09) */
665 665
666 666 typedef struct
667 667 {
668 668 #ifdef EMLXS_BIG_ENDIAN
669 669 uint32_t unused2:6;
670 670 uint32_t recvSeq:1;
671 671 uint32_t recvNotify:1;
672 672 uint32_t numMask:8;
673 673 uint32_t profile:8;
674 674 uint32_t unused1:4;
675 675 uint32_t ring:4;
676 676 #endif
677 677 #ifdef EMLXS_LITTLE_ENDIAN
678 678 uint32_t ring:4;
679 679 uint32_t unused1:4;
680 680 uint32_t profile:8;
681 681 uint32_t numMask:8;
682 682 uint32_t recvNotify:1;
683 683 uint32_t recvSeq:1;
684 684 uint32_t unused2:6;
685 685 #endif
686 686 #ifdef EMLXS_BIG_ENDIAN
687 687 uint16_t maxRespXchg;
688 688 uint16_t maxOrigXchg;
689 689 #endif
690 690 #ifdef EMLXS_LITTLE_ENDIAN
691 691 uint16_t maxOrigXchg;
692 692 uint16_t maxRespXchg;
693 693 #endif
694 694 RR_REG rrRegs[6];
695 695 } CONFIG_RING_VAR;
696 696
697 697
698 698 /* Structure for MB Command RESET_RING (10) */
699 699
700 700 typedef struct
701 701 {
702 702 uint32_t ring_no;
703 703 } RESET_RING_VAR;
704 704
705 705
706 706 /* Structure for MB Command READ_CONFIG (11) */
707 707 /* Good for SLI2/3 only */
708 708
709 709 typedef struct
710 710 {
711 711 #ifdef EMLXS_BIG_ENDIAN
712 712 uint32_t cr:1;
713 713 uint32_t ci:1;
714 714 uint32_t cr_delay:6;
715 715 uint32_t cr_count:8;
716 716 uint32_t InitBBC:8;
717 717 uint32_t MaxBBC:8;
718 718 #endif
719 719 #ifdef EMLXS_LITTLE_ENDIAN
720 720 uint32_t MaxBBC:8;
721 721 uint32_t InitBBC:8;
722 722 uint32_t cr_count:8;
723 723 uint32_t cr_delay:6;
724 724 uint32_t ci:1;
725 725 uint32_t cr:1;
726 726 #endif
727 727 #ifdef EMLXS_BIG_ENDIAN
728 728 uint32_t topology:8;
729 729 uint32_t myDid:24;
730 730 #endif
731 731 #ifdef EMLXS_LITTLE_ENDIAN
732 732 uint32_t myDid:24;
733 733 uint32_t topology:8;
734 734 #endif
735 735 /* Defines for topology (defined previously) */
736 736 #ifdef EMLXS_BIG_ENDIAN
737 737 uint32_t AR:1;
738 738 uint32_t IR:1;
739 739 uint32_t rsvd1:29;
740 740 uint32_t ack0:1;
741 741 #endif
742 742 #ifdef EMLXS_LITTLE_ENDIAN
743 743 uint32_t ack0:1;
744 744 uint32_t rsvd1:29;
745 745 uint32_t IR:1;
746 746 uint32_t AR:1;
747 747 #endif
748 748 uint32_t edtov;
749 749 uint32_t arbtov;
750 750 uint32_t ratov;
751 751 uint32_t rttov;
752 752 uint32_t altov;
753 753 uint32_t lmt;
754 754
755 755 #define LMT_1GB_CAPABLE 0x0004
756 756 #define LMT_2GB_CAPABLE 0x0008
757 757 #define LMT_4GB_CAPABLE 0x0040
758 758 #define LMT_8GB_CAPABLE 0x0080
759 759 #define LMT_10GB_CAPABLE 0x0100
760 760 #define LMT_16GB_CAPABLE 0x0200
761 761 /* E2E supported on adapters >= 8GB */
762 762 #define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
763 763
764 764 uint32_t rsvd2;
765 765 uint32_t rsvd3;
766 766 uint32_t max_xri;
767 767 uint32_t max_iocb;
768 768 uint32_t max_rpi;
769 769 uint32_t avail_xri;
770 770 uint32_t avail_iocb;
771 771 uint32_t avail_rpi;
772 772 uint32_t max_vpi;
773 773 uint32_t max_alpa;
774 774 uint32_t rsvd4;
775 775 uint32_t avail_vpi;
776 776
777 777 } READ_CONFIG_VAR;
778 778
779 779
780 780 /* Structure for MB Command READ_CONFIG(0x11) */
781 781 /* Good for SLI4 only */
782 782
783 783 typedef struct
784 784 {
785 785 #ifdef EMLXS_BIG_ENDIAN
786 786 uint32_t extents:1; /* Word 1 */
787 787 uint32_t rsvd1:31;
788 788
789 789 uint32_t topology:8; /* Word 2 */
790 790 uint32_t rsvd2:15;
791 791 uint32_t ldv:1;
792 792 uint32_t link_type:2;
793 793 uint32_t link_number:6;
794 794 #endif
795 795 #ifdef EMLXS_LITTLE_ENDIAN
796 796 uint32_t rsvd1:31; /* Word 1 */
797 797 uint32_t extents:1;
798 798
799 799 uint32_t link_number:6; /* Word 2 */
800 800 uint32_t link_type:2;
801 801 uint32_t ldv:1;
802 802 uint32_t rsvd2:15;
803 803 uint32_t topology:8;
804 804 #endif
805 805 uint32_t rsvd3; /* Word 3 */
806 806 uint32_t edtov; /* Word 4 */
807 807 uint32_t rsvd4; /* Word 5 */
808 808 uint32_t ratov; /* Word 6 */
809 809 uint32_t rsvd5; /* Word 7 */
810 810 uint32_t rsvd6; /* Word 8 */
811 811 uint32_t lmt; /* Word 9 */
812 812 uint32_t rsvd8; /* Word 10 */
813 813 uint32_t rsvd9; /* Word 11 */
814 814
815 815 #ifdef EMLXS_BIG_ENDIAN
816 816 uint16_t XRICount; /* Word 12 */
817 817 uint16_t XRIBase; /* Word 12 */
818 818
819 819 uint16_t RPICount; /* Word 13 */
820 820 uint16_t RPIBase; /* Word 13 */
821 821
822 822 uint16_t VPICount; /* Word 14 */
823 823 uint16_t VPIBase; /* Word 14 */
824 824
825 825 uint16_t VFICount; /* Word 15 */
826 826 uint16_t VFIBase; /* Word 15 */
827 827
828 828 uint16_t FCFICount; /* Word 16 */
829 829 uint16_t rsvd10; /* Word 16 */
830 830
831 831 uint16_t EQCount; /* Word 17 */
832 832 uint16_t RQCount; /* Word 17 */
833 833
834 834 uint16_t CQCount; /* Word 18 */
835 835 uint16_t WQCount; /* Word 18 */
836 836 #endif
837 837 #ifdef EMLXS_LITTLE_ENDIAN
838 838 uint16_t XRIBase; /* Word 12 */
839 839 uint16_t XRICount; /* Word 12 */
840 840
841 841 uint16_t RPIBase; /* Word 13 */
842 842 uint16_t RPICount; /* Word 13 */
843 843
844 844 uint16_t VPIBase; /* Word 14 */
845 845 uint16_t VPICount; /* Word 14 */
846 846
847 847 uint16_t VFIBase; /* Word 15 */
848 848 uint16_t VFICount; /* Word 15 */
849 849
850 850 uint16_t rsvd10; /* Word 16 */
851 851 uint16_t FCFICount; /* Word 16 */
852 852
853 853 uint16_t RQCount; /* Word 17 */
854 854 uint16_t EQCount; /* Word 17 */
855 855
856 856 uint16_t WQCount; /* Word 18 */
857 857 uint16_t CQCount; /* Word 18 */
858 858 #endif
859 859
860 860 } READ_CONFIG4_VAR;
861 861
862 862 /* Structure for MB Command READ_RCONFIG (12) */
863 863
864 864 typedef struct
865 865 {
866 866 #ifdef EMLXS_BIG_ENDIAN
867 867 uint32_t rsvd2:7;
868 868 uint32_t recvNotify:1;
869 869 uint32_t numMask:8;
870 870 uint32_t profile:8;
871 871 uint32_t rsvd1:4;
872 872 uint32_t ring:4;
873 873 #endif
874 874 #ifdef EMLXS_LITTLE_ENDIAN
875 875 uint32_t ring:4;
876 876 uint32_t rsvd1:4;
877 877 uint32_t profile:8;
878 878 uint32_t numMask:8;
879 879 uint32_t recvNotify:1;
880 880 uint32_t rsvd2:7;
881 881 #endif
882 882 #ifdef EMLXS_BIG_ENDIAN
883 883 uint16_t maxResp;
884 884 uint16_t maxOrig;
885 885 #endif
886 886 #ifdef EMLXS_LITTLE_ENDIAN
887 887 uint16_t maxOrig;
888 888 uint16_t maxResp;
889 889 #endif
890 890 RR_REG rrRegs[6];
891 891 #ifdef EMLXS_BIG_ENDIAN
892 892 uint16_t cmdRingOffset;
893 893 uint16_t cmdEntryCnt;
894 894 uint16_t rspRingOffset;
895 895 uint16_t rspEntryCnt;
896 896 uint16_t nextCmdOffset;
897 897 uint16_t rsvd3;
898 898 uint16_t nextRspOffset;
899 899 uint16_t rsvd4;
900 900 #endif
901 901 #ifdef EMLXS_LITTLE_ENDIAN
902 902 uint16_t cmdEntryCnt;
903 903 uint16_t cmdRingOffset;
904 904 uint16_t rspEntryCnt;
905 905 uint16_t rspRingOffset;
906 906 uint16_t rsvd3;
907 907 uint16_t nextCmdOffset;
908 908 uint16_t rsvd4;
909 909 uint16_t nextRspOffset;
910 910 #endif
911 911 } READ_RCONF_VAR;
912 912
913 913
914 914 /* Structure for MB Command READ_SPARM (13) */
915 915 /* Structure for MB Command READ_SPARM64 (0x8D) */
916 916 /* Good for SLI2/3 and SLI4 */
917 917
918 918 typedef struct
919 919 {
920 920 uint32_t rsvd1;
921 921 uint32_t rsvd2;
922 922 union
923 923 {
924 924 ULP_BDE sp; /* This BDE points to SERV_PARM */
925 925 /* structure */
926 926 ULP_BDE64 sp64;
927 927 } un;
928 928 uint32_t rsvd3;
929 929
930 930 #ifdef EMLXS_BIG_ENDIAN
931 931 uint16_t portNameCnt;
932 932 uint16_t portNameOffset;
933 933
934 934 uint16_t fabricNameCnt;
935 935 uint16_t fabricNameOffset;
936 936
937 937 uint16_t lportNameCnt;
938 938 uint16_t lportNameOffset;
939 939
940 940 uint16_t lfabricNameCnt;
941 941 uint16_t lfabricNameOffset;
942 942
943 943 #endif
944 944 #ifdef EMLXS_LITTLE_ENDIAN
945 945 uint16_t portNameOffset;
946 946 uint16_t portNameCnt;
947 947
948 948 uint16_t fabricNameOffset;
949 949 uint16_t fabricNameCnt;
950 950
951 951 uint16_t lportNameOffset;
952 952 uint16_t lportNameCnt;
953 953
954 954 uint16_t lfabricNameOffset;
955 955 uint16_t lfabricNameCnt;
956 956
957 957 #endif
958 958
959 959 } READ_SPARM_VAR;
960 960
961 961
962 962 /* Structure for MB Command READ_STATUS (14) */
963 963 /* Good for SLI2/3 and SLI4 */
964 964
965 965 typedef struct
966 966 {
967 967 #ifdef EMLXS_BIG_ENDIAN
968 968 uint32_t rsvd1:31;
969 969 uint32_t clrCounters:1;
970 970
971 971 uint16_t activeXriCnt;
972 972 uint16_t activeRpiCnt;
973 973 #endif
974 974 #ifdef EMLXS_LITTLE_ENDIAN
975 975 uint32_t clrCounters:1;
976 976 uint32_t rsvd1:31;
977 977
978 978 uint16_t activeRpiCnt;
979 979 uint16_t activeXriCnt;
980 980 #endif
981 981 uint32_t xmitByteCnt;
982 982 uint32_t rcvByteCnt;
983 983 uint32_t xmitFrameCnt;
984 984 uint32_t rcvFrameCnt;
985 985 uint32_t xmitSeqCnt;
986 986 uint32_t rcvSeqCnt;
987 987 uint32_t totalOrigExchanges;
988 988 uint32_t totalRespExchanges;
989 989 uint32_t rcvPbsyCnt;
990 990 uint32_t rcvFbsyCnt;
991 991 } READ_STATUS_VAR;
992 992
993 993
994 994 /* Structure for MB Command READ_RPI (15) */
995 995 /* Structure for MB Command READ_RPI64 (0x8F) */
996 996
997 997 typedef struct
998 998 {
999 999 #ifdef EMLXS_BIG_ENDIAN
1000 1000 uint16_t nextRpi;
1001 1001 uint16_t reqRpi;
1002 1002 uint32_t rsvd2:8;
1003 1003 uint32_t DID:24;
1004 1004 #endif
1005 1005 #ifdef EMLXS_LITTLE_ENDIAN
1006 1006 uint16_t reqRpi;
1007 1007 uint16_t nextRpi;
1008 1008 uint32_t DID:24;
1009 1009 uint32_t rsvd2:8;
1010 1010 #endif
1011 1011 union
1012 1012 {
1013 1013 ULP_BDE sp;
1014 1014 ULP_BDE64 sp64;
1015 1015 } un;
1016 1016 } READ_RPI_VAR;
1017 1017
1018 1018
1019 1019 /* Structure for MB Command READ_XRI (16) */
1020 1020
1021 1021 typedef struct
1022 1022 {
1023 1023 #ifdef EMLXS_BIG_ENDIAN
1024 1024 uint16_t nextXri;
1025 1025 uint16_t reqXri;
1026 1026 uint16_t rsvd1;
1027 1027 uint16_t rpi;
1028 1028 uint32_t rsvd2:8;
1029 1029 uint32_t DID:24;
1030 1030 uint32_t rsvd3:8;
1031 1031 uint32_t SID:24;
1032 1032 uint32_t rsvd4;
1033 1033 uint8_t seqId;
1034 1034 uint8_t rsvd5;
1035 1035 uint16_t seqCount;
1036 1036 uint16_t oxId;
1037 1037 uint16_t rxId;
1038 1038 uint32_t rsvd6:30;
1039 1039 uint32_t si:1;
1040 1040 uint32_t exchOrig:1;
1041 1041 #endif
1042 1042 #ifdef EMLXS_LITTLE_ENDIAN
1043 1043 uint16_t reqXri;
1044 1044 uint16_t nextXri;
1045 1045 uint16_t rpi;
1046 1046 uint16_t rsvd1;
1047 1047 uint32_t DID:24;
1048 1048 uint32_t rsvd2:8;
1049 1049 uint32_t SID:24;
1050 1050 uint32_t rsvd3:8;
1051 1051 uint32_t rsvd4;
1052 1052 uint16_t seqCount;
1053 1053 uint8_t rsvd5;
1054 1054 uint8_t seqId;
1055 1055 uint16_t rxId;
1056 1056 uint16_t oxId;
1057 1057 uint32_t exchOrig:1;
1058 1058 uint32_t si:1;
1059 1059 uint32_t rsvd6:30;
1060 1060 #endif
1061 1061 } READ_XRI_VAR;
1062 1062
1063 1063
1064 1064 /* Structure for MB Command READ_REV (17) */
1065 1065 /* Good for SLI2/3 only */
1066 1066
1067 1067 typedef struct
1068 1068 {
1069 1069 #ifdef EMLXS_BIG_ENDIAN
1070 1070 uint32_t cv:1;
1071 1071 uint32_t rr:1;
1072 1072 uint32_t co:1;
1073 1073 uint32_t rp:1;
1074 1074 uint32_t cv3:1;
1075 1075 uint32_t rf3:1;
1076 1076 uint32_t rsvd1:10;
1077 1077 uint32_t offset:14;
1078 1078 uint32_t rv:2;
1079 1079 #endif
1080 1080 #ifdef EMLXS_LITTLE_ENDIAN
1081 1081 uint32_t rv:2;
1082 1082 uint32_t offset:14;
1083 1083 uint32_t rsvd1:10;
1084 1084 uint32_t rf3:1;
1085 1085 uint32_t cv3:1;
1086 1086 uint32_t rp:1;
1087 1087 uint32_t co:1;
1088 1088 uint32_t rr:1;
1089 1089 uint32_t cv:1;
1090 1090 #endif
1091 1091 uint32_t biuRev;
1092 1092 uint32_t smRev;
1093 1093 union
1094 1094 {
1095 1095 uint32_t smFwRev;
1096 1096 struct
1097 1097 {
1098 1098 #ifdef EMLXS_BIG_ENDIAN
1099 1099 uint8_t ProgType;
1100 1100 uint8_t ProgId;
1101 1101 uint16_t ProgVer:4;
1102 1102 uint16_t ProgRev:4;
1103 1103 uint16_t ProgFixLvl:2;
1104 1104 uint16_t ProgDistType:2;
1105 1105 uint16_t DistCnt:4;
1106 1106 #endif
1107 1107 #ifdef EMLXS_LITTLE_ENDIAN
1108 1108 uint16_t DistCnt:4;
1109 1109 uint16_t ProgDistType:2;
1110 1110 uint16_t ProgFixLvl:2;
1111 1111 uint16_t ProgRev:4;
1112 1112 uint16_t ProgVer:4;
1113 1113 uint8_t ProgId;
1114 1114 uint8_t ProgType;
1115 1115 #endif
1116 1116 } b;
1117 1117 } un;
1118 1118 uint32_t endecRev;
1119 1119 #ifdef EMLXS_BIG_ENDIAN
1120 1120 uint8_t feaLevelHigh;
1121 1121 uint8_t feaLevelLow;
1122 1122 uint8_t fcphHigh;
1123 1123 uint8_t fcphLow;
1124 1124 #endif
1125 1125 #ifdef EMLXS_LITTLE_ENDIAN
1126 1126 uint8_t fcphLow;
1127 1127 uint8_t fcphHigh;
1128 1128 uint8_t feaLevelLow;
1129 1129 uint8_t feaLevelHigh;
1130 1130 #endif
1131 1131 uint32_t postKernRev;
1132 1132 uint32_t opFwRev;
1133 1133 uint8_t opFwName[16];
1134 1134
1135 1135 uint32_t sliFwRev1;
1136 1136 uint8_t sliFwName1[16];
1137 1137 uint32_t sliFwRev2;
1138 1138 uint8_t sliFwName2[16];
1139 1139 } READ_REV_VAR;
1140 1140
1141 1141 /* Structure for MB Command READ_REV (17) */
1142 1142 /* Good for SLI4 only */
1143 1143
1144 1144 typedef struct
1145 1145 {
1146 1146 #ifdef EMLXS_BIG_ENDIAN
1147 1147 uint32_t Rsvd3:2;
1148 1148 uint32_t VPD:1;
1149 1149 uint32_t rsvd2:6;
1150 1150 uint32_t dcbxMode:2;
1151 1151 uint32_t FCoE:1;
1152 1152 uint32_t sliLevel:4;
1153 1153 uint32_t rsvd1:16;
1154 1154 #endif
1155 1155 #ifdef EMLXS_LITTLE_ENDIAN
1156 1156 uint32_t rsvd1:16;
1157 1157 uint32_t sliLevel:4;
1158 1158 uint32_t FCoE:1;
1159 1159 uint32_t dcbxMode:2;
1160 1160 uint32_t rsvd2:6;
1161 1161 uint32_t VPD:1;
1162 1162 uint32_t Rsvd3:2;
1163 1163 #endif
1164 1164
1165 1165 uint32_t HwRev1;
1166 1166 uint32_t HwRev2;
1167 1167 uint32_t Rsvd4;
1168 1168 uint32_t HwRev3;
1169 1169
1170 1170 #ifdef EMLXS_BIG_ENDIAN
1171 1171 uint8_t feaLevelHigh;
1172 1172 uint8_t feaLevelLow;
1173 1173 uint8_t fcphHigh;
1174 1174 uint8_t fcphLow;
1175 1175 #endif
1176 1176 #ifdef EMLXS_LITTLE_ENDIAN
1177 1177 uint8_t fcphLow;
1178 1178 uint8_t fcphHigh;
1179 1179 uint8_t feaLevelLow;
1180 1180 uint8_t feaLevelHigh;
1181 1181 #endif
1182 1182
1183 1183 uint32_t Redboot;
1184 1184
1185 1185 uint32_t ARMFwId;
1186 1186 uint8_t ARMFwName[16];
1187 1187
1188 1188 uint32_t ULPFwId;
1189 1189 uint8_t ULPFwName[16];
1190 1190
1191 1191 uint32_t Rsvd6[30];
1192 1192
1193 1193 ULP_BDE64 VPDBde;
1194 1194
1195 1195 uint32_t ReturnedVPDLength;
1196 1196
1197 1197 } READ_REV4_VAR;
1198 1198
1199 1199 #define EMLXS_DCBX_MODE_CIN 0 /* Mapped to nonFIP mode */
1200 1200 #define EMLXS_DCBX_MODE_CEE 1 /* Mapped to FIP mode */
1201 1201
1202 1202 /* Structure for MB Command READ_LINK_STAT (18) */
1203 1203 /* Good for SLI2/3 and SLI4 */
1204 1204
1205 1205 typedef struct
1206 1206 {
1207 1207 uint32_t rsvd1;
1208 1208 uint32_t linkFailureCnt;
1209 1209 uint32_t lossSyncCnt;
1210 1210
1211 1211 uint32_t lossSignalCnt;
1212 1212 uint32_t primSeqErrCnt;
1213 1213 uint32_t invalidXmitWord;
1214 1214 uint32_t crcCnt;
1215 1215 uint32_t primSeqTimeout;
1216 1216 uint32_t elasticOverrun;
1217 1217 uint32_t arbTimeout;
1218 1218
1219 1219 uint32_t rxBufCredit;
1220 1220 uint32_t rxBufCreditCur;
1221 1221
1222 1222 uint32_t txBufCredit;
1223 1223 uint32_t txBufCreditCur;
1224 1224
1225 1225 uint32_t EOFaCnt;
1226 1226 uint32_t EOFdtiCnt;
1227 1227 uint32_t EOFniCnt;
1228 1228 uint32_t SOFfCnt;
1229 1229 uint32_t DropAERCnt;
1230 1230 uint32_t DropRcv;
1231 1231 } READ_LNK_VAR;
1232 1232
1233 1233
1234 1234 /* Structure for MB Command REG_LOGIN (19) */
1235 1235 /* Structure for MB Command REG_LOGIN64 (0x93) */
1236 1236 /* Structure for MB Command REG_RPI (0x93) */
1237 1237 /* Good for SLI2/3 and SLI4 */
1238 1238
1239 1239 typedef struct
1240 1240 {
1241 1241 #ifdef EMLXS_BIG_ENDIAN
1242 1242 uint16_t rsvd1;
1243 1243 uint16_t rpi;
1244 1244 uint32_t CI:1;
1245 1245 uint32_t rsvd2:1;
1246 1246 uint32_t TERP:1;
1247 1247 uint32_t rsvd3:4;
1248 1248 uint32_t update:1;
1249 1249 uint32_t did:24;
1250 1250 #endif
1251 1251 #ifdef EMLXS_LITTLE_ENDIAN
1252 1252 uint16_t rpi;
1253 1253 uint16_t rsvd1;
1254 1254 uint32_t did:24;
1255 1255 uint32_t update:1;
1256 1256 uint32_t rsvd3:4;
1257 1257 uint32_t TERP:1;
1258 1258 uint32_t rsvd2:1;
1259 1259 uint32_t CI:1;
1260 1260 #endif
1261 1261 union
1262 1262 {
1263 1263 ULP_BDE sp;
1264 1264 ULP_BDE64 sp64;
1265 1265 } un;
1266 1266
1267 1267 #ifdef EMLXS_BIG_ENDIAN
1268 1268 uint16_t rsvd6;
1269 1269 uint16_t vpi;
1270 1270 #endif
1271 1271 #ifdef EMLXS_LITTLE_ENDIAN
1272 1272 uint16_t vpi;
1273 1273 uint16_t rsvd6;
1274 1274 #endif
1275 1275 } REG_LOGIN_VAR;
1276 1276
1277 1277 /* Word 30 contents for REG_LOGIN */
1278 1278 typedef union
1279 1279 {
1280 1280 struct
1281 1281 {
1282 1282 #ifdef EMLXS_BIG_ENDIAN
1283 1283 uint16_t rsvd1:12;
1284 1284 uint16_t class:4;
1285 1285 uint16_t xri;
1286 1286 #endif
1287 1287 #ifdef EMLXS_LITTLE_ENDIAN
1288 1288 uint16_t xri;
1289 1289 uint16_t class:4;
1290 1290 uint16_t rsvd1:12;
1291 1291 #endif
1292 1292 } f;
1293 1293 uint32_t word;
1294 1294 } REG_WD30;
1295 1295
1296 1296
1297 1297 /* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */
1298 1298 /* Structure for MB Command UNREG_RPI (0x14) - SLI4 */
1299 1299
1300 1300 typedef struct
1301 1301 {
1302 1302 #ifdef EMLXS_BIG_ENDIAN
1303 1303 uint16_t ll:2; /* SLI4 only */
1304 1304 uint16_t rsvd1:14;
1305 1305 uint16_t rpi;
1306 1306 #endif
1307 1307 #ifdef EMLXS_LITTLE_ENDIAN
1308 1308 uint16_t rpi;
1309 1309 uint16_t rsvd1:14;
1310 1310 uint16_t ll:2; /* SLI4 only */
1311 1311 #endif
1312 1312
1313 1313 uint32_t rsvd2;
1314 1314 uint32_t rsvd3;
1315 1315 uint32_t rsvd4;
1316 1316 uint32_t rsvd5;
1317 1317 #ifdef EMLXS_BIG_ENDIAN
1318 1318 uint16_t rsvd6;
1319 1319 uint16_t vpi;
1320 1320 #endif
1321 1321 #ifdef EMLXS_LITTLE_ENDIAN
1322 1322 uint16_t vpi;
1323 1323 uint16_t rsvd6;
1324 1324 #endif
1325 1325 } UNREG_LOGIN_VAR;
1326 1326
1327 1327 /* Structure for MB Command REG_FCFI (0xA0) */
1328 1328 /* Good for SLI4 only */
1329 1329
1330 1330 typedef struct
1331 1331 {
1332 1332 #ifdef EMLXS_BIG_ENDIAN
1333 1333 uint16_t FCFI;
1334 1334 uint16_t InfoIndex;
1335 1335
1336 1336 uint16_t RQId0;
1337 1337 uint16_t RQId1;
1338 1338 uint16_t RQId2;
1339 1339 uint16_t RQId3;
1340 1340
1341 1341 uint8_t Id0_type;
1342 1342 uint8_t Id0_type_mask;
1343 1343 uint8_t Id0_rctl;
1344 1344 uint8_t Id0_rctl_mask;
1345 1345
1346 1346 uint8_t Id1_type;
1347 1347 uint8_t Id1_type_mask;
1348 1348 uint8_t Id1_rctl;
1349 1349 uint8_t Id1_rctl_mask;
1350 1350
1351 1351 uint8_t Id2_type;
1352 1352 uint8_t Id2_type_mask;
1353 1353 uint8_t Id2_rctl;
1354 1354 uint8_t Id2_rctl_mask;
1355 1355
1356 1356 uint8_t Id3_type;
1357 1357 uint8_t Id3_type_mask;
1358 1358 uint8_t Id3_rctl;
1359 1359 uint8_t Id3_rctl_mask;
1360 1360
1361 1361 uint32_t Rsvd1: 17;
1362 1362 uint32_t mam: 2;
1363 1363 uint32_t vv: 1;
1364 1364 uint32_t vlanTag: 12;
1365 1365 #endif
1366 1366 #ifdef EMLXS_LITTLE_ENDIAN
1367 1367 uint16_t InfoIndex;
1368 1368 uint16_t FCFI;
1369 1369
1370 1370 uint16_t RQId1;
1371 1371 uint16_t RQId0;
1372 1372 uint16_t RQId3;
1373 1373 uint16_t RQId2;
1374 1374
1375 1375 uint8_t Id0_rctl_mask;
1376 1376 uint8_t Id0_rctl;
1377 1377 uint8_t Id0_type_mask;
1378 1378 uint8_t Id0_type;
1379 1379
1380 1380 uint8_t Id1_rctl_mask;
1381 1381 uint8_t Id1_rctl;
1382 1382 uint8_t Id1_type_mask;
1383 1383 uint8_t Id1_type;
1384 1384
1385 1385 uint8_t Id2_rctl_mask;
1386 1386 uint8_t Id2_rctl;
1387 1387 uint8_t Id2_type_mask;
1388 1388 uint8_t Id2_type;
1389 1389
1390 1390 uint8_t Id3_rctl_mask;
1391 1391 uint8_t Id3_rctl;
1392 1392 uint8_t Id3_type_mask;
1393 1393 uint8_t Id3_type;
1394 1394
1395 1395 uint32_t vlanTag: 12;
1396 1396 uint32_t vv: 1;
1397 1397 uint32_t mam: 2;
1398 1398 uint32_t Rsvd1: 17;
1399 1399 #endif
1400 1400
1401 1401 } REG_FCFI_VAR;
1402 1402
1403 1403 /* Defines for mam */
1404 1404 #define EMLXS_REG_FCFI_MAM_SPMA 1 /* Server Provided MAC Address */
1405 1405 #define EMLXS_REG_FCFI_MAM_FPMA 2 /* Fabric Provided MAC Address */
1406 1406
1407 1407 /* Structure for MB Command UNREG_FCFI (0xA2) */
1408 1408 /* Good for SLI4 only */
1409 1409
1410 1410 typedef struct
1411 1411 {
1412 1412 uint32_t Rsvd1;
1413 1413 #ifdef EMLXS_BIG_ENDIAN
1414 1414 uint16_t Rsvd2;
1415 1415 uint16_t FCFI;
1416 1416 #endif
1417 1417 #ifdef EMLXS_LITTLE_ENDIAN
1418 1418 uint16_t FCFI;
1419 1419 uint16_t Rsvd2;
1420 1420 #endif
1421 1421 } UNREG_FCFI_VAR;
1422 1422
1423 1423 /* Structure for MB Command RESUME_RPI (0x9E) */
1424 1424 /* Good for SLI4 only */
1425 1425
1426 1426 typedef struct
1427 1427 {
1428 1428 #ifdef EMLXS_BIG_ENDIAN
1429 1429 uint16_t Rsvd1;
1430 1430 uint16_t RPI;
1431 1431
1432 1432 uint32_t EventTag;
1433 1433 uint32_t rsvd2[3];
1434 1434
1435 1435 uint16_t VFI;
1436 1436 uint16_t VPI;
1437 1437 #endif
1438 1438 #ifdef EMLXS_LITTLE_ENDIAN
1439 1439 uint16_t RPI;
1440 1440 uint16_t Rsvd1;
1441 1441
1442 1442 uint32_t EventTag;
1443 1443 uint32_t rsvd2[3];
1444 1444
1445 1445 uint16_t VPI;
1446 1446 uint16_t VFI;
1447 1447 #endif
1448 1448
1449 1449 } RESUME_RPI_VAR;
1450 1450
1451 1451
1452 1452 /* Structure for MB Command UNREG_D_ID (0x23) */
1453 1453
1454 1454 typedef struct
1455 1455 {
1456 1456 uint32_t did;
1457 1457
1458 1458 uint32_t rsvd2;
1459 1459 uint32_t rsvd3;
1460 1460 uint32_t rsvd4;
1461 1461 uint32_t rsvd5;
1462 1462 #ifdef EMLXS_BIG_ENDIAN
1463 1463 uint16_t rsvd6;
1464 1464 uint16_t vpi;
1465 1465 #endif
1466 1466 #ifdef EMLXS_LITTLE_ENDIAN
1467 1467 uint16_t vpi;
1468 1468 uint16_t rsvd6;
1469 1469 #endif
1470 1470 } UNREG_D_ID_VAR;
1471 1471
1472 1472
1473 1473 /* Structure for MB Command READ_LA (21) */
1474 1474 /* Structure for MB Command READ_LA64 (0x95) */
1475 1475
1476 1476 typedef struct
1477 1477 {
1478 1478 uint32_t eventTag; /* Event tag */
1479 1479 #ifdef EMLXS_BIG_ENDIAN
1480 1480 uint32_t rsvd2:19;
1481 1481 uint32_t fa:1;
1482 1482 uint32_t mm:1;
1483 1483 uint32_t tc:1;
1484 1484 uint32_t pb:1;
1485 1485 uint32_t il:1;
1486 1486 uint32_t attType:8;
1487 1487 #endif
1488 1488 #ifdef EMLXS_LITTLE_ENDIAN
1489 1489 uint32_t attType:8;
1490 1490 uint32_t il:1;
1491 1491 uint32_t pb:1;
1492 1492 uint32_t tc:1;
1493 1493 uint32_t mm:1;
1494 1494 uint32_t fa:1;
1495 1495 uint32_t rsvd2:19;
1496 1496 #endif
1497 1497 #define AT_RESERVED 0x00 /* Reserved - attType */
1498 1498 #define AT_LINK_UP 0x01 /* Link is up */
1499 1499 #define AT_LINK_DOWN 0x02 /* Link is down */
1500 1500 #define AT_NO_HARD_ALPA 0x03 /* SLI4 */
1501 1501
1502 1502 #ifdef EMLXS_BIG_ENDIAN
1503 1503 uint8_t granted_AL_PA;
1504 1504 uint8_t lipAlPs;
1505 1505 uint8_t lipType;
1506 1506 uint8_t topology;
1507 1507 #endif
1508 1508 #ifdef EMLXS_LITTLE_ENDIAN
1509 1509 uint8_t topology;
1510 1510 uint8_t lipType;
1511 1511 uint8_t lipAlPs;
1512 1512 uint8_t granted_AL_PA;
1513 1513 #endif
1514 1514
1515 1515 /* lipType */
1516 1516 #define LT_PORT_INIT 0x00 /* An L_PORT initing (F7, AL_PS) - lipType */
1517 1517 #define LT_PORT_ERR 0x01 /* Err @L_PORT rcv'er (F8, AL_PS) */
1518 1518 #define LT_RESET_APORT 0x02 /* Lip Reset of some other port */
1519 1519 #define LT_RESET_MYPORT 0x03 /* Lip Reset of my port */
1520 1520
1521 1521 /* topology */
1522 1522 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
1523 1523 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL (private) */
1524 1524
1525 1525 union
1526 1526 {
1527 1527 ULP_BDE lilpBde; /* This BDE points to a */
1528 1528 /* 128 byte buffer to store */
1529 1529 /* the LILP AL_PA position */
1530 1530 /* map into */
1531 1531 ULP_BDE64 lilpBde64;
1532 1532 } un;
1533 1533 #ifdef EMLXS_BIG_ENDIAN
1534 1534 uint32_t Dlu:1;
1535 1535 uint32_t Dtf:1;
1536 1536 uint32_t Drsvd2:14;
1537 1537 uint32_t DlnkSpeed:8;
1538 1538 uint32_t DnlPort:4;
1539 1539 uint32_t Dtx:2;
1540 1540 uint32_t Drx:2;
1541 1541 #endif
1542 1542 #ifdef EMLXS_LITTLE_ENDIAN
1543 1543 uint32_t Drx:2;
1544 1544 uint32_t Dtx:2;
1545 1545 uint32_t DnlPort:4;
1546 1546 uint32_t DlnkSpeed:8;
1547 1547 uint32_t Drsvd2:14;
1548 1548 uint32_t Dtf:1;
1549 1549 uint32_t Dlu:1;
1550 1550 #endif
1551 1551 #ifdef EMLXS_BIG_ENDIAN
1552 1552 uint32_t Ulu:1;
1553 1553 uint32_t Utf:1;
1554 1554 uint32_t Ursvd2:14;
1555 1555 uint32_t UlnkSpeed:8;
1556 1556 uint32_t UnlPort:4;
1557 1557 uint32_t Utx:2;
1558 1558 uint32_t Urx:2;
1559 1559 #endif
1560 1560 #ifdef EMLXS_LITTLE_ENDIAN
1561 1561 uint32_t Urx:2;
1562 1562 uint32_t Utx:2;
1563 1563 uint32_t UnlPort:4;
1564 1564 uint32_t UlnkSpeed:8;
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1565 1565 uint32_t Ursvd2:14;
1566 1566 uint32_t Utf:1;
1567 1567 uint32_t Ulu:1;
1568 1568 #endif
1569 1569 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
1570 1570 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
1571 1571 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
1572 1572 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
1573 1573 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
1574 1574 #define LA_16GHZ_LINK 0x80 /* lnkSpeed */
1575 +#define LA_32GHZ_LINK 0x90 /* lnkSpeed */
1575 1576 } READ_LA_VAR;
1576 1577
1577 1578
1578 1579 /* Structure for MB Command CLEAR_LA (22) */
1579 1580
1580 1581 typedef struct
1581 1582 {
1582 1583 uint32_t eventTag; /* Event tag */
1583 1584 uint32_t rsvd1;
1584 1585 } CLEAR_LA_VAR;
1585 1586
1586 1587 /* Structure for MB Command DUMP */
1587 1588 /* Good for SLI2/3 only */
1588 1589
1589 1590 typedef struct
1590 1591 {
1591 1592 #ifdef EMLXS_BIG_ENDIAN
1592 1593 uint32_t rsvd:25;
1593 1594 uint32_t ra:1;
1594 1595 uint32_t co:1;
1595 1596 uint32_t cv:1;
1596 1597 uint32_t type:4;
1597 1598
1598 1599 uint32_t entry_index:16;
1599 1600 uint32_t region_id:16;
1600 1601 #endif
1601 1602 #ifdef EMLXS_LITTLE_ENDIAN
1602 1603 uint32_t type:4;
1603 1604 uint32_t cv:1;
1604 1605 uint32_t co:1;
1605 1606 uint32_t ra:1;
1606 1607 uint32_t rsvd:25;
1607 1608
1608 1609 uint32_t region_id:16;
1609 1610 uint32_t entry_index:16;
1610 1611 #endif
1611 1612 uint32_t base_adr;
1612 1613 uint32_t word_cnt;
1613 1614 uint32_t resp_offset;
1614 1615 } DUMP_VAR;
1615 1616
1616 1617 /* Structure for MB Command DUMP */
1617 1618 /* Good for SLI4 only */
1618 1619
1619 1620 typedef struct
1620 1621 {
1621 1622 #ifdef EMLXS_BIG_ENDIAN
1622 1623 uint32_t ppi:4;
1623 1624 uint32_t phy_index:4;
1624 1625 uint32_t rsvd:20;
1625 1626 uint32_t type:4;
1626 1627
1627 1628 uint32_t entry_index:16;
1628 1629 uint32_t region_id:16;
1629 1630 #endif
1630 1631 #ifdef EMLXS_LITTLE_ENDIAN
1631 1632 uint32_t type:4;
1632 1633 uint32_t rsvd:20;
1633 1634 uint32_t phy_index:4;
1634 1635 uint32_t ppi:4;
1635 1636
1636 1637 uint32_t region_id:16;
1637 1638 uint32_t entry_index:16;
1638 1639 #endif
1639 1640 uint32_t available_cnt;
1640 1641 uint32_t addrLow;
1641 1642 uint32_t addrHigh;
1642 1643 uint32_t rsp_cnt;
1643 1644 } DUMP4_VAR;
1644 1645
1645 1646 /*
1646 1647 * Dump type
1647 1648 */
1648 1649 #define DMP_MEM_REG 0x1
1649 1650 #define DMP_NV_PARAMS 0x2
1650 1651
1651 1652 /*
1652 1653 * Dump region ID
1653 1654 */
1654 1655 #define NODE_CFG_A_REGION_ID 0
1655 1656 #define NODE_CFG_B_REGION_ID 1
1656 1657 #define NODE_CFG_C_REGION_ID 2
1657 1658 #define NODE_CFG_D_REGION_ID 3
1658 1659 #define WAKE_UP_PARMS_REGION_ID 4
1659 1660 #define DEF_PCI_CFG_REGION_ID 5
1660 1661 #define PCI_CFG_1_REGION_ID 6
1661 1662 #define PCI_CFG_2_REGION_ID 7
1662 1663 #define RSVD1_REGION_ID 8
1663 1664 #define RSVD2_REGION_ID 9
1664 1665 #define RSVD3_REGION_ID 10
1665 1666 #define RSVD4_REGION_ID 11
1666 1667 #define RSVD5_REGION_ID 12
1667 1668 #define RSVD6_REGION_ID 13
1668 1669 #define RSVD7_REGION_ID 14
1669 1670 #define DIAG_TRACE_REGION_ID 15
1670 1671 #define WWN_REGION_ID 16
1671 1672
1672 1673 #define DMP_VPD_REGION 14
1673 1674 #define DMP_VPD_SIZE 1024
1674 1675 #define DMP_VPD_DUMP_WCOUNT 24
1675 1676
1676 1677 #define DMP_FCOE_REGION 23
1677 1678 #define DMP_FCOE_DUMP_WCOUNT 256
1678 1679
1679 1680
1680 1681 /* Structure for MB Command UPDATE_CFG */
1681 1682 /* Good for SLI2/3 and SLI4 */
1682 1683
1683 1684 typedef struct
1684 1685 {
1685 1686 #ifdef EMLXS_BIG_ENDIAN
1686 1687 uint32_t rsvd2:16;
1687 1688 uint32_t proc_type:8;
1688 1689 uint32_t rsvd1:1;
1689 1690 uint32_t Abit:1;
1690 1691 uint32_t Obit:1;
1691 1692 uint32_t Vbit:1;
1692 1693 uint32_t req_type:4;
1693 1694 #define INIT_REGION 1
1694 1695 #define UPDATE_DATA 2
1695 1696 #define CLEAN_UP_CFG 3
1696 1697 uint32_t entry_len:16;
1697 1698 uint32_t region_id:16;
1698 1699 #endif
1699 1700
1700 1701 #ifdef EMLXS_LITTLE_ENDIAN
1701 1702 uint32_t req_type:4;
1702 1703 #define INIT_REGION 1
1703 1704 #define UPDATE_DATA 2
1704 1705 #define CLEAN_UP_CFG 3
1705 1706 uint32_t Vbit:1;
1706 1707 uint32_t Obit:1;
1707 1708 uint32_t Abit:1;
1708 1709 uint32_t rsvd1:1;
1709 1710 uint32_t proc_type:8;
1710 1711 uint32_t rsvd2:16;
1711 1712
1712 1713 uint32_t region_id:16;
1713 1714 uint32_t entry_len:16;
1714 1715 #endif
1715 1716
1716 1717 uint32_t rsp_info;
1717 1718 uint32_t byte_len;
1718 1719 uint32_t cfg_data;
1719 1720 } UPDATE_CFG_VAR;
1720 1721
1721 1722 /* Structure for MB Command DEL_LD_ENTRY (29) */
1722 1723
1723 1724 typedef struct
1724 1725 {
1725 1726 #ifdef EMLXS_LITTLE_ENDIAN
1726 1727 uint32_t list_req:2;
1727 1728 uint32_t list_rsp:2;
1728 1729 uint32_t rsvd:28;
1729 1730 #else
1730 1731 uint32_t rsvd:28;
1731 1732 uint32_t list_rsp:2;
1732 1733 uint32_t list_req:2;
1733 1734 #endif
1734 1735
1735 1736 #define FLASH_LOAD_LIST 1
1736 1737 #define RAM_LOAD_LIST 2
1737 1738 #define BOTH_LISTS 3
1738 1739
1739 1740 PROG_ID prog_id;
1740 1741 } DEL_LD_ENTRY_VAR;
1741 1742
1742 1743 /* Structure for MB Command LOAD_AREA (81) */
1743 1744 typedef struct
1744 1745 {
1745 1746 #ifdef EMLXS_LITTLE_ENDIAN
1746 1747 uint32_t load_cmplt:1;
1747 1748 uint32_t method:1;
1748 1749 uint32_t rsvd1:1;
1749 1750 uint32_t update_flash:1;
1750 1751 uint32_t erase_or_prog:1;
1751 1752 uint32_t version:1;
1752 1753 uint32_t rsvd2:2;
1753 1754 uint32_t progress:8;
1754 1755 uint32_t step:8;
1755 1756 uint32_t area_id:8;
1756 1757 #else
1757 1758 uint32_t area_id:8;
1758 1759 uint32_t step:8;
1759 1760 uint32_t progress:8;
1760 1761 uint32_t rsvd2:2;
1761 1762 uint32_t version:1;
1762 1763 uint32_t erase_or_prog:1;
1763 1764 uint32_t update_flash:1;
1764 1765 uint32_t rsvd1:1;
1765 1766 uint32_t method:1;
1766 1767 uint32_t load_cmplt:1;
1767 1768 #endif
1768 1769 uint32_t dl_to_adr;
1769 1770 uint32_t dl_len;
1770 1771 union
1771 1772 {
1772 1773 uint32_t dl_from_slim_offset;
1773 1774 ULP_BDE dl_from_bde;
1774 1775 ULP_BDE64 dl_from_bde64;
1775 1776 PROG_ID prog_id;
1776 1777 } un;
1777 1778 } LOAD_AREA_VAR;
1778 1779
1779 1780 /* Structure for MB Command LOAD_EXP_ROM (9C) */
1780 1781 typedef struct
1781 1782 {
1782 1783 #ifdef EMLXS_LITTLE_ENDIAN
1783 1784 uint32_t rsvd1:8;
1784 1785 uint32_t progress:8;
1785 1786 uint32_t step:8;
1786 1787 uint32_t rsvd2:8;
1787 1788 #else
1788 1789 uint32_t rsvd2:8;
1789 1790 uint32_t step:8;
1790 1791 uint32_t progress:8;
1791 1792 uint32_t rsvd1:8;
1792 1793 #endif
1793 1794 uint32_t dl_to_adr;
1794 1795 uint32_t rsvd3;
1795 1796 union
1796 1797 {
1797 1798 uint32_t word[2];
1798 1799 PROG_ID prog_id;
1799 1800 } un;
1800 1801 } LOAD_EXP_ROM_VAR;
1801 1802
1802 1803
1803 1804 /* Structure for MB Command CONFIG_HBQ (7C) */
1804 1805
1805 1806 typedef struct
1806 1807 {
1807 1808 #ifdef EMLXS_BIG_ENDIAN
1808 1809 uint32_t rsvd1:7;
1809 1810 uint32_t recvNotify:1; /* Receive Notification */
1810 1811 uint32_t numMask:8; /* # Mask Entries */
1811 1812 uint32_t profile:8; /* Selection Profile */
1812 1813 uint32_t rsvd2:8;
1813 1814 #endif
1814 1815 #ifdef EMLXS_LITTLE_ENDIAN
1815 1816 uint32_t rsvd2:8;
1816 1817 uint32_t profile:8; /* Selection Profile */
1817 1818 uint32_t numMask:8; /* # Mask Entries */
1818 1819 uint32_t recvNotify:1; /* Receive Notification */
1819 1820 uint32_t rsvd1:7;
1820 1821 #endif
1821 1822
1822 1823 #ifdef EMLXS_BIG_ENDIAN
1823 1824 uint32_t hbqId:16;
1824 1825 uint32_t rsvd3:12;
1825 1826 uint32_t ringMask:4;
1826 1827 #endif
1827 1828 #ifdef EMLXS_LITTLE_ENDIAN
1828 1829 uint32_t ringMask:4;
1829 1830 uint32_t rsvd3:12;
1830 1831 uint32_t hbqId:16;
1831 1832 #endif
1832 1833
1833 1834 #ifdef EMLXS_BIG_ENDIAN
1834 1835 uint32_t numEntries:16;
1835 1836 uint32_t rsvd4:8;
1836 1837 uint32_t headerLen:8;
1837 1838 #endif
1838 1839 #ifdef EMLXS_LITTLE_ENDIAN
1839 1840 uint32_t headerLen:8;
1840 1841 uint32_t rsvd4:8;
1841 1842 uint32_t numEntries:16;
1842 1843 #endif
1843 1844
1844 1845 uint32_t hbqaddrLow;
1845 1846 uint32_t hbqaddrHigh;
1846 1847
1847 1848 #ifdef EMLXS_BIG_ENDIAN
1848 1849 uint32_t rsvd5:31;
1849 1850 uint32_t logEntry:1;
1850 1851 #endif
1851 1852 #ifdef EMLXS_LITTLE_ENDIAN
1852 1853 uint32_t logEntry:1;
1853 1854 uint32_t rsvd5:31;
1854 1855 #endif
1855 1856
1856 1857 uint32_t rsvd6; /* w7 */
1857 1858 uint32_t rsvd7; /* w8 */
1858 1859 uint32_t rsvd8; /* w9 */
1859 1860
1860 1861 HBQ_MASK hbqMasks[6];
1861 1862
1862 1863 union
1863 1864 {
1864 1865 uint32_t allprofiles[12];
1865 1866
1866 1867 struct
1867 1868 {
1868 1869 #ifdef EMLXS_BIG_ENDIAN
1869 1870 uint32_t seqlenoff:16;
1870 1871 uint32_t maxlen:16;
1871 1872 #endif
1872 1873 #ifdef EMLXS_LITTLE_ENDIAN
1873 1874 uint32_t maxlen:16;
1874 1875 uint32_t seqlenoff:16;
1875 1876 #endif
1876 1877 #ifdef EMLXS_BIG_ENDIAN
1877 1878 uint32_t rsvd1:28;
1878 1879 uint32_t seqlenbcnt:4;
1879 1880 #endif
1880 1881 #ifdef EMLXS_LITTLE_ENDIAN
1881 1882 uint32_t seqlenbcnt:4;
1882 1883 uint32_t rsvd1:28;
1883 1884 #endif
1884 1885 uint32_t rsvd[10];
1885 1886 } profile2;
1886 1887
1887 1888 struct
1888 1889 {
1889 1890 #ifdef EMLXS_BIG_ENDIAN
1890 1891 uint32_t seqlenoff:16;
1891 1892 uint32_t maxlen:16;
1892 1893 #endif
1893 1894 #ifdef EMLXS_LITTLE_ENDIAN
1894 1895 uint32_t maxlen:16;
1895 1896 uint32_t seqlenoff:16;
1896 1897 #endif
1897 1898 #ifdef EMLXS_BIG_ENDIAN
1898 1899 uint32_t cmdcodeoff:28;
1899 1900 uint32_t rsvd1:12;
1900 1901 uint32_t seqlenbcnt:4;
1901 1902 #endif
1902 1903 #ifdef EMLXS_LITTLE_ENDIAN
1903 1904 uint32_t seqlenbcnt:4;
1904 1905 uint32_t rsvd1:12;
1905 1906 uint32_t cmdcodeoff:28;
1906 1907 #endif
1907 1908 uint32_t cmdmatch[8];
1908 1909
1909 1910 uint32_t rsvd[2];
1910 1911 } profile3;
1911 1912
1912 1913 struct
1913 1914 {
1914 1915 #ifdef EMLXS_BIG_ENDIAN
1915 1916 uint32_t seqlenoff:16;
1916 1917 uint32_t maxlen:16;
1917 1918 #endif
1918 1919 #ifdef EMLXS_LITTLE_ENDIAN
1919 1920 uint32_t maxlen:16;
1920 1921 uint32_t seqlenoff:16;
1921 1922 #endif
1922 1923 #ifdef EMLXS_BIG_ENDIAN
1923 1924 uint32_t cmdcodeoff:28;
1924 1925 uint32_t rsvd1:12;
1925 1926 uint32_t seqlenbcnt:4;
1926 1927 #endif
1927 1928 #ifdef EMLXS_LITTLE_ENDIAN
1928 1929 uint32_t seqlenbcnt:4;
1929 1930 uint32_t rsvd1:12;
1930 1931 uint32_t cmdcodeoff:28;
1931 1932 #endif
1932 1933 uint32_t cmdmatch[8];
1933 1934
1934 1935 uint32_t rsvd[2];
1935 1936 } profile5;
1936 1937 } profiles;
1937 1938 } CONFIG_HBQ_VAR;
1938 1939
1939 1940
1940 1941 /* Structure for MB Command REG_VPI(0x96) */
1941 1942 /* Good for SLI2/3 and SLI4 */
1942 1943
1943 1944 typedef struct
1944 1945 {
1945 1946 #ifdef EMLXS_BIG_ENDIAN
1946 1947 uint32_t rsvd1;
1947 1948 uint32_t rsvd2:7;
1948 1949 uint32_t upd:1;
1949 1950 uint32_t sid:24;
1950 1951 uint32_t portname[2]; /* N_PORT name */
1951 1952 uint32_t rsvd5;
1952 1953 uint16_t vfi;
1953 1954 uint16_t vpi;
1954 1955 #endif
1955 1956 #ifdef EMLXS_LITTLE_ENDIAN
1956 1957 uint32_t rsvd1;
1957 1958 uint32_t sid:24;
1958 1959 uint32_t upd:1;
1959 1960 uint32_t rsvd2:7;
1960 1961 uint32_t portname[2]; /* N_PORT name */
1961 1962 uint32_t rsvd5;
1962 1963 uint16_t vpi;
1963 1964 uint16_t vfi;
1964 1965 #endif
1965 1966 } REG_VPI_VAR;
1966 1967
1967 1968 /* Structure for MB Command INIT_VPI(0xA3) */
1968 1969 /* Good for SLI4 only */
1969 1970
1970 1971 typedef struct
1971 1972 {
1972 1973 #ifdef EMLXS_BIG_ENDIAN
1973 1974 uint16_t vfi;
1974 1975 uint16_t vpi;
1975 1976 #endif
1976 1977 #ifdef EMLXS_LITTLE_ENDIAN
1977 1978 uint16_t vpi;
1978 1979 uint16_t vfi;
1979 1980 #endif
1980 1981 } INIT_VPI_VAR;
1981 1982
1982 1983 /* Structure for MB Command UNREG_VPI (0x97) */
1983 1984 /* Good for SLI2/3 */
1984 1985
1985 1986 typedef struct
1986 1987 {
1987 1988 uint32_t rsvd1;
1988 1989 uint32_t rsvd2;
1989 1990 uint32_t rsvd3;
1990 1991 uint32_t rsvd4;
1991 1992 uint32_t rsvd5;
1992 1993 #ifdef EMLXS_BIG_ENDIAN
1993 1994 uint16_t rsvd6;
1994 1995 uint16_t vpi;
1995 1996 #endif
1996 1997 #ifdef EMLXS_LITTLE_ENDIAN
1997 1998 uint16_t vpi;
1998 1999 uint16_t rsvd6;
1999 2000 #endif
2000 2001 } UNREG_VPI_VAR;
2001 2002
2002 2003 /* Structure for MB Command UNREG_VPI (0x97) */
2003 2004 /* Good for SLI4 */
2004 2005
2005 2006 typedef struct
2006 2007 {
2007 2008 uint32_t rsvd1;
2008 2009 #ifdef EMLXS_BIG_ENDIAN
2009 2010 uint8_t ii:2;
2010 2011 uint16_t rsvd2:14;
2011 2012 uint16_t index;
2012 2013 #endif
2013 2014 #ifdef EMLXS_LITTLE_ENDIAN
2014 2015 uint16_t index;
2015 2016 uint16_t rsvd2:14;
2016 2017 uint8_t ii:2;
2017 2018 #endif
2018 2019 } UNREG_VPI_VAR4;
2019 2020
2020 2021 /* Structure for MB Command REG_VFI(0x9F) */
2021 2022 /* Good for SLI4 only */
2022 2023
2023 2024 typedef struct
2024 2025 {
2025 2026 #ifdef EMLXS_BIG_ENDIAN
2026 2027 uint16_t rsvd1:2;
2027 2028 uint16_t upd:1;
2028 2029 uint16_t vp:1;
2029 2030 uint16_t rsvd2:12;
2030 2031 uint16_t vfi;
2031 2032
2032 2033 uint16_t vpi;
2033 2034 uint16_t fcfi;
2034 2035
2035 2036 uint32_t portname[2]; /* N_PORT name */
2036 2037
2037 2038 ULP_BDE64 bde;
2038 2039
2039 2040 /* CHANGE with next firmware drop */
2040 2041 uint32_t edtov;
2041 2042 uint32_t ratov;
2042 2043
2043 2044 uint32_t rsvd5:8;
2044 2045 uint32_t sid:24;
2045 2046 #endif
2046 2047 #ifdef EMLXS_LITTLE_ENDIAN
2047 2048 uint16_t vfi;
2048 2049 uint16_t rsvd2:12;
2049 2050 uint16_t vp:1;
2050 2051 uint16_t upd:1;
2051 2052 uint16_t rsvd1:2;
2052 2053
2053 2054 uint16_t fcfi;
2054 2055 uint16_t vpi;
2055 2056
2056 2057 uint32_t portname[2]; /* N_PORT name */
2057 2058
2058 2059 ULP_BDE64 bde;
2059 2060
2060 2061 /* CHANGE with next firmware drop */
2061 2062 uint32_t edtov;
2062 2063 uint32_t ratov;
2063 2064
2064 2065 uint32_t sid:24;
2065 2066 uint32_t rsvd5:8;
2066 2067 #endif
2067 2068 } REG_VFI_VAR;
2068 2069
2069 2070 /* Structure for MB Command INIT_VFI(0xA4) */
2070 2071 /* Good for SLI4 only */
2071 2072
2072 2073 typedef struct
2073 2074 {
2074 2075 #ifdef EMLXS_BIG_ENDIAN
2075 2076 uint32_t vr:1;
2076 2077 uint32_t vt:1;
2077 2078 uint32_t vf:1;
2078 2079 uint32_t rsvd1:13;
2079 2080 uint32_t vfi:16;
2080 2081
2081 2082 uint16_t rsvd2;
2082 2083 uint16_t fcfi;
2083 2084
2084 2085 uint32_t rsvd3:16;
2085 2086 uint32_t pri:3;
2086 2087 uint32_t vf_id:12;
2087 2088 uint32_t rsvd4:1;
2088 2089
2089 2090 uint32_t hop_count:8;
2090 2091 uint32_t rsvd5:24;
2091 2092 #endif
2092 2093 #ifdef EMLXS_LITTLE_ENDIAN
2093 2094 uint32_t vfi:16;
2094 2095 uint32_t rsvd1:13;
2095 2096 uint32_t vf:1;
2096 2097 uint32_t vt:1;
2097 2098 uint32_t vr:1;
2098 2099
2099 2100 uint16_t fcfi;
2100 2101 uint16_t rsvd2;
2101 2102
2102 2103 uint32_t rsvd4:1;
2103 2104 uint32_t vf_id:12;
2104 2105 uint32_t pri:3;
2105 2106 uint32_t rsvd3:16;
2106 2107
2107 2108 uint32_t rsvd5:24;
2108 2109 uint32_t hop_count:8;
2109 2110 #endif
2110 2111 } INIT_VFI_VAR;
2111 2112
2112 2113 /* Structure for MB Command UNREG_VFI (0xA1) */
2113 2114 /* Good for SLI4 only */
2114 2115
2115 2116 typedef struct
2116 2117 {
2117 2118 #ifdef EMLXS_BIG_ENDIAN
2118 2119 uint32_t rsvd1:3;
2119 2120 uint32_t vp:1;
2120 2121 uint32_t rsvd2:28;
2121 2122
2122 2123 uint16_t vpi;
2123 2124 uint16_t vfi;
2124 2125 #endif
2125 2126 #ifdef EMLXS_LITTLE_ENDIAN
2126 2127 uint32_t rsvd2:28;
2127 2128 uint32_t vp:1;
2128 2129 uint32_t rsvd1:3;
2129 2130
2130 2131 uint16_t vfi;
2131 2132 uint16_t vpi;
2132 2133 #endif
2133 2134 } UNREG_VFI_VAR;
2134 2135
2135 2136
2136 2137
2137 2138 typedef struct
2138 2139 {
2139 2140 #ifdef EMLXS_BIG_ENDIAN
2140 2141 uint32_t read_log:1;
2141 2142 uint32_t clear_log:1;
2142 2143 uint32_t mbox_rsp:1;
2143 2144 uint32_t resv:28;
2144 2145 #endif
2145 2146 #ifdef EMLXS_LITTLE_ENDIAN
2146 2147 uint32_t resv:28;
2147 2148 uint32_t mbox_rsp:1;
2148 2149 uint32_t clear_log:1;
2149 2150 uint32_t read_log:1;
2150 2151 #endif
2151 2152
2152 2153 uint32_t offset;
2153 2154
2154 2155 union
2155 2156 {
2156 2157 ULP_BDE sp;
2157 2158 ULP_BDE64 sp64;
2158 2159 } un;
2159 2160 } READ_EVT_LOG_VAR;
2160 2161
2161 2162 typedef struct
2162 2163 {
2163 2164
2164 2165 #ifdef EMLXS_BIG_ENDIAN
2165 2166 uint16_t split_log_next;
2166 2167 uint16_t log_next;
2167 2168
2168 2169 uint32_t size;
2169 2170
2170 2171 uint32_t format:8;
2171 2172 uint32_t resv2:22;
2172 2173 uint32_t log_level:1;
2173 2174 uint32_t split_log:1;
2174 2175 #endif
2175 2176 #ifdef EMLXS_LITTLE_ENDIAN
2176 2177 uint16_t log_next;
2177 2178 uint16_t split_log_next;
2178 2179
2179 2180 uint32_t size;
2180 2181
2181 2182 uint32_t split_log:1;
2182 2183 uint32_t log_level:1;
2183 2184 uint32_t resv2:22;
2184 2185 uint32_t format:8;
2185 2186 #endif
2186 2187
2187 2188 uint32_t offset;
2188 2189 } LOG_STATUS_VAR;
2189 2190
2190 2191
2191 2192 /* Structure for MB Command CONFIG_PORT (0x88) */
2192 2193 typedef struct
2193 2194 {
2194 2195 #ifdef EMLXS_BIG_ENDIAN
2195 2196 uint32_t cBE:1;
2196 2197 uint32_t cET:1;
2197 2198 uint32_t cHpcb:1;
2198 2199 uint32_t rMA:1;
2199 2200 uint32_t sli_mode:4;
2200 2201 uint32_t pcbLen:24; /* bit 23:0 of memory based port */
2201 2202 /* config block */
2202 2203 #endif
2203 2204 #ifdef EMLXS_LITTLE_ENDIAN
2204 2205 uint32_t pcbLen:24; /* bit 23:0 of memory based port */
2205 2206 /* config block */
2206 2207 uint32_t sli_mode:4;
2207 2208 uint32_t rMA:1;
2208 2209 uint32_t cHpcb:1;
2209 2210 uint32_t cET:1;
2210 2211 uint32_t cBE:1;
2211 2212 #endif
2212 2213
2213 2214 uint32_t pcbLow; /* bit 31:0 of memory based port */
2214 2215 /* config block */
2215 2216 uint32_t pcbHigh; /* bit 63:32 of memory based port */
2216 2217 /* config block */
2217 2218 uint32_t hbainit[5];
2218 2219
2219 2220 #ifdef EMLXS_BIG_ENDIAN
2220 2221 uint32_t hps:1; /* Host pointers in SLIM */
2221 2222 uint32_t rsvd:31;
2222 2223 #endif
2223 2224 #ifdef EMLXS_LITTLE_ENDIAN
2224 2225 uint32_t rsvd:31;
2225 2226 uint32_t hps:1; /* Host pointers in SLIM */
2226 2227 #endif
2227 2228
2228 2229 #ifdef EMLXS_BIG_ENDIAN
2229 2230 uint32_t rsvd1:24;
2230 2231 uint32_t cmv:1; /* Configure Max VPIs */
2231 2232 uint32_t ccrp:1; /* Config Command Ring Polling */
2232 2233 uint32_t csah:1; /* Configure Synchronous Abort */
2233 2234 /* Handling */
2234 2235 uint32_t chbs:1; /* Cofigure Host Backing store */
2235 2236 uint32_t cinb:1; /* Enable Interrupt Notification */
2236 2237 /* Block */
2237 2238 uint32_t cerbm:1; /* Configure Enhanced Receive */
2238 2239 /* Buffer Management */
2239 2240 uint32_t cmx:1; /* Configure Max XRIs */
2240 2241 uint32_t cmr:1; /* Configure Max RPIs */
2241 2242 #endif
2242 2243 #ifdef EMLXS_LITTLE_ENDIAN
2243 2244 uint32_t cmr:1; /* Configure Max RPIs */
2244 2245 uint32_t cmx:1; /* Configure Max XRIs */
2245 2246 uint32_t cerbm:1; /* Configure Enhanced Receive */
2246 2247 /* Buffer Management */
2247 2248 uint32_t cinb:1; /* Enable Interrupt Notification */
2248 2249 /* Block */
2249 2250 uint32_t chbs:1; /* Cofigure Host Backing store */
2250 2251 uint32_t csah:1; /* Configure Synchronous Abort */
2251 2252 /* Handling */
2252 2253 uint32_t ccrp:1; /* Config Command Ring Polling */
2253 2254 uint32_t cmv:1; /* Configure Max VPIs */
2254 2255 uint32_t rsvd1:24;
2255 2256 #endif
2256 2257 #ifdef EMLXS_BIG_ENDIAN
2257 2258 uint32_t rsvd2:19; /* Reserved */
2258 2259 uint32_t gdss:1; /* Configure Data Security SLI */
2259 2260 uint32_t rsvd3:3; /* Reserved */
2260 2261 uint32_t gbg:1; /* Grant BlockGuard */
2261 2262 uint32_t gmv:1; /* Grant Max VPIs */
2262 2263 uint32_t gcrp:1; /* Grant Command Ring Polling */
2263 2264 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2264 2265 uint32_t ghbs:1; /* Grant Host Backing Store */
2265 2266 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2266 2267 uint32_t gerbm:1; /* Grant ERBM Request */
2267 2268 uint32_t gmx:1; /* Grant Max XRIs */
2268 2269 uint32_t gmr:1; /* Grant Max RPIs */
2269 2270 #endif
2270 2271 #ifdef EMLXS_LITTLE_ENDIAN
2271 2272 uint32_t gmr:1; /* Grant Max RPIs */
2272 2273 uint32_t gmx:1; /* Grant Max XRIs */
2273 2274 uint32_t gerbm:1; /* Grant ERBM Request */
2274 2275 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2275 2276 uint32_t ghbs:1; /* Grant Host Backing Store */
2276 2277 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2277 2278 uint32_t gcrp:1; /* Grant Command Ring Polling */
2278 2279 uint32_t gmv:1; /* Grant Max VPIs */
2279 2280 uint32_t gbg:1; /* Grant BlockGuard */
2280 2281 uint32_t rsvd3:3; /* Reserved */
2281 2282 uint32_t gdss:1; /* Configure Data Security SLI */
2282 2283 uint32_t rsvd2:19; /* Reserved */
2283 2284 #endif
2284 2285
2285 2286 #ifdef EMLXS_BIG_ENDIAN
2286 2287 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2287 2288 uint32_t max_xri:16; /* Max XRIs Port should configure */
2288 2289 #endif
2289 2290 #ifdef EMLXS_LITTLE_ENDIAN
2290 2291 uint32_t max_xri:16; /* Max XRIs Port should configure */
2291 2292 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2292 2293 #endif
2293 2294
2294 2295 #ifdef EMLXS_BIG_ENDIAN
2295 2296 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2296 2297 uint32_t rsvd4:16; /* Max HBQs Host expect to configure */
2297 2298 #endif
2298 2299 #ifdef EMLXS_LITTLE_ENDIAN
2299 2300 uint32_t rsvd4:16; /* Max HBQs Host expect to configure */
2300 2301 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2301 2302 #endif
2302 2303
2303 2304 uint32_t rsvd5; /* Reserved */
2304 2305
2305 2306 #ifdef EMLXS_BIG_ENDIAN
2306 2307 uint32_t rsvd6:16; /* Reserved */
2307 2308 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2308 2309 #endif
2309 2310 #ifdef EMLXS_LITTLE_ENDIAN
2310 2311 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2311 2312 uint32_t rsvd6:16; /* Reserved */
2312 2313 #endif
2313 2314 } CONFIG_PORT_VAR;
2314 2315
2315 2316 /* Structure for MB Command REQUEST_FEATURES (0x9D) */
2316 2317 /* Good for SLI4 only */
2317 2318
2318 2319 typedef struct
2319 2320 {
2320 2321 #ifdef EMLXS_BIG_ENDIAN
2321 2322 uint32_t rsvd1:31;
2322 2323 uint32_t QueryMode:1;
2323 2324 #endif
2324 2325 #ifdef EMLXS_LITTLE_ENDIAN
2325 2326 uint32_t QueryMode:1;
2326 2327 uint32_t rsvd1:31;
2327 2328 #endif
2328 2329
2329 2330 uint32_t featuresRequested;
2330 2331 uint32_t featuresEnabled;
2331 2332
2332 2333 } REQUEST_FEATURES_VAR;
2333 2334
2334 2335 #define SLI4_FEATURE_INHIBIT_AUTO_ABTS 0x0001
2335 2336 #define SLI4_FEATURE_NPIV 0x0002
2336 2337 #define SLI4_FEATURE_DIF 0x0004
2337 2338 #define SLI4_FEATURE_VIRTUAL_FABRICS 0x0008
2338 2339 #define SLI4_FEATURE_FCP_INITIATOR 0x0010
2339 2340 #define SLI4_FEATURE_FCP_TARGET 0x0020
2340 2341 #define SLI4_FEATURE_FCP_COMBO 0x0040
2341 2342 #define SLI4_FEATURE_RSVD1 0x0080
2342 2343 #define SLI4_FEATURE_RQD 0x0100
2343 2344 #define SLI4_FEATURE_INHIBIT_AUTO_ABTS_R 0x0200
2344 2345 #define SLI4_FEATURE_HIGH_LOGIN_MODE 0x0400
2345 2346 #define SLI4_FEATURE_PERF_HINT 0x0800
2346 2347
2347 2348
2348 2349 /* SLI-2 Port Control Block */
2349 2350
2350 2351 /* SLIM POINTER */
2351 2352 #define SLIMOFF 0x30 /* WORD */
2352 2353
2353 2354 typedef struct _SLI2_RDSC
2354 2355 {
2355 2356 uint32_t cmdEntries;
2356 2357 uint32_t cmdAddrLow;
2357 2358 uint32_t cmdAddrHigh;
2358 2359
2359 2360 uint32_t rspEntries;
2360 2361 uint32_t rspAddrLow;
2361 2362 uint32_t rspAddrHigh;
2362 2363 } SLI2_RDSC;
2363 2364
2364 2365 typedef struct _PCB
2365 2366 {
2366 2367 #ifdef EMLXS_BIG_ENDIAN
2367 2368 uint32_t type:8;
2368 2369 #define TYPE_NATIVE_SLI2 0x01;
2369 2370 uint32_t feature:8;
2370 2371 #define FEATURE_INITIAL_SLI2 0x01;
2371 2372 uint32_t rsvd:12;
2372 2373 uint32_t maxRing:4;
2373 2374 #endif
2374 2375 #ifdef EMLXS_LITTLE_ENDIAN
2375 2376 uint32_t maxRing:4;
2376 2377 uint32_t rsvd:12;
2377 2378 uint32_t feature:8;
2378 2379 #define FEATURE_INITIAL_SLI2 0x01;
2379 2380 uint32_t type:8;
2380 2381 #define TYPE_NATIVE_SLI2 0x01;
2381 2382 #endif
2382 2383
2383 2384 uint32_t mailBoxSize;
2384 2385 uint32_t mbAddrLow;
2385 2386 uint32_t mbAddrHigh;
2386 2387
2387 2388 uint32_t hgpAddrLow;
2388 2389 uint32_t hgpAddrHigh;
2389 2390
2390 2391 uint32_t pgpAddrLow;
2391 2392 uint32_t pgpAddrHigh;
2392 2393 SLI2_RDSC rdsc[MAX_RINGS_AVAILABLE];
2393 2394 } PCB;
2394 2395
2395 2396 /* NEW_FEATURE */
2396 2397 typedef struct
2397 2398 {
2398 2399 #ifdef EMLXS_BIG_ENDIAN
2399 2400 uint32_t rsvd0:27;
2400 2401 uint32_t discardFarp:1;
2401 2402 uint32_t IPEnable:1;
2402 2403 uint32_t nodeName:1;
2403 2404 uint32_t portName:1;
2404 2405 uint32_t filterEnable:1;
2405 2406 #endif
2406 2407 #ifdef EMLXS_LITTLE_ENDIAN
2407 2408 uint32_t filterEnable:1;
2408 2409 uint32_t portName:1;
2409 2410 uint32_t nodeName:1;
2410 2411 uint32_t IPEnable:1;
2411 2412 uint32_t discardFarp:1;
2412 2413 uint32_t rsvd:27;
2413 2414 #endif
2414 2415 NAME_TYPE portname;
2415 2416 NAME_TYPE nodename;
2416 2417 uint32_t rsvd1;
2417 2418 uint32_t rsvd2;
2418 2419 uint32_t rsvd3;
2419 2420 uint32_t IPAddress;
2420 2421 } CONFIG_FARP_VAR;
2421 2422
2422 2423
2423 2424 /* NEW_FEATURE */
2424 2425 typedef struct
2425 2426 {
2426 2427 #ifdef EMLXS_BIG_ENDIAN
2427 2428 uint32_t defaultMessageNumber:16;
2428 2429 uint32_t rsvd1:3;
2429 2430 uint32_t nid:5;
2430 2431 uint32_t rsvd2:5;
2431 2432 uint32_t defaultPresent:1;
2432 2433 uint32_t addAssociations:1;
2433 2434 uint32_t reportAssociations:1;
2434 2435 #endif
2435 2436 #ifdef EMLXS_LITTLE_ENDIAN
2436 2437 uint32_t reportAssociations:1;
2437 2438 uint32_t addAssociations:1;
2438 2439 uint32_t defaultPresent:1;
2439 2440 uint32_t rsvd2:5;
2440 2441 uint32_t nid:5;
2441 2442 uint32_t rsvd1:3;
2442 2443 uint32_t defaultMessageNumber:16;
2443 2444 #endif
2444 2445 uint32_t attConditions;
2445 2446 uint8_t attentionId[16];
2446 2447 uint16_t messageNumberByHA[32];
2447 2448 uint16_t messageNumberByID[16];
2448 2449 uint32_t rsvd3;
2449 2450 } CONFIG_MSI_VAR;
2450 2451
2451 2452
2452 2453 /* NEW_FEATURE */
2453 2454 typedef struct
2454 2455 {
2455 2456 #ifdef EMLXS_BIG_ENDIAN
2456 2457 uint32_t defaultMessageNumber:8;
2457 2458 uint32_t rsvd1:11;
2458 2459 uint32_t nid:5;
2459 2460 uint32_t rsvd2:5;
2460 2461 uint32_t defaultPresent:1;
2461 2462 uint32_t addAssociations:1;
2462 2463 uint32_t reportAssociations:1;
2463 2464 #endif
2464 2465 #ifdef EMLXS_LITTLE_ENDIAN
2465 2466 uint32_t reportAssociations:1;
2466 2467 uint32_t addAssociations:1;
2467 2468 uint32_t defaultPresent:1;
2468 2469 uint32_t rsvd2:5;
2469 2470 uint32_t nid:5;
2470 2471 uint32_t rsvd1:11;
2471 2472 uint32_t defaultMessageNumber:8;
2472 2473 #endif
2473 2474 uint32_t attConditions1;
2474 2475 uint32_t attConditions2;
2475 2476 uint8_t attentionId[16];
2476 2477 uint8_t messageNumberByHA[64];
2477 2478 uint8_t messageNumberByID[16];
2478 2479 uint32_t autoClearByHA1;
2479 2480 uint32_t autoClearByHA2;
2480 2481 uint32_t autoClearByID;
2481 2482 uint32_t resv3;
2482 2483 } CONFIG_MSIX_VAR;
2483 2484
2484 2485
2485 2486 /* Union of all Mailbox Command types */
2486 2487
2487 2488 typedef union
2488 2489 {
2489 2490 uint32_t varWords[31];
2490 2491 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2491 2492 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2492 2493 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2493 2494 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2494 2495 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2495 2496 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2496 2497 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2497 2498 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2498 2499 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2499 2500 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2500 2501 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2501 2502 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2502 2503 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2503 2504 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2504 2505 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2505 2506 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2506 2507 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2507 2508 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2508 2509 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2509 2510 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2510 2511 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2511 2512 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2512 2513 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2513 2514 UPDATE_CFG_VAR varUpdateCfg; /* cmd = 0x1b Warm Start */
2514 2515 /* UPDATE_CFG cmd */
2515 2516 DEL_LD_ENTRY_VAR varDelLdEntry; /* cmd = 0x1d (DEL_LD_ENTRY) */
2516 2517 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2517 2518 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) */
2518 2519 CONFIG_MSI_VAR varCfgMSI; /* cmd = 0x90 (CONFIG_MSI) */
2519 2520 CONFIG_MSIX_VAR varCfgMSIX; /* cmd = 0x30 (CONFIG_MSIX) */
2520 2521 CONFIG_HBQ_VAR varCfgHbq; /* cmd = 0x7C (CONFIG_HBQ) */
2521 2522 LOAD_AREA_VAR varLdArea; /* cmd = 0x81 (LOAD_AREA) */
2522 2523 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2523 2524 LOAD_EXP_ROM_VAR varLdExpRom; /* cmd = 0x9C (LOAD_XP_ROM) */
2524 2525 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2525 2526 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
2526 2527 READ_EVT_LOG_VAR varRdEvtLog; /* cmd = 0x38 (READ_EVT_LOG) */
2527 2528 LOG_STATUS_VAR varLogStat; /* cmd = 0x37 */
2528 2529
2529 2530 } MAILVARIANTS;
2530 2531
2531 2532 #define MAILBOX_CMD_BSIZE 128
2532 2533 #define MAILBOX_CMD_WSIZE 32
2533 2534
2534 2535 /*
2535 2536 * SLI-2 specific structures
2536 2537 */
2537 2538
2538 2539 typedef struct _SLI1_DESC
2539 2540 {
2540 2541 emlxs_rings_t mbxCring[4];
2541 2542 uint32_t mbxUnused[24];
2542 2543 } SLI1_DESC; /* 128 bytes */
2543 2544
2544 2545 typedef struct
2545 2546 {
2546 2547 uint32_t cmdPutInx;
2547 2548 uint32_t rspGetInx;
2548 2549 } HGP;
2549 2550
2550 2551 typedef struct
2551 2552 {
2552 2553 uint32_t cmdGetInx;
2553 2554 uint32_t rspPutInx;
2554 2555 } PGP;
2555 2556
2556 2557 typedef struct _SLI2_DESC
2557 2558 {
2558 2559 HGP host[4];
2559 2560 PGP port[4];
2560 2561 uint32_t HBQ_PortGetIdx[16];
2561 2562 } SLI2_DESC; /* 128 bytes */
2562 2563
2563 2564 typedef union
2564 2565 {
2565 2566 SLI1_DESC s1; /* 32 words, 128 bytes */
2566 2567 SLI2_DESC s2; /* 32 words, 128 bytes */
2567 2568 } SLI_VAR;
2568 2569
2569 2570 typedef volatile struct
2570 2571 {
2571 2572 #ifdef EMLXS_BIG_ENDIAN
2572 2573 uint16_t mbxStatus;
2573 2574 uint8_t mbxCommand;
2574 2575 uint8_t mbxReserved:6;
2575 2576 uint8_t mbxHc:1;
2576 2577 uint8_t mbxOwner:1; /* Low order bit first word */
2577 2578 #endif
2578 2579 #ifdef EMLXS_LITTLE_ENDIAN
2579 2580 uint8_t mbxOwner:1; /* Low order bit first word */
2580 2581 uint8_t mbxHc:1;
2581 2582 uint8_t mbxReserved:6;
2582 2583 uint8_t mbxCommand;
2583 2584 uint16_t mbxStatus;
2584 2585 #endif
2585 2586 MAILVARIANTS un; /* 124 bytes */
2586 2587 SLI_VAR us; /* 128 bytes */
2587 2588 } MAILBOX; /* 256 bytes */
2588 2589
2589 2590
2590 2591
2591 2592 /* SLI4 IOCTL Mailbox */
2592 2593 /* ALL SLI4 specific mbox commands have a standard request /response header */
2593 2594 /* Word 0 is just like SLI 3 */
2594 2595
2595 2596 typedef struct mbox_req_hdr
2596 2597 {
2597 2598 #ifdef EMLXS_BIG_ENDIAN
2598 2599 uint32_t domain:8; /* word 6 */
2599 2600 uint32_t port:8;
2600 2601 uint32_t subsystem:8;
2601 2602 uint32_t opcode:8;
2602 2603
2603 2604 uint32_t timeout; /* word 7 */
2604 2605
2605 2606 uint32_t req_length; /* word 8 */
2606 2607
2607 2608 uint32_t reserved1:24; /* word 9 */
2608 2609 uint32_t version:8; /* word 9 */
2609 2610 #endif
2610 2611 #ifdef EMLXS_LITTLE_ENDIAN
2611 2612 uint32_t opcode:8;
2612 2613 uint32_t subsystem:8;
2613 2614 uint32_t port:8;
2614 2615 uint32_t domain:8; /* word 6 */
2615 2616
2616 2617 uint32_t timeout; /* word 7 */
2617 2618
2618 2619 uint32_t req_length; /* word 8 */
2619 2620
2620 2621 uint32_t version:8; /* word 9 */
2621 2622 uint32_t reserved1:24; /* word 9 */
2622 2623 #endif
2623 2624
2624 2625 } mbox_req_hdr_t;
2625 2626
2626 2627
2627 2628 typedef struct mbox_req_hdr2
2628 2629 {
2629 2630 #ifdef EMLXS_BIG_ENDIAN
2630 2631 uint32_t vf_number:16; /* word 6 */
2631 2632 uint32_t subsystem:8;
2632 2633 uint32_t opcode:8;
2633 2634
2634 2635 uint32_t timeout; /* word 7 */
2635 2636
2636 2637 uint32_t req_length; /* word 8 */
2637 2638
2638 2639 uint32_t vh_number:6; /* word 9 */
2639 2640 uint32_t pf_number:10;
2640 2641 uint32_t reserved1:8;
2641 2642 uint32_t version:8;
2642 2643 #endif
2643 2644 #ifdef EMLXS_LITTLE_ENDIAN
2644 2645 uint32_t opcode:8;
2645 2646 uint32_t subsystem:8;
2646 2647 uint32_t vf_number:16; /* word 6 */
2647 2648
2648 2649 uint32_t timeout; /* word 7 */
2649 2650
2650 2651 uint32_t req_length; /* word 8 */
2651 2652
2652 2653 uint32_t version:8;
2653 2654 uint32_t reserved1:8;
2654 2655 uint32_t pf_number:10;
2655 2656 uint32_t vh_number:6; /* word 9 */
2656 2657 #endif
2657 2658
2658 2659 } mbox_req_hdr2_t;
2659 2660
2660 2661 typedef struct mbox_rsp_hdr
2661 2662 {
2662 2663 #ifdef EMLXS_BIG_ENDIAN
2663 2664 uint32_t domain:8; /* word 6 */
2664 2665 uint32_t reserved1:8;
2665 2666 uint32_t subsystem:8;
2666 2667 uint32_t opcode:8;
2667 2668
2668 2669 uint32_t reserved2:16; /* word 7 */
2669 2670 uint32_t extra_status:8;
2670 2671 uint32_t status:8;
2671 2672 #endif
2672 2673 #ifdef EMLXS_LITTLE_ENDIAN
2673 2674 uint32_t opcode:8;
2674 2675 uint32_t subsystem:8;
2675 2676 uint32_t reserved1:8;
2676 2677 uint32_t domain:8; /* word 6 */
2677 2678
2678 2679 uint32_t status:8;
2679 2680 uint32_t extra_status:8;
2680 2681 uint32_t reserved2:16; /* word 7 */
2681 2682 #endif
2682 2683 uint32_t rsp_length; /* word 8 */
2683 2684 uint32_t allocated_length; /* word 9 */
2684 2685 } mbox_rsp_hdr_t;
2685 2686
2686 2687 #define MBX_RSP_STATUS_SUCCESS 0x00
2687 2688 #define MBX_RSP_STATUS_FAILED 0x01
2688 2689 #define MBX_RSP_STATUS_ILLEGAL_REQ 0x02
2689 2690 #define MBX_RSP_STATUS_ILLEGAL_FIELD 0x03
2690 2691 #define MBX_RSP_STATUS_FCF_IN_USE 0x3A
2691 2692 #define MBX_RSP_STATUS_NO_FCF 0x43
2692 2693
2693 2694 #define MGMT_ADDI_STATUS_INCOMPATIBLE 0xA2
2694 2695
2695 2696 typedef struct be_req_hdr
2696 2697 {
2697 2698 #ifdef EMLXS_BIG_ENDIAN
2698 2699 uint32_t special:8; /* word 1 */
2699 2700 uint32_t reserved2:16; /* word 1 */
2700 2701 uint32_t sge_cnt:5; /* word 1 */
2701 2702 uint32_t reserved1:2; /* word 1 */
2702 2703 uint32_t embedded:1; /* word 1 */
2703 2704 #endif
2704 2705 #ifdef EMLXS_LITTLE_ENDIAN
2705 2706 uint32_t embedded:1; /* word 1 */
2706 2707 uint32_t reserved1:2; /* word 1 */
2707 2708 uint32_t sge_cnt:5; /* word 1 */
2708 2709 uint32_t reserved2:16; /* word 1 */
2709 2710 uint32_t special:8; /* word 1 */
2710 2711 #endif
2711 2712 uint32_t payload_length; /* word 2 */
2712 2713 uint32_t tag_low; /* word 3 */
2713 2714 uint32_t tag_hi; /* word 4 */
2714 2715 uint32_t reserved3; /* word 5 */
2715 2716 union
2716 2717 {
2717 2718 mbox_req_hdr_t hdr_req;
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2718 2719 mbox_req_hdr2_t hdr_req2;
2719 2720 mbox_rsp_hdr_t hdr_rsp;
2720 2721 } un_hdr;
2721 2722 } be_req_hdr_t;
2722 2723
2723 2724 #define EMLXS_MAX_NONEMBED_SIZE (1024 * 64)
2724 2725
2725 2726 /* SLI_CONFIG Mailbox commands */
2726 2727
2727 2728 #define IOCTL_SUBSYSTEM_COMMON 0x01
2729 +#define IOCTL_SUBSYSTEM_LOWLEVEL 0x0B
2728 2730 #define IOCTL_SUBSYSTEM_FCOE 0x0C
2729 2731 #define IOCTL_SUBSYSTEM_DCBX 0x10
2730 2732
2731 2733 #define COMMON_OPCODE_READ_FLASHROM 0x06
2732 2734 #define COMMON_OPCODE_WRITE_FLASHROM 0x07
2733 2735 #define COMMON_OPCODE_CQ_CREATE 0x0C
2734 2736 #define COMMON_OPCODE_EQ_CREATE 0x0D
2735 2737 #define COMMON_OPCODE_MQ_CREATE 0x15
2736 2738 #define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20
2737 2739 #define COMMON_OPCODE_NOP 0x21
2738 2740 #define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A
2739 2741 #define COMMON_OPCODE_RESET 0x3D
2740 2742 #define COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1 0x3E
2741 2743
2742 2744 #define COMMON_OPCODE_GET_BOOT_CFG 0x42
2743 2745 #define COMMON_OPCODE_SET_BOOT_CFG 0x43
2744 2746 #define COMMON_OPCODE_MANAGE_FAT 0x44
2745 2747 #define COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1 0x47
2746 2748 #define COMMON_OPCODE_GET_PORT_NAME 0x4D
2747 2749
2748 2750 #define COMMON_OPCODE_MQ_CREATE_EXT 0x5A
2749 2751 #define COMMON_OPCODE_GET_VPD_DATA 0x5B
2750 2752 #define COMMON_OPCODE_GET_PHY_DETAILS 0x66
2751 2753 #define COMMON_OPCODE_SEND_ACTIVATION 0x73
2752 2754 #define COMMON_OPCODE_RESET_LICENSES 0x74
2753 2755 #define COMMON_OPCODE_GET_CNTL_ADDL_ATTRIB 0x79
2754 2756
2755 2757 #define COMMON_OPCODE_GET_EXTENTS_INFO 0x9A
2756 2758 #define COMMON_OPCODE_GET_EXTENTS 0x9B
2757 2759 #define COMMON_OPCODE_ALLOC_EXTENTS 0x9C
2758 2760 #define COMMON_OPCODE_DEALLOC_EXTENTS 0x9D
2759 2761
2760 2762 #define COMMON_OPCODE_GET_PROFILE_CAPS 0xA1
2761 2763 #define COMMON_OPCODE_GET_MR_PROFILE_CAPS 0xA2
2762 2764 #define COMMON_OPCODE_SET_MR_PROFILE_CAPS 0xA3
2763 2765 #define COMMON_OPCODE_GET_PROFILE_CFG 0xA4
2764 2766 #define COMMON_OPCODE_SET_PROFILE_CFG 0xA5
2765 2767 #define COMMON_OPCODE_GET_PROFILE_LIST 0xA6
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2766 2768 #define COMMON_OPCODE_GET_ACTIVE_PROFILE 0xA7
2767 2769 #define COMMON_OPCODE_SET_ACTIVE_PROFILE 0xA8
2768 2770 #define COMMON_OPCODE_SET_FACTORY_PROFILE_CFG 0xA9
2769 2771
2770 2772 #define COMMON_OPCODE_READ_OBJ 0xAB
2771 2773 #define COMMON_OPCODE_WRITE_OBJ 0xAC
2772 2774 #define COMMON_OPCODE_READ_OBJ_LIST 0xAD
2773 2775 #define COMMON_OPCODE_DELETE_OBJ 0xAE
2774 2776 #define COMMON_OPCODE_GET_SLI4_PARAMS 0xB5
2775 2777
2778 +#define LOWLEVEL_OPCODE_GPIO_RDWR 0x30
2779 +
2776 2780 #define FCOE_OPCODE_WQ_CREATE 0x01
2777 2781 #define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03
2778 2782 #define FCOE_OPCODE_RQ_CREATE 0x05
2779 2783 #define FCOE_OPCODE_READ_FCF_TABLE 0x08
2780 2784 #define FCOE_OPCODE_ADD_FCF_TABLE 0x09
2781 2785 #define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A
2782 2786 #define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B
2783 2787 #define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10
2784 2788 #define FCOE_OPCODE_SET_FCLINK_SETTINGS 0x21
2785 2789
2786 2790 #define DCBX_OPCODE_GET_DCBX_MODE 0x04
2787 2791 #define DCBX_OPCODE_SET_DCBX_MODE 0x05
2788 2792
2789 2793 typedef struct
2790 2794 {
2791 2795 struct
2792 2796 {
2793 2797 uint32_t opcode;
2794 2798 #define MGMT_FLASHROM_OPCODE_FLASH 1
2795 2799 #define MGMT_FLASHROM_OPCODE_SAVE 2
2796 2800 #define MGMT_FLASHROM_OPCODE_CLEAR 3
2797 2801 #define MGMT_FLASHROM_OPCODE_REPORT 4
2798 2802 #define MGMT_FLASHROM_OPCODE_INFO 5
2799 2803 #define MGMT_FLASHROM_OPCODE_CRC 6
2800 2804 #define MGMT_FLASHROM_OPCODE_OFFSET_FLASH 7
2801 2805 #define MGMT_FLASHROM_OPCODE_OFFSET_SAVE 8
2802 2806 #define MGMT_PHY_FLASHROM_OPCODE_FLASH 9
2803 2807 #define MGMT_PHY_FLASHROM_OPCODE_SAVE 10
2804 2808
2805 2809 uint32_t optype;
2806 2810 #define MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE 0
2807 2811 #define MGMT_FLASHROM_OPTYPE_REDBOOT 1
2808 2812 #define MGMT_FLASHROM_OPTYPE_ISCSI_BIOS 2
2809 2813 #define MGMT_FLASHROM_OPTYPE_PXE_BIOS 3
2810 2814 #define MGMT_FLASHROM_OPTYPE_CTRLS 4
2811 2815 #define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 5
2812 2816 #define MGMT_FLASHROM_OPTYPE_CFG_INI 6
2813 2817 #define MGMT_FLASHROM_OPTYPE_ROM_OFFSET 7
2814 2818 #define MGMT_FLASHROM_OPTYPE_FCOE_BIOS 8
2815 2819 #define MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP 9
2816 2820 #define MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE 10
2817 2821 #define MGMT_FLASHROM_OPTYPE_FCOE_BACKUP 11
2818 2822 #define MGMT_FLASHROM_OPTYPE_CTRLP 12
2819 2823 #define MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE 13
2820 2824 #define MGMT_FLASHROM_OPTYPE_CFG_NIC 14
2821 2825 #define MGMT_FLASHROM_OPTYPE_CFG_DCBX 15
2822 2826 #define MGMT_FLASHROM_OPTYPE_CFG_PXE_BIOS 16
2823 2827 #define MGMT_FLASHROM_OPTYPE_CFG_ALL 17
2824 2828 #define MGMT_FLASHROM_OPTYPE_PHY_FIRMWARE 0xff /* Driver defined */
2825 2829
2826 2830 uint32_t data_buffer_size; /* Align to 4KB */
2827 2831 uint32_t offset;
2828 2832 uint32_t data_buffer; /* image starts here */
2829 2833
2830 2834 } params;
2831 2835
2832 2836 } IOCTL_COMMON_FLASHROM;
2833 2837
2834 2838
2835 2839 typedef struct
2836 2840 {
2837 2841 union
2838 2842 {
2839 2843 struct
2840 2844 {
2841 2845 uint32_t rsvd;
2842 2846 } request;
2843 2847
2844 2848
2845 2849 struct
2846 2850 {
2847 2851 #ifdef EMLXS_BIG_ENDIAN
2848 2852 uint16_t interface_type;
2849 2853 uint16_t phy_type;
2850 2854 #endif
2851 2855 #ifdef EMLXS_LITTLE_ENDIAN
2852 2856 uint16_t phy_type;
2853 2857 uint16_t interface_type;
2854 2858 #endif
2855 2859
2856 2860 /* phy_type */
2857 2861 #define PHY_XAUI 0x0
2858 2862 #define PHY_AEL_2020 0x1 /* eluris/Netlogic */
2859 2863 #define PHY_LSI_BRCM1 0x2 /* Peak pre-production board */
2860 2864 #define PHY_LSI_BRCM2 0x3 /* Peak production board */
2861 2865 #define PHY_SOLARFLARE 0x4 /* Dell recommended */
2862 2866 #define PHY_AMCC_QT2025 0x5 /* AMCC PHY */
2863 2867 #define PHY_AMCC_QT2225 0x6 /* AMCC PHY */
2864 2868 #define PHY_BRCM_5931 0x7 /* Broadcom Phy used by HP LOM */
2865 2869 #define PHY_BE3_INTERNAL_10GB 0x8 /* Internal 10GbPHY in BE3 */
2866 2870 #define PHY_BE3_INTERNAL_1GB 0x9 /* Internal 1Gb PHY in BE3 */
2867 2871 #define PHY_TN_2022 0xa /* Teranetics dual port 65nm PHY */
2868 2872 #define PHY_MARVELL_88E1340 0xb /* Marvel 1G PHY */
2869 2873 #define PHY_MARVELL_88E1322 0xc /* Marvel 1G PHY */
2870 2874 #define PHY_TN_8022 0xd /* Teranetics dual port 40nm PHY */
2871 2875 #define PHY_TYPE_NOT_SUPPORTED
2872 2876
2873 2877 /* interface_type */
2874 2878 #define CX4_10GB_TYPE 0x0
2875 2879 #define XFP_10GB_TYPE 0x1
2876 2880 #define SFP_1GB_TYPE 0x2
2877 2881 #define SFP_PLUS_10GB_TYPE 0x3
2878 2882 #define KR_10GB_TYPE 0x4
2879 2883 #define KX4_10GB_TYPE 0x5
2880 2884 #define BASET_10GB_TYPE 0x6 /* 10G BaseT */
2881 2885 #define BASET_1000_TYPE 0x7 /* 1000 BaseT */
2882 2886 #define BASEX_1000_TYPE 0x8 /* 1000 BaseX */
2883 2887 #define SGMII_TYPE 0x9
2884 2888 #define INTERFACE_10GB_DISABLED 0xff /* Interface type not supported */
2885 2889
2886 2890 uint32_t misc_params;
2887 2891 uint32_t rsvd[4];
2888 2892 } response;
2889 2893
2890 2894 } params;
2891 2895
2892 2896 } IOCTL_COMMON_GET_PHY_DETAILS;
2893 2897
2894 2898
2895 2899 typedef struct
2896 2900 {
2897 2901 union
2898 2902 {
2899 2903 struct
2900 2904 {
2901 2905 uint32_t rsvd;
2902 2906 } request;
2903 2907
2904 2908
2905 2909 struct
2906 2910 {
2907 2911 #ifdef EMLXS_BIG_ENDIAN
2908 2912 uint8_t port3_name;
2909 2913 uint8_t port2_name;
2910 2914 uint8_t port1_name;
2911 2915 uint8_t port0_name;
2912 2916 #endif
2913 2917 #ifdef EMLXS_LITTLE_ENDIAN
2914 2918 uint8_t port0_name;
2915 2919 uint8_t port1_name;
2916 2920 uint8_t port2_name;
2917 2921 uint8_t port3_name;
2918 2922 #endif
2919 2923 } response;
2920 2924
2921 2925 } params;
2922 2926
2923 2927 } IOCTL_COMMON_GET_PORT_NAME;
2924 2928
2925 2929
2926 2930 typedef struct
2927 2931 {
2928 2932 union
2929 2933 {
2930 2934 struct
2931 2935 {
2932 2936 #ifdef EMLXS_BIG_ENDIAN
2933 2937 uint32_t rsvd:30;
2934 2938 uint32_t pt:2;
2935 2939 #endif
2936 2940 #ifdef EMLXS_LITTLE_ENDIAN
2937 2941 uint32_t pt:2;
2938 2942 uint32_t rsvd:30;
2939 2943 #endif
2940 2944 #define PORT_TYPE_GIGE 0
2941 2945 #define PORT_TYPE_FC 1
2942 2946 } request;
2943 2947
2944 2948
2945 2949 struct
2946 2950 {
2947 2951 #ifdef EMLXS_BIG_ENDIAN
2948 2952 uint8_t port3_name;
2949 2953 uint8_t port2_name;
2950 2954 uint8_t port1_name;
2951 2955 uint8_t port0_name;
2952 2956 #endif
2953 2957 #ifdef EMLXS_LITTLE_ENDIAN
2954 2958 uint8_t port0_name;
2955 2959 uint8_t port1_name;
2956 2960 uint8_t port2_name;
2957 2961 uint8_t port3_name;
2958 2962 #endif
2959 2963 } response;
2960 2964
2961 2965 } params;
2962 2966
2963 2967 } IOCTL_COMMON_GET_PORT_NAME_V1;
2964 2968
2965 2969
2966 2970 typedef struct
2967 2971 {
2968 2972 union
2969 2973 {
2970 2974 struct
2971 2975 {
2972 2976 uint32_t fat_operation;
2973 2977 #define RETRIEVE_FAT 0
2974 2978 #define QUERY_FAT 1
2975 2979 #define CLEAR_FAT 2
2976 2980
2977 2981 uint32_t read_log_offset;
2978 2982 uint32_t read_log_length;
2979 2983 uint32_t data_buffer_size;
2980 2984 uint32_t data_buffer;
2981 2985 } request;
2982 2986
2983 2987 struct
2984 2988 {
2985 2989 uint32_t log_size;
2986 2990 uint32_t read_log_length;
2987 2991 uint32_t rsvd0;
2988 2992 uint32_t rsvd1;
2989 2993 uint32_t data_buffer;
2990 2994 } response;
2991 2995
2992 2996 } params;
2993 2997
2994 2998 } IOCTL_COMMON_MANAGE_FAT;
2995 2999
2996 3000
2997 3001 typedef struct
2998 3002 {
2999 3003 union
3000 3004 {
3001 3005 struct
3002 3006 {
3003 3007 #ifdef EMLXS_BIG_ENDIAN
3004 3008 uint32_t EOF:1; /* word 4 */
3005 3009 uint32_t rsvd0:7;
3006 3010 uint32_t desired_write_length:24;
3007 3011 #endif
3008 3012 #ifdef EMLXS_LITTLE_ENDIAN
3009 3013 uint32_t desired_write_length:24;
3010 3014 uint32_t rsvd0:7;
3011 3015 uint32_t EOF:1; /* word 4 */
3012 3016 #endif
3013 3017 uint32_t write_offset; /* word 5 */
3014 3018 char object_name[(4 * 26)]; /* word 6 - 31 */
3015 3019 uint32_t buffer_desc_count; /* word 32 */
3016 3020
3017 3021 #ifdef EMLXS_BIG_ENDIAN
3018 3022 uint32_t rsvd:8; /* word 33 */
3019 3023 uint32_t buffer_length:24;
3020 3024 #endif
3021 3025 #ifdef EMLXS_LITTLE_ENDIAN
3022 3026 uint32_t buffer_length:24;
3023 3027 uint32_t rsvd:8; /* word 33 */
3024 3028 #endif
3025 3029 uint32_t buffer_addrlo; /* word 34 */
3026 3030 uint32_t buffer_addrhi; /* word 35 */
3027 3031 } request;
3028 3032
3029 3033 struct
3030 3034 {
3031 3035 uint32_t actual_write_length;
3032 3036
3033 3037 #ifdef EMLXS_BIG_ENDIAN
3034 3038 uint32_t rsvd:24;
3035 3039 uint32_t change_status:8;
3036 3040 #endif
3037 3041 #ifdef EMLXS_LITTLE_ENDIAN
3038 3042 uint32_t change_status:8;
3039 3043 uint32_t rsvd:24;
3040 3044 #endif
3041 3045 #define CS_NO_RESET 0
3042 3046 #define CS_REBOOT_RQD 1
3043 3047 #define CS_FW_RESET_RQD 2
3044 3048 #define CS_PROTO_RESET_RQD 3
3045 3049 } response;
3046 3050
3047 3051 } params;
3048 3052
3049 3053 } IOCTL_COMMON_WRITE_OBJECT;
3050 3054
3051 3055
3052 3056 typedef struct
3053 3057 {
3054 3058 union
3055 3059 {
3056 3060 struct
3057 3061 {
3058 3062 #ifdef EMLXS_BIG_ENDIAN
3059 3063 uint32_t descriptor_offset:16; /* word 4 */
3060 3064 uint32_t descriptor_count:16;
3061 3065 #endif
3062 3066 #ifdef EMLXS_LITTLE_ENDIAN
3063 3067 uint32_t descriptor_count:16;
3064 3068 uint32_t descriptor_offset:16; /* word 4 */
3065 3069 #endif
3066 3070 uint32_t reserved; /* word 5 */
3067 3071 char object_name[(4 * 26)]; /* word 6 - 31 */
3068 3072 uint32_t buffer_desc_count; /* word 32 */
3069 3073
3070 3074 #ifdef EMLXS_BIG_ENDIAN
3071 3075 uint32_t rsvd:8; /* word 33 */
3072 3076 uint32_t buffer_length:24;
3073 3077 #endif
3074 3078 #ifdef EMLXS_LITTLE_ENDIAN
3075 3079 uint32_t buffer_length:24;
3076 3080 uint32_t rsvd:8; /* word 33 */
3077 3081 #endif
3078 3082 uint32_t buffer_addrlo; /* word 34 */
3079 3083 uint32_t buffer_addrhi; /* word 35 */
3080 3084 } request;
3081 3085
3082 3086 struct
3083 3087 {
3084 3088 #ifdef EMLXS_BIG_ENDIAN
3085 3089 uint32_t reserved:16;
3086 3090 uint32_t actual_descriptor_count:16;
3087 3091 #endif
3088 3092 #ifdef EMLXS_LITTLE_ENDIAN
3089 3093 uint32_t actual_descriptor_count:16;
3090 3094 uint32_t reserved:16;
3091 3095 #endif
3092 3096 } response;
3093 3097
3094 3098 } params;
3095 3099
3096 3100 } IOCTL_COMMON_READ_OBJECT_LIST;
3097 3101
3098 3102
3099 3103 typedef struct
3100 3104 {
3101 3105 union
3102 3106 {
3103 3107 struct
3104 3108 {
3105 3109 #ifdef EMLXS_BIG_ENDIAN
3106 3110 uint32_t reserved:16; /* word 4 */
3107 3111 uint32_t boot_instance:8;
3108 3112 uint32_t boot_status:8;
3109 3113 #endif
3110 3114 #ifdef EMLXS_LITTLE_ENDIAN
3111 3115 uint32_t boot_status:8;
3112 3116 uint32_t boot_instance:8;
3113 3117 uint32_t reserved:16; /* word 4 */
3114 3118 #endif
3115 3119 } request;
3116 3120
3117 3121 struct
3118 3122 {
3119 3123 #ifdef EMLXS_BIG_ENDIAN
3120 3124 uint32_t reserved:16; /* word 4 */
3121 3125 uint32_t boot_instance:8;
3122 3126 uint32_t boot_status:8;
3123 3127 #endif
3124 3128 #ifdef EMLXS_LITTLE_ENDIAN
3125 3129 uint32_t boot_status:8;
3126 3130 uint32_t boot_instance:8;
3127 3131 uint32_t reserved:16; /* word 4 */
3128 3132 #endif
3129 3133 } response;
3130 3134
3131 3135 } params;
3132 3136
3133 3137 } IOCTL_COMMON_BOOT_CFG;
3134 3138
3135 3139
3136 3140 /* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
3137 3141 typedef struct _BE_FW_CFG
3138 3142 {
3139 3143 uint32_t BEConfigNumber;
3140 3144 uint32_t ASICRevision;
3141 3145 uint32_t PhysicalPort;
3142 3146 uint32_t FunctionMode;
3143 3147 uint32_t ULPMode;
3144 3148
3145 3149 } BE_FW_CFG;
3146 3150
3147 3151 typedef struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
3148 3152 {
3149 3153 union
3150 3154 {
3151 3155 struct
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3152 3156 {
3153 3157 uint32_t rsvd0;
3154 3158 } request;
3155 3159
3156 3160 BE_FW_CFG response;
3157 3161
3158 3162 } params;
3159 3163
3160 3164 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
3161 3165
3166 +/* IOCTL_LOWLEVEL_GPIO_RDWR */
3167 +typedef struct _IOCTL_LOWLEVEL_GPIO_RDWR
3168 +{
3169 + union
3170 + {
3171 + struct
3172 + {
3173 + uint32_t GpioAction;
3174 +#define LOWLEVEL_GPIO_ACT_READ 0
3175 +#define LOWLEVEL_GPIO_ACT_WRITE 1
3176 +#define LOWLEVEL_GPIO_ACT_RDSENSE 2
3177 +#define LOWLEVEL_GPIO_ACT_STSENSE 3
3162 3178
3179 + uint32_t LogicalPin;
3180 + uint32_t PinValue;
3181 +#define LOWLEVEL_GPIO_STSENSE_IN 0
3182 +#define LOWLEVEL_GPIO_STSENSE_OUT 1
3163 3183
3184 + uint32_t OutputValue;
3185 + } request;
3186 +
3187 + struct
3188 + {
3189 + uint32_t PinValue;
3190 + } response;
3191 + } params;
3192 +} IOCTL_LOWLEVEL_GPIO_RDWR;
3193 +
3164 3194 /* IOCTL_FCOE_READ_FCF_TABLE */
3165 3195 typedef struct
3166 3196 {
3167 3197 uint32_t max_recv_size;
3168 3198 uint32_t fka_adv_period;
3169 3199 uint32_t fip_priority;
3170 3200
3171 3201 #ifdef EMLXS_BIG_ENDIAN
3172 3202 uint8_t fcf_mac_address_hi[4];
3173 3203
3174 3204 uint8_t mac_address_provider;
3175 3205 uint8_t fcf_available;
3176 3206 uint8_t fcf_mac_address_low[2];
3177 3207
3178 3208 uint8_t fabric_name_identifier[8];
3179 3209
3180 3210 uint8_t fcf_sol:1;
3181 3211 uint8_t rsvd0:5;
3182 3212 uint8_t fcf_fc:1;
3183 3213 uint8_t fcf_valid:1;
3184 3214 uint8_t fc_map[3];
3185 3215
3186 3216 uint16_t fcf_state;
3187 3217 uint16_t fcf_index;
3188 3218 #endif
3189 3219 #ifdef EMLXS_LITTLE_ENDIAN
3190 3220 uint8_t fcf_mac_address_hi[4];
3191 3221
3192 3222 uint8_t fcf_mac_address_low[2];
3193 3223 uint8_t fcf_available;
3194 3224 uint8_t mac_address_provider;
3195 3225
3196 3226 uint8_t fabric_name_identifier[8];
3197 3227
3198 3228 uint8_t fc_map[3];
3199 3229 uint8_t fcf_valid:1;
3200 3230 uint8_t fcf_fc:1;
3201 3231 uint8_t rsvd0:5;
3202 3232 uint8_t fcf_sol:1;
3203 3233
3204 3234 uint16_t fcf_index;
3205 3235 uint16_t fcf_state;
3206 3236 #endif
3207 3237
3208 3238 uint8_t vlan_bitmap[512];
3209 3239 uint8_t switch_name_identifier[8];
3210 3240
3211 3241 } FCF_RECORD_t;
3212 3242
3213 3243 #define EMLXS_FCOE_MAX_RCV_SZ 0x800
3214 3244
3215 3245 /* defines for mac_address_provider */
3216 3246 #define EMLXS_MAM_BOTH 0 /* Both SPMA and FPMA */
3217 3247 #define EMLXS_MAM_FPMA 1 /* Fabric Provided MAC Address */
3218 3248 #define EMLXS_MAM_SPMA 2 /* Server Provided MAC Address */
3219 3249
3220 3250 typedef struct
3221 3251 {
3222 3252 union
3223 3253 {
3224 3254 struct
3225 3255 {
3226 3256 #ifdef EMLXS_BIG_ENDIAN
3227 3257 uint16_t rsvd0;
3228 3258 uint16_t fcf_index;
3229 3259 #endif
3230 3260 #ifdef EMLXS_LITTLE_ENDIAN
3231 3261 uint16_t fcf_index;
3232 3262 uint16_t rsvd0;
3233 3263 #endif
3234 3264
3235 3265 } request;
3236 3266
3237 3267 struct
3238 3268 {
3239 3269 uint32_t event_tag;
3240 3270 #ifdef EMLXS_BIG_ENDIAN
3241 3271 uint16_t rsvd0;
3242 3272 uint16_t next_valid_fcf_index;
3243 3273 #endif
3244 3274 #ifdef EMLXS_LITTLE_ENDIAN
3245 3275 uint16_t next_valid_fcf_index;
3246 3276 uint16_t rsvd0;
3247 3277 #endif
3248 3278 FCF_RECORD_t fcf_entry[1];
3249 3279
3250 3280 } response;
3251 3281
3252 3282 } params;
3253 3283
3254 3284 } IOCTL_FCOE_READ_FCF_TABLE;
3255 3285
3256 3286
3257 3287 /* IOCTL_FCOE_ADD_FCF_TABLE */
3258 3288 typedef struct
3259 3289 {
3260 3290 union
3261 3291 {
3262 3292 struct
3263 3293 {
3264 3294 #ifdef EMLXS_BIG_ENDIAN
3265 3295 uint16_t rsvd0;
3266 3296 uint16_t fcf_index;
3267 3297 #endif
3268 3298 #ifdef EMLXS_LITTLE_ENDIAN
3269 3299 uint16_t fcf_index;
3270 3300 uint16_t rsvd0;
3271 3301 #endif
3272 3302 FCF_RECORD_t fcf_entry;
3273 3303
3274 3304 } request;
3275 3305 } params;
3276 3306
3277 3307 } IOCTL_FCOE_ADD_FCF_TABLE;
3278 3308
3279 3309
3280 3310 /* IOCTL_FCOE_DELETE_FCF_TABLE */
3281 3311 typedef struct
3282 3312 {
3283 3313 union
3284 3314 {
3285 3315 struct
3286 3316 {
3287 3317 #ifdef EMLXS_BIG_ENDIAN
3288 3318 uint16_t fcf_indexes[1];
3289 3319 uint16_t fcf_count;
3290 3320 #endif
3291 3321 #ifdef EMLXS_LITTLE_ENDIAN
3292 3322 uint16_t fcf_count;
3293 3323 uint16_t fcf_indexes[1];
3294 3324 #endif
3295 3325
3296 3326 } request;
3297 3327 } params;
3298 3328
3299 3329 } IOCTL_FCOE_DELETE_FCF_TABLE;
3300 3330
3301 3331
3302 3332 /* IOCTL_FCOE_REDISCOVER_FCF_TABLE */
3303 3333 typedef struct
3304 3334 {
3305 3335 union
3306 3336 {
3307 3337 struct
3308 3338 {
3309 3339 #ifdef EMLXS_BIG_ENDIAN
3310 3340 uint16_t rsvd0;
3311 3341 uint16_t fcf_count;
3312 3342 #endif
3313 3343 #ifdef EMLXS_LITTLE_ENDIAN
3314 3344 uint16_t fcf_count;
3315 3345 uint16_t rsvd0;
3316 3346 #endif
3317 3347 uint32_t rsvd1;
3318 3348 uint16_t fcf_index[1];
3319 3349
3320 3350 } request;
3321 3351 } params;
3322 3352
3323 3353 } IOCTL_FCOE_REDISCOVER_FCF_TABLE;
3324 3354
3325 3355
3326 3356 #define FCOE_FCF_MAC0 0x0E
3327 3357 #define FCOE_FCF_MAC1 0xFC
3328 3358 #define FCOE_FCF_MAC2 0x00
3329 3359 #define FCOE_FCF_MAC3 0xFF
3330 3360 #define FCOE_FCF_MAC4 0xFF
3331 3361 #define FCOE_FCF_MAC5 0xFE
3332 3362
3333 3363 #define FCOE_FCF_MAP0 0x0E
3334 3364 #define FCOE_FCF_MAP1 0xFC
3335 3365 #define FCOE_FCF_MAP2 0x00
3336 3366
3337 3367 #define MGMT_STATUS_FCF_IN_USE 0x3a
3338 3368
3339 3369 /* IOCTL_COMMON_NOP */
3340 3370 typedef struct _IOCTL_COMMON_NOP
3341 3371 {
3342 3372 union
3343 3373 {
3344 3374 struct
3345 3375 {
3346 3376 uint64_t context;
3347 3377 } request;
3348 3378
3349 3379 struct
3350 3380 {
3351 3381 uint64_t context;
3352 3382 } response;
3353 3383
3354 3384 } params;
3355 3385
3356 3386 } IOCTL_COMMON_NOP;
3357 3387
3358 3388
3359 3389 /* Context for EQ create */
3360 3390 typedef struct _EQ_CONTEXT
3361 3391 {
3362 3392 #ifdef EMLXS_BIG_ENDIAN
3363 3393 uint32_t Size:1;
3364 3394 uint32_t Rsvd2:1;
3365 3395 uint32_t Valid:1;
3366 3396 uint32_t Rsvd1:29;
3367 3397
3368 3398 uint32_t Armed:1;
3369 3399 uint32_t Rsvd4:2;
3370 3400 uint32_t Count:3;
3371 3401 uint32_t Rsvd3:26;
3372 3402
3373 3403 uint32_t Rsvd6:9;
3374 3404 uint32_t DelayMult:10;
3375 3405 uint32_t Rsvd5:13;
3376 3406 #endif
3377 3407 #ifdef EMLXS_LITTLE_ENDIAN
3378 3408 uint32_t Rsvd1:29;
3379 3409 uint32_t Valid:1;
3380 3410 uint32_t Rsvd2:1;
3381 3411 uint32_t Size:1;
3382 3412
3383 3413 uint32_t Rsvd3:26;
3384 3414 uint32_t Count:3;
3385 3415 uint32_t Rsvd4:2;
3386 3416 uint32_t Armed:1;
3387 3417
3388 3418 uint32_t Rsvd5:13;
3389 3419 uint32_t DelayMult:10;
3390 3420 uint32_t Rsvd6:9;
3391 3421 #endif
3392 3422
3393 3423 uint32_t Rsvd7;
3394 3424
3395 3425 } EQ_CONTEXT;
3396 3426
3397 3427
3398 3428 /* define for Count field */
3399 3429 #define EQ_ELEMENT_COUNT_1024 2
3400 3430 #define EQ_ELEMENT_COUNT_2048 3
3401 3431 #define EQ_ELEMENT_COUNT_4096 4
3402 3432
3403 3433 /* define for Size field */
3404 3434 #define EQ_ELEMENT_SIZE_4 0
3405 3435
3406 3436 /* define for DelayMullt - used for interrupt coalescing */
3407 3437 #define EQ_DELAY_MULT 64
3408 3438
3409 3439 /* Context for CQ create */
3410 3440 typedef struct _CQ_CONTEXT
3411 3441 {
3412 3442 #ifdef EMLXS_BIG_ENDIAN
3413 3443 uint32_t Eventable:1;
3414 3444 uint32_t Rsvd3:1;
3415 3445 uint32_t Valid:1;
3416 3446 uint32_t Count:2;
3417 3447 uint32_t Rsvd2:12;
3418 3448 uint32_t NoDelay:1;
3419 3449 uint32_t CoalesceWM:2;
3420 3450 uint32_t Rsvd1:12;
3421 3451
3422 3452 uint32_t Armed:1;
3423 3453 uint32_t Rsvd5:1;
3424 3454 uint32_t EQId:8;
3425 3455 uint32_t Rsvd4:22;
3426 3456
3427 3457 uint32_t Rsvd6;
3428 3458 #endif
3429 3459 #ifdef EMLXS_LITTLE_ENDIAN
3430 3460 uint32_t Rsvd1:12;
3431 3461 uint32_t CoalesceWM:2;
3432 3462 uint32_t NoDelay:1;
3433 3463 uint32_t Rsvd2:12;
3434 3464 uint32_t Count:2;
3435 3465 uint32_t Valid:1;
3436 3466 uint32_t Rsvd3:1;
3437 3467 uint32_t Eventable:1;
3438 3468
3439 3469 uint32_t Rsvd4:22;
3440 3470 uint32_t EQId:8;
3441 3471 uint32_t Rsvd5:1;
3442 3472 uint32_t Armed:1;
3443 3473
3444 3474 uint32_t Rsvd6;
3445 3475 #endif
3446 3476
3447 3477 uint32_t Rsvd7;
3448 3478
3449 3479 } CQ_CONTEXT;
3450 3480
3451 3481 typedef struct _CQ_CONTEXT_V2
3452 3482 {
3453 3483 #ifdef EMLXS_BIG_ENDIAN
3454 3484 uint32_t Eventable:1;
3455 3485 uint32_t Rsvd3:1;
3456 3486 uint32_t Valid:1;
3457 3487 uint32_t CqeCnt:2;
3458 3488 uint32_t CqeSize:2;
3459 3489 uint32_t Rsvd2:9;
3460 3490 uint32_t AutoValid:1;
3461 3491 uint32_t NoDelay:1;
3462 3492 uint32_t CoalesceWM:2;
3463 3493 uint32_t Rsvd1:12;
3464 3494
3465 3495 uint32_t Armed:1;
3466 3496 uint32_t Rsvd4:15;
3467 3497 uint32_t EQId:16;
3468 3498
3469 3499 uint32_t Rsvd5:16;
3470 3500 uint32_t Count1:16;
3471 3501 #endif
3472 3502 #ifdef EMLXS_LITTLE_ENDIAN
3473 3503 uint32_t Rsvd1:12;
3474 3504 uint32_t CoalesceWM:2;
3475 3505 uint32_t NoDelay:1;
3476 3506 uint32_t AutoValid:1;
3477 3507 uint32_t Rsvd2:9;
3478 3508 uint32_t CqeSize:2;
3479 3509 uint32_t CqeCnt:2;
3480 3510 uint32_t Valid:1;
3481 3511 uint32_t Rsvd3:1;
3482 3512 uint32_t Eventable:1;
3483 3513
3484 3514 uint32_t EQId:16;
3485 3515 uint32_t Rsvd4:15;
3486 3516 uint32_t Armed:1;
3487 3517
3488 3518 uint32_t Count1:16;
3489 3519 uint32_t Rsvd5:16;
3490 3520 #endif
3491 3521
3492 3522 uint32_t Rsvd7;
3493 3523
3494 3524 } CQ_CONTEXT_V2;
3495 3525
3496 3526 /* CqeSize */
3497 3527 #define CQE_SIZE_16_BYTES 0
3498 3528 #define CQE_SIZE_32_BYTES 1
3499 3529
3500 3530 /* define for Count field */
3501 3531 #define CQ_ELEMENT_COUNT_256 0
3502 3532 #define CQ_ELEMENT_COUNT_512 1
3503 3533 #define CQ_ELEMENT_COUNT_1024 2
3504 3534 #define CQ_ELEMENT_COUNT_SPECIFIED 3
3505 3535
3506 3536 /* Context for MQ create */
3507 3537 typedef struct _MQ_CONTEXT
3508 3538 {
3509 3539 #ifdef EMLXS_BIG_ENDIAN
3510 3540 uint32_t CQId:10;
3511 3541 uint32_t Rsvd2:2;
3512 3542 uint32_t Size:4;
3513 3543 uint32_t Rsvd1:16;
3514 3544
3515 3545 uint32_t Valid:1;
3516 3546 uint32_t Rsvd3:31;
3517 3547
3518 3548 uint32_t Rsvd4:21;
3519 3549 uint32_t ACQId:10;
3520 3550 uint32_t ACQV:1;
3521 3551 #endif
3522 3552 #ifdef EMLXS_LITTLE_ENDIAN
3523 3553 uint32_t Rsvd1:16;
3524 3554 uint32_t Size:4;
3525 3555 uint32_t Rsvd2:2;
3526 3556 uint32_t CQId:10;
3527 3557
3528 3558 uint32_t Rsvd3:31;
3529 3559 uint32_t Valid:1;
3530 3560
3531 3561 uint32_t ACQV:1;
3532 3562 uint32_t ACQId:10;
3533 3563 uint32_t Rsvd4:21;
3534 3564 #endif
3535 3565
3536 3566 uint32_t Rsvd5;
3537 3567
3538 3568 } MQ_CONTEXT;
3539 3569
3540 3570
3541 3571 typedef struct _MQ_CONTEXT_V1
3542 3572 {
3543 3573 #ifdef EMLXS_BIG_ENDIAN
3544 3574 uint32_t Rsvd2:12;
3545 3575 uint32_t Size:4;
3546 3576 uint32_t ACQId:16;
3547 3577
3548 3578 uint32_t Valid:1;
3549 3579 uint32_t Rsvd3:31;
3550 3580
3551 3581 uint32_t Rsvd4:31;
3552 3582 uint32_t ACQV:1;
3553 3583 #endif
3554 3584 #ifdef EMLXS_LITTLE_ENDIAN
3555 3585 uint32_t ACQId:16;
3556 3586 uint32_t Size:4;
3557 3587 uint32_t Rsvd2:12;
3558 3588
3559 3589 uint32_t Rsvd3:31;
3560 3590 uint32_t Valid:1;
3561 3591
3562 3592 uint32_t ACQV:1;
3563 3593 uint32_t Rsvd4:31;
3564 3594 #endif
3565 3595
3566 3596 uint32_t Rsvd5;
3567 3597
3568 3598 } MQ_CONTEXT_V1;
3569 3599
3570 3600
3571 3601 /* define for Size field */
3572 3602 #define MQ_ELEMENT_COUNT_16 0x05
3573 3603
3574 3604 /* Context for RQ create */
3575 3605 typedef struct _RQ_CONTEXT
3576 3606 {
3577 3607 #ifdef EMLXS_BIG_ENDIAN
3578 3608 uint32_t Rsvd2:12;
3579 3609 uint32_t RqeCnt:4;
3580 3610 uint32_t Rsvd1:16;
3581 3611
3582 3612 uint32_t Rsvd3;
3583 3613
3584 3614 uint32_t CQId:16;
3585 3615 uint32_t BufferSize:16;
3586 3616 #endif
3587 3617 #ifdef EMLXS_LITTLE_ENDIAN
3588 3618 uint32_t Rsvd1:16;
3589 3619 uint32_t RqeCnt:4;
3590 3620 uint32_t Rsvd2:12;
3591 3621
3592 3622 uint32_t Rsvd3;
3593 3623
3594 3624 uint32_t BufferSize:16;
3595 3625 uint32_t CQId:16;
3596 3626 #endif
3597 3627
3598 3628 uint32_t Rsvd5;
3599 3629
3600 3630 } RQ_CONTEXT;
3601 3631
3602 3632 typedef struct _RQ_CONTEXT_V1
3603 3633 {
3604 3634 #ifdef EMLXS_BIG_ENDIAN
3605 3635 uint32_t RqeCnt:16;
3606 3636 uint32_t Rsvd1:4;
3607 3637 uint32_t RqeSize:4;
3608 3638 uint32_t PageSize:8;
3609 3639
3610 3640 uint32_t Rsvd2;
3611 3641
3612 3642 uint32_t CQId:16;
3613 3643 uint32_t Rsvd:16;
3614 3644 #endif
3615 3645 #ifdef EMLXS_LITTLE_ENDIAN
3616 3646 uint32_t PageSize:8;
3617 3647 uint32_t RqeSize:4;
3618 3648 uint32_t Rsvd1:4;
3619 3649 uint32_t RqeCnt:16;
3620 3650
3621 3651 uint32_t Rsvd2;
3622 3652
3623 3653 uint32_t Rsvd:16;
3624 3654 uint32_t CQId:16;
3625 3655 #endif
3626 3656
3627 3657 uint32_t BufferSize;
3628 3658
3629 3659 } RQ_CONTEXT_V1;
3630 3660
3631 3661 /* RqeSize */
3632 3662 #define RQE_SIZE_8_BYTES 0x02
3633 3663 #define RQE_SIZE_16_BYTES 0x03
3634 3664 #define RQE_SIZE_32_BYTES 0x04
3635 3665 #define RQE_SIZE_64_BYTES 0x05
3636 3666 #define RQE_SIZE_128_BYTES 0x06
3637 3667
3638 3668 /* RQ PageSize */
3639 3669 #define RQ_PAGE_SIZE_4K 0x01
3640 3670 #define RQ_PAGE_SIZE_8K 0x02
3641 3671 #define RQ_PAGE_SIZE_16K 0x04
3642 3672 #define RQ_PAGE_SIZE_32K 0x08
3643 3673 #define RQ_PAGE_SIZE_64K 0x10
3644 3674
3645 3675
3646 3676 /* IOCTL_COMMON_EQ_CREATE */
3647 3677 typedef struct
3648 3678 {
3649 3679 union
3650 3680 {
3651 3681 struct
3652 3682 {
3653 3683 #ifdef EMLXS_BIG_ENDIAN
3654 3684 uint16_t Rsvd1;
3655 3685 uint16_t NumPages;
3656 3686 #endif
3657 3687 #ifdef EMLXS_LITTLE_ENDIAN
3658 3688 uint16_t NumPages;
3659 3689 uint16_t Rsvd1;
3660 3690 #endif
3661 3691 EQ_CONTEXT EQContext;
3662 3692 BE_PHYS_ADDR Pages[8];
3663 3693 } request;
3664 3694
3665 3695 struct
3666 3696 {
3667 3697 #ifdef EMLXS_BIG_ENDIAN
3668 3698 uint16_t MsiIndex; /* V1 only */
3669 3699 uint16_t EQId;
3670 3700 #endif
3671 3701 #ifdef EMLXS_LITTLE_ENDIAN
3672 3702 uint16_t EQId;
3673 3703 uint16_t MsiIndex; /* V1 only */
3674 3704 #endif
3675 3705 } response;
3676 3706 } params;
3677 3707
3678 3708 } IOCTL_COMMON_EQ_CREATE;
3679 3709
3680 3710
3681 3711 typedef struct
3682 3712 {
3683 3713 #ifdef EMLXS_BIG_ENDIAN
3684 3714 uint32_t Rsvd1:24; /* Word 0 */
3685 3715 uint32_t ProtocolType:8;
3686 3716
3687 3717 uint32_t Rsvd3:3; /* Word 1 */
3688 3718 uint32_t SliHint2:5;
3689 3719 uint32_t SliHint1:8;
3690 3720 uint32_t IfType:4;
3691 3721 uint32_t SliFamily:4;
3692 3722 uint32_t Revision:4;
3693 3723 uint32_t Rsvd2:3;
3694 3724 uint32_t FT:1;
3695 3725
3696 3726 uint32_t EqRsvd3:4; /* Word 2 */
3697 3727 uint32_t EqeCntMethod:4;
3698 3728 uint32_t EqPageSize:8;
3699 3729 uint32_t EqRsvd2:4;
3700 3730 uint32_t EqeSize:4;
3701 3731 uint32_t EqRsvd1:4;
3702 3732 uint32_t EqPageCnt:4;
3703 3733
3704 3734 uint32_t EqRsvd4:16; /* Word 3 */
3705 3735 uint32_t EqeCntMask:16;
3706 3736
3707 3737 uint32_t CqRsvd3:4; /* Word 4 */
3708 3738 uint32_t CqeCntMethod:4;
3709 3739 uint32_t CqPageSize:8;
3710 3740 uint32_t CQV:2;
3711 3741 uint32_t CqRsvd2:2;
3712 3742 uint32_t CqeSize:4;
3713 3743 uint32_t CqRsvd1:4;
3714 3744 uint32_t CqPageCnt:4;
3715 3745
3716 3746 uint32_t CqRsvd4:16; /* Word 5 */
3717 3747 uint32_t CqeCntMask:16;
3718 3748
3719 3749 uint32_t MqRsvd2:4; /* Word 6 */
3720 3750 uint32_t MqeCntMethod:4;
3721 3751 uint32_t MqPageSize:8;
3722 3752 uint32_t MQV:2;
3723 3753 uint32_t MqRsvd1:10;
3724 3754 uint32_t MqPageCnt:4;
3725 3755
3726 3756 uint32_t MqRsvd3:16; /* Word 7 */
3727 3757 uint32_t MqeCntMask:16;
3728 3758
3729 3759 uint32_t WqRsvd3:4; /* Word 8 */
3730 3760 uint32_t WqeCntMethod:4;
3731 3761 uint32_t WqPageSize:8;
3732 3762 uint32_t WQV:2;
3733 3763 uint32_t WqeRsvd2:2;
3734 3764 uint32_t WqeSize:4;
3735 3765 uint32_t WqRsvd1:4;
3736 3766 uint32_t WqPageCnt:4;
3737 3767
3738 3768 uint32_t WqRsvd4:16; /* Word 9 */
3739 3769 uint32_t WqeCntMask:16;
3740 3770
3741 3771 uint32_t RqRsvd3:4; /* Word 10 */
3742 3772 uint32_t RqeCntMethod:4;
3743 3773 uint32_t RqPageSize:8;
3744 3774 uint32_t RQV:2;
3745 3775 uint32_t RqeRsvd2:2;
3746 3776 uint32_t RqeSize:4;
3747 3777 uint32_t RqRsvd1:4;
3748 3778 uint32_t RqPageCnt:4;
3749 3779
3750 3780 uint32_t RqDbWin:4; /* Word 11 */
3751 3781 uint32_t RqRsvd4:12;
3752 3782 uint32_t RqeCntMask:16;
3753 3783
3754 3784 uint32_t Loopback:4; /* Word 12 */
3755 3785 uint32_t Rsvd4:12;
3756 3786 uint32_t PHWQ:1;
3757 3787 uint32_t PHON:1;
3758 3788 uint32_t PHOFF:1;
3759 3789 uint32_t TRIR:1;
3760 3790 uint32_t TRTY:1;
3761 3791 uint32_t TCCA:1;
3762 3792 uint32_t MWQE:1;
3763 3793 uint32_t ASSI:1;
3764 3794 uint32_t TERP:1;
3765 3795 uint32_t TGT:1;
3766 3796 uint32_t AREG:1;
3767 3797 uint32_t FBRR:1;
3768 3798 uint32_t SGLR:1;
3769 3799 uint32_t HDRR:1;
3770 3800 uint32_t EXT:1;
3771 3801 uint32_t FCOE:1;
3772 3802
3773 3803 uint32_t SgeLength; /* Word 13 */
3774 3804
3775 3805 uint32_t SglRsvd2:8; /* Word 14 */
3776 3806 uint32_t SglAlign:8;
3777 3807 uint32_t SglPageSize:8;
3778 3808 uint32_t SglRsvd1:4;
3779 3809 uint32_t SglPageCnt:4;
3780 3810
3781 3811 uint32_t Rsvd5:16; /* Word 15 */
3782 3812 uint32_t MinRqSize:16;
3783 3813
3784 3814 uint32_t MaxRqSize; /* Word 16 */
3785 3815
3786 3816 uint32_t RPIMax:16;
3787 3817 uint32_t XRIMax:16; /* Word 17 */
3788 3818
3789 3819 uint32_t VFIMax:16;
3790 3820 uint32_t VPIMax:16; /* Word 18 */
3791 3821 #endif
3792 3822 #ifdef EMLXS_LITTLE_ENDIAN
3793 3823 uint32_t ProtocolType:8; /* Word 0 */
3794 3824 uint32_t Rsvd1:24;
3795 3825
3796 3826 uint32_t FT:1; /* Word 1 */
3797 3827 uint32_t Rsvd2:3;
3798 3828 uint32_t Revision:4;
3799 3829 uint32_t SliFamily:4;
3800 3830 uint32_t IfType:4;
3801 3831 uint32_t SliHint1:8;
3802 3832 uint32_t SliHint2:5;
3803 3833 uint32_t Rsvd3:3;
3804 3834
3805 3835 uint32_t EqPageCnt:4; /* Word 2 */
3806 3836 uint32_t EqRsvd1:4;
3807 3837 uint32_t EqeSize:4;
3808 3838 uint32_t EqRsvd2:4;
3809 3839 uint32_t EqPageSize:8;
3810 3840 uint32_t EqeCntMethod:4;
3811 3841 uint32_t EqRsvd3:4;
3812 3842
3813 3843 uint32_t EqeCntMask:16; /* Word 3 */
3814 3844 uint32_t EqRsvd4:16;
3815 3845
3816 3846 uint32_t CqPageCnt:4; /* Word 4 */
3817 3847 uint32_t CqRsvd1:4;
3818 3848 uint32_t CqeSize:4;
3819 3849 uint32_t CqRsvd2:2;
3820 3850 uint32_t CQV:2;
3821 3851 uint32_t CqPageSize:8;
3822 3852 uint32_t CqeCntMethod:4;
3823 3853 uint32_t CqRsvd3:4;
3824 3854
3825 3855 uint32_t CqeCntMask:16; /* Word 5 */
3826 3856 uint32_t CqRsvd4:16;
3827 3857
3828 3858 uint32_t MqPageCnt:4; /* Word 6 */
3829 3859 uint32_t MqRsvd1:10;
3830 3860 uint32_t MQV:2;
3831 3861 uint32_t MqPageSize:8;
3832 3862 uint32_t MqeCntMethod:4;
3833 3863 uint32_t MqRsvd2:4;
3834 3864
3835 3865 uint32_t MqeCntMask:16; /* Word 7 */
3836 3866 uint32_t MqRsvd3:16;
3837 3867
3838 3868 uint32_t WqPageCnt:4; /* Word 8 */
3839 3869 uint32_t WqRsvd1:4;
3840 3870 uint32_t WqeSize:4;
3841 3871 uint32_t WqeRsvd2:2;
3842 3872 uint32_t WQV:2;
3843 3873 uint32_t WqPageSize:8;
3844 3874 uint32_t WqeCntMethod:4;
3845 3875 uint32_t WqRsvd3:4;
3846 3876
3847 3877 uint32_t WqeCntMask:16; /* Word 9 */
3848 3878 uint32_t WqRsvd4:16;
3849 3879
3850 3880 uint32_t RqPageCnt:4; /* Word 10 */
3851 3881 uint32_t RqRsvd1:4;
3852 3882 uint32_t RqeSize:4;
3853 3883 uint32_t RqeRsvd2:2;
3854 3884 uint32_t RQV:2;
3855 3885 uint32_t RqPageSize:8;
3856 3886 uint32_t RqeCntMethod:4;
3857 3887 uint32_t RqRsvd3:4;
3858 3888
3859 3889 uint32_t RqeCntMask:16; /* Word 11 */
3860 3890 uint32_t RqRsvd4:12;
3861 3891 uint32_t RqDbWin:4;
3862 3892
3863 3893 uint32_t FCOE:1; /* Word 12 */
3864 3894 uint32_t EXT:1;
3865 3895 uint32_t HDRR:1;
3866 3896 uint32_t SGLR:1;
3867 3897 uint32_t FBRR:1;
3868 3898 uint32_t AREG:1;
3869 3899 uint32_t TGT:1;
3870 3900 uint32_t TERP:1;
3871 3901 uint32_t ASSI:1;
3872 3902 uint32_t MWQE:1;
3873 3903 uint32_t TCCA:1;
3874 3904 uint32_t TRTY:1;
3875 3905 uint32_t TRIR:1;
3876 3906 uint32_t PHOFF:1;
3877 3907 uint32_t PHON:1;
3878 3908 uint32_t PHWQ:1;
3879 3909 uint32_t Rsvd4:12;
3880 3910 uint32_t Loopback:4;
3881 3911
3882 3912 uint32_t SgeLength; /* Word 13 */
3883 3913
3884 3914 uint32_t SglPageCnt:4; /* Word 14 */
3885 3915 uint32_t SglRsvd1:4;
3886 3916 uint32_t SglPageSize:8;
3887 3917 uint32_t SglAlign:8;
3888 3918 uint32_t SglRsvd2:8;
3889 3919
3890 3920 uint32_t MinRqSize:16; /* Word 15 */
3891 3921 uint32_t Rsvd5:16;
3892 3922
3893 3923 uint32_t MaxRqSize; /* Word 16 */
3894 3924
3895 3925 uint32_t XRIMax:16; /* Word 17 */
3896 3926 uint32_t RPIMax:16;
3897 3927
3898 3928 uint32_t VPIMax:16; /* Word 18 */
3899 3929 uint32_t VFIMax:16;
3900 3930 #endif
3901 3931
3902 3932 uint32_t Rsvd6; /* Word 19 */
3903 3933
3904 3934 } sli_params_t;
3905 3935
3906 3936 /* SliFamily values */
3907 3937 #define SLI_FAMILY_BE2 0x0
3908 3938 #define SLI_FAMILY_BE3 0x1
3909 3939 #define SLI_FAMILY_LANCER_A 0xA
3910 3940 #define SLI_FAMILY_LANCER_B 0xB
3911 3941
3912 3942
3913 3943
3914 3944 /* IOCTL_COMMON_SLI4_PARAMS */
3915 3945 typedef struct
3916 3946 {
3917 3947 union
3918 3948 {
3919 3949 struct
3920 3950 {
3921 3951 uint32_t Rsvd1;
3922 3952 } request;
3923 3953
3924 3954 struct
3925 3955 {
3926 3956 sli_params_t param;
3927 3957 } response;
3928 3958 } params;
3929 3959
3930 3960 } IOCTL_COMMON_SLI4_PARAMS;
3931 3961
3932 3962
3933 3963 #define MAX_EXTENTS 16 /* 1 to 104 */
3934 3964
3935 3965 /* IOCTL_COMMON_EXTENTS */
3936 3966 typedef struct
3937 3967 {
3938 3968 union
3939 3969 {
3940 3970 struct
3941 3971 {
3942 3972 #ifdef EMLXS_BIG_ENDIAN
3943 3973 uint16_t RscCnt;
3944 3974 uint16_t RscType;
3945 3975 #endif
3946 3976 #ifdef EMLXS_LITTLE_ENDIAN
3947 3977 uint16_t RscType;
3948 3978 uint16_t RscCnt;
3949 3979 #endif
3950 3980 } request;
3951 3981
3952 3982 struct
3953 3983 {
3954 3984 #ifdef EMLXS_BIG_ENDIAN
3955 3985 uint16_t ExtentSize;
3956 3986 uint16_t ExtentCnt;
3957 3987 #endif
3958 3988 #ifdef EMLXS_LITTLE_ENDIAN
3959 3989 uint16_t ExtentCnt;
3960 3990 uint16_t ExtentSize;
3961 3991 #endif
3962 3992
3963 3993 uint16_t RscId[MAX_EXTENTS];
3964 3994
3965 3995 } response;
3966 3996 } params;
3967 3997
3968 3998 } IOCTL_COMMON_EXTENTS;
3969 3999
3970 4000 /* RscType */
3971 4001 #define RSC_TYPE_FCOE_VFI 0x20
3972 4002 #define RSC_TYPE_FCOE_VPI 0x21
3973 4003 #define RSC_TYPE_FCOE_RPI 0x22
3974 4004 #define RSC_TYPE_FCOE_XRI 0x23
3975 4005
3976 4006
3977 4007
3978 4008 /* IOCTL_COMMON_CQ_CREATE */
3979 4009 typedef struct
3980 4010 {
3981 4011 union
3982 4012 {
3983 4013 struct
3984 4014 {
3985 4015 #ifdef EMLXS_BIG_ENDIAN
3986 4016 uint16_t Rsvd1;
3987 4017 uint16_t NumPages;
3988 4018 #endif
3989 4019 #ifdef EMLXS_LITTLE_ENDIAN
3990 4020 uint16_t NumPages;
3991 4021 uint16_t Rsvd1;
3992 4022 #endif
3993 4023 CQ_CONTEXT CQContext;
3994 4024 BE_PHYS_ADDR Pages[4];
3995 4025 } request;
3996 4026
3997 4027 struct
3998 4028 {
3999 4029 #ifdef EMLXS_BIG_ENDIAN
4000 4030 uint16_t Rsvd1;
4001 4031 uint16_t CQId;
4002 4032 #endif
4003 4033 #ifdef EMLXS_LITTLE_ENDIAN
4004 4034 uint16_t CQId;
4005 4035 uint16_t Rsvd1;
4006 4036 #endif
4007 4037 } response;
4008 4038 } params;
4009 4039
4010 4040 } IOCTL_COMMON_CQ_CREATE;
4011 4041
4012 4042
4013 4043 /* IOCTL_COMMON_CQ_CREATE_V2 */
4014 4044 typedef struct
4015 4045 {
4016 4046 union
4017 4047 {
4018 4048 struct
4019 4049 {
4020 4050 #ifdef EMLXS_BIG_ENDIAN
4021 4051 uint8_t Rsvd1;
4022 4052 uint8_t PageSize;
4023 4053 uint16_t NumPages;
4024 4054 #endif
4025 4055 #ifdef EMLXS_LITTLE_ENDIAN
4026 4056 uint16_t NumPages;
4027 4057 uint8_t PageSize;
4028 4058 uint8_t Rsvd1;
4029 4059 #endif
4030 4060 CQ_CONTEXT_V2 CQContext;
4031 4061 BE_PHYS_ADDR Pages[8];
4032 4062 } request;
4033 4063
4034 4064 struct
4035 4065 {
4036 4066 #ifdef EMLXS_BIG_ENDIAN
4037 4067 uint16_t Rsvd1;
4038 4068 uint16_t CQId;
4039 4069 #endif
4040 4070 #ifdef EMLXS_LITTLE_ENDIAN
4041 4071 uint16_t CQId;
4042 4072 uint16_t Rsvd1;
4043 4073 #endif
4044 4074 } response;
4045 4075 } params;
4046 4076
4047 4077 } IOCTL_COMMON_CQ_CREATE_V2;
4048 4078
4049 4079 #define CQ_PAGE_SIZE_4K 0x01
4050 4080 #define CQ_PAGE_SIZE_8K 0x02
4051 4081 #define CQ_PAGE_SIZE_16K 0x04
4052 4082 #define CQ_PAGE_SIZE_32K 0x08
4053 4083 #define CQ_PAGE_SIZE_64K 0x10
4054 4084
4055 4085
4056 4086
4057 4087 /* IOCTL_COMMON_MQ_CREATE */
4058 4088 typedef struct
4059 4089 {
4060 4090 union
4061 4091 {
4062 4092 struct
4063 4093 {
4064 4094 #ifdef EMLXS_BIG_ENDIAN
4065 4095 uint16_t Rsvd1;
4066 4096 uint16_t NumPages;
4067 4097 #endif
4068 4098 #ifdef EMLXS_LITTLE_ENDIAN
4069 4099 uint16_t NumPages;
4070 4100 uint16_t Rsvd1;
4071 4101 #endif
4072 4102 MQ_CONTEXT MQContext;
4073 4103 BE_PHYS_ADDR Pages[8];
4074 4104 } request;
4075 4105
4076 4106 struct
4077 4107 {
4078 4108 #ifdef EMLXS_BIG_ENDIAN
4079 4109 uint16_t Rsvd1;
4080 4110 uint16_t MQId;
4081 4111 #endif
4082 4112 #ifdef EMLXS_LITTLE_ENDIAN
4083 4113 uint16_t MQId;
4084 4114 uint16_t Rsvd1;
4085 4115 #endif
4086 4116 } response;
4087 4117 } params;
4088 4118
4089 4119 } IOCTL_COMMON_MQ_CREATE;
4090 4120
4091 4121
4092 4122 /* IOCTL_COMMON_MQ_CREATE_EXT */
4093 4123 typedef struct
4094 4124 {
4095 4125 union
4096 4126 {
4097 4127 struct
4098 4128 {
4099 4129 #ifdef EMLXS_BIG_ENDIAN
4100 4130 uint16_t rsvd0;
4101 4131 uint16_t num_pages;
4102 4132 #endif
4103 4133 #ifdef EMLXS_LITTLE_ENDIAN
4104 4134 uint16_t num_pages;
4105 4135 uint16_t rsvd0;
4106 4136 #endif
4107 4137 uint32_t async_event_bitmap;
4108 4138
4109 4139 #define ASYNC_LINK_EVENT 0x00000002
4110 4140 #define ASYNC_FCF_EVENT 0x00000004
4111 4141 #define ASYNC_DCBX_EVENT 0x00000008
4112 4142 #define ASYNC_iSCSI_EVENT 0x00000010
4113 4143 #define ASYNC_GROUP5_EVENT 0x00000020
4114 4144 #define ASYNC_FC_EVENT 0x00010000
4115 4145 #define ASYNC_PORT_EVENT 0x00020000
4116 4146 #define ASYNC_VF_EVENT 0x00040000
4117 4147 #define ASYNC_MR_EVENT 0x00080000
4118 4148
4119 4149 MQ_CONTEXT context;
4120 4150 BE_PHYS_ADDR pages[8];
4121 4151 } request;
4122 4152
4123 4153 struct
4124 4154 {
4125 4155 #ifdef EMLXS_BIG_ENDIAN
4126 4156 uint16_t rsvd0;
4127 4157 uint16_t MQId;
4128 4158 #endif
4129 4159 #ifdef EMLXS_LITTLE_ENDIAN
4130 4160 uint16_t MQId;
4131 4161 uint16_t rsvd0;
4132 4162 #endif
4133 4163 } response;
4134 4164
4135 4165 } params;
4136 4166
4137 4167 } IOCTL_COMMON_MQ_CREATE_EXT;
4138 4168
4139 4169
4140 4170 /* IOCTL_COMMON_MQ_CREATE_EXT_V1 */
4141 4171 typedef struct
4142 4172 {
4143 4173 union
4144 4174 {
4145 4175 struct
4146 4176 {
4147 4177 #ifdef EMLXS_BIG_ENDIAN
4148 4178 uint16_t CQId;
4149 4179 uint16_t num_pages;
4150 4180 #endif
4151 4181 #ifdef EMLXS_LITTLE_ENDIAN
4152 4182 uint16_t num_pages;
4153 4183 uint16_t CQId;
4154 4184 #endif
4155 4185 uint32_t async_event_bitmap;
4156 4186
4157 4187 MQ_CONTEXT_V1 context;
4158 4188 BE_PHYS_ADDR pages[8];
4159 4189 } request;
4160 4190
4161 4191 struct
4162 4192 {
4163 4193 #ifdef EMLXS_BIG_ENDIAN
4164 4194 uint16_t rsvd0;
4165 4195 uint16_t MQId;
4166 4196 #endif
4167 4197 #ifdef EMLXS_LITTLE_ENDIAN
4168 4198 uint16_t MQId;
4169 4199 uint16_t rsvd0;
4170 4200 #endif
4171 4201 } response;
4172 4202
4173 4203 } params;
4174 4204
4175 4205 } IOCTL_COMMON_MQ_CREATE_EXT_V1;
4176 4206
4177 4207
4178 4208 /* IOCTL_FCOE_RQ_CREATE */
4179 4209 typedef struct
4180 4210 {
4181 4211 union
4182 4212 {
4183 4213 struct
4184 4214 {
4185 4215 #ifdef EMLXS_BIG_ENDIAN
4186 4216 uint16_t Rsvd0;
4187 4217 uint16_t NumPages;
4188 4218 #endif
4189 4219 #ifdef EMLXS_LITTLE_ENDIAN
4190 4220 uint16_t NumPages;
4191 4221 uint16_t Rsvd0;
4192 4222 #endif
4193 4223 RQ_CONTEXT RQContext;
4194 4224 BE_PHYS_ADDR Pages[8];
4195 4225 } request;
4196 4226
4197 4227 struct
4198 4228 {
4199 4229 #ifdef EMLXS_BIG_ENDIAN
4200 4230 uint16_t Rsvd1;
4201 4231 uint16_t RQId;
4202 4232 #endif
4203 4233 #ifdef EMLXS_LITTLE_ENDIAN
4204 4234 uint16_t RQId;
4205 4235 uint16_t Rsvd1;
4206 4236 #endif
4207 4237 } response;
4208 4238
4209 4239 } params;
4210 4240
4211 4241 } IOCTL_FCOE_RQ_CREATE;
4212 4242
4213 4243
4214 4244 /* IOCTL_FCOE_RQ_CREATE_V1 */
4215 4245 typedef struct
4216 4246 {
4217 4247 union
4218 4248 {
4219 4249 struct
4220 4250 {
4221 4251 #ifdef EMLXS_BIG_ENDIAN
4222 4252 uint32_t DNB:1;
4223 4253 uint32_t DFD:1;
4224 4254 uint32_t DIM:1;
4225 4255 uint32_t Rsvd0:13;
4226 4256 uint32_t NumPages:16;
4227 4257 #endif
4228 4258 #ifdef EMLXS_LITTLE_ENDIAN
4229 4259 uint32_t NumPages:16;
4230 4260 uint32_t Rsvd0:13;
4231 4261 uint32_t DIM:1;
4232 4262 uint32_t DFD:1;
4233 4263 uint32_t DNB:1;
4234 4264 #endif
4235 4265 RQ_CONTEXT_V1 RQContext;
4236 4266 BE_PHYS_ADDR Pages[8];
4237 4267 } request;
4238 4268
4239 4269 struct
4240 4270 {
4241 4271 #ifdef EMLXS_BIG_ENDIAN
4242 4272 uint16_t Rsvd1;
4243 4273 uint16_t RQId;
4244 4274 #endif
4245 4275 #ifdef EMLXS_LITTLE_ENDIAN
4246 4276 uint16_t RQId;
4247 4277 uint16_t Rsvd1;
4248 4278 #endif
4249 4279 } response;
4250 4280
4251 4281 } params;
4252 4282
4253 4283 } IOCTL_FCOE_RQ_CREATE_V1;
4254 4284
4255 4285
4256 4286 /* IOCTL_FCOE_WQ_CREATE */
4257 4287 typedef struct
4258 4288 {
4259 4289 union
4260 4290 {
4261 4291 struct
4262 4292 {
4263 4293 #ifdef EMLXS_BIG_ENDIAN
4264 4294 uint16_t CQId;
4265 4295 uint16_t NumPages;
4266 4296 #endif
4267 4297 #ifdef EMLXS_LITTLE_ENDIAN
4268 4298 uint16_t NumPages;
4269 4299 uint16_t CQId;
4270 4300 #endif
4271 4301 BE_PHYS_ADDR Pages[4];
4272 4302 } request;
4273 4303
4274 4304 struct
4275 4305 {
4276 4306 #ifdef EMLXS_BIG_ENDIAN
4277 4307 uint16_t Rsvd0;
4278 4308 uint16_t WQId;
4279 4309 #endif
4280 4310 #ifdef EMLXS_LITTLE_ENDIAN
4281 4311 uint16_t WQId;
4282 4312 uint16_t Rsvd0;
4283 4313 #endif
4284 4314 } response;
4285 4315
4286 4316 } params;
4287 4317
4288 4318 } IOCTL_FCOE_WQ_CREATE;
4289 4319
4290 4320
4291 4321 /* IOCTL_FCOE_WQ_CREATE_V1 */
4292 4322 typedef struct
4293 4323 {
4294 4324 union
4295 4325 {
4296 4326 struct
4297 4327 {
4298 4328 #ifdef EMLXS_BIG_ENDIAN
4299 4329 uint16_t CQId;
4300 4330 uint16_t NumPages;
4301 4331
4302 4332 uint32_t WqeCnt:16;
4303 4333 uint32_t Rsvd1:4;
4304 4334 uint32_t WqeSize:4;
4305 4335 uint32_t PageSize:8;
4306 4336 #endif
4307 4337 #ifdef EMLXS_LITTLE_ENDIAN
4308 4338 uint16_t NumPages;
4309 4339 uint16_t CQId;
4310 4340
4311 4341 uint32_t PageSize:8;
4312 4342 uint32_t WqeSize:4;
4313 4343 uint32_t Rsvd1:4;
4314 4344 uint32_t WqeCnt:16;
4315 4345 #endif
4316 4346 uint32_t Rsvd:2;
4317 4347 BE_PHYS_ADDR Pages[4];
4318 4348 } request;
4319 4349
4320 4350 struct
4321 4351 {
4322 4352 #ifdef EMLXS_BIG_ENDIAN
4323 4353 uint16_t Rsvd0;
4324 4354 uint16_t WQId;
4325 4355 #endif
4326 4356 #ifdef EMLXS_LITTLE_ENDIAN
4327 4357 uint16_t WQId;
4328 4358 uint16_t Rsvd0;
4329 4359 #endif
4330 4360 } response;
4331 4361
4332 4362 } params;
4333 4363
4334 4364 } IOCTL_FCOE_WQ_CREATE_V1;
4335 4365
4336 4366 /* WqeSize */
4337 4367 #define WQE_SIZE_64_BYTES 0x05
4338 4368 #define WQE_SIZE_128_BYTES 0x06
4339 4369
4340 4370 /* PageSize */
4341 4371 #define WQ_PAGE_SIZE_4K 0x01
4342 4372 #define WQ_PAGE_SIZE_8K 0x02
4343 4373 #define WQ_PAGE_SIZE_16K 0x04
4344 4374 #define WQ_PAGE_SIZE_32K 0x08
4345 4375 #define WQ_PAGE_SIZE_64K 0x10
4346 4376
4347 4377
4348 4378
4349 4379 /* IOCTL_FCOE_CFG_POST_SGL_PAGES */
4350 4380 typedef struct _FCOE_SGL_PAGES
4351 4381 {
4352 4382 BE_PHYS_ADDR sgl_page0; /* 1st page per XRI */
4353 4383 BE_PHYS_ADDR sgl_page1; /* 2nd page per XRI */
4354 4384
4355 4385 } FCOE_SGL_PAGES;
4356 4386
4357 4387 typedef struct
4358 4388 {
4359 4389 union
4360 4390 {
4361 4391 struct
4362 4392 {
4363 4393 #ifdef EMLXS_BIG_ENDIAN
4364 4394 uint16_t xri_count;
4365 4395 uint16_t xri_start;
4366 4396 #endif
4367 4397 #ifdef EMLXS_LITTLE_ENDIAN
4368 4398 uint16_t xri_start;
4369 4399 uint16_t xri_count;
4370 4400 #endif
4371 4401 FCOE_SGL_PAGES pages[1];
4372 4402 } request;
4373 4403
4374 4404 struct
4375 4405 {
4376 4406 uint32_t rsvd0;
4377 4407 } response;
4378 4408
4379 4409 } params;
4380 4410
4381 4411 uint32_t rsvd0[2];
4382 4412
4383 4413 } IOCTL_FCOE_CFG_POST_SGL_PAGES;
4384 4414
4385 4415
4386 4416 /* IOCTL_FCOE_POST_HDR_TEMPLATES */
4387 4417 typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
4388 4418 {
4389 4419 union
4390 4420 {
4391 4421 struct
4392 4422 {
4393 4423 #ifdef EMLXS_BIG_ENDIAN
4394 4424 uint16_t num_pages;
4395 4425 uint16_t rpi_offset;
4396 4426 #endif
4397 4427 #ifdef EMLXS_LITTLE_ENDIAN
4398 4428 uint16_t rpi_offset;
4399 4429 uint16_t num_pages;
4400 4430 #endif
4401 4431 BE_PHYS_ADDR pages[32];
4402 4432
4403 4433 }request;
4404 4434
4405 4435 }params;
4406 4436
4407 4437 } IOCTL_FCOE_POST_HDR_TEMPLATES;
4408 4438
4409 4439
4410 4440
4411 4441 #define EMLXS_IOCTL_DCBX_MODE_CEE 0 /* Mapped to FIP mode */
4412 4442 #define EMLXS_IOCTL_DCBX_MODE_CIN 1 /* Mapped to nonFIP mode */
4413 4443
4414 4444 /* IOCTL_DCBX_GET_DCBX_MODE */
4415 4445 typedef struct _IOCTL_DCBX_GET_DCBX_MODE
4416 4446 {
4417 4447 union
4418 4448 {
4419 4449 struct
4420 4450 {
4421 4451 #ifdef EMLXS_BIG_ENDIAN
4422 4452 uint8_t rsvd0[3];
4423 4453 uint8_t port_num;
4424 4454 #endif
4425 4455 #ifdef EMLXS_LITTLE_ENDIAN
4426 4456 uint8_t port_num;
4427 4457 uint8_t rsvd0[3];
4428 4458 #endif
4429 4459 } request;
4430 4460
4431 4461 struct
4432 4462 {
4433 4463 #ifdef EMLXS_BIG_ENDIAN
4434 4464 uint8_t rsvd1[3];
4435 4465 uint8_t dcbx_mode;
4436 4466 #endif
4437 4467 #ifdef EMLXS_LITTLE_ENDIAN
4438 4468 uint8_t dcbx_mode;
4439 4469 uint8_t rsvd1[3];
4440 4470 #endif
4441 4471 } response;
4442 4472
4443 4473 } params;
4444 4474
4445 4475 } IOCTL_DCBX_GET_DCBX_MODE;
4446 4476
4447 4477
4448 4478 /* IOCTL_DCBX_SET_DCBX_MODE */
4449 4479 typedef struct _IOCTL_DCBX_SET_DCBX_MODE
4450 4480 {
4451 4481 union
4452 4482 {
4453 4483 struct
4454 4484 {
4455 4485 #ifdef EMLXS_BIG_ENDIAN
4456 4486 uint8_t rsvd0[2];
4457 4487 uint8_t dcbx_mode;
4458 4488 uint8_t port_num;
4459 4489 #endif
4460 4490 #ifdef EMLXS_LITTLE_ENDIAN
4461 4491 uint8_t port_num;
4462 4492 uint8_t dcbx_mode;
4463 4493 uint8_t rsvd0[2];
4464 4494 #endif
4465 4495 } request;
4466 4496
4467 4497 struct
4468 4498 {
4469 4499 uint32_t rsvd1;
4470 4500 } response;
4471 4501
4472 4502 } params;
4473 4503
4474 4504 } IOCTL_DCBX_SET_DCBX_MODE;
4475 4505
4476 4506
4477 4507 /* IOCTL_COMMON_GET_CNTL_ATTRIB */
4478 4508 typedef struct
4479 4509 {
4480 4510 char flashrom_version_string[32];
4481 4511 char manufacturer_name[32];
4482 4512 char rsvd0[28];
4483 4513 uint32_t default_extended_timeout;
4484 4514 char controller_model_number[32];
4485 4515 char controller_description[64];
4486 4516 char controller_serial_number[32];
4487 4517 char ip_version_string[32];
4488 4518 char firmware_version_string[32];
4489 4519 char bios_version_string[32];
4490 4520 char redboot_version_string[32];
4491 4521 char driver_version_string[32];
4492 4522 char fw_on_flash_version_string[32];
4493 4523 uint32_t functionalities_supported;
4494 4524 uint16_t max_cdblength;
4495 4525 uint8_t asic_revision;
4496 4526 uint8_t generational_guid[16];
4497 4527 uint8_t hba_port_count;
4498 4528 uint16_t default_link_down_timeout;
4499 4529 uint8_t iscsi_ver_min_max;
4500 4530 uint8_t multifunction_device;
4501 4531 uint8_t cache_valid;
4502 4532 uint8_t hba_status;
4503 4533 uint8_t max_domains_supported;
4504 4534 uint8_t phy_port;
4505 4535 uint32_t firmware_post_status;
4506 4536 uint32_t hba_mtu[2];
4507 4537
4508 4538 } MGMT_HBA_ATTRIB;
4509 4539
4510 4540 typedef struct
4511 4541 {
4512 4542 MGMT_HBA_ATTRIB hba_attribs;
4513 4543 uint16_t pci_vendor_id;
4514 4544 uint16_t pci_device_id;
4515 4545 uint16_t pci_sub_vendor_id;
4516 4546 uint16_t pci_sub_system_id;
4517 4547 uint8_t pci_bus_number;
4518 4548 uint8_t pci_device_number;
4519 4549 uint8_t pci_function_number;
4520 4550 uint8_t interface_type;
4521 4551 uint64_t unique_identifier;
4522 4552
4523 4553 } MGMT_CONTROLLER_ATTRIB;
4524 4554
4525 4555 typedef struct
4526 4556 {
4527 4557 union
4528 4558 {
4529 4559 struct
4530 4560 {
4531 4561 uint32_t rsvd0;
4532 4562 } request;
4533 4563
4534 4564 struct
4535 4565 {
4536 4566 MGMT_CONTROLLER_ATTRIB cntl_attributes_info;
4537 4567 } response;
4538 4568
4539 4569 } params;
4540 4570
4541 4571 } IOCTL_COMMON_GET_CNTL_ATTRIB;
4542 4572
4543 4573
4544 4574 typedef union
4545 4575 {
4546 4576 IOCTL_COMMON_NOP NOPVar;
4547 4577 IOCTL_FCOE_WQ_CREATE WQCreateVar;
4548 4578 IOCTL_FCOE_WQ_CREATE_V1 WQCreateVar1;
4549 4579 IOCTL_FCOE_RQ_CREATE RQCreateVar;
4550 4580 IOCTL_FCOE_RQ_CREATE_V1 RQCreateVar1;
4551 4581 IOCTL_COMMON_EQ_CREATE EQCreateVar;
4552 4582 IOCTL_COMMON_CQ_CREATE CQCreateVar;
4553 4583 IOCTL_COMMON_CQ_CREATE_V2 CQCreateVar2;
4554 4584 IOCTL_COMMON_MQ_CREATE MQCreateVar;
4555 4585 IOCTL_COMMON_MQ_CREATE_EXT MQCreateExtVar;
4556 4586 IOCTL_COMMON_MQ_CREATE_EXT_V1 MQCreateExtVar1;
4557 4587 IOCTL_FCOE_CFG_POST_SGL_PAGES PostSGLVar;
4558 4588 IOCTL_COMMON_GET_CNTL_ATTRIB GetCntlAttributesVar;
4559 4589 IOCTL_FCOE_READ_FCF_TABLE ReadFCFTableVar;
4560 4590 IOCTL_FCOE_ADD_FCF_TABLE AddFCFTableVar;
4561 4591 IOCTL_FCOE_REDISCOVER_FCF_TABLE RediscoverFCFTableVar;
4562 4592 IOCTL_COMMON_FLASHROM FlashRomVar;
4563 4593 IOCTL_COMMON_MANAGE_FAT FATVar;
4564 4594 IOCTL_DCBX_GET_DCBX_MODE GetDCBX;
4565 4595 IOCTL_DCBX_SET_DCBX_MODE SetDCBX;
4566 4596 IOCTL_COMMON_SLI4_PARAMS Sli4ParamVar;
4567 4597 IOCTL_COMMON_EXTENTS ExtentsVar;
4568 4598 IOCTL_COMMON_GET_PHY_DETAILS PHYDetailsVar;
4569 4599 IOCTL_COMMON_GET_PORT_NAME PortNameVar;
4570 4600 IOCTL_COMMON_GET_PORT_NAME_V1 PortNameVar1;
4571 4601 IOCTL_COMMON_WRITE_OBJECT WriteObjVar;
4572 4602 IOCTL_COMMON_BOOT_CFG BootCfgVar;
4573 4603
4574 4604 } IOCTL_VARIANTS;
4575 4605
4576 4606 /* Structure for MB Command SLI_CONFIG(0x9b) */
4577 4607 /* Good for SLI4 only */
4578 4608
4579 4609 typedef struct
4580 4610 {
4581 4611 be_req_hdr_t be;
4582 4612 BE_PHYS_ADDR payload;
4583 4613 } SLI_CONFIG_VAR;
4584 4614
4585 4615 #define IOCTL_HEADER_SZ (4 * sizeof (uint32_t))
4586 4616
4587 4617
4588 4618 typedef union
4589 4619 {
4590 4620 uint32_t varWords[63];
4591 4621 READ_NV_VAR varRDnvp; /* cmd = x02 (READ_NVPARMS) */
4592 4622 INIT_LINK_VAR varInitLnk; /* cmd = x05 (INIT_LINK) */
4593 4623 CONFIG_LINK varCfgLnk; /* cmd = x07 (CONFIG_LINK) */
4594 4624 READ_REV4_VAR varRdRev4; /* cmd = x11 (READ_REV) */
4595 4625 READ_LNK_VAR varRdLnk; /* cmd = x12 (READ_LNK_STAT) */
4596 4626 DUMP4_VAR varDmp4; /* cmd = x17 (DUMP) */
4597 4627 UPDATE_CFG_VAR varUpdateCfg; /* cmd = x1b (update Cfg) */
4598 4628 BIU_DIAG_VAR varBIUdiag; /* cmd = x84 (RUN_BIU_DIAG64) */
4599 4629 READ_SPARM_VAR varRdSparm; /* cmd = x8D (READ_SPARM64) */
4600 4630 REG_FCFI_VAR varRegFCFI; /* cmd = xA0 (REG_FCFI) */
4601 4631 UNREG_FCFI_VAR varUnRegFCFI; /* cmd = xA2 (UNREG_FCFI) */
4602 4632 READ_LA_VAR varReadLA; /* cmd = x95 (READ_LA64) */
4603 4633 READ_CONFIG4_VAR varRdConfig4; /* cmd = x0B (READ_CONFIG) */
4604 4634 RESUME_RPI_VAR varResumeRPI; /* cmd = x9E (RESUME_RPI) */
4605 4635 REG_LOGIN_VAR varRegLogin; /* cmd = x93 (REG_RPI) */
4606 4636 UNREG_LOGIN_VAR varUnregLogin; /* cmd = x14 (UNREG_RPI) */
4607 4637 REG_VPI_VAR varRegVPI4; /* cmd = x96 (REG_VPI) */
4608 4638 UNREG_VPI_VAR4 varUnRegVPI4; /* cmd = x97 (UNREG_VPI) */
4609 4639 REG_VFI_VAR varRegVFI4; /* cmd = x9F (REG_VFI) */
4610 4640 UNREG_VFI_VAR varUnRegVFI4; /* cmd = xA1 (UNREG_VFI) */
4611 4641 REQUEST_FEATURES_VAR varReqFeatures; /* cmd = x9D (REQ_FEATURES) */
4612 4642 SLI_CONFIG_VAR varSLIConfig; /* cmd = x9B (SLI_CONFIG) */
4613 4643 INIT_VPI_VAR varInitVPI4; /* cmd = xA3 (INIT_VPI) */
4614 4644 INIT_VFI_VAR varInitVFI4; /* cmd = xA4 (INIT_VFI) */
4615 4645
4616 4646 } MAILVARIANTS4; /* Used for SLI-4 */
4617 4647
4618 4648 #define MAILBOX_CMD_SLI4_BSIZE 256
4619 4649 #define MAILBOX_CMD_SLI4_WSIZE 64
4620 4650
4621 4651 #define MAILBOX_CMD_MAX_BSIZE 256
4622 4652 #define MAILBOX_CMD_MAX_WSIZE 64
4623 4653
4624 4654
4625 4655 typedef volatile struct
4626 4656 {
4627 4657 #ifdef EMLXS_BIG_ENDIAN
4628 4658 uint16_t mbxStatus;
4629 4659 uint8_t mbxCommand;
4630 4660 uint8_t mbxReserved:6;
4631 4661 uint8_t mbxHc:1;
4632 4662 uint8_t mbxOwner:1; /* Low order bit first word */
4633 4663 #endif
4634 4664 #ifdef EMLXS_LITTLE_ENDIAN
4635 4665 uint8_t mbxOwner:1; /* Low order bit first word */
4636 4666 uint8_t mbxHc:1;
4637 4667 uint8_t mbxReserved:6;
4638 4668 uint8_t mbxCommand;
4639 4669 uint16_t mbxStatus;
4640 4670 #endif
4641 4671 MAILVARIANTS4 un; /* 252 bytes */
4642 4672 } MAILBOX4; /* Used for SLI-4 */
4643 4673
4644 4674 /*
4645 4675 * End Structure Definitions for Mailbox Commands
4646 4676 */
4647 4677
4648 4678
4649 4679 typedef struct emlxs_mbq
4650 4680 {
4651 4681 volatile uint32_t mbox[MAILBOX_CMD_MAX_WSIZE];
4652 4682 struct emlxs_mbq *next;
4653 4683
4654 4684 /* Defferred handling pointers */
4655 4685 void *nonembed; /* ptr to data buffer */
4656 4686 /* structure */
4657 4687 void *bp; /* ptr to data buffer */
4658 4688 /* structure */
4659 4689 void *sbp; /* ptr to emlxs_buf_t */
4660 4690 /* structure */
4661 4691 void *ubp; /* ptr to fc_unsol_buf_t */
4662 4692 /* structure */
4663 4693 void *iocbq; /* ptr to IOCBQ structure */
4664 4694 void *context; /* ptr to mbox context data */
4665 4695 void *port; /* Sending port */
4666 4696 uint32_t flag;
4667 4697
4668 4698 #define MBQ_POOL_ALLOCATED 0x00000001
4669 4699 #define MBQ_PASSTHRU 0x00000002
4670 4700 #define MBQ_EMBEDDED 0x00000004
4671 4701 #define MBQ_BOOTSTRAP 0x00000008
4672 4702 #define MBQ_COMPLETED 0x00010000 /* Used for MBX_SLEEP */
4673 4703 #define MBQ_INIT_MASK 0x0000ffff
4674 4704
4675 4705 #ifdef MBOX_EXT_SUPPORT
4676 4706 uint8_t *extbuf; /* ptr to mailbox ext buffer */
4677 4707 uint32_t extsize; /* size of mailbox ext buffer */
4678 4708 #endif /* MBOX_EXT_SUPPORT */
4679 4709 uint32_t (*mbox_cmpl)();
4680 4710 } emlxs_mbq_t;
4681 4711 typedef emlxs_mbq_t MAILBOXQ;
4682 4712
4683 4713
4684 4714 /* We currently do not support IOCBs in SLI1 mode */
4685 4715 typedef struct
4686 4716 {
4687 4717 MAILBOX mbx;
4688 4718 #ifdef MBOX_EXT_SUPPORT
4689 4719 uint8_t mbxExt[MBOX_EXTENSION_SIZE];
4690 4720 #endif /* MBOX_EXT_SUPPORT */
4691 4721 uint8_t pad[(SLI_SLIM1_SIZE -
4692 4722 (sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))];
4693 4723 } SLIM1;
4694 4724
4695 4725
4696 4726 typedef struct
4697 4727 {
4698 4728 MAILBOX mbx;
4699 4729 #ifdef MBOX_EXT_SUPPORT
4700 4730 uint8_t mbxExt[MBOX_EXTENSION_SIZE];
4701 4731 #endif /* MBOX_EXT_SUPPORT */
4702 4732 PCB pcb;
4703 4733 uint8_t IOCBs[SLI_IOCB_MAX_SIZE];
4704 4734 } SLIM2;
4705 4735
4706 4736
4707 4737 /* def for new 2MB Flash (Pegasus ...) */
4708 4738 #define MBX_LOAD_AREA 0x81
4709 4739 #define MBX_LOAD_EXP_ROM 0x9C
4710 4740
4711 4741 #define FILE_TYPE_AWC 0xE1A01001
4712 4742 #define FILE_TYPE_DWC 0xE1A02002
4713 4743 #define FILE_TYPE_BWC 0xE1A03003
4714 4744
4715 4745 #define AREA_ID_MASK 0xFFFFFF0F
4716 4746 #define AREA_ID_AWC 0x00000001
4717 4747 #define AREA_ID_DWC 0x00000002
4718 4748 #define AREA_ID_BWC 0x00000003
4719 4749
4720 4750 #define CMD_START_ERASE 1
4721 4751 #define CMD_CONTINUE_ERASE 2
4722 4752 #define CMD_DOWNLOAD 3
4723 4753 #define CMD_END_DOWNLOAD 4
4724 4754
4725 4755 #define RSP_ERASE_STARTED 1
4726 4756 #define RSP_ERASE_COMPLETE 2
4727 4757 #define RSP_DOWNLOAD_MORE 3
4728 4758 #define RSP_DOWNLOAD_DONE 4
4729 4759
4730 4760 #define EROM_CMD_FIND_IMAGE 8
4731 4761 #define EROM_CMD_CONTINUE_ERASE 9
4732 4762 #define EROM_CMD_COPY 10
4733 4763
4734 4764 #define EROM_RSP_ERASE_STARTED 8
4735 4765 #define EROM_RSP_ERASE_COMPLETE 9
4736 4766 #define EROM_RSP_COPY_MORE 10
4737 4767 #define EROM_RSP_COPY_DONE 11
4738 4768
4739 4769 #define ALLext 1
4740 4770 #define DWCext 2
4741 4771 #define BWCext 3
4742 4772
4743 4773 #define NO_ALL 0
4744 4774 #define ALL_WITHOUT_BWC 1
4745 4775 #define ALL_WITH_BWC 2
4746 4776
4747 4777 #define KERNEL_START_ADDRESS 0x000000
4748 4778 #define DOWNLOAD_START_ADDRESS 0x040000
4749 4779 #define EXP_ROM_START_ADDRESS 0x180000
4750 4780 #define SCRATCH_START_ADDRESS 0x1C0000
4751 4781 #define CONFIG_START_ADDRESS 0x1E0000
4752 4782
4753 4783
4754 4784 typedef struct SliAifHdr
4755 4785 {
4756 4786 uint32_t CompressBr;
4757 4787 uint32_t RelocBr;
4758 4788 uint32_t ZinitBr;
4759 4789 uint32_t EntryBr;
4760 4790 uint32_t Area_ID;
4761 4791 uint32_t RoSize;
4762 4792 uint32_t RwSize;
4763 4793 uint32_t DbgSize;
4764 4794 uint32_t ZinitSize;
4765 4795 uint32_t DbgType;
4766 4796 uint32_t ImageBase;
4767 4797 uint32_t Area_Size;
4768 4798 uint32_t AddressMode;
4769 4799 uint32_t DataBase;
4770 4800 uint32_t AVersion;
4771 4801 uint32_t Spare2;
4772 4802 uint32_t DebugSwi;
4773 4803 uint32_t ZinitCode[15];
4774 4804 } AIF_HDR, *PAIF_HDR;
4775 4805
4776 4806 typedef struct ImageHdr
4777 4807 {
4778 4808 uint32_t BlockSize;
4779 4809 PROG_ID Id;
4780 4810 uint32_t Flags;
4781 4811 uint32_t EntryAdr;
4782 4812 uint32_t InitAdr;
4783 4813 uint32_t ExitAdr;
4784 4814 uint32_t ImageBase;
4785 4815 uint32_t ImageSize;
4786 4816 uint32_t ZinitSize;
4787 4817 uint32_t RelocSize;
4788 4818 uint32_t HdrCks;
4789 4819 } IMAGE_HDR, *PIMAGE_HDR;
4790 4820
4791 4821
4792 4822
4793 4823 typedef struct
4794 4824 {
4795 4825 PROG_ID prog_id;
4796 4826 #ifdef EMLXS_BIG_ENDIAN
4797 4827 uint32_t pci_cfg_rsvd:27;
4798 4828 uint32_t use_hdw_def:1;
4799 4829 uint32_t pci_cfg_sel:3;
4800 4830 uint32_t pci_cfg_lookup_sel:1;
4801 4831 #endif
4802 4832 #ifdef EMLXS_LITTLE_ENDIAN
4803 4833 uint32_t pci_cfg_lookup_sel:1;
4804 4834 uint32_t pci_cfg_sel:3;
4805 4835 uint32_t use_hdw_def:1;
4806 4836 uint32_t pci_cfg_rsvd:27;
4807 4837 #endif
4808 4838 union
4809 4839 {
4810 4840 PROG_ID boot_bios_id;
4811 4841 uint32_t boot_bios_wd[2];
4812 4842 } u0;
4813 4843 PROG_ID sli1_prog_id;
4814 4844 PROG_ID sli2_prog_id;
4815 4845 PROG_ID sli3_prog_id;
4816 4846 PROG_ID sli4_prog_id;
4817 4847 union
4818 4848 {
4819 4849 PROG_ID EROM_prog_id;
4820 4850 uint32_t EROM_prog_wd[2];
4821 4851 } u1;
4822 4852 } WAKE_UP_PARMS, *PWAKE_UP_PARMS;
4823 4853
4824 4854
4825 4855 #define PROG_DESCR_STR_LEN 24
4826 4856 #define MAX_LOAD_ENTRY 32
4827 4857
4828 4858 typedef struct
4829 4859 {
4830 4860 uint32_t next;
4831 4861 uint32_t prev;
4832 4862 uint32_t start_adr;
4833 4863 uint32_t len;
4834 4864 union
4835 4865 {
4836 4866 PROG_ID id;
4837 4867 uint32_t wd[2];
4838 4868 } un;
4839 4869 uint8_t prog_descr[PROG_DESCR_STR_LEN];
4840 4870 } LOAD_ENTRY;
4841 4871
4842 4872 typedef struct
4843 4873 {
4844 4874 uint32_t head;
4845 4875 uint32_t tail;
4846 4876 uint32_t entry_cnt;
4847 4877 LOAD_ENTRY load_entry[MAX_LOAD_ENTRY];
4848 4878 } LOAD_LIST;
4849 4879
4850 4880 #ifdef __cplusplus
4851 4881 }
4852 4882 #endif
4853 4883
4854 4884 #endif /* _EMLXS_MBOX_H */
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