1555 uint32_t UlnkSpeed:8;
1556 uint32_t UnlPort:4;
1557 uint32_t Utx:2;
1558 uint32_t Urx:2;
1559 #endif
1560 #ifdef EMLXS_LITTLE_ENDIAN
1561 uint32_t Urx:2;
1562 uint32_t Utx:2;
1563 uint32_t UnlPort:4;
1564 uint32_t UlnkSpeed:8;
1565 uint32_t Ursvd2:14;
1566 uint32_t Utf:1;
1567 uint32_t Ulu:1;
1568 #endif
1569 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
1570 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
1571 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
1572 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
1573 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
1574 #define LA_16GHZ_LINK 0x80 /* lnkSpeed */
1575 } READ_LA_VAR;
1576
1577
1578 /* Structure for MB Command CLEAR_LA (22) */
1579
1580 typedef struct
1581 {
1582 uint32_t eventTag; /* Event tag */
1583 uint32_t rsvd1;
1584 } CLEAR_LA_VAR;
1585
1586 /* Structure for MB Command DUMP */
1587 /* Good for SLI2/3 only */
1588
1589 typedef struct
1590 {
1591 #ifdef EMLXS_BIG_ENDIAN
1592 uint32_t rsvd:25;
1593 uint32_t ra:1;
1594 uint32_t co:1;
2708 uint32_t reserved2:16; /* word 1 */
2709 uint32_t special:8; /* word 1 */
2710 #endif
2711 uint32_t payload_length; /* word 2 */
2712 uint32_t tag_low; /* word 3 */
2713 uint32_t tag_hi; /* word 4 */
2714 uint32_t reserved3; /* word 5 */
2715 union
2716 {
2717 mbox_req_hdr_t hdr_req;
2718 mbox_req_hdr2_t hdr_req2;
2719 mbox_rsp_hdr_t hdr_rsp;
2720 } un_hdr;
2721 } be_req_hdr_t;
2722
2723 #define EMLXS_MAX_NONEMBED_SIZE (1024 * 64)
2724
2725 /* SLI_CONFIG Mailbox commands */
2726
2727 #define IOCTL_SUBSYSTEM_COMMON 0x01
2728 #define IOCTL_SUBSYSTEM_FCOE 0x0C
2729 #define IOCTL_SUBSYSTEM_DCBX 0x10
2730
2731 #define COMMON_OPCODE_READ_FLASHROM 0x06
2732 #define COMMON_OPCODE_WRITE_FLASHROM 0x07
2733 #define COMMON_OPCODE_CQ_CREATE 0x0C
2734 #define COMMON_OPCODE_EQ_CREATE 0x0D
2735 #define COMMON_OPCODE_MQ_CREATE 0x15
2736 #define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20
2737 #define COMMON_OPCODE_NOP 0x21
2738 #define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A
2739 #define COMMON_OPCODE_RESET 0x3D
2740 #define COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1 0x3E
2741
2742 #define COMMON_OPCODE_GET_BOOT_CFG 0x42
2743 #define COMMON_OPCODE_SET_BOOT_CFG 0x43
2744 #define COMMON_OPCODE_MANAGE_FAT 0x44
2745 #define COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1 0x47
2746 #define COMMON_OPCODE_GET_PORT_NAME 0x4D
2747
2756 #define COMMON_OPCODE_GET_EXTENTS 0x9B
2757 #define COMMON_OPCODE_ALLOC_EXTENTS 0x9C
2758 #define COMMON_OPCODE_DEALLOC_EXTENTS 0x9D
2759
2760 #define COMMON_OPCODE_GET_PROFILE_CAPS 0xA1
2761 #define COMMON_OPCODE_GET_MR_PROFILE_CAPS 0xA2
2762 #define COMMON_OPCODE_SET_MR_PROFILE_CAPS 0xA3
2763 #define COMMON_OPCODE_GET_PROFILE_CFG 0xA4
2764 #define COMMON_OPCODE_SET_PROFILE_CFG 0xA5
2765 #define COMMON_OPCODE_GET_PROFILE_LIST 0xA6
2766 #define COMMON_OPCODE_GET_ACTIVE_PROFILE 0xA7
2767 #define COMMON_OPCODE_SET_ACTIVE_PROFILE 0xA8
2768 #define COMMON_OPCODE_SET_FACTORY_PROFILE_CFG 0xA9
2769
2770 #define COMMON_OPCODE_READ_OBJ 0xAB
2771 #define COMMON_OPCODE_WRITE_OBJ 0xAC
2772 #define COMMON_OPCODE_READ_OBJ_LIST 0xAD
2773 #define COMMON_OPCODE_DELETE_OBJ 0xAE
2774 #define COMMON_OPCODE_GET_SLI4_PARAMS 0xB5
2775
2776 #define FCOE_OPCODE_WQ_CREATE 0x01
2777 #define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03
2778 #define FCOE_OPCODE_RQ_CREATE 0x05
2779 #define FCOE_OPCODE_READ_FCF_TABLE 0x08
2780 #define FCOE_OPCODE_ADD_FCF_TABLE 0x09
2781 #define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A
2782 #define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B
2783 #define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10
2784 #define FCOE_OPCODE_SET_FCLINK_SETTINGS 0x21
2785
2786 #define DCBX_OPCODE_GET_DCBX_MODE 0x04
2787 #define DCBX_OPCODE_SET_DCBX_MODE 0x05
2788
2789 typedef struct
2790 {
2791 struct
2792 {
2793 uint32_t opcode;
2794 #define MGMT_FLASHROM_OPCODE_FLASH 1
2795 #define MGMT_FLASHROM_OPCODE_SAVE 2
3142 uint32_t FunctionMode;
3143 uint32_t ULPMode;
3144
3145 } BE_FW_CFG;
3146
3147 typedef struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
3148 {
3149 union
3150 {
3151 struct
3152 {
3153 uint32_t rsvd0;
3154 } request;
3155
3156 BE_FW_CFG response;
3157
3158 } params;
3159
3160 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
3161
3162
3163
3164 /* IOCTL_FCOE_READ_FCF_TABLE */
3165 typedef struct
3166 {
3167 uint32_t max_recv_size;
3168 uint32_t fka_adv_period;
3169 uint32_t fip_priority;
3170
3171 #ifdef EMLXS_BIG_ENDIAN
3172 uint8_t fcf_mac_address_hi[4];
3173
3174 uint8_t mac_address_provider;
3175 uint8_t fcf_available;
3176 uint8_t fcf_mac_address_low[2];
3177
3178 uint8_t fabric_name_identifier[8];
3179
3180 uint8_t fcf_sol:1;
3181 uint8_t rsvd0:5;
3182 uint8_t fcf_fc:1;
3183 uint8_t fcf_valid:1;
|
1555 uint32_t UlnkSpeed:8;
1556 uint32_t UnlPort:4;
1557 uint32_t Utx:2;
1558 uint32_t Urx:2;
1559 #endif
1560 #ifdef EMLXS_LITTLE_ENDIAN
1561 uint32_t Urx:2;
1562 uint32_t Utx:2;
1563 uint32_t UnlPort:4;
1564 uint32_t UlnkSpeed:8;
1565 uint32_t Ursvd2:14;
1566 uint32_t Utf:1;
1567 uint32_t Ulu:1;
1568 #endif
1569 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
1570 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
1571 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
1572 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
1573 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
1574 #define LA_16GHZ_LINK 0x80 /* lnkSpeed */
1575 #define LA_32GHZ_LINK 0x90 /* lnkSpeed */
1576 } READ_LA_VAR;
1577
1578
1579 /* Structure for MB Command CLEAR_LA (22) */
1580
1581 typedef struct
1582 {
1583 uint32_t eventTag; /* Event tag */
1584 uint32_t rsvd1;
1585 } CLEAR_LA_VAR;
1586
1587 /* Structure for MB Command DUMP */
1588 /* Good for SLI2/3 only */
1589
1590 typedef struct
1591 {
1592 #ifdef EMLXS_BIG_ENDIAN
1593 uint32_t rsvd:25;
1594 uint32_t ra:1;
1595 uint32_t co:1;
2709 uint32_t reserved2:16; /* word 1 */
2710 uint32_t special:8; /* word 1 */
2711 #endif
2712 uint32_t payload_length; /* word 2 */
2713 uint32_t tag_low; /* word 3 */
2714 uint32_t tag_hi; /* word 4 */
2715 uint32_t reserved3; /* word 5 */
2716 union
2717 {
2718 mbox_req_hdr_t hdr_req;
2719 mbox_req_hdr2_t hdr_req2;
2720 mbox_rsp_hdr_t hdr_rsp;
2721 } un_hdr;
2722 } be_req_hdr_t;
2723
2724 #define EMLXS_MAX_NONEMBED_SIZE (1024 * 64)
2725
2726 /* SLI_CONFIG Mailbox commands */
2727
2728 #define IOCTL_SUBSYSTEM_COMMON 0x01
2729 #define IOCTL_SUBSYSTEM_LOWLEVEL 0x0B
2730 #define IOCTL_SUBSYSTEM_FCOE 0x0C
2731 #define IOCTL_SUBSYSTEM_DCBX 0x10
2732
2733 #define COMMON_OPCODE_READ_FLASHROM 0x06
2734 #define COMMON_OPCODE_WRITE_FLASHROM 0x07
2735 #define COMMON_OPCODE_CQ_CREATE 0x0C
2736 #define COMMON_OPCODE_EQ_CREATE 0x0D
2737 #define COMMON_OPCODE_MQ_CREATE 0x15
2738 #define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20
2739 #define COMMON_OPCODE_NOP 0x21
2740 #define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A
2741 #define COMMON_OPCODE_RESET 0x3D
2742 #define COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1 0x3E
2743
2744 #define COMMON_OPCODE_GET_BOOT_CFG 0x42
2745 #define COMMON_OPCODE_SET_BOOT_CFG 0x43
2746 #define COMMON_OPCODE_MANAGE_FAT 0x44
2747 #define COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1 0x47
2748 #define COMMON_OPCODE_GET_PORT_NAME 0x4D
2749
2758 #define COMMON_OPCODE_GET_EXTENTS 0x9B
2759 #define COMMON_OPCODE_ALLOC_EXTENTS 0x9C
2760 #define COMMON_OPCODE_DEALLOC_EXTENTS 0x9D
2761
2762 #define COMMON_OPCODE_GET_PROFILE_CAPS 0xA1
2763 #define COMMON_OPCODE_GET_MR_PROFILE_CAPS 0xA2
2764 #define COMMON_OPCODE_SET_MR_PROFILE_CAPS 0xA3
2765 #define COMMON_OPCODE_GET_PROFILE_CFG 0xA4
2766 #define COMMON_OPCODE_SET_PROFILE_CFG 0xA5
2767 #define COMMON_OPCODE_GET_PROFILE_LIST 0xA6
2768 #define COMMON_OPCODE_GET_ACTIVE_PROFILE 0xA7
2769 #define COMMON_OPCODE_SET_ACTIVE_PROFILE 0xA8
2770 #define COMMON_OPCODE_SET_FACTORY_PROFILE_CFG 0xA9
2771
2772 #define COMMON_OPCODE_READ_OBJ 0xAB
2773 #define COMMON_OPCODE_WRITE_OBJ 0xAC
2774 #define COMMON_OPCODE_READ_OBJ_LIST 0xAD
2775 #define COMMON_OPCODE_DELETE_OBJ 0xAE
2776 #define COMMON_OPCODE_GET_SLI4_PARAMS 0xB5
2777
2778 #define LOWLEVEL_OPCODE_GPIO_RDWR 0x30
2779
2780 #define FCOE_OPCODE_WQ_CREATE 0x01
2781 #define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03
2782 #define FCOE_OPCODE_RQ_CREATE 0x05
2783 #define FCOE_OPCODE_READ_FCF_TABLE 0x08
2784 #define FCOE_OPCODE_ADD_FCF_TABLE 0x09
2785 #define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A
2786 #define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B
2787 #define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10
2788 #define FCOE_OPCODE_SET_FCLINK_SETTINGS 0x21
2789
2790 #define DCBX_OPCODE_GET_DCBX_MODE 0x04
2791 #define DCBX_OPCODE_SET_DCBX_MODE 0x05
2792
2793 typedef struct
2794 {
2795 struct
2796 {
2797 uint32_t opcode;
2798 #define MGMT_FLASHROM_OPCODE_FLASH 1
2799 #define MGMT_FLASHROM_OPCODE_SAVE 2
3146 uint32_t FunctionMode;
3147 uint32_t ULPMode;
3148
3149 } BE_FW_CFG;
3150
3151 typedef struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
3152 {
3153 union
3154 {
3155 struct
3156 {
3157 uint32_t rsvd0;
3158 } request;
3159
3160 BE_FW_CFG response;
3161
3162 } params;
3163
3164 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
3165
3166 /* IOCTL_LOWLEVEL_GPIO_RDWR */
3167 typedef struct _IOCTL_LOWLEVEL_GPIO_RDWR
3168 {
3169 union
3170 {
3171 struct
3172 {
3173 uint32_t GpioAction;
3174 #define LOWLEVEL_GPIO_ACT_READ 0
3175 #define LOWLEVEL_GPIO_ACT_WRITE 1
3176 #define LOWLEVEL_GPIO_ACT_RDSENSE 2
3177 #define LOWLEVEL_GPIO_ACT_STSENSE 3
3178
3179 uint32_t LogicalPin;
3180 uint32_t PinValue;
3181 #define LOWLEVEL_GPIO_STSENSE_IN 0
3182 #define LOWLEVEL_GPIO_STSENSE_OUT 1
3183
3184 uint32_t OutputValue;
3185 } request;
3186
3187 struct
3188 {
3189 uint32_t PinValue;
3190 } response;
3191 } params;
3192 } IOCTL_LOWLEVEL_GPIO_RDWR;
3193
3194 /* IOCTL_FCOE_READ_FCF_TABLE */
3195 typedef struct
3196 {
3197 uint32_t max_recv_size;
3198 uint32_t fka_adv_period;
3199 uint32_t fip_priority;
3200
3201 #ifdef EMLXS_BIG_ENDIAN
3202 uint8_t fcf_mac_address_hi[4];
3203
3204 uint8_t mac_address_provider;
3205 uint8_t fcf_available;
3206 uint8_t fcf_mac_address_low[2];
3207
3208 uint8_t fabric_name_identifier[8];
3209
3210 uint8_t fcf_sol:1;
3211 uint8_t rsvd0:5;
3212 uint8_t fcf_fc:1;
3213 uint8_t fcf_valid:1;
|