1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _EMLXS_MBOX_H
28 #define _EMLXS_MBOX_H
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 /* SLI 2/3 Mailbox defines */
35
36 #define MBOX_SIZE 256
37 #define MBOX_EXTENSION_OFFSET MBOX_SIZE
38
39 #ifdef MBOX_EXT_SUPPORT
40 #define MBOX_EXTENSION_SIZE 1024
41 #else
42 #define MBOX_EXTENSION_SIZE 0
43 #endif /* MBOX_EXT_SUPPORT */
44
45
46
47 /* ==== Mailbox Commands ==== */
48 #define MBX_SHUTDOWN 0x00 /* terminate testing */
49 #define MBX_LOAD_SM 0x01
50 #define MBX_READ_NV 0x02
51 #define MBX_WRITE_NV 0x03
52 #define MBX_RUN_BIU_DIAG 0x04
53 #define MBX_INIT_LINK 0x05
54 #define MBX_DOWN_LINK 0x06
55 #define MBX_CONFIG_LINK 0x07
56 #define MBX_PART_SLIM 0x08
57 #define MBX_CONFIG_RING 0x09
58 #define MBX_RESET_RING 0x0A
59 #define MBX_READ_CONFIG 0x0B
60 #define MBX_READ_RCONFIG 0x0C
61 #define MBX_READ_SPARM 0x0D
62 #define MBX_READ_STATUS 0x0E
63 #define MBX_READ_RPI 0x0F
64 #define MBX_READ_XRI 0x10
65 #define MBX_READ_REV 0x11
66 #define MBX_READ_LNK_STAT 0x12
67 #define MBX_REG_LOGIN 0x13
68 #define MBX_UNREG_LOGIN 0x14 /* SLI2/3 */
69 #define MBX_UNREG_RPI 0x14 /* SLI4 */
70 #define MBX_READ_LA 0x15
71 #define MBX_CLEAR_LA 0x16
72 #define MBX_DUMP_MEMORY 0x17
73 #define MBX_DUMP_CONTEXT 0x18
74 #define MBX_RUN_DIAGS 0x19
75 #define MBX_RESTART 0x1A
76 #define MBX_UPDATE_CFG 0x1B
77 #define MBX_DOWN_LOAD 0x1C
78 #define MBX_DEL_LD_ENTRY 0x1D
79 #define MBX_RUN_PROGRAM 0x1E
80 #define MBX_SET_MASK 0x20
81 #define MBX_SET_VARIABLE 0x21
82 #define MBX_UNREG_D_ID 0x23
83 #define MBX_KILL_BOARD 0x24
84 #define MBX_CONFIG_FARP 0x25
85 #define MBX_BEACON 0x2A
86 #define MBX_READ_VPI 0x2B
87 #define MBX_CONFIG_MSIX 0x30
88 #define MBX_HEARTBEAT 0x31
89 #define MBX_WRITE_VPARMS 0x32
90 #define MBX_ASYNC_EVENT 0x33
91
92 #define MBX_READ_EVENT_LOG_STATUS 0x37
93 #define MBX_READ_EVENT_LOG 0x38
94 #define MBX_WRITE_EVENT_LOG 0x39
95 #define MBX_NV_LOG 0x3A
96 #define MBX_PORT_CAPABILITIES 0x3B
97 #define MBX_IOV_CONTROL 0x3C
98 #define MBX_IOV_MBX 0x3D
99
100
101 #define MBX_CONFIG_HBQ 0x7C /* SLI3 */
102 #define MBX_LOAD_AREA 0x81
103 #define MBX_RUN_BIU_DIAG64 0x84
104 #define MBX_GET_DEBUG 0x86
105 #define MBX_CONFIG_PORT 0x88
106 #define MBX_READ_SPARM64 0x8D
107 #define MBX_READ_RPI64 0x8F
108 #define MBX_CONFIG_MSI 0x90
109 #define MBX_REG_LOGIN64 0x93 /* SLI2/3 */
110 #define MBX_REG_RPI 0x93 /* SLI4 */
111 #define MBX_READ_LA64 0x95 /* SLI2/3 */
112 #define MBX_READ_TOPOLOGY 0x95 /* SLI4 */
113 #define MBX_REG_VPI 0x96 /* NPIV */
114 #define MBX_UNREG_VPI 0x97 /* NPIV */
115 #define MBX_FLASH_WR_ULA 0x98
116 #define MBX_SET_DEBUG 0x99
117 #define MBX_SLI_CONFIG 0x9B
118 #define MBX_LOAD_EXP_ROM 0x9C
119 #define MBX_REQUEST_FEATURES 0x9D
120 #define MBX_RESUME_RPI 0x9E
121 #define MBX_REG_VFI 0x9F
122 #define MBX_REG_FCFI 0xA0
123 #define MBX_UNREG_VFI 0xA1
124 #define MBX_UNREG_FCFI 0xA2
125 #define MBX_INIT_VFI 0xA3
126 #define MBX_INIT_VPI 0xA4
127 #define MBX_ACCESS_VDATA 0xA5
128 #define MBX_MAX_CMDS 0xA6
129
130
131 /*
132 * Define Status
133 */
134 #define MBX_SUCCESS 0x0
135 #define MBX_FAILURE 0x1
136 #define MBXERR_NUM_IOCBS 0x2
137 #define MBXERR_IOCBS_EXCEEDED 0x3
138 #define MBXERR_BAD_RING_NUMBER 0x4
139 #define MBXERR_MASK_ENTRIES_RANGE 0x5
140 #define MBXERR_MASKS_EXCEEDED 0x6
141 #define MBXERR_BAD_PROFILE 0x7
142 #define MBXERR_BAD_DEF_CLASS 0x8
143 #define MBXERR_BAD_MAX_RESPONDER 0x9
144 #define MBXERR_BAD_MAX_ORIGINATOR 0xA
145 #define MBXERR_RPI_REGISTERED 0xB
146 #define MBXERR_RPI_FULL 0xC
147 #define MBXERR_NO_RESOURCES 0xD
148 #define MBXERR_BAD_RCV_LENGTH 0xE
149 #define MBXERR_DMA_ERROR 0xF
150 #define MBXERR_NOT_SUPPORTED 0x10
151 #define MBXERR_UNSUPPORTED_FEATURE 0x11
152 #define MBXERR_UNKNOWN_COMMAND 0x12
153 #define MBXERR_BAD_IP_BIT 0x13
154 #define MBXERR_BAD_PCB_ALIGN 0x14
155 #define MBXERR_BAD_HBQ_ID 0x15
156 #define MBXERR_BAD_HBQ_STATE 0x16
157 #define MBXERR_BAD_HBQ_MASK_NUM 0x17
158 #define MBXERR_BAD_HBQ_MASK_SUBSET 0x18
159 #define MBXERR_HBQ_CREATE_FAIL 0x19
160 #define MBXERR_HBQ_EXISTING 0x1A
161 #define MBXERR_HBQ_RSPRING_FULL 0x1B
162 #define MBXERR_HBQ_DUP_MASK 0x1C
163 #define MBXERR_HBQ_INVAL_GET_PTR 0x1D
164 #define MBXERR_BAD_HBQ_SIZE 0x1E
165 #define MBXERR_BAD_HBQ_ORDER 0x1F
166 #define MBXERR_INVALID_ID 0x20
167
168 #define MBXERR_INVALID_VFI 0x30
169
170 #define MBXERR_FLASH_WRITE_FAILED 0x100
171
172 #define MBXERR_INVALID_LINKSPEED 0x500
173
174 #define MBXERR_BAD_REDIRECT 0x900
175 #define MBXERR_RING_ALREADY_CONFIG 0x901
176
177 #define MBXERR_RING_INACTIVE 0xA00
178
179 #define MBXERR_RPI_INACTIVE 0xF00
180
181 #define MBXERR_NO_ACTIVE_XRI 0x1100
182 #define MBXERR_XRI_NOT_ACTIVE 0x1101
183
184 #define MBXERR_RPI_INUSE 0x1400
185
186 #define MBXERR_NO_LINK_ATTENTION 0x1500
187
188 #define MBXERR_INVALID_SLI_MODE 0x8800
189 #define MBXERR_INVALID_HOST_PTR 0x8801
190 #define MBXERR_CANT_CFG_SLI_MODE 0x8802
191 #define MBXERR_BAD_OVERLAY 0x8803
192 #define MBXERR_INVALID_FEAT_REQ 0x8804
193
194 #define MBXERR_CONFIG_CANT_COMPLETE 0x88FF
195
196 #define MBXERR_DID_ALREADY_REGISTERED 0x9600
197 #define MBXERR_DID_INCONSISTENT 0x9601
198 #define MBXERR_VPI_TOO_LARGE 0x9603
199
200 #define MBXERR_STILL_ASSOCIATED 0x9700
201
202 #define MBXERR_INVALID_VF_STATE 0x9F00
203 #define MBXERR_VFI_ALREADY_REGISTERED 0x9F02
204 #define MBXERR_VFI_TOO_LARGE 0x9F03
205
206 #define MBXERR_LOAD_FW_FAILED 0xFFFE
207 #define MBXERR_FIND_FW_FAILED 0xFFFF
208
209 /* Driver special codes */
210 #define MBX_DRIVER_RESERVED 0xF9 /* Set to lowest drv status */
211 #define MBX_NONEMBED_ERROR 0xF9
212 #define MBX_OVERTEMP_ERROR 0xFA
213 #define MBX_HARDWARE_ERROR 0xFB
214 #define MBX_DRVR_ERROR 0xFC
215 #define MBX_BUSY 0xFD
216 #define MBX_TIMEOUT 0xFE
217 #define MBX_NOT_FINISHED 0xFF
218
219 /*
220 * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
221 */
222 #define MBX_POLL 0x01 /* poll mailbox till command done, */
223 /* then return */
224 #define MBX_SLEEP 0x02 /* sleep till mailbox intr cmpl */
225 /* wakes thread up */
226 #define MBX_WAIT 0x03 /* wait for comand done, then return */
227 #define MBX_NOWAIT 0x04 /* issue command then return immediately */
228 #define MBX_BOOTSTRAP 0x80 /* issue a command on the bootstrap mbox */
229
230
231
232 /*
233 * Begin Structure Definitions for Mailbox Commands
234 */
235
236 typedef struct revcompat
237 {
238 #ifdef EMLXS_BIG_ENDIAN
239 uint32_t ldflag:1; /* Set in SRAM descriptor */
240 uint32_t ldcount:7; /* For use by program load */
241 uint32_t kernel:4; /* Kernel ID */
242 uint32_t kver:4; /* Kernel compatibility version */
243 uint32_t SMver:4; /* Sequence Manager version */
244 /* 0 if none */
245 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */
246 uint32_t BIUtype:4; /* PCI = 0 */
247 uint32_t BIUver:4; /* BIU version, 0 if none */
248 #endif
249 #ifdef EMLXS_LITTLE_ENDIAN
250 uint32_t BIUver:4; /* BIU version, 0 if none */
251 uint32_t BIUtype:4; /* PCI = 0 */
252 uint32_t ENDECver:4; /* ENDEC+ version, 0 if none */
253 uint32_t SMver:4; /* Sequence Manager version */
254 /* 0 if none */
255 uint32_t kver:4; /* Kernel compatibility version */
256 uint32_t kernel:4; /* Kernel ID */
257 uint32_t ldcount:7; /* For use by program load */
258 uint32_t ldflag:1; /* Set in SRAM descriptor */
259 #endif
260 } REVCOMPAT;
261
262 typedef struct id_word
263 {
264 #ifdef EMLXS_BIG_ENDIAN
265 uint8_t Type;
266 uint8_t Id;
267 uint8_t Ver;
268 uint8_t Rev;
269 #endif
270 #ifdef EMLXS_LITTLE_ENDIAN
271 uint8_t Rev;
272 uint8_t Ver;
273 uint8_t Id;
274 uint8_t Type;
275 #endif
276 union
277 {
278 REVCOMPAT cp;
279 uint32_t revcomp;
280 } un;
281 } PROG_ID;
282
283 typedef struct
284 {
285 #ifdef EMLXS_BIG_ENDIAN
286 uint8_t tval;
287 uint8_t tmask;
288 uint8_t rval;
289 uint8_t rmask;
290 #endif
291 #ifdef EMLXS_LITTLE_ENDIAN
292 uint8_t rmask;
293 uint8_t rval;
294 uint8_t tmask;
295 uint8_t tval;
296 #endif
297 } RR_REG;
298
299
300 /* Structure used for a HBQ entry */
301 typedef struct
302 {
303 ULP_BDE64 bde;
304 union UN_TAG
305 {
306 uint32_t w;
307 struct
308 {
309 #ifdef EMLXS_BIG_ENDIAN
310 uint32_t HBQ_tag:4;
311 uint32_t HBQE_tag:28;
312 #endif
313 #ifdef EMLXS_LITTLE_ENDIAN
314 uint32_t HBQE_tag:28;
315 uint32_t HBQ_tag:4;
316 #endif
317 } ext;
318 } unt;
319 } HBQE_t;
320
321 typedef struct
322 {
323 #ifdef EMLXS_BIG_ENDIAN
324 uint8_t tmatch;
325 uint8_t tmask;
326 uint8_t rctlmatch;
327 uint8_t rctlmask;
328 #endif
329 #ifdef EMLXS_LITTLE_ENDIAN
330 uint8_t rctlmask;
331 uint8_t rctlmatch;
332 uint8_t tmask;
333 uint8_t tmatch;
334 #endif
335 } HBQ_MASK;
336
337 #define EMLXS_MAX_HBQ_BUFFERS 4096
338
339 typedef struct
340 {
341 uint32_t HBQ_num_mask; /* number of mask entries in */
342 /* port array */
343 uint32_t HBQ_recvNotify; /* Rcv buffer notification */
344 uint32_t HBQ_numEntries; /* # of entries in HBQ */
345 uint32_t HBQ_headerLen; /* 0 if not profile 4 or 5 */
346 uint32_t HBQ_logEntry; /* Set to 1 if this HBQ used */
347 /* for LogEntry */
348 uint32_t HBQ_profile; /* Selection profile 0=all, */
349 /* 7=logentry */
350 uint32_t HBQ_ringMask; /* Binds HBQ to a ring e.g. */
351 /* Ring0=b0001, ring2=b0100 */
352 uint32_t HBQ_id; /* index of this hbq in ring */
353 /* of HBQs[] */
354 uint32_t HBQ_PutIdx_next; /* Index to next HBQ slot to */
355 /* use */
356 uint32_t HBQ_PutIdx; /* HBQ slot to use */
357 uint32_t HBQ_GetIdx; /* Local copy of Get index */
358 /* from Port */
359 uint16_t HBQ_PostBufCnt; /* Current number of entries */
360 /* in list */
361 MATCHMAP *HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
362 MATCHMAP HBQ_host_buf; /* HBQ host buffer for HBQEs */
363 HBQ_MASK HBQ_Masks[6];
364
365 union
366 {
367 uint32_t allprofiles[12];
368
369 struct
370 {
371 #ifdef EMLXS_BIG_ENDIAN
372 uint32_t seqlenoff:16;
373 uint32_t maxlen:16;
374 #endif
375 #ifdef EMLXS_LITTLE_ENDIAN
376 uint32_t maxlen:16;
377 uint32_t seqlenoff:16;
378 #endif
379 #ifdef EMLXS_BIG_ENDIAN
380 uint32_t rsvd1:28;
381 uint32_t seqlenbcnt:4;
382 #endif
383 #ifdef EMLXS_LITTLE_ENDIAN
384 uint32_t seqlenbcnt:4;
385 uint32_t rsvd1:28;
386 #endif
387 uint32_t rsvd[10];
388 } profile2;
389
390 struct
391 {
392 #ifdef EMLXS_BIG_ENDIAN
393 uint32_t seqlenoff:16;
394 uint32_t maxlen:16;
395 #endif
396 #ifdef EMLXS_LITTLE_ENDIAN
397 uint32_t maxlen:16;
398 uint32_t seqlenoff:16;
399 #endif
400 #ifdef EMLXS_BIG_ENDIAN
401 uint32_t cmdcodeoff:28;
402 uint32_t rsvd1:12;
403 uint32_t seqlenbcnt:4;
404 #endif
405 #ifdef EMLXS_LITTLE_ENDIAN
406 uint32_t seqlenbcnt:4;
407 uint32_t rsvd1:12;
408 uint32_t cmdcodeoff:28;
409 #endif
410 uint32_t cmdmatch[8];
411
412 uint32_t rsvd[2];
413 } profile3;
414
415 struct
416 {
417 #ifdef EMLXS_BIG_ENDIAN
418 uint32_t seqlenoff:16;
419 uint32_t maxlen:16;
420 #endif
421 #ifdef EMLXS_LITTLE_ENDIAN
422 uint32_t maxlen:16;
423 uint32_t seqlenoff:16;
424 #endif
425 #ifdef EMLXS_BIG_ENDIAN
426 uint32_t cmdcodeoff:28;
427 uint32_t rsvd1:12;
428 uint32_t seqlenbcnt:4;
429 #endif
430 #ifdef EMLXS_LITTLE_ENDIAN
431 uint32_t seqlenbcnt:4;
432 uint32_t rsvd1:12;
433 uint32_t cmdcodeoff:28;
434 #endif
435 uint32_t cmdmatch[8];
436
437 uint32_t rsvd[2];
438 } profile5;
439 } profiles;
440 } HBQ_INIT_t;
441
442
443
444 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
445
446
447 typedef struct
448 {
449 #ifdef EMLXS_BIG_ENDIAN
450 uint32_t rsvd2:24;
451 uint32_t keep:1;
452 uint32_t acknowledgment:1;
453 uint32_t version:1;
454 uint32_t erase_or_prog:1;
455 uint32_t update_flash:1;
456 uint32_t update_ram:1;
457 uint32_t method:1;
458 uint32_t load_cmplt:1;
459 #endif
460 #ifdef EMLXS_LITTLE_ENDIAN
461 uint32_t load_cmplt:1;
462 uint32_t method:1;
463 uint32_t update_ram:1;
464 uint32_t update_flash:1;
465 uint32_t erase_or_prog:1;
466 uint32_t version:1;
467 uint32_t acknowledgment:1;
468 uint32_t keep:1;
469 uint32_t rsvd2:24;
470 #endif
471
472 #define DL_FROM_BDE 0 /* method */
473 #define DL_FROM_SLIM 1
474
475 #define PROGRAM_FLASH 0 /* erase_or_prog */
476 #define ERASE_FLASH 1
477
478 uint32_t dl_to_adr;
479 uint32_t dl_len;
480 union
481 {
482 uint32_t dl_from_slim_offset;
483 ULP_BDE dl_from_bde;
484 ULP_BDE64 dl_from_bde64;
485 PROG_ID prog_id;
486 } un;
487 } LOAD_SM_VAR;
488
489
490 /* Structure for MB Command READ_NVPARM (02) */
491 /* Good for SLI2/3 and SLI4 */
492
493 typedef struct
494 {
495 uint32_t rsvd1[3]; /* Read as all one's */
496 uint32_t rsvd2; /* Read as all zero's */
497 uint32_t portname[2]; /* N_PORT name */
498 uint32_t nodename[2]; /* NODE name */
499 #ifdef EMLXS_BIG_ENDIAN
500 uint32_t pref_DID:24;
501 uint32_t hardAL_PA:8;
502 #endif
503 #ifdef EMLXS_LITTLE_ENDIAN
504 uint32_t hardAL_PA:8;
505 uint32_t pref_DID:24;
506 #endif
507 uint32_t rsvd3[21]; /* Read as all one's */
508 } READ_NV_VAR;
509
510
511 /* Structure for MB Command WRITE_NVPARMS (03) */
512 /* Good for SLI2/3 and SLI4 */
513
514 typedef struct
515 {
516 uint32_t rsvd1[3]; /* Must be all one's */
517 uint32_t rsvd2; /* Must be all zero's */
518 uint32_t portname[2]; /* N_PORT name */
519 uint32_t nodename[2]; /* NODE name */
520 #ifdef EMLXS_BIG_ENDIAN
521 uint32_t pref_DID:24;
522 uint32_t hardAL_PA:8;
523 #endif
524 #ifdef EMLXS_LITTLE_ENDIAN
525 uint32_t hardAL_PA:8;
526 uint32_t pref_DID:24;
527 #endif
528 uint32_t rsvd3[21]; /* Must be all one's */
529 } WRITE_NV_VAR;
530
531
532 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
533 /* Good for SLI2/3 and SLI4 */
534
535 typedef struct
536 {
537 uint32_t rsvd1;
538 union
539 {
540 struct
541 {
542 ULP_BDE64 xmit_bde64;
543 ULP_BDE64 rcv_bde64;
544 } s2;
545 } un;
546 } BIU_DIAG_VAR;
547
548
549 /* Structure for MB Command INIT_LINK (05) */
550 /* Good for SLI2/3 and SLI4 */
551
552 typedef struct
553 {
554 #ifdef EMLXS_BIG_ENDIAN
555 uint32_t rsvd1:24;
556 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */
557 /* Reset to */
558 #endif
559 #ifdef EMLXS_LITTLE_ENDIAN
560 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective */
561 /* Reset to */
562 uint32_t rsvd1:24;
563 #endif
564
565 #ifdef EMLXS_BIG_ENDIAN
566 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
567 uint8_t rsvd2;
568 uint16_t link_flags;
569 #endif
570 #ifdef EMLXS_LITTLE_ENDIAN
571 uint16_t link_flags;
572 uint8_t rsvd2;
573 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
574 #endif
575 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) */
576 /* ENDEC loopback */
577 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
578 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
579 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
580 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
581 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
582
583 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
584 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
585 #define FLAGS_PREABORT_RETURN 0x4000 /* Bit 14 */
586
587 uint32_t link_speed; /* NEW_FEATURE */
588 #define LINK_SPEED_AUTO 0 /* Auto selection */
589 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
590 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
591 } INIT_LINK_VAR;
592
593
594 /* Structure for MB Command DOWN_LINK (06) */
595 /* Good for SLI2/3 and SLI4 */
596
597 typedef struct
598 {
599 uint32_t rsvd1;
600 } DOWN_LINK_VAR;
601
602
603 /* Structure for MB Command CONFIG_LINK (07) */
604
605 typedef struct
606 {
607 #ifdef EMLXS_BIG_ENDIAN
608 uint32_t cr:1;
609 uint32_t ci:1;
610 uint32_t cr_delay:6;
611 uint32_t cr_count:8;
612 uint32_t rsvd1:8;
613 uint32_t MaxBBC:8;
614 #endif
615 #ifdef EMLXS_LITTLE_ENDIAN
616 uint32_t MaxBBC:8;
617 uint32_t rsvd1:8;
618 uint32_t cr_count:8;
619 uint32_t cr_delay:6;
620 uint32_t ci:1;
621 uint32_t cr:1;
622 #endif
623 uint32_t myId;
624 uint32_t rsvd2;
625 uint32_t edtov;
626 uint32_t arbtov;
627 uint32_t ratov;
628 uint32_t rttov;
629 uint32_t altov;
630 uint32_t crtov;
631 uint32_t citov;
632 #ifdef EMLXS_BIG_ENDIAN
633 uint32_t rrq_enable:1;
634 uint32_t rrq_immed:1;
635 uint32_t rsvd4:29;
636 uint32_t ack0_enable:1;
637 #endif
638 #ifdef EMLXS_LITTLE_ENDIAN
639 uint32_t ack0_enable:1;
640 uint32_t rsvd4:29;
641 uint32_t rrq_immed:1;
642 uint32_t rrq_enable:1;
643 #endif
644 } CONFIG_LINK;
645
646
647 /* Structure for MB Command PART_SLIM (08) */
648
649 typedef struct
650 {
651 #ifdef EMLXS_BIG_ENDIAN
652 uint32_t unused1:24;
653 uint32_t numRing:8;
654 #endif
655 #ifdef EMLXS_LITTLE_ENDIAN
656 uint32_t numRing:8;
657 uint32_t unused1:24;
658 #endif
659 emlxs_ring_def_t ringdef[4];
660 uint32_t hbainit;
661 } PART_SLIM_VAR;
662
663
664 /* Structure for MB Command CONFIG_RING (09) */
665
666 typedef struct
667 {
668 #ifdef EMLXS_BIG_ENDIAN
669 uint32_t unused2:6;
670 uint32_t recvSeq:1;
671 uint32_t recvNotify:1;
672 uint32_t numMask:8;
673 uint32_t profile:8;
674 uint32_t unused1:4;
675 uint32_t ring:4;
676 #endif
677 #ifdef EMLXS_LITTLE_ENDIAN
678 uint32_t ring:4;
679 uint32_t unused1:4;
680 uint32_t profile:8;
681 uint32_t numMask:8;
682 uint32_t recvNotify:1;
683 uint32_t recvSeq:1;
684 uint32_t unused2:6;
685 #endif
686 #ifdef EMLXS_BIG_ENDIAN
687 uint16_t maxRespXchg;
688 uint16_t maxOrigXchg;
689 #endif
690 #ifdef EMLXS_LITTLE_ENDIAN
691 uint16_t maxOrigXchg;
692 uint16_t maxRespXchg;
693 #endif
694 RR_REG rrRegs[6];
695 } CONFIG_RING_VAR;
696
697
698 /* Structure for MB Command RESET_RING (10) */
699
700 typedef struct
701 {
702 uint32_t ring_no;
703 } RESET_RING_VAR;
704
705
706 /* Structure for MB Command READ_CONFIG (11) */
707 /* Good for SLI2/3 only */
708
709 typedef struct
710 {
711 #ifdef EMLXS_BIG_ENDIAN
712 uint32_t cr:1;
713 uint32_t ci:1;
714 uint32_t cr_delay:6;
715 uint32_t cr_count:8;
716 uint32_t InitBBC:8;
717 uint32_t MaxBBC:8;
718 #endif
719 #ifdef EMLXS_LITTLE_ENDIAN
720 uint32_t MaxBBC:8;
721 uint32_t InitBBC:8;
722 uint32_t cr_count:8;
723 uint32_t cr_delay:6;
724 uint32_t ci:1;
725 uint32_t cr:1;
726 #endif
727 #ifdef EMLXS_BIG_ENDIAN
728 uint32_t topology:8;
729 uint32_t myDid:24;
730 #endif
731 #ifdef EMLXS_LITTLE_ENDIAN
732 uint32_t myDid:24;
733 uint32_t topology:8;
734 #endif
735 /* Defines for topology (defined previously) */
736 #ifdef EMLXS_BIG_ENDIAN
737 uint32_t AR:1;
738 uint32_t IR:1;
739 uint32_t rsvd1:29;
740 uint32_t ack0:1;
741 #endif
742 #ifdef EMLXS_LITTLE_ENDIAN
743 uint32_t ack0:1;
744 uint32_t rsvd1:29;
745 uint32_t IR:1;
746 uint32_t AR:1;
747 #endif
748 uint32_t edtov;
749 uint32_t arbtov;
750 uint32_t ratov;
751 uint32_t rttov;
752 uint32_t altov;
753 uint32_t lmt;
754
755 #define LMT_1GB_CAPABLE 0x0004
756 #define LMT_2GB_CAPABLE 0x0008
757 #define LMT_4GB_CAPABLE 0x0040
758 #define LMT_8GB_CAPABLE 0x0080
759 #define LMT_10GB_CAPABLE 0x0100
760 #define LMT_16GB_CAPABLE 0x0200
761 /* E2E supported on adapters >= 8GB */
762 #define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
763
764 uint32_t rsvd2;
765 uint32_t rsvd3;
766 uint32_t max_xri;
767 uint32_t max_iocb;
768 uint32_t max_rpi;
769 uint32_t avail_xri;
770 uint32_t avail_iocb;
771 uint32_t avail_rpi;
772 uint32_t max_vpi;
773 uint32_t max_alpa;
774 uint32_t rsvd4;
775 uint32_t avail_vpi;
776
777 } READ_CONFIG_VAR;
778
779
780 /* Structure for MB Command READ_CONFIG(0x11) */
781 /* Good for SLI4 only */
782
783 typedef struct
784 {
785 #ifdef EMLXS_BIG_ENDIAN
786 uint32_t extents:1; /* Word 1 */
787 uint32_t rsvd1:31;
788
789 uint32_t topology:8; /* Word 2 */
790 uint32_t rsvd2:15;
791 uint32_t ldv:1;
792 uint32_t link_type:2;
793 uint32_t link_number:6;
794 #endif
795 #ifdef EMLXS_LITTLE_ENDIAN
796 uint32_t rsvd1:31; /* Word 1 */
797 uint32_t extents:1;
798
799 uint32_t link_number:6; /* Word 2 */
800 uint32_t link_type:2;
801 uint32_t ldv:1;
802 uint32_t rsvd2:15;
803 uint32_t topology:8;
804 #endif
805 uint32_t rsvd3; /* Word 3 */
806 uint32_t edtov; /* Word 4 */
807 uint32_t rsvd4; /* Word 5 */
808 uint32_t ratov; /* Word 6 */
809 uint32_t rsvd5; /* Word 7 */
810 uint32_t rsvd6; /* Word 8 */
811 uint32_t lmt; /* Word 9 */
812 uint32_t rsvd8; /* Word 10 */
813 uint32_t rsvd9; /* Word 11 */
814
815 #ifdef EMLXS_BIG_ENDIAN
816 uint16_t XRICount; /* Word 12 */
817 uint16_t XRIBase; /* Word 12 */
818
819 uint16_t RPICount; /* Word 13 */
820 uint16_t RPIBase; /* Word 13 */
821
822 uint16_t VPICount; /* Word 14 */
823 uint16_t VPIBase; /* Word 14 */
824
825 uint16_t VFICount; /* Word 15 */
826 uint16_t VFIBase; /* Word 15 */
827
828 uint16_t FCFICount; /* Word 16 */
829 uint16_t rsvd10; /* Word 16 */
830
831 uint16_t EQCount; /* Word 17 */
832 uint16_t RQCount; /* Word 17 */
833
834 uint16_t CQCount; /* Word 18 */
835 uint16_t WQCount; /* Word 18 */
836 #endif
837 #ifdef EMLXS_LITTLE_ENDIAN
838 uint16_t XRIBase; /* Word 12 */
839 uint16_t XRICount; /* Word 12 */
840
841 uint16_t RPIBase; /* Word 13 */
842 uint16_t RPICount; /* Word 13 */
843
844 uint16_t VPIBase; /* Word 14 */
845 uint16_t VPICount; /* Word 14 */
846
847 uint16_t VFIBase; /* Word 15 */
848 uint16_t VFICount; /* Word 15 */
849
850 uint16_t rsvd10; /* Word 16 */
851 uint16_t FCFICount; /* Word 16 */
852
853 uint16_t RQCount; /* Word 17 */
854 uint16_t EQCount; /* Word 17 */
855
856 uint16_t WQCount; /* Word 18 */
857 uint16_t CQCount; /* Word 18 */
858 #endif
859
860 } READ_CONFIG4_VAR;
861
862 /* Structure for MB Command READ_RCONFIG (12) */
863
864 typedef struct
865 {
866 #ifdef EMLXS_BIG_ENDIAN
867 uint32_t rsvd2:7;
868 uint32_t recvNotify:1;
869 uint32_t numMask:8;
870 uint32_t profile:8;
871 uint32_t rsvd1:4;
872 uint32_t ring:4;
873 #endif
874 #ifdef EMLXS_LITTLE_ENDIAN
875 uint32_t ring:4;
876 uint32_t rsvd1:4;
877 uint32_t profile:8;
878 uint32_t numMask:8;
879 uint32_t recvNotify:1;
880 uint32_t rsvd2:7;
881 #endif
882 #ifdef EMLXS_BIG_ENDIAN
883 uint16_t maxResp;
884 uint16_t maxOrig;
885 #endif
886 #ifdef EMLXS_LITTLE_ENDIAN
887 uint16_t maxOrig;
888 uint16_t maxResp;
889 #endif
890 RR_REG rrRegs[6];
891 #ifdef EMLXS_BIG_ENDIAN
892 uint16_t cmdRingOffset;
893 uint16_t cmdEntryCnt;
894 uint16_t rspRingOffset;
895 uint16_t rspEntryCnt;
896 uint16_t nextCmdOffset;
897 uint16_t rsvd3;
898 uint16_t nextRspOffset;
899 uint16_t rsvd4;
900 #endif
901 #ifdef EMLXS_LITTLE_ENDIAN
902 uint16_t cmdEntryCnt;
903 uint16_t cmdRingOffset;
904 uint16_t rspEntryCnt;
905 uint16_t rspRingOffset;
906 uint16_t rsvd3;
907 uint16_t nextCmdOffset;
908 uint16_t rsvd4;
909 uint16_t nextRspOffset;
910 #endif
911 } READ_RCONF_VAR;
912
913
914 /* Structure for MB Command READ_SPARM (13) */
915 /* Structure for MB Command READ_SPARM64 (0x8D) */
916 /* Good for SLI2/3 and SLI4 */
917
918 typedef struct
919 {
920 uint32_t rsvd1;
921 uint32_t rsvd2;
922 union
923 {
924 ULP_BDE sp; /* This BDE points to SERV_PARM */
925 /* structure */
926 ULP_BDE64 sp64;
927 } un;
928 uint32_t rsvd3;
929
930 #ifdef EMLXS_BIG_ENDIAN
931 uint16_t portNameCnt;
932 uint16_t portNameOffset;
933
934 uint16_t fabricNameCnt;
935 uint16_t fabricNameOffset;
936
937 uint16_t lportNameCnt;
938 uint16_t lportNameOffset;
939
940 uint16_t lfabricNameCnt;
941 uint16_t lfabricNameOffset;
942
943 #endif
944 #ifdef EMLXS_LITTLE_ENDIAN
945 uint16_t portNameOffset;
946 uint16_t portNameCnt;
947
948 uint16_t fabricNameOffset;
949 uint16_t fabricNameCnt;
950
951 uint16_t lportNameOffset;
952 uint16_t lportNameCnt;
953
954 uint16_t lfabricNameOffset;
955 uint16_t lfabricNameCnt;
956
957 #endif
958
959 } READ_SPARM_VAR;
960
961
962 /* Structure for MB Command READ_STATUS (14) */
963 /* Good for SLI2/3 and SLI4 */
964
965 typedef struct
966 {
967 #ifdef EMLXS_BIG_ENDIAN
968 uint32_t rsvd1:31;
969 uint32_t clrCounters:1;
970
971 uint16_t activeXriCnt;
972 uint16_t activeRpiCnt;
973 #endif
974 #ifdef EMLXS_LITTLE_ENDIAN
975 uint32_t clrCounters:1;
976 uint32_t rsvd1:31;
977
978 uint16_t activeRpiCnt;
979 uint16_t activeXriCnt;
980 #endif
981 uint32_t xmitByteCnt;
982 uint32_t rcvByteCnt;
983 uint32_t xmitFrameCnt;
984 uint32_t rcvFrameCnt;
985 uint32_t xmitSeqCnt;
986 uint32_t rcvSeqCnt;
987 uint32_t totalOrigExchanges;
988 uint32_t totalRespExchanges;
989 uint32_t rcvPbsyCnt;
990 uint32_t rcvFbsyCnt;
991 } READ_STATUS_VAR;
992
993
994 /* Structure for MB Command READ_RPI (15) */
995 /* Structure for MB Command READ_RPI64 (0x8F) */
996
997 typedef struct
998 {
999 #ifdef EMLXS_BIG_ENDIAN
1000 uint16_t nextRpi;
1001 uint16_t reqRpi;
1002 uint32_t rsvd2:8;
1003 uint32_t DID:24;
1004 #endif
1005 #ifdef EMLXS_LITTLE_ENDIAN
1006 uint16_t reqRpi;
1007 uint16_t nextRpi;
1008 uint32_t DID:24;
1009 uint32_t rsvd2:8;
1010 #endif
1011 union
1012 {
1013 ULP_BDE sp;
1014 ULP_BDE64 sp64;
1015 } un;
1016 } READ_RPI_VAR;
1017
1018
1019 /* Structure for MB Command READ_XRI (16) */
1020
1021 typedef struct
1022 {
1023 #ifdef EMLXS_BIG_ENDIAN
1024 uint16_t nextXri;
1025 uint16_t reqXri;
1026 uint16_t rsvd1;
1027 uint16_t rpi;
1028 uint32_t rsvd2:8;
1029 uint32_t DID:24;
1030 uint32_t rsvd3:8;
1031 uint32_t SID:24;
1032 uint32_t rsvd4;
1033 uint8_t seqId;
1034 uint8_t rsvd5;
1035 uint16_t seqCount;
1036 uint16_t oxId;
1037 uint16_t rxId;
1038 uint32_t rsvd6:30;
1039 uint32_t si:1;
1040 uint32_t exchOrig:1;
1041 #endif
1042 #ifdef EMLXS_LITTLE_ENDIAN
1043 uint16_t reqXri;
1044 uint16_t nextXri;
1045 uint16_t rpi;
1046 uint16_t rsvd1;
1047 uint32_t DID:24;
1048 uint32_t rsvd2:8;
1049 uint32_t SID:24;
1050 uint32_t rsvd3:8;
1051 uint32_t rsvd4;
1052 uint16_t seqCount;
1053 uint8_t rsvd5;
1054 uint8_t seqId;
1055 uint16_t rxId;
1056 uint16_t oxId;
1057 uint32_t exchOrig:1;
1058 uint32_t si:1;
1059 uint32_t rsvd6:30;
1060 #endif
1061 } READ_XRI_VAR;
1062
1063
1064 /* Structure for MB Command READ_REV (17) */
1065 /* Good for SLI2/3 only */
1066
1067 typedef struct
1068 {
1069 #ifdef EMLXS_BIG_ENDIAN
1070 uint32_t cv:1;
1071 uint32_t rr:1;
1072 uint32_t co:1;
1073 uint32_t rp:1;
1074 uint32_t cv3:1;
1075 uint32_t rf3:1;
1076 uint32_t rsvd1:10;
1077 uint32_t offset:14;
1078 uint32_t rv:2;
1079 #endif
1080 #ifdef EMLXS_LITTLE_ENDIAN
1081 uint32_t rv:2;
1082 uint32_t offset:14;
1083 uint32_t rsvd1:10;
1084 uint32_t rf3:1;
1085 uint32_t cv3:1;
1086 uint32_t rp:1;
1087 uint32_t co:1;
1088 uint32_t rr:1;
1089 uint32_t cv:1;
1090 #endif
1091 uint32_t biuRev;
1092 uint32_t smRev;
1093 union
1094 {
1095 uint32_t smFwRev;
1096 struct
1097 {
1098 #ifdef EMLXS_BIG_ENDIAN
1099 uint8_t ProgType;
1100 uint8_t ProgId;
1101 uint16_t ProgVer:4;
1102 uint16_t ProgRev:4;
1103 uint16_t ProgFixLvl:2;
1104 uint16_t ProgDistType:2;
1105 uint16_t DistCnt:4;
1106 #endif
1107 #ifdef EMLXS_LITTLE_ENDIAN
1108 uint16_t DistCnt:4;
1109 uint16_t ProgDistType:2;
1110 uint16_t ProgFixLvl:2;
1111 uint16_t ProgRev:4;
1112 uint16_t ProgVer:4;
1113 uint8_t ProgId;
1114 uint8_t ProgType;
1115 #endif
1116 } b;
1117 } un;
1118 uint32_t endecRev;
1119 #ifdef EMLXS_BIG_ENDIAN
1120 uint8_t feaLevelHigh;
1121 uint8_t feaLevelLow;
1122 uint8_t fcphHigh;
1123 uint8_t fcphLow;
1124 #endif
1125 #ifdef EMLXS_LITTLE_ENDIAN
1126 uint8_t fcphLow;
1127 uint8_t fcphHigh;
1128 uint8_t feaLevelLow;
1129 uint8_t feaLevelHigh;
1130 #endif
1131 uint32_t postKernRev;
1132 uint32_t opFwRev;
1133 uint8_t opFwName[16];
1134
1135 uint32_t sliFwRev1;
1136 uint8_t sliFwName1[16];
1137 uint32_t sliFwRev2;
1138 uint8_t sliFwName2[16];
1139 } READ_REV_VAR;
1140
1141 /* Structure for MB Command READ_REV (17) */
1142 /* Good for SLI4 only */
1143
1144 typedef struct
1145 {
1146 #ifdef EMLXS_BIG_ENDIAN
1147 uint32_t Rsvd3:2;
1148 uint32_t VPD:1;
1149 uint32_t rsvd2:6;
1150 uint32_t dcbxMode:2;
1151 uint32_t FCoE:1;
1152 uint32_t sliLevel:4;
1153 uint32_t rsvd1:16;
1154 #endif
1155 #ifdef EMLXS_LITTLE_ENDIAN
1156 uint32_t rsvd1:16;
1157 uint32_t sliLevel:4;
1158 uint32_t FCoE:1;
1159 uint32_t dcbxMode:2;
1160 uint32_t rsvd2:6;
1161 uint32_t VPD:1;
1162 uint32_t Rsvd3:2;
1163 #endif
1164
1165 uint32_t HwRev1;
1166 uint32_t HwRev2;
1167 uint32_t Rsvd4;
1168 uint32_t HwRev3;
1169
1170 #ifdef EMLXS_BIG_ENDIAN
1171 uint8_t feaLevelHigh;
1172 uint8_t feaLevelLow;
1173 uint8_t fcphHigh;
1174 uint8_t fcphLow;
1175 #endif
1176 #ifdef EMLXS_LITTLE_ENDIAN
1177 uint8_t fcphLow;
1178 uint8_t fcphHigh;
1179 uint8_t feaLevelLow;
1180 uint8_t feaLevelHigh;
1181 #endif
1182
1183 uint32_t Redboot;
1184
1185 uint32_t ARMFwId;
1186 uint8_t ARMFwName[16];
1187
1188 uint32_t ULPFwId;
1189 uint8_t ULPFwName[16];
1190
1191 uint32_t Rsvd6[30];
1192
1193 ULP_BDE64 VPDBde;
1194
1195 uint32_t ReturnedVPDLength;
1196
1197 } READ_REV4_VAR;
1198
1199 #define EMLXS_DCBX_MODE_CIN 0 /* Mapped to nonFIP mode */
1200 #define EMLXS_DCBX_MODE_CEE 1 /* Mapped to FIP mode */
1201
1202 /* Structure for MB Command READ_LINK_STAT (18) */
1203 /* Good for SLI2/3 and SLI4 */
1204
1205 typedef struct
1206 {
1207 uint32_t rsvd1;
1208 uint32_t linkFailureCnt;
1209 uint32_t lossSyncCnt;
1210
1211 uint32_t lossSignalCnt;
1212 uint32_t primSeqErrCnt;
1213 uint32_t invalidXmitWord;
1214 uint32_t crcCnt;
1215 uint32_t primSeqTimeout;
1216 uint32_t elasticOverrun;
1217 uint32_t arbTimeout;
1218
1219 uint32_t rxBufCredit;
1220 uint32_t rxBufCreditCur;
1221
1222 uint32_t txBufCredit;
1223 uint32_t txBufCreditCur;
1224
1225 uint32_t EOFaCnt;
1226 uint32_t EOFdtiCnt;
1227 uint32_t EOFniCnt;
1228 uint32_t SOFfCnt;
1229 uint32_t DropAERCnt;
1230 uint32_t DropRcv;
1231 } READ_LNK_VAR;
1232
1233
1234 /* Structure for MB Command REG_LOGIN (19) */
1235 /* Structure for MB Command REG_LOGIN64 (0x93) */
1236 /* Structure for MB Command REG_RPI (0x93) */
1237 /* Good for SLI2/3 and SLI4 */
1238
1239 typedef struct
1240 {
1241 #ifdef EMLXS_BIG_ENDIAN
1242 uint16_t rsvd1;
1243 uint16_t rpi;
1244 uint32_t CI:1;
1245 uint32_t rsvd2:1;
1246 uint32_t TERP:1;
1247 uint32_t rsvd3:4;
1248 uint32_t update:1;
1249 uint32_t did:24;
1250 #endif
1251 #ifdef EMLXS_LITTLE_ENDIAN
1252 uint16_t rpi;
1253 uint16_t rsvd1;
1254 uint32_t did:24;
1255 uint32_t update:1;
1256 uint32_t rsvd3:4;
1257 uint32_t TERP:1;
1258 uint32_t rsvd2:1;
1259 uint32_t CI:1;
1260 #endif
1261 union
1262 {
1263 ULP_BDE sp;
1264 ULP_BDE64 sp64;
1265 } un;
1266
1267 #ifdef EMLXS_BIG_ENDIAN
1268 uint16_t rsvd6;
1269 uint16_t vpi;
1270 #endif
1271 #ifdef EMLXS_LITTLE_ENDIAN
1272 uint16_t vpi;
1273 uint16_t rsvd6;
1274 #endif
1275 } REG_LOGIN_VAR;
1276
1277 /* Word 30 contents for REG_LOGIN */
1278 typedef union
1279 {
1280 struct
1281 {
1282 #ifdef EMLXS_BIG_ENDIAN
1283 uint16_t rsvd1:12;
1284 uint16_t class:4;
1285 uint16_t xri;
1286 #endif
1287 #ifdef EMLXS_LITTLE_ENDIAN
1288 uint16_t xri;
1289 uint16_t class:4;
1290 uint16_t rsvd1:12;
1291 #endif
1292 } f;
1293 uint32_t word;
1294 } REG_WD30;
1295
1296
1297 /* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */
1298 /* Structure for MB Command UNREG_RPI (0x14) - SLI4 */
1299
1300 typedef struct
1301 {
1302 #ifdef EMLXS_BIG_ENDIAN
1303 uint16_t ll:2; /* SLI4 only */
1304 uint16_t rsvd1:14;
1305 uint16_t rpi;
1306 #endif
1307 #ifdef EMLXS_LITTLE_ENDIAN
1308 uint16_t rpi;
1309 uint16_t rsvd1:14;
1310 uint16_t ll:2; /* SLI4 only */
1311 #endif
1312
1313 uint32_t rsvd2;
1314 uint32_t rsvd3;
1315 uint32_t rsvd4;
1316 uint32_t rsvd5;
1317 #ifdef EMLXS_BIG_ENDIAN
1318 uint16_t rsvd6;
1319 uint16_t vpi;
1320 #endif
1321 #ifdef EMLXS_LITTLE_ENDIAN
1322 uint16_t vpi;
1323 uint16_t rsvd6;
1324 #endif
1325 } UNREG_LOGIN_VAR;
1326
1327 /* Structure for MB Command REG_FCFI (0xA0) */
1328 /* Good for SLI4 only */
1329
1330 typedef struct
1331 {
1332 #ifdef EMLXS_BIG_ENDIAN
1333 uint16_t FCFI;
1334 uint16_t InfoIndex;
1335
1336 uint16_t RQId0;
1337 uint16_t RQId1;
1338 uint16_t RQId2;
1339 uint16_t RQId3;
1340
1341 uint8_t Id0_type;
1342 uint8_t Id0_type_mask;
1343 uint8_t Id0_rctl;
1344 uint8_t Id0_rctl_mask;
1345
1346 uint8_t Id1_type;
1347 uint8_t Id1_type_mask;
1348 uint8_t Id1_rctl;
1349 uint8_t Id1_rctl_mask;
1350
1351 uint8_t Id2_type;
1352 uint8_t Id2_type_mask;
1353 uint8_t Id2_rctl;
1354 uint8_t Id2_rctl_mask;
1355
1356 uint8_t Id3_type;
1357 uint8_t Id3_type_mask;
1358 uint8_t Id3_rctl;
1359 uint8_t Id3_rctl_mask;
1360
1361 uint32_t Rsvd1: 17;
1362 uint32_t mam: 2;
1363 uint32_t vv: 1;
1364 uint32_t vlanTag: 12;
1365 #endif
1366 #ifdef EMLXS_LITTLE_ENDIAN
1367 uint16_t InfoIndex;
1368 uint16_t FCFI;
1369
1370 uint16_t RQId1;
1371 uint16_t RQId0;
1372 uint16_t RQId3;
1373 uint16_t RQId2;
1374
1375 uint8_t Id0_rctl_mask;
1376 uint8_t Id0_rctl;
1377 uint8_t Id0_type_mask;
1378 uint8_t Id0_type;
1379
1380 uint8_t Id1_rctl_mask;
1381 uint8_t Id1_rctl;
1382 uint8_t Id1_type_mask;
1383 uint8_t Id1_type;
1384
1385 uint8_t Id2_rctl_mask;
1386 uint8_t Id2_rctl;
1387 uint8_t Id2_type_mask;
1388 uint8_t Id2_type;
1389
1390 uint8_t Id3_rctl_mask;
1391 uint8_t Id3_rctl;
1392 uint8_t Id3_type_mask;
1393 uint8_t Id3_type;
1394
1395 uint32_t vlanTag: 12;
1396 uint32_t vv: 1;
1397 uint32_t mam: 2;
1398 uint32_t Rsvd1: 17;
1399 #endif
1400
1401 } REG_FCFI_VAR;
1402
1403 /* Defines for mam */
1404 #define EMLXS_REG_FCFI_MAM_SPMA 1 /* Server Provided MAC Address */
1405 #define EMLXS_REG_FCFI_MAM_FPMA 2 /* Fabric Provided MAC Address */
1406
1407 /* Structure for MB Command UNREG_FCFI (0xA2) */
1408 /* Good for SLI4 only */
1409
1410 typedef struct
1411 {
1412 uint32_t Rsvd1;
1413 #ifdef EMLXS_BIG_ENDIAN
1414 uint16_t Rsvd2;
1415 uint16_t FCFI;
1416 #endif
1417 #ifdef EMLXS_LITTLE_ENDIAN
1418 uint16_t FCFI;
1419 uint16_t Rsvd2;
1420 #endif
1421 } UNREG_FCFI_VAR;
1422
1423 /* Structure for MB Command RESUME_RPI (0x9E) */
1424 /* Good for SLI4 only */
1425
1426 typedef struct
1427 {
1428 #ifdef EMLXS_BIG_ENDIAN
1429 uint16_t Rsvd1;
1430 uint16_t RPI;
1431
1432 uint32_t EventTag;
1433 uint32_t rsvd2[3];
1434
1435 uint16_t VFI;
1436 uint16_t VPI;
1437 #endif
1438 #ifdef EMLXS_LITTLE_ENDIAN
1439 uint16_t RPI;
1440 uint16_t Rsvd1;
1441
1442 uint32_t EventTag;
1443 uint32_t rsvd2[3];
1444
1445 uint16_t VPI;
1446 uint16_t VFI;
1447 #endif
1448
1449 } RESUME_RPI_VAR;
1450
1451
1452 /* Structure for MB Command UNREG_D_ID (0x23) */
1453
1454 typedef struct
1455 {
1456 uint32_t did;
1457
1458 uint32_t rsvd2;
1459 uint32_t rsvd3;
1460 uint32_t rsvd4;
1461 uint32_t rsvd5;
1462 #ifdef EMLXS_BIG_ENDIAN
1463 uint16_t rsvd6;
1464 uint16_t vpi;
1465 #endif
1466 #ifdef EMLXS_LITTLE_ENDIAN
1467 uint16_t vpi;
1468 uint16_t rsvd6;
1469 #endif
1470 } UNREG_D_ID_VAR;
1471
1472
1473 /* Structure for MB Command READ_LA (21) */
1474 /* Structure for MB Command READ_LA64 (0x95) */
1475
1476 typedef struct
1477 {
1478 uint32_t eventTag; /* Event tag */
1479 #ifdef EMLXS_BIG_ENDIAN
1480 uint32_t rsvd2:19;
1481 uint32_t fa:1;
1482 uint32_t mm:1;
1483 uint32_t tc:1;
1484 uint32_t pb:1;
1485 uint32_t il:1;
1486 uint32_t attType:8;
1487 #endif
1488 #ifdef EMLXS_LITTLE_ENDIAN
1489 uint32_t attType:8;
1490 uint32_t il:1;
1491 uint32_t pb:1;
1492 uint32_t tc:1;
1493 uint32_t mm:1;
1494 uint32_t fa:1;
1495 uint32_t rsvd2:19;
1496 #endif
1497 #define AT_RESERVED 0x00 /* Reserved - attType */
1498 #define AT_LINK_UP 0x01 /* Link is up */
1499 #define AT_LINK_DOWN 0x02 /* Link is down */
1500 #define AT_NO_HARD_ALPA 0x03 /* SLI4 */
1501
1502 #ifdef EMLXS_BIG_ENDIAN
1503 uint8_t granted_AL_PA;
1504 uint8_t lipAlPs;
1505 uint8_t lipType;
1506 uint8_t topology;
1507 #endif
1508 #ifdef EMLXS_LITTLE_ENDIAN
1509 uint8_t topology;
1510 uint8_t lipType;
1511 uint8_t lipAlPs;
1512 uint8_t granted_AL_PA;
1513 #endif
1514
1515 /* lipType */
1516 #define LT_PORT_INIT 0x00 /* An L_PORT initing (F7, AL_PS) - lipType */
1517 #define LT_PORT_ERR 0x01 /* Err @L_PORT rcv'er (F8, AL_PS) */
1518 #define LT_RESET_APORT 0x02 /* Lip Reset of some other port */
1519 #define LT_RESET_MYPORT 0x03 /* Lip Reset of my port */
1520
1521 /* topology */
1522 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
1523 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL (private) */
1524
1525 union
1526 {
1527 ULP_BDE lilpBde; /* This BDE points to a */
1528 /* 128 byte buffer to store */
1529 /* the LILP AL_PA position */
1530 /* map into */
1531 ULP_BDE64 lilpBde64;
1532 } un;
1533 #ifdef EMLXS_BIG_ENDIAN
1534 uint32_t Dlu:1;
1535 uint32_t Dtf:1;
1536 uint32_t Drsvd2:14;
1537 uint32_t DlnkSpeed:8;
1538 uint32_t DnlPort:4;
1539 uint32_t Dtx:2;
1540 uint32_t Drx:2;
1541 #endif
1542 #ifdef EMLXS_LITTLE_ENDIAN
1543 uint32_t Drx:2;
1544 uint32_t Dtx:2;
1545 uint32_t DnlPort:4;
1546 uint32_t DlnkSpeed:8;
1547 uint32_t Drsvd2:14;
1548 uint32_t Dtf:1;
1549 uint32_t Dlu:1;
1550 #endif
1551 #ifdef EMLXS_BIG_ENDIAN
1552 uint32_t Ulu:1;
1553 uint32_t Utf:1;
1554 uint32_t Ursvd2:14;
1555 uint32_t UlnkSpeed:8;
1556 uint32_t UnlPort:4;
1557 uint32_t Utx:2;
1558 uint32_t Urx:2;
1559 #endif
1560 #ifdef EMLXS_LITTLE_ENDIAN
1561 uint32_t Urx:2;
1562 uint32_t Utx:2;
1563 uint32_t UnlPort:4;
1564 uint32_t UlnkSpeed:8;
1565 uint32_t Ursvd2:14;
1566 uint32_t Utf:1;
1567 uint32_t Ulu:1;
1568 #endif
1569 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
1570 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
1571 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
1572 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
1573 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
1574 #define LA_16GHZ_LINK 0x80 /* lnkSpeed */
1575 #define LA_32GHZ_LINK 0x90 /* lnkSpeed */
1576 } READ_LA_VAR;
1577
1578
1579 /* Structure for MB Command CLEAR_LA (22) */
1580
1581 typedef struct
1582 {
1583 uint32_t eventTag; /* Event tag */
1584 uint32_t rsvd1;
1585 } CLEAR_LA_VAR;
1586
1587 /* Structure for MB Command DUMP */
1588 /* Good for SLI2/3 only */
1589
1590 typedef struct
1591 {
1592 #ifdef EMLXS_BIG_ENDIAN
1593 uint32_t rsvd:25;
1594 uint32_t ra:1;
1595 uint32_t co:1;
1596 uint32_t cv:1;
1597 uint32_t type:4;
1598
1599 uint32_t entry_index:16;
1600 uint32_t region_id:16;
1601 #endif
1602 #ifdef EMLXS_LITTLE_ENDIAN
1603 uint32_t type:4;
1604 uint32_t cv:1;
1605 uint32_t co:1;
1606 uint32_t ra:1;
1607 uint32_t rsvd:25;
1608
1609 uint32_t region_id:16;
1610 uint32_t entry_index:16;
1611 #endif
1612 uint32_t base_adr;
1613 uint32_t word_cnt;
1614 uint32_t resp_offset;
1615 } DUMP_VAR;
1616
1617 /* Structure for MB Command DUMP */
1618 /* Good for SLI4 only */
1619
1620 typedef struct
1621 {
1622 #ifdef EMLXS_BIG_ENDIAN
1623 uint32_t ppi:4;
1624 uint32_t phy_index:4;
1625 uint32_t rsvd:20;
1626 uint32_t type:4;
1627
1628 uint32_t entry_index:16;
1629 uint32_t region_id:16;
1630 #endif
1631 #ifdef EMLXS_LITTLE_ENDIAN
1632 uint32_t type:4;
1633 uint32_t rsvd:20;
1634 uint32_t phy_index:4;
1635 uint32_t ppi:4;
1636
1637 uint32_t region_id:16;
1638 uint32_t entry_index:16;
1639 #endif
1640 uint32_t available_cnt;
1641 uint32_t addrLow;
1642 uint32_t addrHigh;
1643 uint32_t rsp_cnt;
1644 } DUMP4_VAR;
1645
1646 /*
1647 * Dump type
1648 */
1649 #define DMP_MEM_REG 0x1
1650 #define DMP_NV_PARAMS 0x2
1651
1652 /*
1653 * Dump region ID
1654 */
1655 #define NODE_CFG_A_REGION_ID 0
1656 #define NODE_CFG_B_REGION_ID 1
1657 #define NODE_CFG_C_REGION_ID 2
1658 #define NODE_CFG_D_REGION_ID 3
1659 #define WAKE_UP_PARMS_REGION_ID 4
1660 #define DEF_PCI_CFG_REGION_ID 5
1661 #define PCI_CFG_1_REGION_ID 6
1662 #define PCI_CFG_2_REGION_ID 7
1663 #define RSVD1_REGION_ID 8
1664 #define RSVD2_REGION_ID 9
1665 #define RSVD3_REGION_ID 10
1666 #define RSVD4_REGION_ID 11
1667 #define RSVD5_REGION_ID 12
1668 #define RSVD6_REGION_ID 13
1669 #define RSVD7_REGION_ID 14
1670 #define DIAG_TRACE_REGION_ID 15
1671 #define WWN_REGION_ID 16
1672
1673 #define DMP_VPD_REGION 14
1674 #define DMP_VPD_SIZE 1024
1675 #define DMP_VPD_DUMP_WCOUNT 24
1676
1677 #define DMP_FCOE_REGION 23
1678 #define DMP_FCOE_DUMP_WCOUNT 256
1679
1680
1681 /* Structure for MB Command UPDATE_CFG */
1682 /* Good for SLI2/3 and SLI4 */
1683
1684 typedef struct
1685 {
1686 #ifdef EMLXS_BIG_ENDIAN
1687 uint32_t rsvd2:16;
1688 uint32_t proc_type:8;
1689 uint32_t rsvd1:1;
1690 uint32_t Abit:1;
1691 uint32_t Obit:1;
1692 uint32_t Vbit:1;
1693 uint32_t req_type:4;
1694 #define INIT_REGION 1
1695 #define UPDATE_DATA 2
1696 #define CLEAN_UP_CFG 3
1697 uint32_t entry_len:16;
1698 uint32_t region_id:16;
1699 #endif
1700
1701 #ifdef EMLXS_LITTLE_ENDIAN
1702 uint32_t req_type:4;
1703 #define INIT_REGION 1
1704 #define UPDATE_DATA 2
1705 #define CLEAN_UP_CFG 3
1706 uint32_t Vbit:1;
1707 uint32_t Obit:1;
1708 uint32_t Abit:1;
1709 uint32_t rsvd1:1;
1710 uint32_t proc_type:8;
1711 uint32_t rsvd2:16;
1712
1713 uint32_t region_id:16;
1714 uint32_t entry_len:16;
1715 #endif
1716
1717 uint32_t rsp_info;
1718 uint32_t byte_len;
1719 uint32_t cfg_data;
1720 } UPDATE_CFG_VAR;
1721
1722 /* Structure for MB Command DEL_LD_ENTRY (29) */
1723
1724 typedef struct
1725 {
1726 #ifdef EMLXS_LITTLE_ENDIAN
1727 uint32_t list_req:2;
1728 uint32_t list_rsp:2;
1729 uint32_t rsvd:28;
1730 #else
1731 uint32_t rsvd:28;
1732 uint32_t list_rsp:2;
1733 uint32_t list_req:2;
1734 #endif
1735
1736 #define FLASH_LOAD_LIST 1
1737 #define RAM_LOAD_LIST 2
1738 #define BOTH_LISTS 3
1739
1740 PROG_ID prog_id;
1741 } DEL_LD_ENTRY_VAR;
1742
1743 /* Structure for MB Command LOAD_AREA (81) */
1744 typedef struct
1745 {
1746 #ifdef EMLXS_LITTLE_ENDIAN
1747 uint32_t load_cmplt:1;
1748 uint32_t method:1;
1749 uint32_t rsvd1:1;
1750 uint32_t update_flash:1;
1751 uint32_t erase_or_prog:1;
1752 uint32_t version:1;
1753 uint32_t rsvd2:2;
1754 uint32_t progress:8;
1755 uint32_t step:8;
1756 uint32_t area_id:8;
1757 #else
1758 uint32_t area_id:8;
1759 uint32_t step:8;
1760 uint32_t progress:8;
1761 uint32_t rsvd2:2;
1762 uint32_t version:1;
1763 uint32_t erase_or_prog:1;
1764 uint32_t update_flash:1;
1765 uint32_t rsvd1:1;
1766 uint32_t method:1;
1767 uint32_t load_cmplt:1;
1768 #endif
1769 uint32_t dl_to_adr;
1770 uint32_t dl_len;
1771 union
1772 {
1773 uint32_t dl_from_slim_offset;
1774 ULP_BDE dl_from_bde;
1775 ULP_BDE64 dl_from_bde64;
1776 PROG_ID prog_id;
1777 } un;
1778 } LOAD_AREA_VAR;
1779
1780 /* Structure for MB Command LOAD_EXP_ROM (9C) */
1781 typedef struct
1782 {
1783 #ifdef EMLXS_LITTLE_ENDIAN
1784 uint32_t rsvd1:8;
1785 uint32_t progress:8;
1786 uint32_t step:8;
1787 uint32_t rsvd2:8;
1788 #else
1789 uint32_t rsvd2:8;
1790 uint32_t step:8;
1791 uint32_t progress:8;
1792 uint32_t rsvd1:8;
1793 #endif
1794 uint32_t dl_to_adr;
1795 uint32_t rsvd3;
1796 union
1797 {
1798 uint32_t word[2];
1799 PROG_ID prog_id;
1800 } un;
1801 } LOAD_EXP_ROM_VAR;
1802
1803
1804 /* Structure for MB Command CONFIG_HBQ (7C) */
1805
1806 typedef struct
1807 {
1808 #ifdef EMLXS_BIG_ENDIAN
1809 uint32_t rsvd1:7;
1810 uint32_t recvNotify:1; /* Receive Notification */
1811 uint32_t numMask:8; /* # Mask Entries */
1812 uint32_t profile:8; /* Selection Profile */
1813 uint32_t rsvd2:8;
1814 #endif
1815 #ifdef EMLXS_LITTLE_ENDIAN
1816 uint32_t rsvd2:8;
1817 uint32_t profile:8; /* Selection Profile */
1818 uint32_t numMask:8; /* # Mask Entries */
1819 uint32_t recvNotify:1; /* Receive Notification */
1820 uint32_t rsvd1:7;
1821 #endif
1822
1823 #ifdef EMLXS_BIG_ENDIAN
1824 uint32_t hbqId:16;
1825 uint32_t rsvd3:12;
1826 uint32_t ringMask:4;
1827 #endif
1828 #ifdef EMLXS_LITTLE_ENDIAN
1829 uint32_t ringMask:4;
1830 uint32_t rsvd3:12;
1831 uint32_t hbqId:16;
1832 #endif
1833
1834 #ifdef EMLXS_BIG_ENDIAN
1835 uint32_t numEntries:16;
1836 uint32_t rsvd4:8;
1837 uint32_t headerLen:8;
1838 #endif
1839 #ifdef EMLXS_LITTLE_ENDIAN
1840 uint32_t headerLen:8;
1841 uint32_t rsvd4:8;
1842 uint32_t numEntries:16;
1843 #endif
1844
1845 uint32_t hbqaddrLow;
1846 uint32_t hbqaddrHigh;
1847
1848 #ifdef EMLXS_BIG_ENDIAN
1849 uint32_t rsvd5:31;
1850 uint32_t logEntry:1;
1851 #endif
1852 #ifdef EMLXS_LITTLE_ENDIAN
1853 uint32_t logEntry:1;
1854 uint32_t rsvd5:31;
1855 #endif
1856
1857 uint32_t rsvd6; /* w7 */
1858 uint32_t rsvd7; /* w8 */
1859 uint32_t rsvd8; /* w9 */
1860
1861 HBQ_MASK hbqMasks[6];
1862
1863 union
1864 {
1865 uint32_t allprofiles[12];
1866
1867 struct
1868 {
1869 #ifdef EMLXS_BIG_ENDIAN
1870 uint32_t seqlenoff:16;
1871 uint32_t maxlen:16;
1872 #endif
1873 #ifdef EMLXS_LITTLE_ENDIAN
1874 uint32_t maxlen:16;
1875 uint32_t seqlenoff:16;
1876 #endif
1877 #ifdef EMLXS_BIG_ENDIAN
1878 uint32_t rsvd1:28;
1879 uint32_t seqlenbcnt:4;
1880 #endif
1881 #ifdef EMLXS_LITTLE_ENDIAN
1882 uint32_t seqlenbcnt:4;
1883 uint32_t rsvd1:28;
1884 #endif
1885 uint32_t rsvd[10];
1886 } profile2;
1887
1888 struct
1889 {
1890 #ifdef EMLXS_BIG_ENDIAN
1891 uint32_t seqlenoff:16;
1892 uint32_t maxlen:16;
1893 #endif
1894 #ifdef EMLXS_LITTLE_ENDIAN
1895 uint32_t maxlen:16;
1896 uint32_t seqlenoff:16;
1897 #endif
1898 #ifdef EMLXS_BIG_ENDIAN
1899 uint32_t cmdcodeoff:28;
1900 uint32_t rsvd1:12;
1901 uint32_t seqlenbcnt:4;
1902 #endif
1903 #ifdef EMLXS_LITTLE_ENDIAN
1904 uint32_t seqlenbcnt:4;
1905 uint32_t rsvd1:12;
1906 uint32_t cmdcodeoff:28;
1907 #endif
1908 uint32_t cmdmatch[8];
1909
1910 uint32_t rsvd[2];
1911 } profile3;
1912
1913 struct
1914 {
1915 #ifdef EMLXS_BIG_ENDIAN
1916 uint32_t seqlenoff:16;
1917 uint32_t maxlen:16;
1918 #endif
1919 #ifdef EMLXS_LITTLE_ENDIAN
1920 uint32_t maxlen:16;
1921 uint32_t seqlenoff:16;
1922 #endif
1923 #ifdef EMLXS_BIG_ENDIAN
1924 uint32_t cmdcodeoff:28;
1925 uint32_t rsvd1:12;
1926 uint32_t seqlenbcnt:4;
1927 #endif
1928 #ifdef EMLXS_LITTLE_ENDIAN
1929 uint32_t seqlenbcnt:4;
1930 uint32_t rsvd1:12;
1931 uint32_t cmdcodeoff:28;
1932 #endif
1933 uint32_t cmdmatch[8];
1934
1935 uint32_t rsvd[2];
1936 } profile5;
1937 } profiles;
1938 } CONFIG_HBQ_VAR;
1939
1940
1941 /* Structure for MB Command REG_VPI(0x96) */
1942 /* Good for SLI2/3 and SLI4 */
1943
1944 typedef struct
1945 {
1946 #ifdef EMLXS_BIG_ENDIAN
1947 uint32_t rsvd1;
1948 uint32_t rsvd2:7;
1949 uint32_t upd:1;
1950 uint32_t sid:24;
1951 uint32_t portname[2]; /* N_PORT name */
1952 uint32_t rsvd5;
1953 uint16_t vfi;
1954 uint16_t vpi;
1955 #endif
1956 #ifdef EMLXS_LITTLE_ENDIAN
1957 uint32_t rsvd1;
1958 uint32_t sid:24;
1959 uint32_t upd:1;
1960 uint32_t rsvd2:7;
1961 uint32_t portname[2]; /* N_PORT name */
1962 uint32_t rsvd5;
1963 uint16_t vpi;
1964 uint16_t vfi;
1965 #endif
1966 } REG_VPI_VAR;
1967
1968 /* Structure for MB Command INIT_VPI(0xA3) */
1969 /* Good for SLI4 only */
1970
1971 typedef struct
1972 {
1973 #ifdef EMLXS_BIG_ENDIAN
1974 uint16_t vfi;
1975 uint16_t vpi;
1976 #endif
1977 #ifdef EMLXS_LITTLE_ENDIAN
1978 uint16_t vpi;
1979 uint16_t vfi;
1980 #endif
1981 } INIT_VPI_VAR;
1982
1983 /* Structure for MB Command UNREG_VPI (0x97) */
1984 /* Good for SLI2/3 */
1985
1986 typedef struct
1987 {
1988 uint32_t rsvd1;
1989 uint32_t rsvd2;
1990 uint32_t rsvd3;
1991 uint32_t rsvd4;
1992 uint32_t rsvd5;
1993 #ifdef EMLXS_BIG_ENDIAN
1994 uint16_t rsvd6;
1995 uint16_t vpi;
1996 #endif
1997 #ifdef EMLXS_LITTLE_ENDIAN
1998 uint16_t vpi;
1999 uint16_t rsvd6;
2000 #endif
2001 } UNREG_VPI_VAR;
2002
2003 /* Structure for MB Command UNREG_VPI (0x97) */
2004 /* Good for SLI4 */
2005
2006 typedef struct
2007 {
2008 uint32_t rsvd1;
2009 #ifdef EMLXS_BIG_ENDIAN
2010 uint8_t ii:2;
2011 uint16_t rsvd2:14;
2012 uint16_t index;
2013 #endif
2014 #ifdef EMLXS_LITTLE_ENDIAN
2015 uint16_t index;
2016 uint16_t rsvd2:14;
2017 uint8_t ii:2;
2018 #endif
2019 } UNREG_VPI_VAR4;
2020
2021 /* Structure for MB Command REG_VFI(0x9F) */
2022 /* Good for SLI4 only */
2023
2024 typedef struct
2025 {
2026 #ifdef EMLXS_BIG_ENDIAN
2027 uint16_t rsvd1:2;
2028 uint16_t upd:1;
2029 uint16_t vp:1;
2030 uint16_t rsvd2:12;
2031 uint16_t vfi;
2032
2033 uint16_t vpi;
2034 uint16_t fcfi;
2035
2036 uint32_t portname[2]; /* N_PORT name */
2037
2038 ULP_BDE64 bde;
2039
2040 /* CHANGE with next firmware drop */
2041 uint32_t edtov;
2042 uint32_t ratov;
2043
2044 uint32_t rsvd5:8;
2045 uint32_t sid:24;
2046 #endif
2047 #ifdef EMLXS_LITTLE_ENDIAN
2048 uint16_t vfi;
2049 uint16_t rsvd2:12;
2050 uint16_t vp:1;
2051 uint16_t upd:1;
2052 uint16_t rsvd1:2;
2053
2054 uint16_t fcfi;
2055 uint16_t vpi;
2056
2057 uint32_t portname[2]; /* N_PORT name */
2058
2059 ULP_BDE64 bde;
2060
2061 /* CHANGE with next firmware drop */
2062 uint32_t edtov;
2063 uint32_t ratov;
2064
2065 uint32_t sid:24;
2066 uint32_t rsvd5:8;
2067 #endif
2068 } REG_VFI_VAR;
2069
2070 /* Structure for MB Command INIT_VFI(0xA4) */
2071 /* Good for SLI4 only */
2072
2073 typedef struct
2074 {
2075 #ifdef EMLXS_BIG_ENDIAN
2076 uint32_t vr:1;
2077 uint32_t vt:1;
2078 uint32_t vf:1;
2079 uint32_t rsvd1:13;
2080 uint32_t vfi:16;
2081
2082 uint16_t rsvd2;
2083 uint16_t fcfi;
2084
2085 uint32_t rsvd3:16;
2086 uint32_t pri:3;
2087 uint32_t vf_id:12;
2088 uint32_t rsvd4:1;
2089
2090 uint32_t hop_count:8;
2091 uint32_t rsvd5:24;
2092 #endif
2093 #ifdef EMLXS_LITTLE_ENDIAN
2094 uint32_t vfi:16;
2095 uint32_t rsvd1:13;
2096 uint32_t vf:1;
2097 uint32_t vt:1;
2098 uint32_t vr:1;
2099
2100 uint16_t fcfi;
2101 uint16_t rsvd2;
2102
2103 uint32_t rsvd4:1;
2104 uint32_t vf_id:12;
2105 uint32_t pri:3;
2106 uint32_t rsvd3:16;
2107
2108 uint32_t rsvd5:24;
2109 uint32_t hop_count:8;
2110 #endif
2111 } INIT_VFI_VAR;
2112
2113 /* Structure for MB Command UNREG_VFI (0xA1) */
2114 /* Good for SLI4 only */
2115
2116 typedef struct
2117 {
2118 #ifdef EMLXS_BIG_ENDIAN
2119 uint32_t rsvd1:3;
2120 uint32_t vp:1;
2121 uint32_t rsvd2:28;
2122
2123 uint16_t vpi;
2124 uint16_t vfi;
2125 #endif
2126 #ifdef EMLXS_LITTLE_ENDIAN
2127 uint32_t rsvd2:28;
2128 uint32_t vp:1;
2129 uint32_t rsvd1:3;
2130
2131 uint16_t vfi;
2132 uint16_t vpi;
2133 #endif
2134 } UNREG_VFI_VAR;
2135
2136
2137
2138 typedef struct
2139 {
2140 #ifdef EMLXS_BIG_ENDIAN
2141 uint32_t read_log:1;
2142 uint32_t clear_log:1;
2143 uint32_t mbox_rsp:1;
2144 uint32_t resv:28;
2145 #endif
2146 #ifdef EMLXS_LITTLE_ENDIAN
2147 uint32_t resv:28;
2148 uint32_t mbox_rsp:1;
2149 uint32_t clear_log:1;
2150 uint32_t read_log:1;
2151 #endif
2152
2153 uint32_t offset;
2154
2155 union
2156 {
2157 ULP_BDE sp;
2158 ULP_BDE64 sp64;
2159 } un;
2160 } READ_EVT_LOG_VAR;
2161
2162 typedef struct
2163 {
2164
2165 #ifdef EMLXS_BIG_ENDIAN
2166 uint16_t split_log_next;
2167 uint16_t log_next;
2168
2169 uint32_t size;
2170
2171 uint32_t format:8;
2172 uint32_t resv2:22;
2173 uint32_t log_level:1;
2174 uint32_t split_log:1;
2175 #endif
2176 #ifdef EMLXS_LITTLE_ENDIAN
2177 uint16_t log_next;
2178 uint16_t split_log_next;
2179
2180 uint32_t size;
2181
2182 uint32_t split_log:1;
2183 uint32_t log_level:1;
2184 uint32_t resv2:22;
2185 uint32_t format:8;
2186 #endif
2187
2188 uint32_t offset;
2189 } LOG_STATUS_VAR;
2190
2191
2192 /* Structure for MB Command CONFIG_PORT (0x88) */
2193 typedef struct
2194 {
2195 #ifdef EMLXS_BIG_ENDIAN
2196 uint32_t cBE:1;
2197 uint32_t cET:1;
2198 uint32_t cHpcb:1;
2199 uint32_t rMA:1;
2200 uint32_t sli_mode:4;
2201 uint32_t pcbLen:24; /* bit 23:0 of memory based port */
2202 /* config block */
2203 #endif
2204 #ifdef EMLXS_LITTLE_ENDIAN
2205 uint32_t pcbLen:24; /* bit 23:0 of memory based port */
2206 /* config block */
2207 uint32_t sli_mode:4;
2208 uint32_t rMA:1;
2209 uint32_t cHpcb:1;
2210 uint32_t cET:1;
2211 uint32_t cBE:1;
2212 #endif
2213
2214 uint32_t pcbLow; /* bit 31:0 of memory based port */
2215 /* config block */
2216 uint32_t pcbHigh; /* bit 63:32 of memory based port */
2217 /* config block */
2218 uint32_t hbainit[5];
2219
2220 #ifdef EMLXS_BIG_ENDIAN
2221 uint32_t hps:1; /* Host pointers in SLIM */
2222 uint32_t rsvd:31;
2223 #endif
2224 #ifdef EMLXS_LITTLE_ENDIAN
2225 uint32_t rsvd:31;
2226 uint32_t hps:1; /* Host pointers in SLIM */
2227 #endif
2228
2229 #ifdef EMLXS_BIG_ENDIAN
2230 uint32_t rsvd1:24;
2231 uint32_t cmv:1; /* Configure Max VPIs */
2232 uint32_t ccrp:1; /* Config Command Ring Polling */
2233 uint32_t csah:1; /* Configure Synchronous Abort */
2234 /* Handling */
2235 uint32_t chbs:1; /* Cofigure Host Backing store */
2236 uint32_t cinb:1; /* Enable Interrupt Notification */
2237 /* Block */
2238 uint32_t cerbm:1; /* Configure Enhanced Receive */
2239 /* Buffer Management */
2240 uint32_t cmx:1; /* Configure Max XRIs */
2241 uint32_t cmr:1; /* Configure Max RPIs */
2242 #endif
2243 #ifdef EMLXS_LITTLE_ENDIAN
2244 uint32_t cmr:1; /* Configure Max RPIs */
2245 uint32_t cmx:1; /* Configure Max XRIs */
2246 uint32_t cerbm:1; /* Configure Enhanced Receive */
2247 /* Buffer Management */
2248 uint32_t cinb:1; /* Enable Interrupt Notification */
2249 /* Block */
2250 uint32_t chbs:1; /* Cofigure Host Backing store */
2251 uint32_t csah:1; /* Configure Synchronous Abort */
2252 /* Handling */
2253 uint32_t ccrp:1; /* Config Command Ring Polling */
2254 uint32_t cmv:1; /* Configure Max VPIs */
2255 uint32_t rsvd1:24;
2256 #endif
2257 #ifdef EMLXS_BIG_ENDIAN
2258 uint32_t rsvd2:19; /* Reserved */
2259 uint32_t gdss:1; /* Configure Data Security SLI */
2260 uint32_t rsvd3:3; /* Reserved */
2261 uint32_t gbg:1; /* Grant BlockGuard */
2262 uint32_t gmv:1; /* Grant Max VPIs */
2263 uint32_t gcrp:1; /* Grant Command Ring Polling */
2264 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2265 uint32_t ghbs:1; /* Grant Host Backing Store */
2266 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2267 uint32_t gerbm:1; /* Grant ERBM Request */
2268 uint32_t gmx:1; /* Grant Max XRIs */
2269 uint32_t gmr:1; /* Grant Max RPIs */
2270 #endif
2271 #ifdef EMLXS_LITTLE_ENDIAN
2272 uint32_t gmr:1; /* Grant Max RPIs */
2273 uint32_t gmx:1; /* Grant Max XRIs */
2274 uint32_t gerbm:1; /* Grant ERBM Request */
2275 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2276 uint32_t ghbs:1; /* Grant Host Backing Store */
2277 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2278 uint32_t gcrp:1; /* Grant Command Ring Polling */
2279 uint32_t gmv:1; /* Grant Max VPIs */
2280 uint32_t gbg:1; /* Grant BlockGuard */
2281 uint32_t rsvd3:3; /* Reserved */
2282 uint32_t gdss:1; /* Configure Data Security SLI */
2283 uint32_t rsvd2:19; /* Reserved */
2284 #endif
2285
2286 #ifdef EMLXS_BIG_ENDIAN
2287 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2288 uint32_t max_xri:16; /* Max XRIs Port should configure */
2289 #endif
2290 #ifdef EMLXS_LITTLE_ENDIAN
2291 uint32_t max_xri:16; /* Max XRIs Port should configure */
2292 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2293 #endif
2294
2295 #ifdef EMLXS_BIG_ENDIAN
2296 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2297 uint32_t rsvd4:16; /* Max HBQs Host expect to configure */
2298 #endif
2299 #ifdef EMLXS_LITTLE_ENDIAN
2300 uint32_t rsvd4:16; /* Max HBQs Host expect to configure */
2301 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2302 #endif
2303
2304 uint32_t rsvd5; /* Reserved */
2305
2306 #ifdef EMLXS_BIG_ENDIAN
2307 uint32_t rsvd6:16; /* Reserved */
2308 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2309 #endif
2310 #ifdef EMLXS_LITTLE_ENDIAN
2311 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2312 uint32_t rsvd6:16; /* Reserved */
2313 #endif
2314 } CONFIG_PORT_VAR;
2315
2316 /* Structure for MB Command REQUEST_FEATURES (0x9D) */
2317 /* Good for SLI4 only */
2318
2319 typedef struct
2320 {
2321 #ifdef EMLXS_BIG_ENDIAN
2322 uint32_t rsvd1:31;
2323 uint32_t QueryMode:1;
2324 #endif
2325 #ifdef EMLXS_LITTLE_ENDIAN
2326 uint32_t QueryMode:1;
2327 uint32_t rsvd1:31;
2328 #endif
2329
2330 uint32_t featuresRequested;
2331 uint32_t featuresEnabled;
2332
2333 } REQUEST_FEATURES_VAR;
2334
2335 #define SLI4_FEATURE_INHIBIT_AUTO_ABTS 0x0001
2336 #define SLI4_FEATURE_NPIV 0x0002
2337 #define SLI4_FEATURE_DIF 0x0004
2338 #define SLI4_FEATURE_VIRTUAL_FABRICS 0x0008
2339 #define SLI4_FEATURE_FCP_INITIATOR 0x0010
2340 #define SLI4_FEATURE_FCP_TARGET 0x0020
2341 #define SLI4_FEATURE_FCP_COMBO 0x0040
2342 #define SLI4_FEATURE_RSVD1 0x0080
2343 #define SLI4_FEATURE_RQD 0x0100
2344 #define SLI4_FEATURE_INHIBIT_AUTO_ABTS_R 0x0200
2345 #define SLI4_FEATURE_HIGH_LOGIN_MODE 0x0400
2346 #define SLI4_FEATURE_PERF_HINT 0x0800
2347
2348
2349 /* SLI-2 Port Control Block */
2350
2351 /* SLIM POINTER */
2352 #define SLIMOFF 0x30 /* WORD */
2353
2354 typedef struct _SLI2_RDSC
2355 {
2356 uint32_t cmdEntries;
2357 uint32_t cmdAddrLow;
2358 uint32_t cmdAddrHigh;
2359
2360 uint32_t rspEntries;
2361 uint32_t rspAddrLow;
2362 uint32_t rspAddrHigh;
2363 } SLI2_RDSC;
2364
2365 typedef struct _PCB
2366 {
2367 #ifdef EMLXS_BIG_ENDIAN
2368 uint32_t type:8;
2369 #define TYPE_NATIVE_SLI2 0x01;
2370 uint32_t feature:8;
2371 #define FEATURE_INITIAL_SLI2 0x01;
2372 uint32_t rsvd:12;
2373 uint32_t maxRing:4;
2374 #endif
2375 #ifdef EMLXS_LITTLE_ENDIAN
2376 uint32_t maxRing:4;
2377 uint32_t rsvd:12;
2378 uint32_t feature:8;
2379 #define FEATURE_INITIAL_SLI2 0x01;
2380 uint32_t type:8;
2381 #define TYPE_NATIVE_SLI2 0x01;
2382 #endif
2383
2384 uint32_t mailBoxSize;
2385 uint32_t mbAddrLow;
2386 uint32_t mbAddrHigh;
2387
2388 uint32_t hgpAddrLow;
2389 uint32_t hgpAddrHigh;
2390
2391 uint32_t pgpAddrLow;
2392 uint32_t pgpAddrHigh;
2393 SLI2_RDSC rdsc[MAX_RINGS_AVAILABLE];
2394 } PCB;
2395
2396 /* NEW_FEATURE */
2397 typedef struct
2398 {
2399 #ifdef EMLXS_BIG_ENDIAN
2400 uint32_t rsvd0:27;
2401 uint32_t discardFarp:1;
2402 uint32_t IPEnable:1;
2403 uint32_t nodeName:1;
2404 uint32_t portName:1;
2405 uint32_t filterEnable:1;
2406 #endif
2407 #ifdef EMLXS_LITTLE_ENDIAN
2408 uint32_t filterEnable:1;
2409 uint32_t portName:1;
2410 uint32_t nodeName:1;
2411 uint32_t IPEnable:1;
2412 uint32_t discardFarp:1;
2413 uint32_t rsvd:27;
2414 #endif
2415 NAME_TYPE portname;
2416 NAME_TYPE nodename;
2417 uint32_t rsvd1;
2418 uint32_t rsvd2;
2419 uint32_t rsvd3;
2420 uint32_t IPAddress;
2421 } CONFIG_FARP_VAR;
2422
2423
2424 /* NEW_FEATURE */
2425 typedef struct
2426 {
2427 #ifdef EMLXS_BIG_ENDIAN
2428 uint32_t defaultMessageNumber:16;
2429 uint32_t rsvd1:3;
2430 uint32_t nid:5;
2431 uint32_t rsvd2:5;
2432 uint32_t defaultPresent:1;
2433 uint32_t addAssociations:1;
2434 uint32_t reportAssociations:1;
2435 #endif
2436 #ifdef EMLXS_LITTLE_ENDIAN
2437 uint32_t reportAssociations:1;
2438 uint32_t addAssociations:1;
2439 uint32_t defaultPresent:1;
2440 uint32_t rsvd2:5;
2441 uint32_t nid:5;
2442 uint32_t rsvd1:3;
2443 uint32_t defaultMessageNumber:16;
2444 #endif
2445 uint32_t attConditions;
2446 uint8_t attentionId[16];
2447 uint16_t messageNumberByHA[32];
2448 uint16_t messageNumberByID[16];
2449 uint32_t rsvd3;
2450 } CONFIG_MSI_VAR;
2451
2452
2453 /* NEW_FEATURE */
2454 typedef struct
2455 {
2456 #ifdef EMLXS_BIG_ENDIAN
2457 uint32_t defaultMessageNumber:8;
2458 uint32_t rsvd1:11;
2459 uint32_t nid:5;
2460 uint32_t rsvd2:5;
2461 uint32_t defaultPresent:1;
2462 uint32_t addAssociations:1;
2463 uint32_t reportAssociations:1;
2464 #endif
2465 #ifdef EMLXS_LITTLE_ENDIAN
2466 uint32_t reportAssociations:1;
2467 uint32_t addAssociations:1;
2468 uint32_t defaultPresent:1;
2469 uint32_t rsvd2:5;
2470 uint32_t nid:5;
2471 uint32_t rsvd1:11;
2472 uint32_t defaultMessageNumber:8;
2473 #endif
2474 uint32_t attConditions1;
2475 uint32_t attConditions2;
2476 uint8_t attentionId[16];
2477 uint8_t messageNumberByHA[64];
2478 uint8_t messageNumberByID[16];
2479 uint32_t autoClearByHA1;
2480 uint32_t autoClearByHA2;
2481 uint32_t autoClearByID;
2482 uint32_t resv3;
2483 } CONFIG_MSIX_VAR;
2484
2485
2486 /* Union of all Mailbox Command types */
2487
2488 typedef union
2489 {
2490 uint32_t varWords[31];
2491 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2492 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2493 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2494 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2495 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2496 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2497 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2498 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2499 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2500 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2501 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2502 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2503 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2504 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2505 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2506 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2507 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2508 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2509 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2510 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2511 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2512 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2513 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2514 UPDATE_CFG_VAR varUpdateCfg; /* cmd = 0x1b Warm Start */
2515 /* UPDATE_CFG cmd */
2516 DEL_LD_ENTRY_VAR varDelLdEntry; /* cmd = 0x1d (DEL_LD_ENTRY) */
2517 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2518 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) */
2519 CONFIG_MSI_VAR varCfgMSI; /* cmd = 0x90 (CONFIG_MSI) */
2520 CONFIG_MSIX_VAR varCfgMSIX; /* cmd = 0x30 (CONFIG_MSIX) */
2521 CONFIG_HBQ_VAR varCfgHbq; /* cmd = 0x7C (CONFIG_HBQ) */
2522 LOAD_AREA_VAR varLdArea; /* cmd = 0x81 (LOAD_AREA) */
2523 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2524 LOAD_EXP_ROM_VAR varLdExpRom; /* cmd = 0x9C (LOAD_XP_ROM) */
2525 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2526 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
2527 READ_EVT_LOG_VAR varRdEvtLog; /* cmd = 0x38 (READ_EVT_LOG) */
2528 LOG_STATUS_VAR varLogStat; /* cmd = 0x37 */
2529
2530 } MAILVARIANTS;
2531
2532 #define MAILBOX_CMD_BSIZE 128
2533 #define MAILBOX_CMD_WSIZE 32
2534
2535 /*
2536 * SLI-2 specific structures
2537 */
2538
2539 typedef struct _SLI1_DESC
2540 {
2541 emlxs_rings_t mbxCring[4];
2542 uint32_t mbxUnused[24];
2543 } SLI1_DESC; /* 128 bytes */
2544
2545 typedef struct
2546 {
2547 uint32_t cmdPutInx;
2548 uint32_t rspGetInx;
2549 } HGP;
2550
2551 typedef struct
2552 {
2553 uint32_t cmdGetInx;
2554 uint32_t rspPutInx;
2555 } PGP;
2556
2557 typedef struct _SLI2_DESC
2558 {
2559 HGP host[4];
2560 PGP port[4];
2561 uint32_t HBQ_PortGetIdx[16];
2562 } SLI2_DESC; /* 128 bytes */
2563
2564 typedef union
2565 {
2566 SLI1_DESC s1; /* 32 words, 128 bytes */
2567 SLI2_DESC s2; /* 32 words, 128 bytes */
2568 } SLI_VAR;
2569
2570 typedef volatile struct
2571 {
2572 #ifdef EMLXS_BIG_ENDIAN
2573 uint16_t mbxStatus;
2574 uint8_t mbxCommand;
2575 uint8_t mbxReserved:6;
2576 uint8_t mbxHc:1;
2577 uint8_t mbxOwner:1; /* Low order bit first word */
2578 #endif
2579 #ifdef EMLXS_LITTLE_ENDIAN
2580 uint8_t mbxOwner:1; /* Low order bit first word */
2581 uint8_t mbxHc:1;
2582 uint8_t mbxReserved:6;
2583 uint8_t mbxCommand;
2584 uint16_t mbxStatus;
2585 #endif
2586 MAILVARIANTS un; /* 124 bytes */
2587 SLI_VAR us; /* 128 bytes */
2588 } MAILBOX; /* 256 bytes */
2589
2590
2591
2592 /* SLI4 IOCTL Mailbox */
2593 /* ALL SLI4 specific mbox commands have a standard request /response header */
2594 /* Word 0 is just like SLI 3 */
2595
2596 typedef struct mbox_req_hdr
2597 {
2598 #ifdef EMLXS_BIG_ENDIAN
2599 uint32_t domain:8; /* word 6 */
2600 uint32_t port:8;
2601 uint32_t subsystem:8;
2602 uint32_t opcode:8;
2603
2604 uint32_t timeout; /* word 7 */
2605
2606 uint32_t req_length; /* word 8 */
2607
2608 uint32_t reserved1:24; /* word 9 */
2609 uint32_t version:8; /* word 9 */
2610 #endif
2611 #ifdef EMLXS_LITTLE_ENDIAN
2612 uint32_t opcode:8;
2613 uint32_t subsystem:8;
2614 uint32_t port:8;
2615 uint32_t domain:8; /* word 6 */
2616
2617 uint32_t timeout; /* word 7 */
2618
2619 uint32_t req_length; /* word 8 */
2620
2621 uint32_t version:8; /* word 9 */
2622 uint32_t reserved1:24; /* word 9 */
2623 #endif
2624
2625 } mbox_req_hdr_t;
2626
2627
2628 typedef struct mbox_req_hdr2
2629 {
2630 #ifdef EMLXS_BIG_ENDIAN
2631 uint32_t vf_number:16; /* word 6 */
2632 uint32_t subsystem:8;
2633 uint32_t opcode:8;
2634
2635 uint32_t timeout; /* word 7 */
2636
2637 uint32_t req_length; /* word 8 */
2638
2639 uint32_t vh_number:6; /* word 9 */
2640 uint32_t pf_number:10;
2641 uint32_t reserved1:8;
2642 uint32_t version:8;
2643 #endif
2644 #ifdef EMLXS_LITTLE_ENDIAN
2645 uint32_t opcode:8;
2646 uint32_t subsystem:8;
2647 uint32_t vf_number:16; /* word 6 */
2648
2649 uint32_t timeout; /* word 7 */
2650
2651 uint32_t req_length; /* word 8 */
2652
2653 uint32_t version:8;
2654 uint32_t reserved1:8;
2655 uint32_t pf_number:10;
2656 uint32_t vh_number:6; /* word 9 */
2657 #endif
2658
2659 } mbox_req_hdr2_t;
2660
2661 typedef struct mbox_rsp_hdr
2662 {
2663 #ifdef EMLXS_BIG_ENDIAN
2664 uint32_t domain:8; /* word 6 */
2665 uint32_t reserved1:8;
2666 uint32_t subsystem:8;
2667 uint32_t opcode:8;
2668
2669 uint32_t reserved2:16; /* word 7 */
2670 uint32_t extra_status:8;
2671 uint32_t status:8;
2672 #endif
2673 #ifdef EMLXS_LITTLE_ENDIAN
2674 uint32_t opcode:8;
2675 uint32_t subsystem:8;
2676 uint32_t reserved1:8;
2677 uint32_t domain:8; /* word 6 */
2678
2679 uint32_t status:8;
2680 uint32_t extra_status:8;
2681 uint32_t reserved2:16; /* word 7 */
2682 #endif
2683 uint32_t rsp_length; /* word 8 */
2684 uint32_t allocated_length; /* word 9 */
2685 } mbox_rsp_hdr_t;
2686
2687 #define MBX_RSP_STATUS_SUCCESS 0x00
2688 #define MBX_RSP_STATUS_FAILED 0x01
2689 #define MBX_RSP_STATUS_ILLEGAL_REQ 0x02
2690 #define MBX_RSP_STATUS_ILLEGAL_FIELD 0x03
2691 #define MBX_RSP_STATUS_FCF_IN_USE 0x3A
2692 #define MBX_RSP_STATUS_NO_FCF 0x43
2693
2694 #define MGMT_ADDI_STATUS_INCOMPATIBLE 0xA2
2695
2696 typedef struct be_req_hdr
2697 {
2698 #ifdef EMLXS_BIG_ENDIAN
2699 uint32_t special:8; /* word 1 */
2700 uint32_t reserved2:16; /* word 1 */
2701 uint32_t sge_cnt:5; /* word 1 */
2702 uint32_t reserved1:2; /* word 1 */
2703 uint32_t embedded:1; /* word 1 */
2704 #endif
2705 #ifdef EMLXS_LITTLE_ENDIAN
2706 uint32_t embedded:1; /* word 1 */
2707 uint32_t reserved1:2; /* word 1 */
2708 uint32_t sge_cnt:5; /* word 1 */
2709 uint32_t reserved2:16; /* word 1 */
2710 uint32_t special:8; /* word 1 */
2711 #endif
2712 uint32_t payload_length; /* word 2 */
2713 uint32_t tag_low; /* word 3 */
2714 uint32_t tag_hi; /* word 4 */
2715 uint32_t reserved3; /* word 5 */
2716 union
2717 {
2718 mbox_req_hdr_t hdr_req;
2719 mbox_req_hdr2_t hdr_req2;
2720 mbox_rsp_hdr_t hdr_rsp;
2721 } un_hdr;
2722 } be_req_hdr_t;
2723
2724 #define EMLXS_MAX_NONEMBED_SIZE (1024 * 64)
2725
2726 /* SLI_CONFIG Mailbox commands */
2727
2728 #define IOCTL_SUBSYSTEM_COMMON 0x01
2729 #define IOCTL_SUBSYSTEM_LOWLEVEL 0x0B
2730 #define IOCTL_SUBSYSTEM_FCOE 0x0C
2731 #define IOCTL_SUBSYSTEM_DCBX 0x10
2732
2733 #define COMMON_OPCODE_READ_FLASHROM 0x06
2734 #define COMMON_OPCODE_WRITE_FLASHROM 0x07
2735 #define COMMON_OPCODE_CQ_CREATE 0x0C
2736 #define COMMON_OPCODE_EQ_CREATE 0x0D
2737 #define COMMON_OPCODE_MQ_CREATE 0x15
2738 #define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20
2739 #define COMMON_OPCODE_NOP 0x21
2740 #define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A
2741 #define COMMON_OPCODE_RESET 0x3D
2742 #define COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1 0x3E
2743
2744 #define COMMON_OPCODE_GET_BOOT_CFG 0x42
2745 #define COMMON_OPCODE_SET_BOOT_CFG 0x43
2746 #define COMMON_OPCODE_MANAGE_FAT 0x44
2747 #define COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1 0x47
2748 #define COMMON_OPCODE_GET_PORT_NAME 0x4D
2749
2750 #define COMMON_OPCODE_MQ_CREATE_EXT 0x5A
2751 #define COMMON_OPCODE_GET_VPD_DATA 0x5B
2752 #define COMMON_OPCODE_GET_PHY_DETAILS 0x66
2753 #define COMMON_OPCODE_SEND_ACTIVATION 0x73
2754 #define COMMON_OPCODE_RESET_LICENSES 0x74
2755 #define COMMON_OPCODE_GET_CNTL_ADDL_ATTRIB 0x79
2756
2757 #define COMMON_OPCODE_GET_EXTENTS_INFO 0x9A
2758 #define COMMON_OPCODE_GET_EXTENTS 0x9B
2759 #define COMMON_OPCODE_ALLOC_EXTENTS 0x9C
2760 #define COMMON_OPCODE_DEALLOC_EXTENTS 0x9D
2761
2762 #define COMMON_OPCODE_GET_PROFILE_CAPS 0xA1
2763 #define COMMON_OPCODE_GET_MR_PROFILE_CAPS 0xA2
2764 #define COMMON_OPCODE_SET_MR_PROFILE_CAPS 0xA3
2765 #define COMMON_OPCODE_GET_PROFILE_CFG 0xA4
2766 #define COMMON_OPCODE_SET_PROFILE_CFG 0xA5
2767 #define COMMON_OPCODE_GET_PROFILE_LIST 0xA6
2768 #define COMMON_OPCODE_GET_ACTIVE_PROFILE 0xA7
2769 #define COMMON_OPCODE_SET_ACTIVE_PROFILE 0xA8
2770 #define COMMON_OPCODE_SET_FACTORY_PROFILE_CFG 0xA9
2771
2772 #define COMMON_OPCODE_READ_OBJ 0xAB
2773 #define COMMON_OPCODE_WRITE_OBJ 0xAC
2774 #define COMMON_OPCODE_READ_OBJ_LIST 0xAD
2775 #define COMMON_OPCODE_DELETE_OBJ 0xAE
2776 #define COMMON_OPCODE_GET_SLI4_PARAMS 0xB5
2777
2778 #define LOWLEVEL_OPCODE_GPIO_RDWR 0x30
2779
2780 #define FCOE_OPCODE_WQ_CREATE 0x01
2781 #define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03
2782 #define FCOE_OPCODE_RQ_CREATE 0x05
2783 #define FCOE_OPCODE_READ_FCF_TABLE 0x08
2784 #define FCOE_OPCODE_ADD_FCF_TABLE 0x09
2785 #define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A
2786 #define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B
2787 #define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10
2788 #define FCOE_OPCODE_SET_FCLINK_SETTINGS 0x21
2789
2790 #define DCBX_OPCODE_GET_DCBX_MODE 0x04
2791 #define DCBX_OPCODE_SET_DCBX_MODE 0x05
2792
2793 typedef struct
2794 {
2795 struct
2796 {
2797 uint32_t opcode;
2798 #define MGMT_FLASHROM_OPCODE_FLASH 1
2799 #define MGMT_FLASHROM_OPCODE_SAVE 2
2800 #define MGMT_FLASHROM_OPCODE_CLEAR 3
2801 #define MGMT_FLASHROM_OPCODE_REPORT 4
2802 #define MGMT_FLASHROM_OPCODE_INFO 5
2803 #define MGMT_FLASHROM_OPCODE_CRC 6
2804 #define MGMT_FLASHROM_OPCODE_OFFSET_FLASH 7
2805 #define MGMT_FLASHROM_OPCODE_OFFSET_SAVE 8
2806 #define MGMT_PHY_FLASHROM_OPCODE_FLASH 9
2807 #define MGMT_PHY_FLASHROM_OPCODE_SAVE 10
2808
2809 uint32_t optype;
2810 #define MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE 0
2811 #define MGMT_FLASHROM_OPTYPE_REDBOOT 1
2812 #define MGMT_FLASHROM_OPTYPE_ISCSI_BIOS 2
2813 #define MGMT_FLASHROM_OPTYPE_PXE_BIOS 3
2814 #define MGMT_FLASHROM_OPTYPE_CTRLS 4
2815 #define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 5
2816 #define MGMT_FLASHROM_OPTYPE_CFG_INI 6
2817 #define MGMT_FLASHROM_OPTYPE_ROM_OFFSET 7
2818 #define MGMT_FLASHROM_OPTYPE_FCOE_BIOS 8
2819 #define MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP 9
2820 #define MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE 10
2821 #define MGMT_FLASHROM_OPTYPE_FCOE_BACKUP 11
2822 #define MGMT_FLASHROM_OPTYPE_CTRLP 12
2823 #define MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE 13
2824 #define MGMT_FLASHROM_OPTYPE_CFG_NIC 14
2825 #define MGMT_FLASHROM_OPTYPE_CFG_DCBX 15
2826 #define MGMT_FLASHROM_OPTYPE_CFG_PXE_BIOS 16
2827 #define MGMT_FLASHROM_OPTYPE_CFG_ALL 17
2828 #define MGMT_FLASHROM_OPTYPE_PHY_FIRMWARE 0xff /* Driver defined */
2829
2830 uint32_t data_buffer_size; /* Align to 4KB */
2831 uint32_t offset;
2832 uint32_t data_buffer; /* image starts here */
2833
2834 } params;
2835
2836 } IOCTL_COMMON_FLASHROM;
2837
2838
2839 typedef struct
2840 {
2841 union
2842 {
2843 struct
2844 {
2845 uint32_t rsvd;
2846 } request;
2847
2848
2849 struct
2850 {
2851 #ifdef EMLXS_BIG_ENDIAN
2852 uint16_t interface_type;
2853 uint16_t phy_type;
2854 #endif
2855 #ifdef EMLXS_LITTLE_ENDIAN
2856 uint16_t phy_type;
2857 uint16_t interface_type;
2858 #endif
2859
2860 /* phy_type */
2861 #define PHY_XAUI 0x0
2862 #define PHY_AEL_2020 0x1 /* eluris/Netlogic */
2863 #define PHY_LSI_BRCM1 0x2 /* Peak pre-production board */
2864 #define PHY_LSI_BRCM2 0x3 /* Peak production board */
2865 #define PHY_SOLARFLARE 0x4 /* Dell recommended */
2866 #define PHY_AMCC_QT2025 0x5 /* AMCC PHY */
2867 #define PHY_AMCC_QT2225 0x6 /* AMCC PHY */
2868 #define PHY_BRCM_5931 0x7 /* Broadcom Phy used by HP LOM */
2869 #define PHY_BE3_INTERNAL_10GB 0x8 /* Internal 10GbPHY in BE3 */
2870 #define PHY_BE3_INTERNAL_1GB 0x9 /* Internal 1Gb PHY in BE3 */
2871 #define PHY_TN_2022 0xa /* Teranetics dual port 65nm PHY */
2872 #define PHY_MARVELL_88E1340 0xb /* Marvel 1G PHY */
2873 #define PHY_MARVELL_88E1322 0xc /* Marvel 1G PHY */
2874 #define PHY_TN_8022 0xd /* Teranetics dual port 40nm PHY */
2875 #define PHY_TYPE_NOT_SUPPORTED
2876
2877 /* interface_type */
2878 #define CX4_10GB_TYPE 0x0
2879 #define XFP_10GB_TYPE 0x1
2880 #define SFP_1GB_TYPE 0x2
2881 #define SFP_PLUS_10GB_TYPE 0x3
2882 #define KR_10GB_TYPE 0x4
2883 #define KX4_10GB_TYPE 0x5
2884 #define BASET_10GB_TYPE 0x6 /* 10G BaseT */
2885 #define BASET_1000_TYPE 0x7 /* 1000 BaseT */
2886 #define BASEX_1000_TYPE 0x8 /* 1000 BaseX */
2887 #define SGMII_TYPE 0x9
2888 #define INTERFACE_10GB_DISABLED 0xff /* Interface type not supported */
2889
2890 uint32_t misc_params;
2891 uint32_t rsvd[4];
2892 } response;
2893
2894 } params;
2895
2896 } IOCTL_COMMON_GET_PHY_DETAILS;
2897
2898
2899 typedef struct
2900 {
2901 union
2902 {
2903 struct
2904 {
2905 uint32_t rsvd;
2906 } request;
2907
2908
2909 struct
2910 {
2911 #ifdef EMLXS_BIG_ENDIAN
2912 uint8_t port3_name;
2913 uint8_t port2_name;
2914 uint8_t port1_name;
2915 uint8_t port0_name;
2916 #endif
2917 #ifdef EMLXS_LITTLE_ENDIAN
2918 uint8_t port0_name;
2919 uint8_t port1_name;
2920 uint8_t port2_name;
2921 uint8_t port3_name;
2922 #endif
2923 } response;
2924
2925 } params;
2926
2927 } IOCTL_COMMON_GET_PORT_NAME;
2928
2929
2930 typedef struct
2931 {
2932 union
2933 {
2934 struct
2935 {
2936 #ifdef EMLXS_BIG_ENDIAN
2937 uint32_t rsvd:30;
2938 uint32_t pt:2;
2939 #endif
2940 #ifdef EMLXS_LITTLE_ENDIAN
2941 uint32_t pt:2;
2942 uint32_t rsvd:30;
2943 #endif
2944 #define PORT_TYPE_GIGE 0
2945 #define PORT_TYPE_FC 1
2946 } request;
2947
2948
2949 struct
2950 {
2951 #ifdef EMLXS_BIG_ENDIAN
2952 uint8_t port3_name;
2953 uint8_t port2_name;
2954 uint8_t port1_name;
2955 uint8_t port0_name;
2956 #endif
2957 #ifdef EMLXS_LITTLE_ENDIAN
2958 uint8_t port0_name;
2959 uint8_t port1_name;
2960 uint8_t port2_name;
2961 uint8_t port3_name;
2962 #endif
2963 } response;
2964
2965 } params;
2966
2967 } IOCTL_COMMON_GET_PORT_NAME_V1;
2968
2969
2970 typedef struct
2971 {
2972 union
2973 {
2974 struct
2975 {
2976 uint32_t fat_operation;
2977 #define RETRIEVE_FAT 0
2978 #define QUERY_FAT 1
2979 #define CLEAR_FAT 2
2980
2981 uint32_t read_log_offset;
2982 uint32_t read_log_length;
2983 uint32_t data_buffer_size;
2984 uint32_t data_buffer;
2985 } request;
2986
2987 struct
2988 {
2989 uint32_t log_size;
2990 uint32_t read_log_length;
2991 uint32_t rsvd0;
2992 uint32_t rsvd1;
2993 uint32_t data_buffer;
2994 } response;
2995
2996 } params;
2997
2998 } IOCTL_COMMON_MANAGE_FAT;
2999
3000
3001 typedef struct
3002 {
3003 union
3004 {
3005 struct
3006 {
3007 #ifdef EMLXS_BIG_ENDIAN
3008 uint32_t EOF:1; /* word 4 */
3009 uint32_t rsvd0:7;
3010 uint32_t desired_write_length:24;
3011 #endif
3012 #ifdef EMLXS_LITTLE_ENDIAN
3013 uint32_t desired_write_length:24;
3014 uint32_t rsvd0:7;
3015 uint32_t EOF:1; /* word 4 */
3016 #endif
3017 uint32_t write_offset; /* word 5 */
3018 char object_name[(4 * 26)]; /* word 6 - 31 */
3019 uint32_t buffer_desc_count; /* word 32 */
3020
3021 #ifdef EMLXS_BIG_ENDIAN
3022 uint32_t rsvd:8; /* word 33 */
3023 uint32_t buffer_length:24;
3024 #endif
3025 #ifdef EMLXS_LITTLE_ENDIAN
3026 uint32_t buffer_length:24;
3027 uint32_t rsvd:8; /* word 33 */
3028 #endif
3029 uint32_t buffer_addrlo; /* word 34 */
3030 uint32_t buffer_addrhi; /* word 35 */
3031 } request;
3032
3033 struct
3034 {
3035 uint32_t actual_write_length;
3036
3037 #ifdef EMLXS_BIG_ENDIAN
3038 uint32_t rsvd:24;
3039 uint32_t change_status:8;
3040 #endif
3041 #ifdef EMLXS_LITTLE_ENDIAN
3042 uint32_t change_status:8;
3043 uint32_t rsvd:24;
3044 #endif
3045 #define CS_NO_RESET 0
3046 #define CS_REBOOT_RQD 1
3047 #define CS_FW_RESET_RQD 2
3048 #define CS_PROTO_RESET_RQD 3
3049 } response;
3050
3051 } params;
3052
3053 } IOCTL_COMMON_WRITE_OBJECT;
3054
3055
3056 typedef struct
3057 {
3058 union
3059 {
3060 struct
3061 {
3062 #ifdef EMLXS_BIG_ENDIAN
3063 uint32_t descriptor_offset:16; /* word 4 */
3064 uint32_t descriptor_count:16;
3065 #endif
3066 #ifdef EMLXS_LITTLE_ENDIAN
3067 uint32_t descriptor_count:16;
3068 uint32_t descriptor_offset:16; /* word 4 */
3069 #endif
3070 uint32_t reserved; /* word 5 */
3071 char object_name[(4 * 26)]; /* word 6 - 31 */
3072 uint32_t buffer_desc_count; /* word 32 */
3073
3074 #ifdef EMLXS_BIG_ENDIAN
3075 uint32_t rsvd:8; /* word 33 */
3076 uint32_t buffer_length:24;
3077 #endif
3078 #ifdef EMLXS_LITTLE_ENDIAN
3079 uint32_t buffer_length:24;
3080 uint32_t rsvd:8; /* word 33 */
3081 #endif
3082 uint32_t buffer_addrlo; /* word 34 */
3083 uint32_t buffer_addrhi; /* word 35 */
3084 } request;
3085
3086 struct
3087 {
3088 #ifdef EMLXS_BIG_ENDIAN
3089 uint32_t reserved:16;
3090 uint32_t actual_descriptor_count:16;
3091 #endif
3092 #ifdef EMLXS_LITTLE_ENDIAN
3093 uint32_t actual_descriptor_count:16;
3094 uint32_t reserved:16;
3095 #endif
3096 } response;
3097
3098 } params;
3099
3100 } IOCTL_COMMON_READ_OBJECT_LIST;
3101
3102
3103 typedef struct
3104 {
3105 union
3106 {
3107 struct
3108 {
3109 #ifdef EMLXS_BIG_ENDIAN
3110 uint32_t reserved:16; /* word 4 */
3111 uint32_t boot_instance:8;
3112 uint32_t boot_status:8;
3113 #endif
3114 #ifdef EMLXS_LITTLE_ENDIAN
3115 uint32_t boot_status:8;
3116 uint32_t boot_instance:8;
3117 uint32_t reserved:16; /* word 4 */
3118 #endif
3119 } request;
3120
3121 struct
3122 {
3123 #ifdef EMLXS_BIG_ENDIAN
3124 uint32_t reserved:16; /* word 4 */
3125 uint32_t boot_instance:8;
3126 uint32_t boot_status:8;
3127 #endif
3128 #ifdef EMLXS_LITTLE_ENDIAN
3129 uint32_t boot_status:8;
3130 uint32_t boot_instance:8;
3131 uint32_t reserved:16; /* word 4 */
3132 #endif
3133 } response;
3134
3135 } params;
3136
3137 } IOCTL_COMMON_BOOT_CFG;
3138
3139
3140 /* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
3141 typedef struct _BE_FW_CFG
3142 {
3143 uint32_t BEConfigNumber;
3144 uint32_t ASICRevision;
3145 uint32_t PhysicalPort;
3146 uint32_t FunctionMode;
3147 uint32_t ULPMode;
3148
3149 } BE_FW_CFG;
3150
3151 typedef struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
3152 {
3153 union
3154 {
3155 struct
3156 {
3157 uint32_t rsvd0;
3158 } request;
3159
3160 BE_FW_CFG response;
3161
3162 } params;
3163
3164 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
3165
3166 /* IOCTL_LOWLEVEL_GPIO_RDWR */
3167 typedef struct _IOCTL_LOWLEVEL_GPIO_RDWR
3168 {
3169 union
3170 {
3171 struct
3172 {
3173 uint32_t GpioAction;
3174 #define LOWLEVEL_GPIO_ACT_READ 0
3175 #define LOWLEVEL_GPIO_ACT_WRITE 1
3176 #define LOWLEVEL_GPIO_ACT_RDSENSE 2
3177 #define LOWLEVEL_GPIO_ACT_STSENSE 3
3178
3179 uint32_t LogicalPin;
3180 uint32_t PinValue;
3181 #define LOWLEVEL_GPIO_STSENSE_IN 0
3182 #define LOWLEVEL_GPIO_STSENSE_OUT 1
3183
3184 uint32_t OutputValue;
3185 } request;
3186
3187 struct
3188 {
3189 uint32_t PinValue;
3190 } response;
3191 } params;
3192 } IOCTL_LOWLEVEL_GPIO_RDWR;
3193
3194 /* IOCTL_FCOE_READ_FCF_TABLE */
3195 typedef struct
3196 {
3197 uint32_t max_recv_size;
3198 uint32_t fka_adv_period;
3199 uint32_t fip_priority;
3200
3201 #ifdef EMLXS_BIG_ENDIAN
3202 uint8_t fcf_mac_address_hi[4];
3203
3204 uint8_t mac_address_provider;
3205 uint8_t fcf_available;
3206 uint8_t fcf_mac_address_low[2];
3207
3208 uint8_t fabric_name_identifier[8];
3209
3210 uint8_t fcf_sol:1;
3211 uint8_t rsvd0:5;
3212 uint8_t fcf_fc:1;
3213 uint8_t fcf_valid:1;
3214 uint8_t fc_map[3];
3215
3216 uint16_t fcf_state;
3217 uint16_t fcf_index;
3218 #endif
3219 #ifdef EMLXS_LITTLE_ENDIAN
3220 uint8_t fcf_mac_address_hi[4];
3221
3222 uint8_t fcf_mac_address_low[2];
3223 uint8_t fcf_available;
3224 uint8_t mac_address_provider;
3225
3226 uint8_t fabric_name_identifier[8];
3227
3228 uint8_t fc_map[3];
3229 uint8_t fcf_valid:1;
3230 uint8_t fcf_fc:1;
3231 uint8_t rsvd0:5;
3232 uint8_t fcf_sol:1;
3233
3234 uint16_t fcf_index;
3235 uint16_t fcf_state;
3236 #endif
3237
3238 uint8_t vlan_bitmap[512];
3239 uint8_t switch_name_identifier[8];
3240
3241 } FCF_RECORD_t;
3242
3243 #define EMLXS_FCOE_MAX_RCV_SZ 0x800
3244
3245 /* defines for mac_address_provider */
3246 #define EMLXS_MAM_BOTH 0 /* Both SPMA and FPMA */
3247 #define EMLXS_MAM_FPMA 1 /* Fabric Provided MAC Address */
3248 #define EMLXS_MAM_SPMA 2 /* Server Provided MAC Address */
3249
3250 typedef struct
3251 {
3252 union
3253 {
3254 struct
3255 {
3256 #ifdef EMLXS_BIG_ENDIAN
3257 uint16_t rsvd0;
3258 uint16_t fcf_index;
3259 #endif
3260 #ifdef EMLXS_LITTLE_ENDIAN
3261 uint16_t fcf_index;
3262 uint16_t rsvd0;
3263 #endif
3264
3265 } request;
3266
3267 struct
3268 {
3269 uint32_t event_tag;
3270 #ifdef EMLXS_BIG_ENDIAN
3271 uint16_t rsvd0;
3272 uint16_t next_valid_fcf_index;
3273 #endif
3274 #ifdef EMLXS_LITTLE_ENDIAN
3275 uint16_t next_valid_fcf_index;
3276 uint16_t rsvd0;
3277 #endif
3278 FCF_RECORD_t fcf_entry[1];
3279
3280 } response;
3281
3282 } params;
3283
3284 } IOCTL_FCOE_READ_FCF_TABLE;
3285
3286
3287 /* IOCTL_FCOE_ADD_FCF_TABLE */
3288 typedef struct
3289 {
3290 union
3291 {
3292 struct
3293 {
3294 #ifdef EMLXS_BIG_ENDIAN
3295 uint16_t rsvd0;
3296 uint16_t fcf_index;
3297 #endif
3298 #ifdef EMLXS_LITTLE_ENDIAN
3299 uint16_t fcf_index;
3300 uint16_t rsvd0;
3301 #endif
3302 FCF_RECORD_t fcf_entry;
3303
3304 } request;
3305 } params;
3306
3307 } IOCTL_FCOE_ADD_FCF_TABLE;
3308
3309
3310 /* IOCTL_FCOE_DELETE_FCF_TABLE */
3311 typedef struct
3312 {
3313 union
3314 {
3315 struct
3316 {
3317 #ifdef EMLXS_BIG_ENDIAN
3318 uint16_t fcf_indexes[1];
3319 uint16_t fcf_count;
3320 #endif
3321 #ifdef EMLXS_LITTLE_ENDIAN
3322 uint16_t fcf_count;
3323 uint16_t fcf_indexes[1];
3324 #endif
3325
3326 } request;
3327 } params;
3328
3329 } IOCTL_FCOE_DELETE_FCF_TABLE;
3330
3331
3332 /* IOCTL_FCOE_REDISCOVER_FCF_TABLE */
3333 typedef struct
3334 {
3335 union
3336 {
3337 struct
3338 {
3339 #ifdef EMLXS_BIG_ENDIAN
3340 uint16_t rsvd0;
3341 uint16_t fcf_count;
3342 #endif
3343 #ifdef EMLXS_LITTLE_ENDIAN
3344 uint16_t fcf_count;
3345 uint16_t rsvd0;
3346 #endif
3347 uint32_t rsvd1;
3348 uint16_t fcf_index[1];
3349
3350 } request;
3351 } params;
3352
3353 } IOCTL_FCOE_REDISCOVER_FCF_TABLE;
3354
3355
3356 #define FCOE_FCF_MAC0 0x0E
3357 #define FCOE_FCF_MAC1 0xFC
3358 #define FCOE_FCF_MAC2 0x00
3359 #define FCOE_FCF_MAC3 0xFF
3360 #define FCOE_FCF_MAC4 0xFF
3361 #define FCOE_FCF_MAC5 0xFE
3362
3363 #define FCOE_FCF_MAP0 0x0E
3364 #define FCOE_FCF_MAP1 0xFC
3365 #define FCOE_FCF_MAP2 0x00
3366
3367 #define MGMT_STATUS_FCF_IN_USE 0x3a
3368
3369 /* IOCTL_COMMON_NOP */
3370 typedef struct _IOCTL_COMMON_NOP
3371 {
3372 union
3373 {
3374 struct
3375 {
3376 uint64_t context;
3377 } request;
3378
3379 struct
3380 {
3381 uint64_t context;
3382 } response;
3383
3384 } params;
3385
3386 } IOCTL_COMMON_NOP;
3387
3388
3389 /* Context for EQ create */
3390 typedef struct _EQ_CONTEXT
3391 {
3392 #ifdef EMLXS_BIG_ENDIAN
3393 uint32_t Size:1;
3394 uint32_t Rsvd2:1;
3395 uint32_t Valid:1;
3396 uint32_t Rsvd1:29;
3397
3398 uint32_t Armed:1;
3399 uint32_t Rsvd4:2;
3400 uint32_t Count:3;
3401 uint32_t Rsvd3:26;
3402
3403 uint32_t Rsvd6:9;
3404 uint32_t DelayMult:10;
3405 uint32_t Rsvd5:13;
3406 #endif
3407 #ifdef EMLXS_LITTLE_ENDIAN
3408 uint32_t Rsvd1:29;
3409 uint32_t Valid:1;
3410 uint32_t Rsvd2:1;
3411 uint32_t Size:1;
3412
3413 uint32_t Rsvd3:26;
3414 uint32_t Count:3;
3415 uint32_t Rsvd4:2;
3416 uint32_t Armed:1;
3417
3418 uint32_t Rsvd5:13;
3419 uint32_t DelayMult:10;
3420 uint32_t Rsvd6:9;
3421 #endif
3422
3423 uint32_t Rsvd7;
3424
3425 } EQ_CONTEXT;
3426
3427
3428 /* define for Count field */
3429 #define EQ_ELEMENT_COUNT_1024 2
3430 #define EQ_ELEMENT_COUNT_2048 3
3431 #define EQ_ELEMENT_COUNT_4096 4
3432
3433 /* define for Size field */
3434 #define EQ_ELEMENT_SIZE_4 0
3435
3436 /* define for DelayMullt - used for interrupt coalescing */
3437 #define EQ_DELAY_MULT 64
3438
3439 /* Context for CQ create */
3440 typedef struct _CQ_CONTEXT
3441 {
3442 #ifdef EMLXS_BIG_ENDIAN
3443 uint32_t Eventable:1;
3444 uint32_t Rsvd3:1;
3445 uint32_t Valid:1;
3446 uint32_t Count:2;
3447 uint32_t Rsvd2:12;
3448 uint32_t NoDelay:1;
3449 uint32_t CoalesceWM:2;
3450 uint32_t Rsvd1:12;
3451
3452 uint32_t Armed:1;
3453 uint32_t Rsvd5:1;
3454 uint32_t EQId:8;
3455 uint32_t Rsvd4:22;
3456
3457 uint32_t Rsvd6;
3458 #endif
3459 #ifdef EMLXS_LITTLE_ENDIAN
3460 uint32_t Rsvd1:12;
3461 uint32_t CoalesceWM:2;
3462 uint32_t NoDelay:1;
3463 uint32_t Rsvd2:12;
3464 uint32_t Count:2;
3465 uint32_t Valid:1;
3466 uint32_t Rsvd3:1;
3467 uint32_t Eventable:1;
3468
3469 uint32_t Rsvd4:22;
3470 uint32_t EQId:8;
3471 uint32_t Rsvd5:1;
3472 uint32_t Armed:1;
3473
3474 uint32_t Rsvd6;
3475 #endif
3476
3477 uint32_t Rsvd7;
3478
3479 } CQ_CONTEXT;
3480
3481 typedef struct _CQ_CONTEXT_V2
3482 {
3483 #ifdef EMLXS_BIG_ENDIAN
3484 uint32_t Eventable:1;
3485 uint32_t Rsvd3:1;
3486 uint32_t Valid:1;
3487 uint32_t CqeCnt:2;
3488 uint32_t CqeSize:2;
3489 uint32_t Rsvd2:9;
3490 uint32_t AutoValid:1;
3491 uint32_t NoDelay:1;
3492 uint32_t CoalesceWM:2;
3493 uint32_t Rsvd1:12;
3494
3495 uint32_t Armed:1;
3496 uint32_t Rsvd4:15;
3497 uint32_t EQId:16;
3498
3499 uint32_t Rsvd5:16;
3500 uint32_t Count1:16;
3501 #endif
3502 #ifdef EMLXS_LITTLE_ENDIAN
3503 uint32_t Rsvd1:12;
3504 uint32_t CoalesceWM:2;
3505 uint32_t NoDelay:1;
3506 uint32_t AutoValid:1;
3507 uint32_t Rsvd2:9;
3508 uint32_t CqeSize:2;
3509 uint32_t CqeCnt:2;
3510 uint32_t Valid:1;
3511 uint32_t Rsvd3:1;
3512 uint32_t Eventable:1;
3513
3514 uint32_t EQId:16;
3515 uint32_t Rsvd4:15;
3516 uint32_t Armed:1;
3517
3518 uint32_t Count1:16;
3519 uint32_t Rsvd5:16;
3520 #endif
3521
3522 uint32_t Rsvd7;
3523
3524 } CQ_CONTEXT_V2;
3525
3526 /* CqeSize */
3527 #define CQE_SIZE_16_BYTES 0
3528 #define CQE_SIZE_32_BYTES 1
3529
3530 /* define for Count field */
3531 #define CQ_ELEMENT_COUNT_256 0
3532 #define CQ_ELEMENT_COUNT_512 1
3533 #define CQ_ELEMENT_COUNT_1024 2
3534 #define CQ_ELEMENT_COUNT_SPECIFIED 3
3535
3536 /* Context for MQ create */
3537 typedef struct _MQ_CONTEXT
3538 {
3539 #ifdef EMLXS_BIG_ENDIAN
3540 uint32_t CQId:10;
3541 uint32_t Rsvd2:2;
3542 uint32_t Size:4;
3543 uint32_t Rsvd1:16;
3544
3545 uint32_t Valid:1;
3546 uint32_t Rsvd3:31;
3547
3548 uint32_t Rsvd4:21;
3549 uint32_t ACQId:10;
3550 uint32_t ACQV:1;
3551 #endif
3552 #ifdef EMLXS_LITTLE_ENDIAN
3553 uint32_t Rsvd1:16;
3554 uint32_t Size:4;
3555 uint32_t Rsvd2:2;
3556 uint32_t CQId:10;
3557
3558 uint32_t Rsvd3:31;
3559 uint32_t Valid:1;
3560
3561 uint32_t ACQV:1;
3562 uint32_t ACQId:10;
3563 uint32_t Rsvd4:21;
3564 #endif
3565
3566 uint32_t Rsvd5;
3567
3568 } MQ_CONTEXT;
3569
3570
3571 typedef struct _MQ_CONTEXT_V1
3572 {
3573 #ifdef EMLXS_BIG_ENDIAN
3574 uint32_t Rsvd2:12;
3575 uint32_t Size:4;
3576 uint32_t ACQId:16;
3577
3578 uint32_t Valid:1;
3579 uint32_t Rsvd3:31;
3580
3581 uint32_t Rsvd4:31;
3582 uint32_t ACQV:1;
3583 #endif
3584 #ifdef EMLXS_LITTLE_ENDIAN
3585 uint32_t ACQId:16;
3586 uint32_t Size:4;
3587 uint32_t Rsvd2:12;
3588
3589 uint32_t Rsvd3:31;
3590 uint32_t Valid:1;
3591
3592 uint32_t ACQV:1;
3593 uint32_t Rsvd4:31;
3594 #endif
3595
3596 uint32_t Rsvd5;
3597
3598 } MQ_CONTEXT_V1;
3599
3600
3601 /* define for Size field */
3602 #define MQ_ELEMENT_COUNT_16 0x05
3603
3604 /* Context for RQ create */
3605 typedef struct _RQ_CONTEXT
3606 {
3607 #ifdef EMLXS_BIG_ENDIAN
3608 uint32_t Rsvd2:12;
3609 uint32_t RqeCnt:4;
3610 uint32_t Rsvd1:16;
3611
3612 uint32_t Rsvd3;
3613
3614 uint32_t CQId:16;
3615 uint32_t BufferSize:16;
3616 #endif
3617 #ifdef EMLXS_LITTLE_ENDIAN
3618 uint32_t Rsvd1:16;
3619 uint32_t RqeCnt:4;
3620 uint32_t Rsvd2:12;
3621
3622 uint32_t Rsvd3;
3623
3624 uint32_t BufferSize:16;
3625 uint32_t CQId:16;
3626 #endif
3627
3628 uint32_t Rsvd5;
3629
3630 } RQ_CONTEXT;
3631
3632 typedef struct _RQ_CONTEXT_V1
3633 {
3634 #ifdef EMLXS_BIG_ENDIAN
3635 uint32_t RqeCnt:16;
3636 uint32_t Rsvd1:4;
3637 uint32_t RqeSize:4;
3638 uint32_t PageSize:8;
3639
3640 uint32_t Rsvd2;
3641
3642 uint32_t CQId:16;
3643 uint32_t Rsvd:16;
3644 #endif
3645 #ifdef EMLXS_LITTLE_ENDIAN
3646 uint32_t PageSize:8;
3647 uint32_t RqeSize:4;
3648 uint32_t Rsvd1:4;
3649 uint32_t RqeCnt:16;
3650
3651 uint32_t Rsvd2;
3652
3653 uint32_t Rsvd:16;
3654 uint32_t CQId:16;
3655 #endif
3656
3657 uint32_t BufferSize;
3658
3659 } RQ_CONTEXT_V1;
3660
3661 /* RqeSize */
3662 #define RQE_SIZE_8_BYTES 0x02
3663 #define RQE_SIZE_16_BYTES 0x03
3664 #define RQE_SIZE_32_BYTES 0x04
3665 #define RQE_SIZE_64_BYTES 0x05
3666 #define RQE_SIZE_128_BYTES 0x06
3667
3668 /* RQ PageSize */
3669 #define RQ_PAGE_SIZE_4K 0x01
3670 #define RQ_PAGE_SIZE_8K 0x02
3671 #define RQ_PAGE_SIZE_16K 0x04
3672 #define RQ_PAGE_SIZE_32K 0x08
3673 #define RQ_PAGE_SIZE_64K 0x10
3674
3675
3676 /* IOCTL_COMMON_EQ_CREATE */
3677 typedef struct
3678 {
3679 union
3680 {
3681 struct
3682 {
3683 #ifdef EMLXS_BIG_ENDIAN
3684 uint16_t Rsvd1;
3685 uint16_t NumPages;
3686 #endif
3687 #ifdef EMLXS_LITTLE_ENDIAN
3688 uint16_t NumPages;
3689 uint16_t Rsvd1;
3690 #endif
3691 EQ_CONTEXT EQContext;
3692 BE_PHYS_ADDR Pages[8];
3693 } request;
3694
3695 struct
3696 {
3697 #ifdef EMLXS_BIG_ENDIAN
3698 uint16_t MsiIndex; /* V1 only */
3699 uint16_t EQId;
3700 #endif
3701 #ifdef EMLXS_LITTLE_ENDIAN
3702 uint16_t EQId;
3703 uint16_t MsiIndex; /* V1 only */
3704 #endif
3705 } response;
3706 } params;
3707
3708 } IOCTL_COMMON_EQ_CREATE;
3709
3710
3711 typedef struct
3712 {
3713 #ifdef EMLXS_BIG_ENDIAN
3714 uint32_t Rsvd1:24; /* Word 0 */
3715 uint32_t ProtocolType:8;
3716
3717 uint32_t Rsvd3:3; /* Word 1 */
3718 uint32_t SliHint2:5;
3719 uint32_t SliHint1:8;
3720 uint32_t IfType:4;
3721 uint32_t SliFamily:4;
3722 uint32_t Revision:4;
3723 uint32_t Rsvd2:3;
3724 uint32_t FT:1;
3725
3726 uint32_t EqRsvd3:4; /* Word 2 */
3727 uint32_t EqeCntMethod:4;
3728 uint32_t EqPageSize:8;
3729 uint32_t EqRsvd2:4;
3730 uint32_t EqeSize:4;
3731 uint32_t EqRsvd1:4;
3732 uint32_t EqPageCnt:4;
3733
3734 uint32_t EqRsvd4:16; /* Word 3 */
3735 uint32_t EqeCntMask:16;
3736
3737 uint32_t CqRsvd3:4; /* Word 4 */
3738 uint32_t CqeCntMethod:4;
3739 uint32_t CqPageSize:8;
3740 uint32_t CQV:2;
3741 uint32_t CqRsvd2:2;
3742 uint32_t CqeSize:4;
3743 uint32_t CqRsvd1:4;
3744 uint32_t CqPageCnt:4;
3745
3746 uint32_t CqRsvd4:16; /* Word 5 */
3747 uint32_t CqeCntMask:16;
3748
3749 uint32_t MqRsvd2:4; /* Word 6 */
3750 uint32_t MqeCntMethod:4;
3751 uint32_t MqPageSize:8;
3752 uint32_t MQV:2;
3753 uint32_t MqRsvd1:10;
3754 uint32_t MqPageCnt:4;
3755
3756 uint32_t MqRsvd3:16; /* Word 7 */
3757 uint32_t MqeCntMask:16;
3758
3759 uint32_t WqRsvd3:4; /* Word 8 */
3760 uint32_t WqeCntMethod:4;
3761 uint32_t WqPageSize:8;
3762 uint32_t WQV:2;
3763 uint32_t WqeRsvd2:2;
3764 uint32_t WqeSize:4;
3765 uint32_t WqRsvd1:4;
3766 uint32_t WqPageCnt:4;
3767
3768 uint32_t WqRsvd4:16; /* Word 9 */
3769 uint32_t WqeCntMask:16;
3770
3771 uint32_t RqRsvd3:4; /* Word 10 */
3772 uint32_t RqeCntMethod:4;
3773 uint32_t RqPageSize:8;
3774 uint32_t RQV:2;
3775 uint32_t RqeRsvd2:2;
3776 uint32_t RqeSize:4;
3777 uint32_t RqRsvd1:4;
3778 uint32_t RqPageCnt:4;
3779
3780 uint32_t RqDbWin:4; /* Word 11 */
3781 uint32_t RqRsvd4:12;
3782 uint32_t RqeCntMask:16;
3783
3784 uint32_t Loopback:4; /* Word 12 */
3785 uint32_t Rsvd4:12;
3786 uint32_t PHWQ:1;
3787 uint32_t PHON:1;
3788 uint32_t PHOFF:1;
3789 uint32_t TRIR:1;
3790 uint32_t TRTY:1;
3791 uint32_t TCCA:1;
3792 uint32_t MWQE:1;
3793 uint32_t ASSI:1;
3794 uint32_t TERP:1;
3795 uint32_t TGT:1;
3796 uint32_t AREG:1;
3797 uint32_t FBRR:1;
3798 uint32_t SGLR:1;
3799 uint32_t HDRR:1;
3800 uint32_t EXT:1;
3801 uint32_t FCOE:1;
3802
3803 uint32_t SgeLength; /* Word 13 */
3804
3805 uint32_t SglRsvd2:8; /* Word 14 */
3806 uint32_t SglAlign:8;
3807 uint32_t SglPageSize:8;
3808 uint32_t SglRsvd1:4;
3809 uint32_t SglPageCnt:4;
3810
3811 uint32_t Rsvd5:16; /* Word 15 */
3812 uint32_t MinRqSize:16;
3813
3814 uint32_t MaxRqSize; /* Word 16 */
3815
3816 uint32_t RPIMax:16;
3817 uint32_t XRIMax:16; /* Word 17 */
3818
3819 uint32_t VFIMax:16;
3820 uint32_t VPIMax:16; /* Word 18 */
3821 #endif
3822 #ifdef EMLXS_LITTLE_ENDIAN
3823 uint32_t ProtocolType:8; /* Word 0 */
3824 uint32_t Rsvd1:24;
3825
3826 uint32_t FT:1; /* Word 1 */
3827 uint32_t Rsvd2:3;
3828 uint32_t Revision:4;
3829 uint32_t SliFamily:4;
3830 uint32_t IfType:4;
3831 uint32_t SliHint1:8;
3832 uint32_t SliHint2:5;
3833 uint32_t Rsvd3:3;
3834
3835 uint32_t EqPageCnt:4; /* Word 2 */
3836 uint32_t EqRsvd1:4;
3837 uint32_t EqeSize:4;
3838 uint32_t EqRsvd2:4;
3839 uint32_t EqPageSize:8;
3840 uint32_t EqeCntMethod:4;
3841 uint32_t EqRsvd3:4;
3842
3843 uint32_t EqeCntMask:16; /* Word 3 */
3844 uint32_t EqRsvd4:16;
3845
3846 uint32_t CqPageCnt:4; /* Word 4 */
3847 uint32_t CqRsvd1:4;
3848 uint32_t CqeSize:4;
3849 uint32_t CqRsvd2:2;
3850 uint32_t CQV:2;
3851 uint32_t CqPageSize:8;
3852 uint32_t CqeCntMethod:4;
3853 uint32_t CqRsvd3:4;
3854
3855 uint32_t CqeCntMask:16; /* Word 5 */
3856 uint32_t CqRsvd4:16;
3857
3858 uint32_t MqPageCnt:4; /* Word 6 */
3859 uint32_t MqRsvd1:10;
3860 uint32_t MQV:2;
3861 uint32_t MqPageSize:8;
3862 uint32_t MqeCntMethod:4;
3863 uint32_t MqRsvd2:4;
3864
3865 uint32_t MqeCntMask:16; /* Word 7 */
3866 uint32_t MqRsvd3:16;
3867
3868 uint32_t WqPageCnt:4; /* Word 8 */
3869 uint32_t WqRsvd1:4;
3870 uint32_t WqeSize:4;
3871 uint32_t WqeRsvd2:2;
3872 uint32_t WQV:2;
3873 uint32_t WqPageSize:8;
3874 uint32_t WqeCntMethod:4;
3875 uint32_t WqRsvd3:4;
3876
3877 uint32_t WqeCntMask:16; /* Word 9 */
3878 uint32_t WqRsvd4:16;
3879
3880 uint32_t RqPageCnt:4; /* Word 10 */
3881 uint32_t RqRsvd1:4;
3882 uint32_t RqeSize:4;
3883 uint32_t RqeRsvd2:2;
3884 uint32_t RQV:2;
3885 uint32_t RqPageSize:8;
3886 uint32_t RqeCntMethod:4;
3887 uint32_t RqRsvd3:4;
3888
3889 uint32_t RqeCntMask:16; /* Word 11 */
3890 uint32_t RqRsvd4:12;
3891 uint32_t RqDbWin:4;
3892
3893 uint32_t FCOE:1; /* Word 12 */
3894 uint32_t EXT:1;
3895 uint32_t HDRR:1;
3896 uint32_t SGLR:1;
3897 uint32_t FBRR:1;
3898 uint32_t AREG:1;
3899 uint32_t TGT:1;
3900 uint32_t TERP:1;
3901 uint32_t ASSI:1;
3902 uint32_t MWQE:1;
3903 uint32_t TCCA:1;
3904 uint32_t TRTY:1;
3905 uint32_t TRIR:1;
3906 uint32_t PHOFF:1;
3907 uint32_t PHON:1;
3908 uint32_t PHWQ:1;
3909 uint32_t Rsvd4:12;
3910 uint32_t Loopback:4;
3911
3912 uint32_t SgeLength; /* Word 13 */
3913
3914 uint32_t SglPageCnt:4; /* Word 14 */
3915 uint32_t SglRsvd1:4;
3916 uint32_t SglPageSize:8;
3917 uint32_t SglAlign:8;
3918 uint32_t SglRsvd2:8;
3919
3920 uint32_t MinRqSize:16; /* Word 15 */
3921 uint32_t Rsvd5:16;
3922
3923 uint32_t MaxRqSize; /* Word 16 */
3924
3925 uint32_t XRIMax:16; /* Word 17 */
3926 uint32_t RPIMax:16;
3927
3928 uint32_t VPIMax:16; /* Word 18 */
3929 uint32_t VFIMax:16;
3930 #endif
3931
3932 uint32_t Rsvd6; /* Word 19 */
3933
3934 } sli_params_t;
3935
3936 /* SliFamily values */
3937 #define SLI_FAMILY_BE2 0x0
3938 #define SLI_FAMILY_BE3 0x1
3939 #define SLI_FAMILY_LANCER_A 0xA
3940 #define SLI_FAMILY_LANCER_B 0xB
3941
3942
3943
3944 /* IOCTL_COMMON_SLI4_PARAMS */
3945 typedef struct
3946 {
3947 union
3948 {
3949 struct
3950 {
3951 uint32_t Rsvd1;
3952 } request;
3953
3954 struct
3955 {
3956 sli_params_t param;
3957 } response;
3958 } params;
3959
3960 } IOCTL_COMMON_SLI4_PARAMS;
3961
3962
3963 #define MAX_EXTENTS 16 /* 1 to 104 */
3964
3965 /* IOCTL_COMMON_EXTENTS */
3966 typedef struct
3967 {
3968 union
3969 {
3970 struct
3971 {
3972 #ifdef EMLXS_BIG_ENDIAN
3973 uint16_t RscCnt;
3974 uint16_t RscType;
3975 #endif
3976 #ifdef EMLXS_LITTLE_ENDIAN
3977 uint16_t RscType;
3978 uint16_t RscCnt;
3979 #endif
3980 } request;
3981
3982 struct
3983 {
3984 #ifdef EMLXS_BIG_ENDIAN
3985 uint16_t ExtentSize;
3986 uint16_t ExtentCnt;
3987 #endif
3988 #ifdef EMLXS_LITTLE_ENDIAN
3989 uint16_t ExtentCnt;
3990 uint16_t ExtentSize;
3991 #endif
3992
3993 uint16_t RscId[MAX_EXTENTS];
3994
3995 } response;
3996 } params;
3997
3998 } IOCTL_COMMON_EXTENTS;
3999
4000 /* RscType */
4001 #define RSC_TYPE_FCOE_VFI 0x20
4002 #define RSC_TYPE_FCOE_VPI 0x21
4003 #define RSC_TYPE_FCOE_RPI 0x22
4004 #define RSC_TYPE_FCOE_XRI 0x23
4005
4006
4007
4008 /* IOCTL_COMMON_CQ_CREATE */
4009 typedef struct
4010 {
4011 union
4012 {
4013 struct
4014 {
4015 #ifdef EMLXS_BIG_ENDIAN
4016 uint16_t Rsvd1;
4017 uint16_t NumPages;
4018 #endif
4019 #ifdef EMLXS_LITTLE_ENDIAN
4020 uint16_t NumPages;
4021 uint16_t Rsvd1;
4022 #endif
4023 CQ_CONTEXT CQContext;
4024 BE_PHYS_ADDR Pages[4];
4025 } request;
4026
4027 struct
4028 {
4029 #ifdef EMLXS_BIG_ENDIAN
4030 uint16_t Rsvd1;
4031 uint16_t CQId;
4032 #endif
4033 #ifdef EMLXS_LITTLE_ENDIAN
4034 uint16_t CQId;
4035 uint16_t Rsvd1;
4036 #endif
4037 } response;
4038 } params;
4039
4040 } IOCTL_COMMON_CQ_CREATE;
4041
4042
4043 /* IOCTL_COMMON_CQ_CREATE_V2 */
4044 typedef struct
4045 {
4046 union
4047 {
4048 struct
4049 {
4050 #ifdef EMLXS_BIG_ENDIAN
4051 uint8_t Rsvd1;
4052 uint8_t PageSize;
4053 uint16_t NumPages;
4054 #endif
4055 #ifdef EMLXS_LITTLE_ENDIAN
4056 uint16_t NumPages;
4057 uint8_t PageSize;
4058 uint8_t Rsvd1;
4059 #endif
4060 CQ_CONTEXT_V2 CQContext;
4061 BE_PHYS_ADDR Pages[8];
4062 } request;
4063
4064 struct
4065 {
4066 #ifdef EMLXS_BIG_ENDIAN
4067 uint16_t Rsvd1;
4068 uint16_t CQId;
4069 #endif
4070 #ifdef EMLXS_LITTLE_ENDIAN
4071 uint16_t CQId;
4072 uint16_t Rsvd1;
4073 #endif
4074 } response;
4075 } params;
4076
4077 } IOCTL_COMMON_CQ_CREATE_V2;
4078
4079 #define CQ_PAGE_SIZE_4K 0x01
4080 #define CQ_PAGE_SIZE_8K 0x02
4081 #define CQ_PAGE_SIZE_16K 0x04
4082 #define CQ_PAGE_SIZE_32K 0x08
4083 #define CQ_PAGE_SIZE_64K 0x10
4084
4085
4086
4087 /* IOCTL_COMMON_MQ_CREATE */
4088 typedef struct
4089 {
4090 union
4091 {
4092 struct
4093 {
4094 #ifdef EMLXS_BIG_ENDIAN
4095 uint16_t Rsvd1;
4096 uint16_t NumPages;
4097 #endif
4098 #ifdef EMLXS_LITTLE_ENDIAN
4099 uint16_t NumPages;
4100 uint16_t Rsvd1;
4101 #endif
4102 MQ_CONTEXT MQContext;
4103 BE_PHYS_ADDR Pages[8];
4104 } request;
4105
4106 struct
4107 {
4108 #ifdef EMLXS_BIG_ENDIAN
4109 uint16_t Rsvd1;
4110 uint16_t MQId;
4111 #endif
4112 #ifdef EMLXS_LITTLE_ENDIAN
4113 uint16_t MQId;
4114 uint16_t Rsvd1;
4115 #endif
4116 } response;
4117 } params;
4118
4119 } IOCTL_COMMON_MQ_CREATE;
4120
4121
4122 /* IOCTL_COMMON_MQ_CREATE_EXT */
4123 typedef struct
4124 {
4125 union
4126 {
4127 struct
4128 {
4129 #ifdef EMLXS_BIG_ENDIAN
4130 uint16_t rsvd0;
4131 uint16_t num_pages;
4132 #endif
4133 #ifdef EMLXS_LITTLE_ENDIAN
4134 uint16_t num_pages;
4135 uint16_t rsvd0;
4136 #endif
4137 uint32_t async_event_bitmap;
4138
4139 #define ASYNC_LINK_EVENT 0x00000002
4140 #define ASYNC_FCF_EVENT 0x00000004
4141 #define ASYNC_DCBX_EVENT 0x00000008
4142 #define ASYNC_iSCSI_EVENT 0x00000010
4143 #define ASYNC_GROUP5_EVENT 0x00000020
4144 #define ASYNC_FC_EVENT 0x00010000
4145 #define ASYNC_PORT_EVENT 0x00020000
4146 #define ASYNC_VF_EVENT 0x00040000
4147 #define ASYNC_MR_EVENT 0x00080000
4148
4149 MQ_CONTEXT context;
4150 BE_PHYS_ADDR pages[8];
4151 } request;
4152
4153 struct
4154 {
4155 #ifdef EMLXS_BIG_ENDIAN
4156 uint16_t rsvd0;
4157 uint16_t MQId;
4158 #endif
4159 #ifdef EMLXS_LITTLE_ENDIAN
4160 uint16_t MQId;
4161 uint16_t rsvd0;
4162 #endif
4163 } response;
4164
4165 } params;
4166
4167 } IOCTL_COMMON_MQ_CREATE_EXT;
4168
4169
4170 /* IOCTL_COMMON_MQ_CREATE_EXT_V1 */
4171 typedef struct
4172 {
4173 union
4174 {
4175 struct
4176 {
4177 #ifdef EMLXS_BIG_ENDIAN
4178 uint16_t CQId;
4179 uint16_t num_pages;
4180 #endif
4181 #ifdef EMLXS_LITTLE_ENDIAN
4182 uint16_t num_pages;
4183 uint16_t CQId;
4184 #endif
4185 uint32_t async_event_bitmap;
4186
4187 MQ_CONTEXT_V1 context;
4188 BE_PHYS_ADDR pages[8];
4189 } request;
4190
4191 struct
4192 {
4193 #ifdef EMLXS_BIG_ENDIAN
4194 uint16_t rsvd0;
4195 uint16_t MQId;
4196 #endif
4197 #ifdef EMLXS_LITTLE_ENDIAN
4198 uint16_t MQId;
4199 uint16_t rsvd0;
4200 #endif
4201 } response;
4202
4203 } params;
4204
4205 } IOCTL_COMMON_MQ_CREATE_EXT_V1;
4206
4207
4208 /* IOCTL_FCOE_RQ_CREATE */
4209 typedef struct
4210 {
4211 union
4212 {
4213 struct
4214 {
4215 #ifdef EMLXS_BIG_ENDIAN
4216 uint16_t Rsvd0;
4217 uint16_t NumPages;
4218 #endif
4219 #ifdef EMLXS_LITTLE_ENDIAN
4220 uint16_t NumPages;
4221 uint16_t Rsvd0;
4222 #endif
4223 RQ_CONTEXT RQContext;
4224 BE_PHYS_ADDR Pages[8];
4225 } request;
4226
4227 struct
4228 {
4229 #ifdef EMLXS_BIG_ENDIAN
4230 uint16_t Rsvd1;
4231 uint16_t RQId;
4232 #endif
4233 #ifdef EMLXS_LITTLE_ENDIAN
4234 uint16_t RQId;
4235 uint16_t Rsvd1;
4236 #endif
4237 } response;
4238
4239 } params;
4240
4241 } IOCTL_FCOE_RQ_CREATE;
4242
4243
4244 /* IOCTL_FCOE_RQ_CREATE_V1 */
4245 typedef struct
4246 {
4247 union
4248 {
4249 struct
4250 {
4251 #ifdef EMLXS_BIG_ENDIAN
4252 uint32_t DNB:1;
4253 uint32_t DFD:1;
4254 uint32_t DIM:1;
4255 uint32_t Rsvd0:13;
4256 uint32_t NumPages:16;
4257 #endif
4258 #ifdef EMLXS_LITTLE_ENDIAN
4259 uint32_t NumPages:16;
4260 uint32_t Rsvd0:13;
4261 uint32_t DIM:1;
4262 uint32_t DFD:1;
4263 uint32_t DNB:1;
4264 #endif
4265 RQ_CONTEXT_V1 RQContext;
4266 BE_PHYS_ADDR Pages[8];
4267 } request;
4268
4269 struct
4270 {
4271 #ifdef EMLXS_BIG_ENDIAN
4272 uint16_t Rsvd1;
4273 uint16_t RQId;
4274 #endif
4275 #ifdef EMLXS_LITTLE_ENDIAN
4276 uint16_t RQId;
4277 uint16_t Rsvd1;
4278 #endif
4279 } response;
4280
4281 } params;
4282
4283 } IOCTL_FCOE_RQ_CREATE_V1;
4284
4285
4286 /* IOCTL_FCOE_WQ_CREATE */
4287 typedef struct
4288 {
4289 union
4290 {
4291 struct
4292 {
4293 #ifdef EMLXS_BIG_ENDIAN
4294 uint16_t CQId;
4295 uint16_t NumPages;
4296 #endif
4297 #ifdef EMLXS_LITTLE_ENDIAN
4298 uint16_t NumPages;
4299 uint16_t CQId;
4300 #endif
4301 BE_PHYS_ADDR Pages[4];
4302 } request;
4303
4304 struct
4305 {
4306 #ifdef EMLXS_BIG_ENDIAN
4307 uint16_t Rsvd0;
4308 uint16_t WQId;
4309 #endif
4310 #ifdef EMLXS_LITTLE_ENDIAN
4311 uint16_t WQId;
4312 uint16_t Rsvd0;
4313 #endif
4314 } response;
4315
4316 } params;
4317
4318 } IOCTL_FCOE_WQ_CREATE;
4319
4320
4321 /* IOCTL_FCOE_WQ_CREATE_V1 */
4322 typedef struct
4323 {
4324 union
4325 {
4326 struct
4327 {
4328 #ifdef EMLXS_BIG_ENDIAN
4329 uint16_t CQId;
4330 uint16_t NumPages;
4331
4332 uint32_t WqeCnt:16;
4333 uint32_t Rsvd1:4;
4334 uint32_t WqeSize:4;
4335 uint32_t PageSize:8;
4336 #endif
4337 #ifdef EMLXS_LITTLE_ENDIAN
4338 uint16_t NumPages;
4339 uint16_t CQId;
4340
4341 uint32_t PageSize:8;
4342 uint32_t WqeSize:4;
4343 uint32_t Rsvd1:4;
4344 uint32_t WqeCnt:16;
4345 #endif
4346 uint32_t Rsvd:2;
4347 BE_PHYS_ADDR Pages[4];
4348 } request;
4349
4350 struct
4351 {
4352 #ifdef EMLXS_BIG_ENDIAN
4353 uint16_t Rsvd0;
4354 uint16_t WQId;
4355 #endif
4356 #ifdef EMLXS_LITTLE_ENDIAN
4357 uint16_t WQId;
4358 uint16_t Rsvd0;
4359 #endif
4360 } response;
4361
4362 } params;
4363
4364 } IOCTL_FCOE_WQ_CREATE_V1;
4365
4366 /* WqeSize */
4367 #define WQE_SIZE_64_BYTES 0x05
4368 #define WQE_SIZE_128_BYTES 0x06
4369
4370 /* PageSize */
4371 #define WQ_PAGE_SIZE_4K 0x01
4372 #define WQ_PAGE_SIZE_8K 0x02
4373 #define WQ_PAGE_SIZE_16K 0x04
4374 #define WQ_PAGE_SIZE_32K 0x08
4375 #define WQ_PAGE_SIZE_64K 0x10
4376
4377
4378
4379 /* IOCTL_FCOE_CFG_POST_SGL_PAGES */
4380 typedef struct _FCOE_SGL_PAGES
4381 {
4382 BE_PHYS_ADDR sgl_page0; /* 1st page per XRI */
4383 BE_PHYS_ADDR sgl_page1; /* 2nd page per XRI */
4384
4385 } FCOE_SGL_PAGES;
4386
4387 typedef struct
4388 {
4389 union
4390 {
4391 struct
4392 {
4393 #ifdef EMLXS_BIG_ENDIAN
4394 uint16_t xri_count;
4395 uint16_t xri_start;
4396 #endif
4397 #ifdef EMLXS_LITTLE_ENDIAN
4398 uint16_t xri_start;
4399 uint16_t xri_count;
4400 #endif
4401 FCOE_SGL_PAGES pages[1];
4402 } request;
4403
4404 struct
4405 {
4406 uint32_t rsvd0;
4407 } response;
4408
4409 } params;
4410
4411 uint32_t rsvd0[2];
4412
4413 } IOCTL_FCOE_CFG_POST_SGL_PAGES;
4414
4415
4416 /* IOCTL_FCOE_POST_HDR_TEMPLATES */
4417 typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
4418 {
4419 union
4420 {
4421 struct
4422 {
4423 #ifdef EMLXS_BIG_ENDIAN
4424 uint16_t num_pages;
4425 uint16_t rpi_offset;
4426 #endif
4427 #ifdef EMLXS_LITTLE_ENDIAN
4428 uint16_t rpi_offset;
4429 uint16_t num_pages;
4430 #endif
4431 BE_PHYS_ADDR pages[32];
4432
4433 }request;
4434
4435 }params;
4436
4437 } IOCTL_FCOE_POST_HDR_TEMPLATES;
4438
4439
4440
4441 #define EMLXS_IOCTL_DCBX_MODE_CEE 0 /* Mapped to FIP mode */
4442 #define EMLXS_IOCTL_DCBX_MODE_CIN 1 /* Mapped to nonFIP mode */
4443
4444 /* IOCTL_DCBX_GET_DCBX_MODE */
4445 typedef struct _IOCTL_DCBX_GET_DCBX_MODE
4446 {
4447 union
4448 {
4449 struct
4450 {
4451 #ifdef EMLXS_BIG_ENDIAN
4452 uint8_t rsvd0[3];
4453 uint8_t port_num;
4454 #endif
4455 #ifdef EMLXS_LITTLE_ENDIAN
4456 uint8_t port_num;
4457 uint8_t rsvd0[3];
4458 #endif
4459 } request;
4460
4461 struct
4462 {
4463 #ifdef EMLXS_BIG_ENDIAN
4464 uint8_t rsvd1[3];
4465 uint8_t dcbx_mode;
4466 #endif
4467 #ifdef EMLXS_LITTLE_ENDIAN
4468 uint8_t dcbx_mode;
4469 uint8_t rsvd1[3];
4470 #endif
4471 } response;
4472
4473 } params;
4474
4475 } IOCTL_DCBX_GET_DCBX_MODE;
4476
4477
4478 /* IOCTL_DCBX_SET_DCBX_MODE */
4479 typedef struct _IOCTL_DCBX_SET_DCBX_MODE
4480 {
4481 union
4482 {
4483 struct
4484 {
4485 #ifdef EMLXS_BIG_ENDIAN
4486 uint8_t rsvd0[2];
4487 uint8_t dcbx_mode;
4488 uint8_t port_num;
4489 #endif
4490 #ifdef EMLXS_LITTLE_ENDIAN
4491 uint8_t port_num;
4492 uint8_t dcbx_mode;
4493 uint8_t rsvd0[2];
4494 #endif
4495 } request;
4496
4497 struct
4498 {
4499 uint32_t rsvd1;
4500 } response;
4501
4502 } params;
4503
4504 } IOCTL_DCBX_SET_DCBX_MODE;
4505
4506
4507 /* IOCTL_COMMON_GET_CNTL_ATTRIB */
4508 typedef struct
4509 {
4510 char flashrom_version_string[32];
4511 char manufacturer_name[32];
4512 char rsvd0[28];
4513 uint32_t default_extended_timeout;
4514 char controller_model_number[32];
4515 char controller_description[64];
4516 char controller_serial_number[32];
4517 char ip_version_string[32];
4518 char firmware_version_string[32];
4519 char bios_version_string[32];
4520 char redboot_version_string[32];
4521 char driver_version_string[32];
4522 char fw_on_flash_version_string[32];
4523 uint32_t functionalities_supported;
4524 uint16_t max_cdblength;
4525 uint8_t asic_revision;
4526 uint8_t generational_guid[16];
4527 uint8_t hba_port_count;
4528 uint16_t default_link_down_timeout;
4529 uint8_t iscsi_ver_min_max;
4530 uint8_t multifunction_device;
4531 uint8_t cache_valid;
4532 uint8_t hba_status;
4533 uint8_t max_domains_supported;
4534 uint8_t phy_port;
4535 uint32_t firmware_post_status;
4536 uint32_t hba_mtu[2];
4537
4538 } MGMT_HBA_ATTRIB;
4539
4540 typedef struct
4541 {
4542 MGMT_HBA_ATTRIB hba_attribs;
4543 uint16_t pci_vendor_id;
4544 uint16_t pci_device_id;
4545 uint16_t pci_sub_vendor_id;
4546 uint16_t pci_sub_system_id;
4547 uint8_t pci_bus_number;
4548 uint8_t pci_device_number;
4549 uint8_t pci_function_number;
4550 uint8_t interface_type;
4551 uint64_t unique_identifier;
4552
4553 } MGMT_CONTROLLER_ATTRIB;
4554
4555 typedef struct
4556 {
4557 union
4558 {
4559 struct
4560 {
4561 uint32_t rsvd0;
4562 } request;
4563
4564 struct
4565 {
4566 MGMT_CONTROLLER_ATTRIB cntl_attributes_info;
4567 } response;
4568
4569 } params;
4570
4571 } IOCTL_COMMON_GET_CNTL_ATTRIB;
4572
4573
4574 typedef union
4575 {
4576 IOCTL_COMMON_NOP NOPVar;
4577 IOCTL_FCOE_WQ_CREATE WQCreateVar;
4578 IOCTL_FCOE_WQ_CREATE_V1 WQCreateVar1;
4579 IOCTL_FCOE_RQ_CREATE RQCreateVar;
4580 IOCTL_FCOE_RQ_CREATE_V1 RQCreateVar1;
4581 IOCTL_COMMON_EQ_CREATE EQCreateVar;
4582 IOCTL_COMMON_CQ_CREATE CQCreateVar;
4583 IOCTL_COMMON_CQ_CREATE_V2 CQCreateVar2;
4584 IOCTL_COMMON_MQ_CREATE MQCreateVar;
4585 IOCTL_COMMON_MQ_CREATE_EXT MQCreateExtVar;
4586 IOCTL_COMMON_MQ_CREATE_EXT_V1 MQCreateExtVar1;
4587 IOCTL_FCOE_CFG_POST_SGL_PAGES PostSGLVar;
4588 IOCTL_COMMON_GET_CNTL_ATTRIB GetCntlAttributesVar;
4589 IOCTL_FCOE_READ_FCF_TABLE ReadFCFTableVar;
4590 IOCTL_FCOE_ADD_FCF_TABLE AddFCFTableVar;
4591 IOCTL_FCOE_REDISCOVER_FCF_TABLE RediscoverFCFTableVar;
4592 IOCTL_COMMON_FLASHROM FlashRomVar;
4593 IOCTL_COMMON_MANAGE_FAT FATVar;
4594 IOCTL_DCBX_GET_DCBX_MODE GetDCBX;
4595 IOCTL_DCBX_SET_DCBX_MODE SetDCBX;
4596 IOCTL_COMMON_SLI4_PARAMS Sli4ParamVar;
4597 IOCTL_COMMON_EXTENTS ExtentsVar;
4598 IOCTL_COMMON_GET_PHY_DETAILS PHYDetailsVar;
4599 IOCTL_COMMON_GET_PORT_NAME PortNameVar;
4600 IOCTL_COMMON_GET_PORT_NAME_V1 PortNameVar1;
4601 IOCTL_COMMON_WRITE_OBJECT WriteObjVar;
4602 IOCTL_COMMON_BOOT_CFG BootCfgVar;
4603
4604 } IOCTL_VARIANTS;
4605
4606 /* Structure for MB Command SLI_CONFIG(0x9b) */
4607 /* Good for SLI4 only */
4608
4609 typedef struct
4610 {
4611 be_req_hdr_t be;
4612 BE_PHYS_ADDR payload;
4613 } SLI_CONFIG_VAR;
4614
4615 #define IOCTL_HEADER_SZ (4 * sizeof (uint32_t))
4616
4617
4618 typedef union
4619 {
4620 uint32_t varWords[63];
4621 READ_NV_VAR varRDnvp; /* cmd = x02 (READ_NVPARMS) */
4622 INIT_LINK_VAR varInitLnk; /* cmd = x05 (INIT_LINK) */
4623 CONFIG_LINK varCfgLnk; /* cmd = x07 (CONFIG_LINK) */
4624 READ_REV4_VAR varRdRev4; /* cmd = x11 (READ_REV) */
4625 READ_LNK_VAR varRdLnk; /* cmd = x12 (READ_LNK_STAT) */
4626 DUMP4_VAR varDmp4; /* cmd = x17 (DUMP) */
4627 UPDATE_CFG_VAR varUpdateCfg; /* cmd = x1b (update Cfg) */
4628 BIU_DIAG_VAR varBIUdiag; /* cmd = x84 (RUN_BIU_DIAG64) */
4629 READ_SPARM_VAR varRdSparm; /* cmd = x8D (READ_SPARM64) */
4630 REG_FCFI_VAR varRegFCFI; /* cmd = xA0 (REG_FCFI) */
4631 UNREG_FCFI_VAR varUnRegFCFI; /* cmd = xA2 (UNREG_FCFI) */
4632 READ_LA_VAR varReadLA; /* cmd = x95 (READ_LA64) */
4633 READ_CONFIG4_VAR varRdConfig4; /* cmd = x0B (READ_CONFIG) */
4634 RESUME_RPI_VAR varResumeRPI; /* cmd = x9E (RESUME_RPI) */
4635 REG_LOGIN_VAR varRegLogin; /* cmd = x93 (REG_RPI) */
4636 UNREG_LOGIN_VAR varUnregLogin; /* cmd = x14 (UNREG_RPI) */
4637 REG_VPI_VAR varRegVPI4; /* cmd = x96 (REG_VPI) */
4638 UNREG_VPI_VAR4 varUnRegVPI4; /* cmd = x97 (UNREG_VPI) */
4639 REG_VFI_VAR varRegVFI4; /* cmd = x9F (REG_VFI) */
4640 UNREG_VFI_VAR varUnRegVFI4; /* cmd = xA1 (UNREG_VFI) */
4641 REQUEST_FEATURES_VAR varReqFeatures; /* cmd = x9D (REQ_FEATURES) */
4642 SLI_CONFIG_VAR varSLIConfig; /* cmd = x9B (SLI_CONFIG) */
4643 INIT_VPI_VAR varInitVPI4; /* cmd = xA3 (INIT_VPI) */
4644 INIT_VFI_VAR varInitVFI4; /* cmd = xA4 (INIT_VFI) */
4645
4646 } MAILVARIANTS4; /* Used for SLI-4 */
4647
4648 #define MAILBOX_CMD_SLI4_BSIZE 256
4649 #define MAILBOX_CMD_SLI4_WSIZE 64
4650
4651 #define MAILBOX_CMD_MAX_BSIZE 256
4652 #define MAILBOX_CMD_MAX_WSIZE 64
4653
4654
4655 typedef volatile struct
4656 {
4657 #ifdef EMLXS_BIG_ENDIAN
4658 uint16_t mbxStatus;
4659 uint8_t mbxCommand;
4660 uint8_t mbxReserved:6;
4661 uint8_t mbxHc:1;
4662 uint8_t mbxOwner:1; /* Low order bit first word */
4663 #endif
4664 #ifdef EMLXS_LITTLE_ENDIAN
4665 uint8_t mbxOwner:1; /* Low order bit first word */
4666 uint8_t mbxHc:1;
4667 uint8_t mbxReserved:6;
4668 uint8_t mbxCommand;
4669 uint16_t mbxStatus;
4670 #endif
4671 MAILVARIANTS4 un; /* 252 bytes */
4672 } MAILBOX4; /* Used for SLI-4 */
4673
4674 /*
4675 * End Structure Definitions for Mailbox Commands
4676 */
4677
4678
4679 typedef struct emlxs_mbq
4680 {
4681 volatile uint32_t mbox[MAILBOX_CMD_MAX_WSIZE];
4682 struct emlxs_mbq *next;
4683
4684 /* Defferred handling pointers */
4685 void *nonembed; /* ptr to data buffer */
4686 /* structure */
4687 void *bp; /* ptr to data buffer */
4688 /* structure */
4689 void *sbp; /* ptr to emlxs_buf_t */
4690 /* structure */
4691 void *ubp; /* ptr to fc_unsol_buf_t */
4692 /* structure */
4693 void *iocbq; /* ptr to IOCBQ structure */
4694 void *context; /* ptr to mbox context data */
4695 void *port; /* Sending port */
4696 uint32_t flag;
4697
4698 #define MBQ_POOL_ALLOCATED 0x00000001
4699 #define MBQ_PASSTHRU 0x00000002
4700 #define MBQ_EMBEDDED 0x00000004
4701 #define MBQ_BOOTSTRAP 0x00000008
4702 #define MBQ_COMPLETED 0x00010000 /* Used for MBX_SLEEP */
4703 #define MBQ_INIT_MASK 0x0000ffff
4704
4705 #ifdef MBOX_EXT_SUPPORT
4706 uint8_t *extbuf; /* ptr to mailbox ext buffer */
4707 uint32_t extsize; /* size of mailbox ext buffer */
4708 #endif /* MBOX_EXT_SUPPORT */
4709 uint32_t (*mbox_cmpl)();
4710 } emlxs_mbq_t;
4711 typedef emlxs_mbq_t MAILBOXQ;
4712
4713
4714 /* We currently do not support IOCBs in SLI1 mode */
4715 typedef struct
4716 {
4717 MAILBOX mbx;
4718 #ifdef MBOX_EXT_SUPPORT
4719 uint8_t mbxExt[MBOX_EXTENSION_SIZE];
4720 #endif /* MBOX_EXT_SUPPORT */
4721 uint8_t pad[(SLI_SLIM1_SIZE -
4722 (sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))];
4723 } SLIM1;
4724
4725
4726 typedef struct
4727 {
4728 MAILBOX mbx;
4729 #ifdef MBOX_EXT_SUPPORT
4730 uint8_t mbxExt[MBOX_EXTENSION_SIZE];
4731 #endif /* MBOX_EXT_SUPPORT */
4732 PCB pcb;
4733 uint8_t IOCBs[SLI_IOCB_MAX_SIZE];
4734 } SLIM2;
4735
4736
4737 /* def for new 2MB Flash (Pegasus ...) */
4738 #define MBX_LOAD_AREA 0x81
4739 #define MBX_LOAD_EXP_ROM 0x9C
4740
4741 #define FILE_TYPE_AWC 0xE1A01001
4742 #define FILE_TYPE_DWC 0xE1A02002
4743 #define FILE_TYPE_BWC 0xE1A03003
4744
4745 #define AREA_ID_MASK 0xFFFFFF0F
4746 #define AREA_ID_AWC 0x00000001
4747 #define AREA_ID_DWC 0x00000002
4748 #define AREA_ID_BWC 0x00000003
4749
4750 #define CMD_START_ERASE 1
4751 #define CMD_CONTINUE_ERASE 2
4752 #define CMD_DOWNLOAD 3
4753 #define CMD_END_DOWNLOAD 4
4754
4755 #define RSP_ERASE_STARTED 1
4756 #define RSP_ERASE_COMPLETE 2
4757 #define RSP_DOWNLOAD_MORE 3
4758 #define RSP_DOWNLOAD_DONE 4
4759
4760 #define EROM_CMD_FIND_IMAGE 8
4761 #define EROM_CMD_CONTINUE_ERASE 9
4762 #define EROM_CMD_COPY 10
4763
4764 #define EROM_RSP_ERASE_STARTED 8
4765 #define EROM_RSP_ERASE_COMPLETE 9
4766 #define EROM_RSP_COPY_MORE 10
4767 #define EROM_RSP_COPY_DONE 11
4768
4769 #define ALLext 1
4770 #define DWCext 2
4771 #define BWCext 3
4772
4773 #define NO_ALL 0
4774 #define ALL_WITHOUT_BWC 1
4775 #define ALL_WITH_BWC 2
4776
4777 #define KERNEL_START_ADDRESS 0x000000
4778 #define DOWNLOAD_START_ADDRESS 0x040000
4779 #define EXP_ROM_START_ADDRESS 0x180000
4780 #define SCRATCH_START_ADDRESS 0x1C0000
4781 #define CONFIG_START_ADDRESS 0x1E0000
4782
4783
4784 typedef struct SliAifHdr
4785 {
4786 uint32_t CompressBr;
4787 uint32_t RelocBr;
4788 uint32_t ZinitBr;
4789 uint32_t EntryBr;
4790 uint32_t Area_ID;
4791 uint32_t RoSize;
4792 uint32_t RwSize;
4793 uint32_t DbgSize;
4794 uint32_t ZinitSize;
4795 uint32_t DbgType;
4796 uint32_t ImageBase;
4797 uint32_t Area_Size;
4798 uint32_t AddressMode;
4799 uint32_t DataBase;
4800 uint32_t AVersion;
4801 uint32_t Spare2;
4802 uint32_t DebugSwi;
4803 uint32_t ZinitCode[15];
4804 } AIF_HDR, *PAIF_HDR;
4805
4806 typedef struct ImageHdr
4807 {
4808 uint32_t BlockSize;
4809 PROG_ID Id;
4810 uint32_t Flags;
4811 uint32_t EntryAdr;
4812 uint32_t InitAdr;
4813 uint32_t ExitAdr;
4814 uint32_t ImageBase;
4815 uint32_t ImageSize;
4816 uint32_t ZinitSize;
4817 uint32_t RelocSize;
4818 uint32_t HdrCks;
4819 } IMAGE_HDR, *PIMAGE_HDR;
4820
4821
4822
4823 typedef struct
4824 {
4825 PROG_ID prog_id;
4826 #ifdef EMLXS_BIG_ENDIAN
4827 uint32_t pci_cfg_rsvd:27;
4828 uint32_t use_hdw_def:1;
4829 uint32_t pci_cfg_sel:3;
4830 uint32_t pci_cfg_lookup_sel:1;
4831 #endif
4832 #ifdef EMLXS_LITTLE_ENDIAN
4833 uint32_t pci_cfg_lookup_sel:1;
4834 uint32_t pci_cfg_sel:3;
4835 uint32_t use_hdw_def:1;
4836 uint32_t pci_cfg_rsvd:27;
4837 #endif
4838 union
4839 {
4840 PROG_ID boot_bios_id;
4841 uint32_t boot_bios_wd[2];
4842 } u0;
4843 PROG_ID sli1_prog_id;
4844 PROG_ID sli2_prog_id;
4845 PROG_ID sli3_prog_id;
4846 PROG_ID sli4_prog_id;
4847 union
4848 {
4849 PROG_ID EROM_prog_id;
4850 uint32_t EROM_prog_wd[2];
4851 } u1;
4852 } WAKE_UP_PARMS, *PWAKE_UP_PARMS;
4853
4854
4855 #define PROG_DESCR_STR_LEN 24
4856 #define MAX_LOAD_ENTRY 32
4857
4858 typedef struct
4859 {
4860 uint32_t next;
4861 uint32_t prev;
4862 uint32_t start_adr;
4863 uint32_t len;
4864 union
4865 {
4866 PROG_ID id;
4867 uint32_t wd[2];
4868 } un;
4869 uint8_t prog_descr[PROG_DESCR_STR_LEN];
4870 } LOAD_ENTRY;
4871
4872 typedef struct
4873 {
4874 uint32_t head;
4875 uint32_t tail;
4876 uint32_t entry_cnt;
4877 LOAD_ENTRY load_entry[MAX_LOAD_ENTRY];
4878 } LOAD_LIST;
4879
4880 #ifdef __cplusplus
4881 }
4882 #endif
4883
4884 #endif /* _EMLXS_MBOX_H */