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MFV: illumos-omnios@aea0472ecb9ee91fa70556d6f6a941c10c989f1d
Add support for Emulex Corporation Lancer Gen6: LPe32000 FC Host Adapter
Author: Andy Fiddaman <omnios@citrus-it.co.uk>
NEX-8705 Drivers for ATTO Celerity FC-162E Gen 5 and Celerity FC-162P Gen 6 16GB FC cards support
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
NEX-1878 update emlxs from source provided by Emulex
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--- old/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h
+++ new/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at
9 9 * http://www.opensource.org/licenses/cddl1.txt.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 24 * Use is subject to license terms.
25 + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
25 26 */
26 27
27 28 #ifndef _EMLXS_FC_H
28 29 #define _EMLXS_FC_H
29 30
30 31 #ifdef __cplusplus
31 32 extern "C" {
32 33 #endif
33 34
34 35 typedef struct emlxs_buf
35 36 {
36 37 fc_packet_t *pkt; /* scsi_pkt reference */
37 38 struct emlxs_port *port; /* pointer to port */
38 39 void *bmp; /* Save the buffer pointer */
39 40 /* list for later use. */
40 41 struct emlxs_buf *fc_fwd; /* Use it by chip_Q */
41 42 struct emlxs_buf *fc_bkwd; /* Use it by chip_Q */
42 43 struct emlxs_buf *next; /* Use it when the iodone */
43 44 struct emlxs_node *node;
44 45 void *channel; /* Save channel and used by */
45 46 /* abort */
46 47 struct emlxs_buf *fpkt; /* Flush pkt pointer */
47 48 struct XRIobj *xrip; /* Exchange resource */
48 49 IOCBQ iocbq;
49 50 kmutex_t mtx;
50 51 uint32_t pkt_flags;
51 52 uint32_t iotag; /* iotag for this cmd */
52 53 uint32_t ticks; /* save the timeout ticks */
53 54 /* for the fc_packet_t */
54 55 uint32_t abort_attempts;
55 56 uint32_t lun;
56 57 #define EMLXS_LUN_NONE 0xFFFFFFFF
57 58
58 59 uint32_t class; /* Save class and used by */
59 60 /* abort */
60 61 uint32_t ucmd; /* Unsolicted command that */
61 62 /* this packet is responding */
62 63 /* to, if any */
63 64 int32_t flush_count; /* Valid only in flush pkts */
64 65 uint32_t did;
65 66
66 67 #ifdef SFCT_SUPPORT
67 68 kmutex_t fct_mtx;
68 69 fc_packet_t *fct_pkt;
69 70 fct_cmd_t *fct_cmd;
70 71
71 72 uint8_t fct_type;
72 73
73 74 #define EMLXS_FCT_ELS_CMD 0x01 /* Unsolicted */
74 75 #define EMLXS_FCT_ELS_REQ 0x02 /* Solicited */
75 76 #define EMLXS_FCT_ELS_RSP 0x04
76 77 #define EMLXS_FCT_CT_REQ 0x08 /* Solicited */
77 78 #define EMLXS_FCT_FCP_CMD 0x10 /* Unsolicted */
78 79 #define EMLXS_FCT_FCP_DATA 0x20
79 80 #define EMLXS_FCT_FCP_STATUS 0x40
80 81
81 82
82 83 uint8_t fct_flags;
83 84
84 85 #define EMLXS_FCT_SEND_STATUS 0x01
85 86 #define EMLXS_FCT_ABORT_INP 0x02
86 87 #define EMLXS_FCT_IO_INP 0x04
87 88 #define EMLXS_FCT_PLOGI_RECEIVED 0x10
88 89 #define EMLXS_FCT_REGISTERED 0x20
89 90
90 91 uint16_t fct_state;
91 92
92 93 #define EMLXS_FCT_FCP_CMD_RECEIVED 1
93 94 #define EMLXS_FCT_ELS_CMD_RECEIVED 2
94 95 #define EMLXS_FCT_CMD_POSTED 3
95 96 #define EMLXS_FCT_CMD_WAITQ 4
96 97 #define EMLXS_FCT_SEND_CMD_RSP 5
97 98 #define EMLXS_FCT_SEND_ELS_RSP 6
98 99 #define EMLXS_FCT_SEND_ELS_REQ 7
99 100 #define EMLXS_FCT_SEND_CT_REQ 8
100 101 #define EMLXS_FCT_RSP_PENDING 9
101 102 #define EMLXS_FCT_REQ_PENDING 10
102 103 #define EMLXS_FCT_REG_PENDING 11
103 104 #define EMLXS_FCT_REG_COMPLETE 12
104 105 #define EMLXS_FCT_OWNED 13
105 106 #define EMLXS_FCT_SEND_FCP_DATA 14
106 107 #define EMLXS_FCT_SEND_FCP_STATUS 15
107 108 #define EMLXS_FCT_DATA_PENDING 16
108 109 #define EMLXS_FCT_STATUS_PENDING 17
109 110 #define EMLXS_FCT_PKT_COMPLETE 18
110 111 #define EMLXS_FCT_PKT_FCPRSP_COMPLETE 19
111 112 #define EMLXS_FCT_PKT_ELSRSP_COMPLETE 20
112 113 #define EMLXS_FCT_PKT_ELSCMD_COMPLETE 21
113 114 #define EMLXS_FCT_PKT_CTCMD_COMPLETE 22
114 115 #define EMLXS_FCT_REQ_COMPLETE 23
115 116 #define EMLXS_FCT_CLOSE_PENDING 24
116 117 #define EMLXS_FCT_ABORT_PENDING 25
117 118 #define EMLXS_FCT_ABORT_DONE 26
118 119 #define EMLXS_FCT_IO_DONE 27
119 120
120 121 #define EMLXS_FCT_IOCB_ISSUED 256 /* For tracing only */
121 122 #define EMLXS_FCT_IOCB_COMPLETE 257 /* For tracing only */
122 123
123 124 stmf_data_buf_t *fct_buf;
124 125
125 126 #endif /* SFCT_SUPPORT */
126 127
127 128 #ifdef SAN_DIAG_SUPPORT
128 129 hrtime_t sd_start_time;
129 130 #endif /* SAN_DIAG_SUPPORT */
130 131
131 132 } emlxs_buf_t;
132 133
133 134
134 135
135 136 #ifdef FCT_IO_TRACE
136 137 #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \
137 138 (_cmd_sbp)->fct_state = _state; \
138 139 emlxs_fct_io_trace((_cmd_sbp)->port, _fct_cmd, _state)
139 140 #else
140 141 /* define to set fct_state */
141 142 #define EMLXS_FCT_STATE_CHG(_fct_cmd, _cmd_sbp, _state) \
142 143 (_cmd_sbp)->fct_state = _state
143 144 #endif /* FCT_IO_TRACE */
144 145
145 146
146 147 /* pkt_flags */
147 148 #define PACKET_IN_COMPLETION 0x00000001
148 149 #define PACKET_IN_TXQ 0x00000002
149 150 #define PACKET_IN_CHIPQ 0x00000004
150 151 #define PACKET_IN_DONEQ 0x00000008
151 152
152 153 #define PACKET_FCP_RESET 0x00000030
153 154 #define PACKET_FCP_TGT_RESET 0x00000010
154 155 #define PACKET_FCP_LUN_RESET 0x00000020
155 156 #define PACKET_POLLED 0x00000040
156 157
157 158 #ifdef EMLXS_I386
158 159 #define PACKET_FCP_SWAPPED 0x00000100
159 160 #define PACKET_ELS_SWAPPED 0x00000200
160 161 #define PACKET_CT_SWAPPED 0x00000400
161 162 #define PACKET_CSP_SWAPPED 0x00000800
162 163 #endif /* EMLXS_I386 */
163 164
164 165 #define PACKET_STALE 0x00001000
165 166
166 167 #define PACKET_IN_TIMEOUT 0x00010000
167 168 #define PACKET_IN_FLUSH 0x00020000
168 169 #define PACKET_IN_ABORT 0x00040000
169 170 #define PACKET_XRI_CLOSED 0x00080000 /* An XRI abort/close was issued */
170 171
171 172 #define PACKET_CHIP_COMP 0x00100000
172 173 #define PACKET_COMPLETED 0x00200000
173 174 #define PACKET_ULP_OWNED 0x00400000
174 175
175 176 #define PACKET_STATE_VALID 0x01000000
176 177 #define PACKET_FCP_RSP_VALID 0x02000000
177 178 #define PACKET_ELS_RSP_VALID 0x04000000
178 179 #define PACKET_CT_RSP_VALID 0x08000000
179 180
180 181 #define PACKET_DELAY_REQUIRED 0x10000000
181 182 #define PACKET_ALLOCATED 0x40000000
182 183 #define PACKET_VALID 0x80000000
183 184
184 185
185 186 #define STALE_PACKET ((emlxs_buf_t *)0xFFFFFFFF)
186 187
187 188
188 189 /*
189 190 * From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT,
190 191 * NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT)
191 192 *
192 193 * FCA unique error codes can begin after FC_REASON_FCA_UNIQUE.
193 194 * Each FCA defines its own set with values greater >= 0x7F
194 195 */
195 196 #define FC_REASON_FCA_DEFINED 0x100
196 197
197 198
198 199 /*
199 200 * Device VPD save area
200 201 */
201 202
202 203 typedef struct emlxs_vpd
203 204 {
204 205 uint32_t biuRev;
205 206 uint32_t smRev;
206 207 uint32_t smFwRev;
207 208 uint32_t endecRev;
208 209 uint16_t rBit;
209 210 uint8_t fcphHigh;
210 211 uint8_t fcphLow;
211 212 uint8_t feaLevelHigh;
212 213 uint8_t feaLevelLow;
213 214
214 215 uint32_t postKernRev;
215 216 char postKernName[32];
216 217
217 218 uint32_t opFwRev;
218 219 char opFwName[32];
219 220 char opFwLabel[32];
220 221
221 222 uint32_t sli1FwRev;
222 223 char sli1FwName[32];
223 224 char sli1FwLabel[32];
224 225
225 226 uint32_t sli2FwRev;
226 227 char sli2FwName[32];
227 228 char sli2FwLabel[32];
228 229
229 230 uint32_t sli3FwRev;
230 231 char sli3FwName[32];
231 232 char sli3FwLabel[32];
232 233
233 234 uint32_t sli4FwRev;
234 235 char sli4FwName[32];
235 236 char sli4FwLabel[32];
236 237
237 238 char fw_version[32];
238 239 char fw_label[32];
239 240
240 241 char fcode_version[32];
241 242 char boot_version[32];
242 243
243 244 char serial_num[32];
244 245 char part_num[32];
245 246 char port_num[20];
246 247 char eng_change[32];
247 248 char manufacturer[80];
248 249 char model[80];
249 250 char model_desc[256];
250 251 char prog_types[256];
251 252 char id[256];
252 253
253 254 uint32_t port_index;
254 255 uint16_t link_speed;
255 256 } emlxs_vpd_t;
256 257
257 258
258 259 typedef struct emlxs_queue
259 260 {
260 261 void *q_first; /* queue first element */
261 262 void *q_last; /* queue last element */
262 263 uint16_t q_cnt; /* current length of queue */
263 264 uint16_t q_max; /* max length queue can get */
264 265 } emlxs_queue_t;
265 266 typedef emlxs_queue_t Q;
266 267
267 268
268 269
269 270 /*
270 271 * This structure is used when allocating a buffer pool.
271 272 * Note: this should be identical to gasket buf_info (fldl.h).
272 273 */
273 274 typedef struct emlxs_buf_info
274 275 {
275 276 int32_t size; /* Specifies the number of bytes to allocate. */
276 277 int32_t align; /* The desired address boundary. */
277 278
278 279 int32_t flags;
279 280
280 281 #define FC_MBUF_DMA 0x01 /* blocks are for DMA */
281 282 #define FC_MBUF_PHYSONLY 0x02 /* For malloc - map a given virtual */
282 283 /* address to physical address (skip */
283 284 /* the malloc). */
284 285 /* For free - just unmap the given */
285 286 /* physical address (skip the free). */
286 287 #define FC_MBUF_IOCTL 0x04 /* called from dfc_ioctl */
287 288 #define FC_MBUF_UNLOCK 0x08 /* called with driver unlocked */
288 289 #define FC_MBUF_SNGLSG 0x10 /* allocate a single contiguous */
289 290 /* physical memory */
290 291 #define FC_MBUF_DMA32 0x20
291 292
292 293 uint64_t phys; /* specifies physical buffer pointer */
293 294 void *virt; /* specifies virtual buffer pointer */
294 295 void *data_handle;
295 296 void *dma_handle;
296 297 } emlxs_buf_info_t;
297 298 typedef emlxs_buf_info_t MBUF_INFO;
298 299
299 300
300 301 #define EMLXS_MAX_HBQ 16 /* Max HBQs handled by firmware */
301 302 #define EMLXS_ELS_HBQ_ID 0
302 303 #define EMLXS_IP_HBQ_ID 1
303 304 #define EMLXS_CT_HBQ_ID 2
304 305 #define EMLXS_FCT_HBQ_ID 3
305 306
306 307 #ifdef SFCT_SUPPORT
307 308 #define EMLXS_NUM_HBQ 4 /* Number of HBQs supported by driver */
308 309 #else
309 310 #define EMLXS_NUM_HBQ 3 /* Number of HBQs supported by driver */
310 311 #endif /* SFCT_SUPPORT */
311 312
312 313
313 314 /*
314 315 * An IO Channel is a object that comprises a xmit/cmpl
315 316 * path for IOs.
316 317 * For SLI3, an IO path maps to a ring (cmd/rsp)
317 318 * For SLI4, an IO path map to a queue pair (WQ/CQ)
318 319 */
319 320 typedef struct emlxs_channel
320 321 {
321 322 struct emlxs_hba *hba; /* ptr to hba for channel */
322 323 void *iopath; /* ptr to SLI3/4 io path */
323 324
324 325 kmutex_t rsp_lock;
325 326 IOCBQ *rsp_head; /* deferred completion head */
326 327 IOCBQ *rsp_tail; /* deferred completion tail */
327 328 emlxs_thread_t intr_thread;
328 329
329 330
330 331 uint16_t channelno;
331 332 uint16_t chan_flag;
332 333
333 334 #define EMLXS_NEEDS_TRIGGER 1
334 335
335 336 /* Protected by EMLXS_TX_CHANNEL_LOCK */
336 337 emlxs_queue_t nodeq; /* Node service queue */
337 338
338 339 kmutex_t channel_cmd_lock;
339 340 uint32_t timeout;
340 341
341 342 /* Channel command counters */
342 343 uint32_t ulpSendCmd;
343 344 uint32_t ulpCmplCmd;
344 345 uint32_t hbaSendCmd;
345 346 uint32_t hbaCmplCmd;
346 347 uint32_t hbaSendCmd_sbp;
347 348 uint32_t hbaCmplCmd_sbp;
348 349
349 350 } emlxs_channel_t;
350 351 typedef emlxs_channel_t CHANNEL;
351 352
352 353 /*
353 354 * Should be able to handle max number of io paths for a
354 355 * SLI4 HBA (EMLXS_MAX_WQS) or for a SLI3 HBA (MAX_RINGS)
355 356 */
356 357 #define MAX_CHANNEL EMLXS_MSI_MAX_INTRS
357 358
358 359
359 360 /* Structure used to access adapter rings */
360 361 typedef struct emlxs_ring
361 362 {
362 363 void *fc_cmdringaddr; /* virtual offset for cmd */
363 364 /* rings */
364 365 void *fc_rspringaddr; /* virtual offset for rsp */
365 366 /* rings */
366 367
367 368 void *fc_mpon; /* index ptr for match */
368 369 /* structure */
369 370 void *fc_mpoff; /* index ptr for match */
370 371 /* structure */
371 372 struct emlxs_hba *hba; /* ptr to hba for ring */
372 373
373 374 uint8_t fc_numCiocb; /* number of command iocb's */
374 375 /* per ring */
375 376 uint8_t fc_numRiocb; /* number of response iocb's */
376 377 /* per ring */
377 378 uint8_t fc_rspidx; /* current index in response */
378 379 /* ring */
379 380 uint8_t fc_cmdidx; /* current index in command */
380 381 /* ring */
381 382 uint8_t fc_port_rspidx;
382 383 uint8_t fc_port_cmdidx;
383 384 uint8_t ringno;
384 385
385 386 uint16_t fc_missbufcnt; /* buf cnt we need to repost */
386 387 CHANNEL *channelp;
387 388
388 389
389 390 } emlxs_ring_t;
390 391 typedef emlxs_ring_t RING;
391 392
392 393
393 394 #ifdef SAN_DIAG_SUPPORT
394 395 /*
395 396 * Although right now it's just 1 field, SAN Diag anticipates that this
396 397 * structure will grow in the future.
397 398 */
398 399 typedef struct sd_timestat_level0 {
399 400 int count;
400 401 } sd_timestat_level0_t;
401 402 #endif
402 403
403 404 typedef struct emlxs_node
404 405 {
405 406 struct emlxs_node *nlp_list_next;
406 407 struct emlxs_node *nlp_list_prev;
407 408
408 409 NAME_TYPE nlp_portname; /* port name */
409 410 NAME_TYPE nlp_nodename; /* node name */
410 411
411 412 uint32_t nlp_DID; /* fibre channel D_ID */
412 413
413 414 uint16_t nlp_Rpi; /* login id returned by */
414 415 /* REG_LOGIN */
415 416 uint16_t nlp_Xri; /* login id returned by */
416 417 /* REG_LOGIN */
417 418
418 419 uint8_t nlp_fcp_info; /* Remote class info */
419 420
420 421 /* nlp_fcp_info */
421 422 #define NLP_FCP_TGT_DEVICE 0x10 /* FCP TGT device */
422 423 #define NLP_FCP_INI_DEVICE 0x20 /* FCP Initiator device */
423 424 #define NLP_FCP_2_DEVICE 0x40 /* FCP-2 TGT device */
424 425 #define NLP_EMLX_VPORT 0x80 /* Virtual port */
425 426
426 427 uint8_t dfc_state;
427 428 #define EMLXS_SET_DFC_STATE(_n, _state) if (_n && _n->nlp_active)\
428 429 {(_n)->dfc_state = (_state); }
429 430
430 431 uint32_t nlp_force_rscn;
431 432 uint32_t nlp_tag; /* Tag used by port_offline */
432 433 uint32_t flag;
433 434
434 435 #define NODE_POOL_ALLOCATED 0x00000001
435 436
436 437 SERV_PARM sparm;
437 438
438 439 /* Protected by EMLXS_TX_CHANNEL_LOCK */
439 440 uint32_t nlp_active; /* Node active flag */
440 441 uint32_t nlp_base;
441 442 uint32_t nlp_flag[MAX_CHANNEL]; /* Node level channel */
442 443 /* flags */
443 444
444 445 /* nlp_flag */
445 446 #define NLP_CLOSED 0x1
446 447 #define NLP_OFFLINE 0x2
447 448 #define NLP_RPI_XRI 0x4
448 449
449 450 uint32_t nlp_tics[MAX_CHANNEL]; /* gate timeout */
450 451 emlxs_queue_t nlp_tx[MAX_CHANNEL]; /* Transmit Q head */
451 452 emlxs_queue_t nlp_ptx[MAX_CHANNEL]; /* Priority transmit */
452 453 /* Queue head */
453 454 void *nlp_next[MAX_CHANNEL]; /* Service Request */
454 455 /* Queue pointer used */
455 456 /* when node needs */
456 457 /* servicing */
457 458 #ifdef DHCHAP_SUPPORT
458 459 emlxs_node_dhc_t node_dhc;
459 460 #endif /* DHCHAP_SUPPORT */
460 461
461 462 #ifdef SAN_DIAG_SUPPORT
462 463 sd_timestat_level0_t sd_dev_bucket[SD_IO_LATENCY_MAX_BUCKETS];
463 464 #endif
464 465
465 466 struct RPIobj *rpip; /* SLI4 only */
466 467 #define EMLXS_NODE_TO_RPI(_p, _n) \
467 468 ((_n)?((_n->rpip)?_n->rpip:emlxs_rpi_find(_p, _n->nlp_Rpi)):NULL)
468 469
469 470 #ifdef NODE_THROTTLE_SUPPORT
470 471 uint32_t io_throttle;
471 472 uint32_t io_active;
472 473 #endif /* NODE_THROTTLE_SUPPORT */
473 474
474 475 } emlxs_node_t;
475 476 typedef emlxs_node_t NODELIST;
476 477
477 478
478 479
479 480 #define NADDR_LEN 6 /* MAC network address length */
480 481 typedef struct emlxs_fcip_nethdr
481 482 {
482 483 NAME_TYPE fc_destname; /* destination port name */
483 484 NAME_TYPE fc_srcname; /* source port name */
484 485 } emlxs_fcip_nethdr_t;
485 486 typedef emlxs_fcip_nethdr_t NETHDR;
486 487
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487 488
488 489 #define MEM_NLP 0 /* memory segment to hold node list entries */
489 490 #define MEM_IOCB 1 /* memory segment to hold iocb commands */
490 491 #define MEM_MBOX 2 /* memory segment to hold mailbox cmds */
491 492 #define MEM_BPL 3 /* and to hold buffer ptr lists - SLI2 */
492 493 #define MEM_BUF 4 /* memory segment to hold buffer data */
493 494 #define MEM_ELSBUF 4 /* memory segment to hold buffer data */
494 495 #define MEM_IPBUF 5 /* memory segment to hold IP buffer data */
495 496 #define MEM_CTBUF 6 /* memory segment to hold CT buffer data */
496 497 #define MEM_FCTBUF 7 /* memory segment to hold FCT buffer data */
498 +#define MEM_SGL1K 8 /* memory segment to hold 1K SGL entries */
499 +#define MEM_SGL2K 9 /* memory segment to hold 2K SGL entries */
500 +#define MEM_SGL4K 10 /* memory segment to hold 4K SGL entries */
497 501
498 502 #ifdef SFCT_SUPPORT
499 -#define FC_MAX_SEG 8
500 -#define MEM_FCTSEG 10 /* must be greater than FC_MAX_SEG */
503 +#define FC_MAX_SEG 11
504 +#define MEM_FCTSEG 13 /* must be greater than FC_MAX_SEG */
501 505 #else
502 -#define FC_MAX_SEG 7
506 +#define FC_MAX_SEG 10
503 507 #endif /* SFCT_SUPPORT */
504 508
505 509
506 510 /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
507 511 #define BPL_TO_SGLLEN(_bpl) ((_bpl/12)-2)
508 512 #define MEM_BPL_SIZE 36 /* Default size */
509 513
510 514 /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
511 515 #define SGL_TO_SGLLEN(_sgl) ((_sgl/16)-2)
512 516 #define MEM_SGL_SIZE 4096 /* Default size */
513 517
514 518 #define MEM_BUF_SIZE 1024
515 519 #define MEM_BUF_COUNT 64
516 520
517 521 #define MEM_ELSBUF_SIZE MEM_BUF_SIZE
518 522 #define MEM_ELSBUF_COUNT hba->max_nodes
519 523 #define MEM_IPBUF_SIZE 65535
520 524 #define MEM_IPBUF_COUNT 60
521 525 #define MEM_CTBUF_SIZE MAX_CT_PAYLOAD /* (1024*320) */
522 526 #define MEM_CTBUF_COUNT 8
523 527 #define MEM_FCTBUF_SIZE 65535
524 528 #define MEM_FCTBUF_COUNT 128
525 529
526 530 typedef struct emlxs_memseg
527 531 {
528 532 void *fc_memget_ptr;
529 533 void *fc_memget_end;
530 534 void *fc_memput_ptr;
531 535 void *fc_memput_end;
532 536
533 537 uint32_t fc_total_memsize;
534 538 uint32_t fc_memsize; /* size of mem blks */
535 539 uint32_t fc_numblks; /* no of mem blks */
536 540 uint32_t fc_memget_cnt; /* no of mem get blks */
537 541 uint32_t fc_memput_cnt; /* no of mem put blks */
538 542 uint32_t fc_memflag; /* emlxs_buf_info_t FLAGS */
539 543 #define FC_MEMSEG_PUT_ENABLED 0x20000000
540 544 #define FC_MEMSEG_GET_ENABLED 0x40000000
541 545 #define FC_MEMSEG_DYNAMIC 0x80000000
542 546
543 547 uint32_t fc_memalign;
544 548 uint32_t fc_memtag;
545 549 char fc_label[32];
546 550
547 551 uint32_t fc_hi_water;
548 552 uint32_t fc_lo_water;
549 553 uint32_t fc_step; /* Dyn increment. Zero = static */
550 554 uint32_t fc_low; /* Lowest free count (dyn only) */
551 555 uint32_t fc_last; /* Last fc_numblks (dyn only) */
552 556
553 557 } emlxs_memseg_t;
554 558 typedef emlxs_memseg_t MEMSEG;
555 559
556 560
557 561 /* Board stat counters */
558 562 typedef struct emlxs_stats
559 563 {
560 564 uint32_t LinkUp;
561 565 uint32_t LinkDown;
562 566 uint32_t LinkEvent;
563 567 uint32_t LinkMultiEvent;
564 568
565 569 uint32_t MboxIssued;
566 570 uint32_t MboxCompleted; /* MboxError + MbxGood */
567 571 uint32_t MboxGood;
568 572 uint32_t MboxError;
569 573 uint32_t MboxBusy;
570 574 uint32_t MboxInvalid;
571 575
572 576 uint32_t IocbIssued[MAX_CHANNEL];
573 577 uint32_t IocbReceived[MAX_CHANNEL];
574 578 uint32_t IocbTxPut[MAX_CHANNEL];
575 579 uint32_t IocbTxGet[MAX_CHANNEL];
576 580 uint32_t IocbRingFull[MAX_CHANNEL];
577 581 uint32_t IocbThrottled;
578 582
579 583 uint32_t IntrEvent[8];
580 584
581 585 uint32_t FcpIssued;
582 586 uint32_t FcpCompleted; /* FcpGood + FcpError */
583 587 uint32_t FcpGood;
584 588 uint32_t FcpError;
585 589
586 590 uint32_t FcpEvent; /* FcpStray + FcpCompleted */
587 591 uint32_t FcpStray;
588 592 #ifdef SFCT_SUPPORT
589 593 uint32_t FctRingEvent;
590 594 uint32_t FctRingError;
591 595 uint32_t FctRingDropped;
592 596 #endif /* SFCT_SUPPORT */
593 597
594 598 uint32_t ElsEvent; /* ElsStray + ElsCmplt (cmd + rsp) */
595 599 uint32_t ElsStray;
596 600
597 601 uint32_t ElsCmdIssued;
598 602 uint32_t ElsCmdCompleted; /* ElsCmdGood + ElsCmdError */
599 603 uint32_t ElsCmdGood;
600 604 uint32_t ElsCmdError;
601 605
602 606 uint32_t ElsRspIssued;
603 607 uint32_t ElsRspCompleted;
604 608
605 609 uint32_t ElsRcvEvent; /* ElsRcvErr + ElsRcvDrop + ElsCmdRcv */
606 610 uint32_t ElsRcvError;
607 611 uint32_t ElsRcvDropped;
608 612 uint32_t ElsCmdReceived; /* ElsRscnRcv + ElsPlogiRcv + ... */
609 613 uint32_t ElsRscnReceived;
610 614 uint32_t ElsFlogiReceived;
611 615 uint32_t ElsPlogiReceived;
612 616 uint32_t ElsPrliReceived;
613 617 uint32_t ElsPrloReceived;
614 618 uint32_t ElsLogoReceived;
615 619 uint32_t ElsAdiscReceived;
616 620 uint32_t ElsAuthReceived;
617 621 uint32_t ElsGenReceived;
618 622
619 623 uint32_t CtEvent; /* CtStray + CtCompleted (cmd + rsp) */
620 624 uint32_t CtStray;
621 625
622 626 uint32_t CtCmdIssued;
623 627 uint32_t CtCmdCompleted; /* CtCmdGood + CtCmdError */
624 628 uint32_t CtCmdGood;
625 629 uint32_t CtCmdError;
626 630
627 631 uint32_t CtRspIssued;
628 632 uint32_t CtRspCompleted;
629 633
630 634 uint32_t CtRcvEvent; /* CtRcvError + CtRcvDrop + CtCmdRcvd */
631 635 uint32_t CtRcvError;
632 636 uint32_t CtRcvDropped;
633 637 uint32_t CtCmdReceived;
634 638
635 639 uint32_t IpEvent; /* IpStray + IpSeqCmpl + IpBcastCmpl */
636 640 uint32_t IpStray;
637 641
638 642 uint32_t IpSeqIssued;
639 643 uint32_t IpSeqCompleted; /* IpSeqGood + IpSeqError */
640 644 uint32_t IpSeqGood;
641 645 uint32_t IpSeqError;
642 646
643 647 uint32_t IpBcastIssued;
644 648 uint32_t IpBcastCompleted; /* IpBcastGood + IpBcastError */
645 649 uint32_t IpBcastGood;
646 650 uint32_t IpBcastError;
647 651
648 652 uint32_t IpRcvEvent; /* IpDrop + IpSeqRcv + IpBcastRcv */
649 653 uint32_t IpDropped;
650 654 uint32_t IpSeqReceived;
651 655 uint32_t IpBcastReceived;
652 656
653 657 uint32_t IpUbPosted;
654 658 uint32_t ElsUbPosted;
655 659 uint32_t CtUbPosted;
656 660 #ifdef SFCT_SUPPORT
657 661 uint32_t FctUbPosted;
658 662 #endif /* SFCT_SUPPORT */
659 663
660 664 uint32_t ResetTime; /* Time of last reset */
661 665
662 666 uint32_t ElsTestReceived;
663 667 uint32_t ElsEstcReceived;
664 668 uint32_t ElsFarprReceived;
665 669 uint32_t ElsEchoReceived;
666 670 uint32_t ElsRlsReceived;
667 671 uint32_t ElsRtvReceived;
668 672
669 673 } emlxs_stats_t;
670 674
671 675
672 676 #define FC_MAX_ADPTMSG (8*28) /* max size of a msg from adapter */
673 677
674 678 #define EMLXS_NUM_THREADS 8
675 679 #define EMLXS_MIN_TASKS 8
676 680 #define EMLXS_MAX_TASKS 8
677 681
678 682 #define EMLXS_NUM_HASH_QUES 32
679 683 #define EMLXS_DID_HASH(x) ((x) & (EMLXS_NUM_HASH_QUES - 1))
680 684
681 685
682 686 /* pkt_tran_flag */
683 687 #define FC_TRAN_COMPLETED 0x8000
684 688
685 689
686 690 typedef struct emlxs_dfc_event
687 691 {
688 692 uint32_t pid;
689 693 uint32_t event;
690 694 uint32_t last_id;
691 695
692 696 void *dataout;
693 697 uint32_t size;
694 698 uint32_t mode;
695 699 } emlxs_dfc_event_t;
696 700
697 701
698 702 typedef struct emlxs_hba_event
699 703 {
700 704 uint32_t last_id;
701 705 uint32_t new;
702 706 uint32_t missed;
703 707 } emlxs_hba_event_t;
704 708
705 709
706 710 #ifdef SFCT_SUPPORT
707 711
708 712 #define TGTPORTSTAT port->fct_stat
709 713
710 714 /*
711 715 * FctP2IOXcnt will count IOs by their fcpDL. Counters
712 716 * are for buckets of various power of 2 sizes.
713 717 * Bucket 0 < 512 > 0
714 718 * Bucket 1 >= 512 < 1024
715 719 * Bucket 2 >= 1024 < 2048
716 720 * Bucket 3 >= 2048 < 4096
717 721 * Bucket 4 >= 4096 < 8192
718 722 * Bucket 5 >= 8192 < 16K
719 723 * Bucket 6 >= 16K < 32K
720 724 * Bucket 7 >= 32K < 64K
721 725 * Bucket 8 >= 64K < 128K
722 726 * Bucket 9 >= 128K < 256K
723 727 * Bucket 10 >= 256K < 512K
724 728 * Bucket 11 >= 512K < 1MB
725 729 * Bucket 12 >= 1MB < 2MB
726 730 * Bucket 13 >= 2MB < 4MB
727 731 * Bucket 14 >= 4MB < 8MB
728 732 * Bucket 15 >= 8MB
729 733 */
730 734 #define MAX_TGTPORT_IOCNT 16
731 735
732 736
733 737 /*
734 738 * These routines will bump the right counter, based on
735 739 * the size of the IO inputed, with the least number of
736 740 * comparisions. A max of 5 comparisions is only needed
737 741 * to classify the IO in one of 16 ranges. A binary search
738 742 * to locate the high bit in the size is used.
739 743 */
740 744 #define EMLXS_BUMP_RDIOCTR(port, cnt) \
741 745 { \
742 746 /* Use binary search to find the first high bit */ \
743 747 if (cnt & 0xffff0000) { \
744 748 if (cnt & 0xff800000) { \
745 749 TGTPORTSTAT.FctP2IORcnt[15]++; \
746 750 } \
747 751 else { \
748 752 /* It must be 0x007f0000 */ \
749 753 if (cnt & 0x00700000) { \
750 754 if (cnt & 0x00400000) { \
751 755 TGTPORTSTAT.FctP2IORcnt[14]++; \
752 756 } \
753 757 else { \
754 758 /* it must be 0x00300000 */ \
755 759 if (cnt & 0x00200000) { \
756 760 TGTPORTSTAT.FctP2IORcnt[13]++; \
757 761 } \
758 762 else { \
759 763 /* It must be 0x00100000 */ \
760 764 TGTPORTSTAT.FctP2IORcnt[12]++; \
761 765 } \
762 766 } \
763 767 } \
764 768 else { \
765 769 /* It must be 0x000f0000 */ \
766 770 if (cnt & 0x000c0000) { \
767 771 if (cnt & 0x00080000) { \
768 772 TGTPORTSTAT.FctP2IORcnt[11]++; \
769 773 } \
770 774 else { \
771 775 /* It must be 0x00040000 */ \
772 776 TGTPORTSTAT.FctP2IORcnt[10]++; \
773 777 } \
774 778 } \
775 779 else { \
776 780 /* It must be 0x00030000 */ \
777 781 if (cnt & 0x00020000) { \
778 782 TGTPORTSTAT.FctP2IORcnt[9]++; \
779 783 } \
780 784 else { \
781 785 /* It must be 0x00010000 */ \
782 786 TGTPORTSTAT.FctP2IORcnt[8]++; \
783 787 } \
784 788 } \
785 789 } \
786 790 } \
787 791 } \
788 792 else { \
789 793 if (cnt & 0x0000fe00) { \
790 794 if (cnt & 0x0000f000) { \
791 795 if (cnt & 0x0000c000) { \
792 796 if (cnt & 0x00008000) { \
793 797 TGTPORTSTAT.FctP2IORcnt[7]++; \
794 798 } \
795 799 else { \
796 800 /* It must be 0x00004000 */ \
797 801 TGTPORTSTAT.FctP2IORcnt[6]++; \
798 802 } \
799 803 } \
800 804 else { \
801 805 /* It must be 0x00000300 */ \
802 806 if (cnt & 0x00000200) { \
803 807 TGTPORTSTAT.FctP2IORcnt[5]++; \
804 808 } \
805 809 else { \
806 810 /* It must be 0x00000100 */ \
807 811 TGTPORTSTAT.FctP2IORcnt[4]++; \
808 812 } \
809 813 } \
810 814 } \
811 815 else { \
812 816 /* It must be 0x00000e00 */ \
813 817 if (cnt & 0x00000800) { \
814 818 TGTPORTSTAT.FctP2IORcnt[3]++; \
815 819 } \
816 820 else { \
817 821 /* It must be 0x00000600 */ \
818 822 if (cnt & 0x00000400) { \
819 823 TGTPORTSTAT.FctP2IORcnt[2]++; \
820 824 } \
821 825 else { \
822 826 /* It must be 0x00000200 */ \
823 827 TGTPORTSTAT.FctP2IORcnt[1]++; \
824 828 } \
825 829 } \
826 830 } \
827 831 } \
828 832 else { \
829 833 /* It must be 0x000001ff */ \
830 834 TGTPORTSTAT.FctP2IORcnt[0]++; \
831 835 } \
832 836 } \
833 837 }
834 838
835 839
836 840 #define EMLXS_BUMP_WRIOCTR(port, cnt) \
837 841 { \
838 842 /* Use binary search to find the first high bit */ \
839 843 if (cnt & 0xffff0000) { \
840 844 if (cnt & 0xff800000) { \
841 845 TGTPORTSTAT.FctP2IOWcnt[15]++; \
842 846 } \
843 847 else { \
844 848 /* It must be 0x007f0000 */ \
845 849 if (cnt & 0x00700000) { \
846 850 if (cnt & 0x00400000) { \
847 851 TGTPORTSTAT.FctP2IOWcnt[14]++; \
848 852 } \
849 853 else { \
850 854 /* It must be 0x00300000 */ \
851 855 if (cnt & 0x00200000) { \
852 856 TGTPORTSTAT.FctP2IOWcnt[13]++; \
853 857 } \
854 858 else { \
855 859 /* It must be 0x00100000 */ \
856 860 TGTPORTSTAT.FctP2IOWcnt[12]++; \
857 861 } \
858 862 } \
859 863 } \
860 864 else { \
861 865 /* It must be 0x000f0000 */ \
862 866 if (cnt & 0x000c0000) { \
863 867 if (cnt & 0x00080000) { \
864 868 TGTPORTSTAT.FctP2IOWcnt[11]++; \
865 869 } \
866 870 else { \
867 871 /* it must be 0x00040000 */ \
868 872 TGTPORTSTAT.FctP2IOWcnt[10]++; \
869 873 } \
870 874 } \
871 875 else { \
872 876 /* It must be 0x00030000 */ \
873 877 if (cnt & 0x00020000) { \
874 878 TGTPORTSTAT.FctP2IOWcnt[9]++; \
875 879 } \
876 880 else { \
877 881 /* It must be 0x00010000 */ \
878 882 TGTPORTSTAT.FctP2IOWcnt[8]++; \
879 883 } \
880 884 } \
881 885 } \
882 886 } \
883 887 } \
884 888 else { \
885 889 if (cnt & 0x0000fe00) { \
886 890 if (cnt & 0x0000f000) { \
887 891 if (cnt & 0x0000c000) { \
888 892 if (cnt & 0x00008000) { \
889 893 TGTPORTSTAT.FctP2IOWcnt[7]++; \
890 894 } \
891 895 else { \
892 896 /* It must be 0x00004000 */ \
893 897 TGTPORTSTAT.FctP2IOWcnt[6]++; \
894 898 } \
895 899 } \
896 900 else { \
897 901 /* It must be 0x00000300 */ \
898 902 if (cnt & 0x00000200) { \
899 903 TGTPORTSTAT.FctP2IOWcnt[5]++; \
900 904 } \
901 905 else { \
902 906 /* It must be 0x00000100 */ \
903 907 TGTPORTSTAT.FctP2IOWcnt[4]++; \
904 908 } \
905 909 } \
906 910 } \
907 911 else { \
908 912 /* It must be 0x00000e00 */ \
909 913 if (cnt & 0x00000800) { \
910 914 TGTPORTSTAT.FctP2IOWcnt[3]++; \
911 915 } \
912 916 else { \
913 917 /* It must be 0x00000600 */ \
914 918 if (cnt & 0x00000400) { \
915 919 TGTPORTSTAT.FctP2IOWcnt[2]++; \
916 920 } \
917 921 else { \
918 922 /* It must be 0x00000200 */ \
919 923 TGTPORTSTAT.FctP2IOWcnt[1]++; \
920 924 } \
921 925 } \
922 926 } \
923 927 } \
924 928 else { \
925 929 /* It must be 0x000001ff */ \
926 930 TGTPORTSTAT.FctP2IOWcnt[0]++; \
927 931 } \
928 932 } \
929 933 }
930 934
931 935 typedef struct emlxs_tgtport_stat
932 936 {
933 937 /* IO counters */
934 938 uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */
935 939 uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */
936 940 uint64_t FctIOCmdCnt; /* Other, ie TUR */
937 941 uint64_t FctCmdReceived; /* total IOs */
938 942 uint64_t FctReadBytes; /* total read bytes */
939 943 uint64_t FctWriteBytes; /* total write bytes */
940 944
941 945 /* IOCB handling counters */
942 946 uint64_t FctEvent; /* FctStray + FctCompleted */
943 947 uint64_t FctCompleted; /* FctCmplGood + FctCmplError */
944 948 uint64_t FctCmplGood;
945 949
946 950 uint32_t FctCmplError;
947 951 uint32_t FctStray;
948 952
949 953 /* Fct event counters */
950 954 uint32_t FctRcvDropped;
951 955 uint32_t FctOverQDepth;
952 956 uint32_t FctOutstandingIO;
953 957 uint32_t FctFailedPortRegister;
954 958 uint32_t FctPortRegister;
955 959 uint32_t FctPortDeregister;
956 960
957 961 uint32_t FctAbortSent;
958 962 uint32_t FctNoBuffer;
959 963 uint32_t FctScsiStatusErr;
960 964 uint32_t FctScsiQfullErr;
961 965 uint32_t FctScsiResidOver;
962 966 uint32_t FctScsiResidUnder;
963 967 uint32_t FctScsiSenseErr;
964 968
965 969 uint32_t FctFiller1;
966 970 } emlxs_tgtport_stat_t;
967 971
968 972 #ifdef FCT_IO_TRACE
969 973 #define MAX_IO_TRACE 67
970 974 typedef struct emlxs_iotrace
971 975 {
972 976 fct_cmd_t *fct_cmd;
973 977 uint32_t xri;
974 978 uint8_t marker; /* 0xff */
975 979 uint8_t trc[MAX_IO_TRACE]; /* trc[0] = index */
976 980 } emlxs_iotrace_t;
977 981 #endif /* FCT_IO_TRACE */
978 982 #endif /* SFCT_SUPPORT */
979 983
980 984
981 985 #include <emlxs_fcf.h>
982 986
983 987 /*
984 988 * Port Information Data Structure
985 989 */
986 990
987 991 typedef struct emlxs_port
988 992 {
989 993 struct emlxs_hba *hba;
990 994
991 995 /* Virtual port management */
992 996 struct VPIobj VPIobj;
993 997 struct VPIobj *vpip; /* &VPIobj */
994 998
995 999 uint32_t vpi; /* Legacy vpi == vpip->index */
996 1000 uint32_t mode;
997 1001 uint32_t mode_mask; /* User configured */
998 1002 #define MODE_NONE 0x00000000
999 1003 #define MODE_INITIATOR 0x00000001
1000 1004 #define MODE_TARGET 0x00000002
1001 1005 #define MODE_ALL 0x00000003
1002 1006
1003 1007 uint32_t flag;
1004 1008 #define EMLXS_PORT_ENABLED 0x00000001 /* vport setting */
1005 1009 #define EMLXS_PORT_CONFIG 0x00000002 /* vport setting */
1006 1010
1007 1011 #define EMLXS_INI_ENABLED 0x00000010 /* emlxs_mode_init */
1008 1012 #define EMLXS_INI_BOUND 0x00000020 /* emlxs_fca_bind_port */
1009 1013 #define EMLXS_TGT_ENABLED 0x00000040 /* emlxs_mode_init */
1010 1014 #define EMLXS_TGT_BOUND 0x00000080 /* emlxs_fct_bind_port */
1011 1015 #define EMLXS_PORT_BOUND (EMLXS_INI_BOUND|EMLXS_TGT_BOUND)
1012 1016
1013 1017 #define EMLXS_PORT_IP_UP 0x00000100
1014 1018 #define EMLXS_PORT_RESTRICTED 0x00000200 /* Restrict logins */
1015 1019
1016 1020 #define EMLXS_PORT_REG_VPI 0x00010000 /* SLI3 */
1017 1021 #define EMLXS_PORT_REG_VPI_CMPL 0x00020000 /* SLI3 */
1018 1022
1019 1023 #define EMLXS_PORT_FLOGI_CMPL 0x01000000 /* Fabric login */
1020 1024 /* completed */
1021 1025
1022 1026 #define EMLXS_PORT_RESET_MASK 0x0000FFFF /* Flags to keep */
1023 1027 /* across hard reset */
1024 1028 #define EMLXS_PORT_LINKDOWN_MASK 0x00FFFFFF /* Flags to keep */
1025 1029 /* across link reset */
1026 1030
1027 1031 uint32_t options;
1028 1032 #define EMLXS_OPT_RESTRICT 0x00000001 /* Force restricted */
1029 1033 /* logins */
1030 1034 #define EMLXS_OPT_UNRESTRICT 0x00000002 /* Force Unrestricted */
1031 1035 /* logins */
1032 1036 #define EMLXS_OPT_RESTRICT_MASK 0x00000003
1033 1037
1034 1038
1035 1039 /* FC world wide names */
1036 1040 NAME_TYPE wwnn;
1037 1041 NAME_TYPE wwpn;
1038 1042 char snn[256];
1039 1043 char spn[256];
1040 1044
1041 1045 /* Common service paramters */
1042 1046 SERV_PARM sparam;
1043 1047 SERV_PARM fabric_sparam;
1044 1048 SERV_PARM prev_fabric_sparam;
1045 1049
1046 1050 /* fc_id management */
1047 1051 uint32_t did;
1048 1052 uint32_t prev_did;
1049 1053
1050 1054 /* support FC_PORT_GET_P2P_INFO only */
1051 1055 uint32_t rdid;
1052 1056
1053 1057 /* FC_AL management */
1054 1058 uint8_t lip_type;
1055 1059 uint8_t granted_alpa;
1056 1060 uint8_t alpa_map[128];
1057 1061
1058 1062 /* Node management */
1059 1063 emlxs_node_t node_base;
1060 1064 uint32_t node_count;
1061 1065 krwlock_t node_rwlock;
1062 1066 emlxs_node_t *node_table[EMLXS_NUM_HASH_QUES];
1063 1067
1064 1068 /* Polled packet management */
1065 1069 kcondvar_t pkt_lock_cv; /* pkt polling */
1066 1070 kmutex_t pkt_lock; /* pkt polling */
1067 1071
1068 1072 /* ULP */
1069 1073 uint32_t ulp_busy;
1070 1074 uint32_t ulp_statec;
1071 1075 void (*ulp_statec_cb) (); /* Port state change */
1072 1076 /* callback routine */
1073 1077 void (*ulp_unsol_cb) (); /* unsolicited event */
1074 1078 /* callback routine */
1075 1079 opaque_t ulp_handle;
1076 1080
1077 1081 /* ULP unsolicited buffers */
1078 1082 kmutex_t ub_lock;
1079 1083 uint32_t ub_count;
1080 1084 emlxs_unsol_buf_t *ub_pool;
1081 1085 uint32_t ub_post[MAX_CHANNEL];
1082 1086 uint32_t ub_timer;
1083 1087
1084 1088 emlxs_ub_priv_t *ub_wait_head; /* Unsolicited IO received */
1085 1089 /* before link up */
1086 1090 emlxs_ub_priv_t *ub_wait_tail; /* Unsolicited IO received */
1087 1091 /* before link up */
1088 1092
1089 1093 #ifdef DHCHAP_SUPPORT
1090 1094 emlxs_port_dhc_t port_dhc;
1091 1095 #endif /* DHCHAP_SUPPORT */
1092 1096
1093 1097 #ifdef SFCT_SUPPORT
1094 1098 emlxs_memseg_t *fct_memseg; /* Array */
1095 1099 uint32_t fct_memseg_cnt;
1096 1100
1097 1101 /* Default buffer counts */
1098 1102 #define FCT_BUF_COUNT_2K 16
1099 1103 #define FCT_BUF_COUNT_4K 0
1100 1104 #define FCT_BUF_COUNT_8K 16
1101 1105 #define FCT_BUF_COUNT_16K 0
1102 1106 #define FCT_BUF_COUNT_32K 0
1103 1107 #define FCT_BUF_COUNT_64K 16
1104 1108 #define FCT_BUF_COUNT_128K 16
1105 1109 #define FCT_BUF_COUNT_256K 0
1106 1110
1107 1111 char cfd_name[24];
1108 1112 stmf_port_provider_t *port_provider;
1109 1113 fct_local_port_t *fct_port;
1110 1114 uint8_t fct_els_only_bmap;
1111 1115 uint32_t fct_flags;
1112 1116
1113 1117 #define FCT_STATE_PORT_ONLINE 0x00000001
1114 1118 #define FCT_STATE_NOT_ACKED 0x00000002
1115 1119 #define FCT_STATE_LINK_UP 0x00000010
1116 1120 #define FCT_STATE_LINK_UP_ACKED 0x00000020
1117 1121 #define FCT_STATE_FLOGI_CMPL 0x00000040
1118 1122
1119 1123 emlxs_tgtport_stat_t fct_stat;
1120 1124
1121 1125 /* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */
1122 1126 emlxs_buf_t *fct_wait_head;
1123 1127 emlxs_buf_t *fct_wait_tail;
1124 1128
1125 1129 /* Used to save context for deferred unsol FLOGIs */
1126 1130 fct_flogi_xchg_t fx;
1127 1131
1128 1132 #ifdef FCT_IO_TRACE
1129 1133 emlxs_iotrace_t *iotrace;
1130 1134 uint16_t iotrace_cnt;
1131 1135 uint16_t iotrace_index;
1132 1136 kmutex_t iotrace_mtx;
1133 1137 #endif /* FCT_IO_TRACE */
1134 1138
1135 1139 #endif /* SFCT_SUPPORT */
1136 1140
1137 1141 uint32_t clean_address_timer;
1138 1142 emlxs_buf_t *clean_address_sbp;
1139 1143
1140 1144 #ifdef SAN_DIAG_SUPPORT
1141 1145 uint8_t sd_io_latency_state;
1142 1146 #define SD_INVALID 0x00
1143 1147 #define SD_COLLECTING 0x01
1144 1148 #define SD_STOPPED 0x02
1145 1149
1146 1150 /* SD event management list */
1147 1151 uint32_t sd_event_mask; /* bit-mask */
1148 1152 emlxs_dfc_event_t sd_events[MAX_DFC_EVENTS];
1149 1153 #endif
1150 1154
1151 1155 } emlxs_port_t;
1152 1156
1153 1157
1154 1158 /* Host Attn reg */
1155 1159 #define FC_HA_REG(_hba) ((volatile uint32_t *) \
1156 1160 ((_hba)->sli.sli3.ha_reg_addr))
1157 1161
1158 1162 /* Chip Attn reg */
1159 1163 #define FC_CA_REG(_hba) ((volatile uint32_t *) \
1160 1164 ((_hba)->sli.sli3.ca_reg_addr))
1161 1165
1162 1166 /* Host Status reg */
1163 1167 #define FC_HS_REG(_hba) ((volatile uint32_t *) \
1164 1168 ((_hba)->sli.sli3.hs_reg_addr))
1165 1169
1166 1170 /* Host Cntl reg */
1167 1171 #define FC_HC_REG(_hba) ((volatile uint32_t *) \
1168 1172 ((_hba)->sli.sli3.hc_reg_addr))
1169 1173
1170 1174 /* BIU Configuration reg */
1171 1175 #define FC_BC_REG(_hba) ((volatile uint32_t *) \
1172 1176 ((_hba)->sli.sli3.bc_reg_addr))
1173 1177
1174 1178 /* Used by SBUS adapter */
1175 1179 /* TITAN Cntl reg */
1176 1180 #define FC_SHC_REG(_hba) ((volatile uint32_t *) \
1177 1181 ((_hba)->sli.sli3.shc_reg_addr))
1178 1182
1179 1183 /* TITAN Status reg */
1180 1184 #define FC_SHS_REG(_hba) ((volatile uint32_t *) \
1181 1185 ((_hba)->sli.sli3.shs_reg_addr))
1182 1186
1183 1187 /* TITAN Update reg */
1184 1188 #define FC_SHU_REG(_hba) ((volatile uint32_t *) \
1185 1189 ((_hba)->sli.sli3.shu_reg_addr))
1186 1190
1187 1191 /* MPU Semaphore reg */
1188 1192 #define FC_SEMA_REG(_hba) ((volatile uint32_t *)\
1189 1193 ((_hba)->sli.sli4.MPUEPSemaphore_reg_addr))
1190 1194
1191 1195 /* Bootstrap Mailbox Doorbell reg */
1192 1196 #define FC_MBDB_REG(_hba) ((volatile uint32_t *) \
1193 1197 ((_hba)->sli.sli4.MBDB_reg_addr))
1194 1198
1195 1199 /* MQ Doorbell reg */
1196 1200 #define FC_MQDB_REG(_hba) ((volatile uint32_t *) \
1197 1201 ((_hba)->sli.sli4.MQDB_reg_addr))
1198 1202
1199 1203 /* CQ Doorbell reg */
1200 1204 #define FC_CQDB_REG(_hba) ((volatile uint32_t *) \
1201 1205 ((_hba)->sli.sli4.CQDB_reg_addr))
1202 1206
1203 1207 /* WQ Doorbell reg */
1204 1208 #define FC_WQDB_REG(_hba) ((volatile uint32_t *) \
1205 1209 ((_hba)->sli.sli4.WQDB_reg_addr))
1206 1210
1207 1211 /* RQ Doorbell reg */
1208 1212 #define FC_RQDB_REG(_hba) ((volatile uint32_t *) \
1209 1213 ((_hba)->sli.sli4.RQDB_reg_addr))
1210 1214
1211 1215
1212 1216 #define FC_SLIM2_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim2.virt)
1213 1217
1214 1218 #define FC_SLIM1_MAILBOX(_hba) ((MAILBOX *)(_hba)->sli.sli3.slim_addr)
1215 1219
1216 1220 #define FC_MAILBOX(_hba) (((_hba)->flag & FC_SLIM2_MODE) ? \
1217 1221 FC_SLIM2_MAILBOX(_hba) : FC_SLIM1_MAILBOX(_hba))
1218 1222
1219 1223 #define WRITE_CSR_REG(_hba, _regp, _value) ddi_put32(\
1220 1224 (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp), \
1221 1225 (uint32_t)(_value))
1222 1226
1223 1227 #define READ_CSR_REG(_hba, _regp) ddi_get32(\
1224 1228 (_hba)->sli.sli3.csr_acc_handle, (uint32_t *)(_regp))
1225 1229
1226 1230 #define WRITE_SLIM_ADDR(_hba, _regp, _value) ddi_put32(\
1227 1231 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp), \
1228 1232 (uint32_t)(_value))
1229 1233
1230 1234 #define READ_SLIM_ADDR(_hba, _regp) ddi_get32(\
1231 1235 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_regp))
1232 1236
1233 1237 #define WRITE_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_put32(\
1234 1238 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1235 1239 (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1236 1240
1237 1241 #define READ_SLIM_COPY(_hba, _bufp, _slimp, _wcnt) ddi_rep_get32(\
1238 1242 (_hba)->sli.sli3.slim_acc_handle, (uint32_t *)(_bufp), \
1239 1243 (uint32_t *)(_slimp), (_wcnt), DDI_DEV_AUTOINCR)
1240 1244
1241 1245 /* Used by SBUS adapter */
1242 1246 #define WRITE_SBUS_CSR_REG(_hba, _regp, _value) ddi_put32(\
1243 1247 (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp), \
1244 1248 (uint32_t)(_value))
1245 1249
1246 1250 #define READ_SBUS_CSR_REG(_hba, _regp) ddi_get32(\
1247 1251 (_hba)->sli.sli3.sbus_csr_handle, (uint32_t *)(_regp))
1248 1252
1249 1253 #define SBUS_WRITE_FLASH_COPY(_hba, _offset, _value) ddi_put8(\
1250 1254 (_hba)->sli.sli3.sbus_flash_acc_handle, \
1251 1255 (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1252 1256 (_offset)), (uint8_t)(_value))
1253 1257
1254 1258 #define SBUS_READ_FLASH_COPY(_hba, _offset) ddi_get8(\
1255 1259 (_hba)->sli.sli3.sbus_flash_acc_handle, \
1256 1260 (uint8_t *)((volatile uint8_t *)(_hba)->sli.sli3.sbus_flash_addr + \
1257 1261 (_offset)))
1258 1262
1259 1263 /* SLI4 registers */
1260 1264 #define WRITE_BAR0_REG(_hba, _regp, _value) ddi_put32(\
1261 1265 (_hba)->sli.sli4.bar0_acc_handle, (uint32_t *)(_regp), \
1262 1266 (uint32_t)(_value))
1263 1267
1264 1268 #define READ_BAR0_REG(_hba, _regp) ddi_get32(\
1265 1269 (_hba)->sli.sli4.bar0_acc_handle, (uint32_t *)(_regp))
1266 1270
1267 1271 #define WRITE_BAR1_REG(_hba, _regp, _value) ddi_put32(\
1268 1272 (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp), \
1269 1273 (uint32_t)(_value))
1270 1274
1271 1275 #define READ_BAR1_REG(_hba, _regp) ddi_get32(\
1272 1276 (_hba)->sli.sli4.bar1_acc_handle, (uint32_t *)(_regp))
1273 1277
1274 1278 #define WRITE_BAR2_REG(_hba, _regp, _value) ddi_put32(\
1275 1279 (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp), \
1276 1280 (uint32_t)(_value))
1277 1281
1278 1282 #define READ_BAR2_REG(_hba, _regp) ddi_get32(\
1279 1283 (_hba)->sli.sli4.bar2_acc_handle, (uint32_t *)(_regp))
1280 1284
1281 1285
1282 1286 #define EMLXS_STATE_CHANGE(_hba, _state)\
1283 1287 { \
1284 1288 mutex_enter(&EMLXS_PORT_LOCK); \
1285 1289 EMLXS_STATE_CHANGE_LOCKED((_hba), (_state)); \
1286 1290 mutex_exit(&EMLXS_PORT_LOCK); \
1287 1291 }
1288 1292
1289 1293 /* Used when EMLXS_PORT_LOCK is already held */
1290 1294 #define EMLXS_STATE_CHANGE_LOCKED(_hba, _state) \
1291 1295 { \
1292 1296 if ((_hba)->state != (_state)) \
1293 1297 { \
1294 1298 uint32_t _st = _state; \
1295 1299 EMLXS_MSGF(EMLXS_CONTEXT, \
1296 1300 &emlxs_state_msg, "%s --> %s", \
1297 1301 emlxs_ffstate_xlate((_hba)->state), \
1298 1302 emlxs_ffstate_xlate(_state)); \
1299 1303 (_hba)->state = (_state); \
1300 1304 if ((_st) == FC_ERROR) \
1301 1305 { \
1302 1306 (_hba)->flag |= FC_HARDWARE_ERROR; \
1303 1307 } \
1304 1308 } \
1305 1309 }
1306 1310
1307 1311 #ifdef FMA_SUPPORT
1308 1312 #define EMLXS_CHK_ACC_HANDLE(_hba, _acc) \
1309 1313 if (emlxs_fm_check_acc_handle(_hba, _acc) != DDI_FM_OK) { \
1310 1314 EMLXS_MSGF(EMLXS_CONTEXT, \
1311 1315 &emlxs_invalid_access_handle_msg, NULL); \
1312 1316 }
1313 1317 #endif /* FMA_SUPPORT */
1314 1318
1315 1319 /*
1316 1320 * This is the HBA control area for the adapter
1317 1321 */
1318 1322
1319 1323 #ifdef MODSYM_SUPPORT
1320 1324
1321 1325 typedef struct emlxs_modsym
1322 1326 {
1323 1327 ddi_modhandle_t mod_fctl; /* For Leadville */
1324 1328
1325 1329 /* Leadville (fctl) */
1326 1330 int (*fc_fca_attach)(dev_info_t *, fc_fca_tran_t *);
1327 1331 int (*fc_fca_detach)(dev_info_t *);
1328 1332 int (*fc_fca_init)(struct dev_ops *);
1329 1333
1330 1334 #ifdef SFCT_SUPPORT
1331 1335 uint32_t fct_modopen;
1332 1336 uint32_t reserved; /* Padding for alignment */
1333 1337
1334 1338 ddi_modhandle_t mod_fct; /* For Comstar */
1335 1339 ddi_modhandle_t mod_stmf; /* For Comstar */
1336 1340
1337 1341 /* Comstar (fct) */
1338 1342 void* (*fct_alloc)(fct_struct_id_t, int, int);
1339 1343 void (*fct_free)(void *);
1340 1344 void* (*fct_scsi_task_alloc)(void *, uint16_t, uint32_t, uint8_t *,
1341 1345 uint16_t, uint16_t);
1342 1346 int (*fct_register_local_port)(fct_local_port_t *);
1343 1347 void (*fct_deregister_local_port)(fct_local_port_t *);
1344 1348 void (*fct_handle_event)(fct_local_port_t *, int, uint32_t, caddr_t);
1345 1349 void (*fct_post_rcvd_cmd)(fct_cmd_t *, stmf_data_buf_t *);
1346 1350 void (*fct_ctl)(void *, int, void *);
1347 1351 void (*fct_queue_cmd_for_termination)(fct_cmd_t *, fct_status_t);
1348 1352 void (*fct_send_response_done)(fct_cmd_t *, fct_status_t, uint32_t);
1349 1353 void (*fct_send_cmd_done)(fct_cmd_t *, fct_status_t, uint32_t);
1350 1354 void (*fct_scsi_data_xfer_done)(fct_cmd_t *, stmf_data_buf_t *,
1351 1355 uint32_t);
1352 1356 fct_status_t (*fct_port_shutdown)
1353 1357 (fct_local_port_t *, uint32_t, char *);
1354 1358 fct_status_t (*fct_port_initialize)
1355 1359 (fct_local_port_t *, uint32_t, char *);
1356 1360 void (*fct_cmd_fca_aborted)
1357 1361 (fct_cmd_t *, fct_status_t, int);
1358 1362 fct_status_t (*fct_handle_rcvd_flogi)
1359 1363 (fct_local_port_t *, fct_flogi_xchg_t *);
1360 1364
1361 1365 /* Comstar (stmf) */
1362 1366 void* (*stmf_alloc)(stmf_struct_id_t, int, int);
1363 1367 void (*stmf_free)(void *);
1364 1368 void (*stmf_deregister_port_provider) (stmf_port_provider_t *);
1365 1369 int (*stmf_register_port_provider) (stmf_port_provider_t *);
1366 1370 #endif /* SFCT_SUPPORT */
1367 1371 } emlxs_modsym_t;
1368 1372 extern emlxs_modsym_t emlxs_modsym;
1369 1373
1370 1374 #define MODSYM(_f) emlxs_modsym._f
1371 1375
1372 1376 #else
1373 1377
1374 1378 #define MODSYM(_f) _f
1375 1379
1376 1380 #endif /* MODSYM_SUPPORT */
1377 1381
1378 1382
1379 1383
1380 1384 typedef struct RPIHdrTmplate
1381 1385 {
1382 1386 uint32_t Word[16]; /* 64 bytes */
1383 1387 } RPIHdrTmplate_t;
1384 1388
1385 1389
1386 1390 typedef struct EQ_DESC
1387 1391 {
1388 1392 uint16_t host_index;
1389 1393 uint16_t max_index;
1390 1394 uint16_t qid;
1391 1395 uint16_t msix_vector;
1392 1396 kmutex_t lastwq_lock;
1393 1397 uint16_t lastwq;
1394 1398 MBUF_INFO addr;
1395 1399
1396 1400 /* Statistics */
1397 1401 uint32_t max_proc;
1398 1402 uint32_t isr_count;
1399 1403 uint32_t num_proc;
1400 1404 } EQ_DESC_t;
1401 1405
1402 1406
1403 1407 typedef struct CQ_DESC
1404 1408 {
1405 1409 uint16_t host_index;
1406 1410 uint16_t max_index;
1407 1411 uint16_t qid;
1408 1412 uint16_t eqid;
1409 1413 uint16_t type;
1410 1414 #define EMLXS_CQ_TYPE_GROUP1 1 /* associated with a MQ and async events */
1411 1415 #define EMLXS_CQ_TYPE_GROUP2 2 /* associated with a WQ and RQ */
1412 1416 uint16_t rsvd;
1413 1417
1414 1418 MBUF_INFO addr;
1415 1419 CHANNEL *channelp; /* ptr to CHANNEL associated with CQ */
1416 1420
1417 1421 /* Statistics */
1418 1422 uint32_t max_proc;
1419 1423 uint32_t isr_count;
1420 1424 uint32_t num_proc;
1421 1425 } CQ_DESC_t;
1422 1426
1423 1427
1424 1428 typedef struct WQ_DESC
1425 1429 {
1426 1430 uint16_t host_index;
1427 1431 uint16_t max_index;
1428 1432 uint16_t port_index;
1429 1433 uint16_t release_depth;
1430 1434 #define WQE_RELEASE_DEPTH (8 * EMLXS_NUM_WQ_PAGES)
1431 1435 uint16_t qid;
1432 1436 uint16_t cqid;
1433 1437 MBUF_INFO addr;
1434 1438
1435 1439 /* Statistics */
1436 1440 uint32_t num_proc;
1437 1441 uint32_t num_busy;
1438 1442 } WQ_DESC_t;
1439 1443
1440 1444
1441 1445 typedef struct RQ_DESC
1442 1446 {
1443 1447 uint16_t host_index;
1444 1448 uint16_t max_index;
1445 1449 uint16_t qid;
1446 1450 uint16_t cqid;
1447 1451
1448 1452 MBUF_INFO addr;
1449 1453 MBUF_INFO rqb[RQ_DEPTH];
1450 1454
1451 1455 kmutex_t lock;
1452 1456
1453 1457 /* Statistics */
1454 1458 uint32_t num_proc;
1455 1459 } RQ_DESC_t;
1456 1460
1457 1461
1458 1462 typedef struct RXQ_DESC
1459 1463 {
1460 1464 kmutex_t lock;
1461 1465 emlxs_queue_t active;
1462 1466
1463 1467 } RXQ_DESC_t;
1464 1468
1465 1469
1466 1470 typedef struct MQ_DESC
1467 1471 {
1468 1472 uint16_t host_index;
1469 1473 uint16_t max_index;
1470 1474 uint16_t qid;
1471 1475 uint16_t cqid;
1472 1476 MBUF_INFO addr;
1473 1477 } MQ_DESC_t;
1474 1478
1475 1479
1476 1480 /* Define the number of queues the driver will be using */
1477 1481 #define EMLXS_MAX_EQS EMLXS_MSI_MAX_INTRS
1478 1482 #define EMLXS_MAX_WQS EMLXS_MAX_WQS_PER_EQ * EMLXS_MAX_EQS
1479 1483 #define EMLXS_MAX_RQS 2 /* ONLY 1 pair is allowed */
1480 1484 #define EMLXS_MAX_MQS 1
1481 1485
1482 1486 /* One CQ for each WQ & (RQ pair) plus one for the MQ */
1483 1487 #define EMLXS_MAX_CQS (EMLXS_MAX_WQS + (EMLXS_MAX_RQS/2) + 1)
1484 1488
1485 1489 /* The First CQ created is ALWAYS for mbox / event handling */
1486 1490 #define EMLXS_CQ_MBOX 0
1487 1491
1488 1492 /* The Second CQ created is ALWAYS for unsol rcv handling */
1489 1493 /* At this time we are allowing ONLY 1 pair of RQs */
1490 1494 #define EMLXS_CQ_RCV 1
1491 1495
1492 1496 /* The remaining CQs are for WQ completions */
1493 1497 #define EMLXS_CQ_OFFSET_WQ 2
1494 1498
1495 1499
1496 1500 /* FCFI RQ Configuration */
1497 1501 #define EMLXS_FCFI_RQ0_INDEX 0
1498 1502 #define EMLXS_FCFI_RQ0_RMASK 0 /* match all */
1499 1503 #define EMLXS_FCFI_RQ0_RCTL 0 /* match all */
1500 1504 #define EMLXS_FCFI_RQ0_TMASK 0 /* match all */
1501 1505 #define EMLXS_FCFI_RQ0_TYPE 0 /* match all */
1502 1506
1503 1507 #define EMLXS_RXQ_ELS 0
1504 1508 #define EMLXS_RXQ_CT 1
1505 1509 #define EMLXS_MAX_RXQS 2
1506 1510
1507 1511 #define PCI_CONFIG_SIZE 0x80
1508 1512
1509 1513 typedef struct emlxs_sli3
1510 1514 {
1511 1515 /* SLIM management */
1512 1516 MATCHMAP slim2;
1513 1517
1514 1518 /* HBQ management */
1515 1519 uint32_t hbq_count; /* Total number of HBQs */
1516 1520 /* configured */
1517 1521 HBQ_INIT_t hbq_table[EMLXS_NUM_HBQ];
1518 1522
1519 1523 /* Adapter memory management */
1520 1524 caddr_t csr_addr;
1521 1525 caddr_t slim_addr;
1522 1526 ddi_acc_handle_t csr_acc_handle;
1523 1527 ddi_acc_handle_t slim_acc_handle;
1524 1528
1525 1529 /* SBUS adapter management */
1526 1530 caddr_t sbus_flash_addr; /* Virt addr of R/W */
1527 1531 /* Flash */
1528 1532 caddr_t sbus_core_addr; /* Virt addr of TITAN */
1529 1533 /* CORE */
1530 1534 caddr_t sbus_csr_addr; /* Virt addr of TITAN */
1531 1535 /* CSR */
1532 1536 ddi_acc_handle_t sbus_flash_acc_handle;
1533 1537 ddi_acc_handle_t sbus_core_acc_handle;
1534 1538 ddi_acc_handle_t sbus_csr_handle;
1535 1539
1536 1540 /* SLI 2/3 Adapter register management */
1537 1541 uint32_t *bc_reg_addr; /* virtual offset for BIU */
1538 1542 /* config reg */
1539 1543 uint32_t *ha_reg_addr; /* virtual offset for host */
1540 1544 /* attn reg */
1541 1545 uint32_t *hc_reg_addr; /* virtual offset for host */
1542 1546 /* ctl reg */
1543 1547 uint32_t *ca_reg_addr; /* virtual offset for FF */
1544 1548 /* attn reg */
1545 1549 uint32_t *hs_reg_addr; /* virtual offset for */
1546 1550 /* status reg */
1547 1551 uint32_t *shc_reg_addr; /* virtual offset for SBUS */
1548 1552 /* Ctrl reg */
1549 1553 uint32_t *shs_reg_addr; /* virtual offset for SBUS */
1550 1554 /* Status reg */
1551 1555 uint32_t *shu_reg_addr; /* virtual offset for SBUS */
1552 1556 /* Update reg */
1553 1557 uint16_t hgp_ring_offset;
1554 1558 uint16_t hgp_hbq_offset;
1555 1559 uint16_t iocb_cmd_size;
1556 1560 uint16_t iocb_rsp_size;
1557 1561 uint32_t hc_copy; /* local copy of HC register */
1558 1562
1559 1563 /* Ring management */
1560 1564 uint32_t ring_count;
1561 1565 emlxs_ring_t ring[MAX_RINGS];
1562 1566 kmutex_t ring_cmd_lock[MAX_RINGS];
1563 1567 uint8_t ring_masks[4]; /* number of masks/rings used */
1564 1568 uint8_t ring_rval[6];
1565 1569 uint8_t ring_rmask[6];
1566 1570 uint8_t ring_tval[6];
1567 1571 uint8_t ring_tmask[6];
1568 1572
1569 1573 /* Protected by EMLXS_FCTAB_LOCK */
1570 1574 MATCHMAP **bpl_table; /* iotag table for */
1571 1575 /* bpl buffers */
1572 1576 uint32_t mem_bpl_size;
1573 1577 } emlxs_sli3_t;
1574 1578
1575 1579 typedef struct emlxs_sli4
1576 1580 {
1577 1581 MATCHMAP bootstrapmb;
1578 1582 caddr_t bar0_addr;
1579 1583 caddr_t bar1_addr;
1580 1584 caddr_t bar2_addr;
1581 1585 ddi_acc_handle_t bar0_acc_handle;
1582 1586 ddi_acc_handle_t bar1_acc_handle;
1583 1587 ddi_acc_handle_t bar2_acc_handle;
1584 1588
1585 1589 /* SLI4 Adapter register management */
1586 1590 uint32_t *MPUEPSemaphore_reg_addr;
1587 1591 uint32_t *MBDB_reg_addr;
1588 1592
1589 1593 uint32_t *CQDB_reg_addr;
1590 1594 uint32_t *MQDB_reg_addr;
1591 1595 uint32_t *WQDB_reg_addr;
1592 1596 uint32_t *RQDB_reg_addr;
1593 1597 uint32_t *SEMA_reg_addr;
1594 1598 uint32_t *STATUS_reg_addr;
1595 1599 uint32_t *CNTL_reg_addr;
1596 1600 uint32_t *ERR1_reg_addr;
1597 1601 uint32_t *ERR2_reg_addr;
1598 1602 uint32_t *PHYSDEV_reg_addr;
1599 1603
1600 1604 uint32_t flag;
1601 1605 #define EMLXS_SLI4_INTR_ENABLED 0x00000001
1602 1606 #define EMLXS_SLI4_HW_ERROR 0x00000002
1603 1607 #define EMLXS_SLI4_DOWN_LINK 0x00000004
1604 1608 #define EMLXS_SLI4_PHON 0x00000008
1605 1609 #define EMLXS_SLI4_PHWQ 0x00000010
1606 1610 #define EMLXS_SLI4_NULL_XRI 0x00000020
1607 1611
1608 1612 #define EMLXS_SLI4_FCF_INIT 0x10000000
1609 1613 #define EMLXS_SLI4_FCOE_MODE 0x80000000
1610 1614
1611 1615 #define SLI4_FCOE_MODE (hba->sli.sli4.flag & EMLXS_SLI4_FCOE_MODE)
1612 1616 #define SLI4_FC_MODE (!SLI4_FCOE_MODE)
1613 1617
1614 1618
1615 1619
1616 1620 uint16_t XRICount;
1617 1621 uint16_t XRIExtCount;
1618 1622 uint16_t XRIExtSize;
1619 1623 uint16_t XRIBase[MAX_EXTENTS];
1620 1624
1621 1625 uint16_t RPICount;
1622 1626 uint16_t RPIExtCount;
1623 1627 uint16_t RPIExtSize;
1624 1628 uint16_t RPIBase[MAX_EXTENTS];
1625 1629
1626 1630 uint16_t VPICount;
1627 1631 uint16_t VPIExtCount;
1628 1632 uint16_t VPIExtSize;
1629 1633 uint16_t VPIBase[MAX_EXTENTS];
1630 1634
1631 1635 uint16_t VFICount;
1632 1636 uint16_t VFIExtCount;
1633 1637 uint16_t VFIExtSize;
1634 1638 uint16_t VFIBase[MAX_EXTENTS];
1635 1639
1636 1640 uint16_t FCFICount;
1637 1641
1638 1642 kmutex_t fcf_lock;
1639 1643 FCFTable_t fcftab;
1640 1644 VFIobj_t *VFI_table;
1641 1645
1642 1646 /* Save Config Region 23 info */
1643 1647 tlv_fcoe_t cfgFCOE;
1644 1648 tlv_fcfconnectlist_t cfgFCF;
1645 1649
1646 1650 MBUF_INFO slim2;
1647 1651 MBUF_INFO dump_region;
1648 1652 #define EMLXS_DUMP_REGION_SIZE 1024
1649 1653
1650 1654 RPIobj_t *RPIp;
1651 1655 MBUF_INFO HeaderTmplate;
1652 1656 XRIobj_t *XRIp;
1653 1657
1654 1658 /* Double linked list for available XRIs */
1655 1659 XRIobj_t *XRIfree_f;
1656 1660 XRIobj_t *XRIfree_b;
1657 1661 uint32_t xrif_count;
1658 1662 uint32_t mem_sgl_size;
1659 1663
1660 1664 /* Double linked list for XRIs in use */
1661 1665 XRIobj_t *XRIinuse_f;
1662 1666 XRIobj_t *XRIinuse_b;
1663 1667 uint32_t xria_count;
1664 1668
1665 1669 kmutex_t que_lock[EMLXS_MAX_WQS];
1666 1670 EQ_DESC_t eq[EMLXS_MAX_EQS];
1667 1671 CQ_DESC_t cq[EMLXS_MAX_CQS];
1668 1672 WQ_DESC_t wq[EMLXS_MAX_WQS];
1669 1673 RQ_DESC_t rq[EMLXS_MAX_RQS];
1670 1674 RXQ_DESC_t rxq[EMLXS_MAX_RXQS];
1671 1675 MQ_DESC_t mq;
1672 1676 uint32_t que_stat_timer;
1673 1677
1674 1678 uint32_t ue_mask_lo;
1675 1679 uint32_t ue_mask_hi;
1676 1680
1677 1681 sli_params_t param;
1678 1682
1679 1683 uint8_t port_name[4];
1680 1684 uint32_t link_number;
1681 1685
1682 1686 } emlxs_sli4_t;
1683 1687
1684 1688
1685 1689 typedef struct emlxs_sli_api
1686 1690 {
1687 1691 int (*sli_map_hdw)();
1688 1692 void (*sli_unmap_hdw)();
1689 1693 int32_t (*sli_online)();
1690 1694 void (*sli_offline)();
1691 1695 uint32_t (*sli_hba_reset)();
1692 1696 void (*sli_hba_kill)();
1693 1697 void (*sli_issue_iocb_cmd)();
1694 1698 uint32_t (*sli_issue_mbox_cmd)();
1695 1699 uint32_t (*sli_prep_fct_iocb)();
1696 1700 uint32_t (*sli_prep_fcp_iocb)();
1697 1701 uint32_t (*sli_prep_ip_iocb)();
1698 1702 uint32_t (*sli_prep_els_iocb)();
1699 1703 uint32_t (*sli_prep_ct_iocb)();
1700 1704 void (*sli_poll_intr)();
1701 1705 int32_t (*sli_intx_intr)();
1702 1706 uint32_t (*sli_msi_intr)();
1703 1707 void (*sli_disable_intr)();
1704 1708 void (*sli_timer)();
1705 1709 void (*sli_poll_erratt)();
1706 1710 uint32_t (*sli_reg_did)();
1707 1711 uint32_t (*sli_unreg_node)();
1708 1712
1709 1713 } emlxs_sli_api_t;
1710 1714
1711 1715
1712 1716 typedef struct emlxs_hba
1713 1717 {
1714 1718 dev_info_t *dip;
1715 1719 int32_t emlxinst;
1716 1720 int32_t ddiinst;
1717 1721 uint8_t pci_function_number;
1718 1722 uint8_t pci_device_number;
1719 1723 uint8_t pci_bus_number;
1720 1724 uint8_t pci_cap_offset[PCI_CAP_MAX_PTR];
1721 1725 uint16_t pci_ecap_offset[PCI_EXT_CAP_MAX_PTR];
1722 1726
1723 1727 #ifdef FMA_SUPPORT
1724 1728 int32_t fm_caps; /* FMA capabilities */
1725 1729 #endif /* FMA_SUPPORT */
1726 1730 fc_fca_tran_t *fca_tran;
1727 1731
1728 1732 /* DMA attributes */
1729 1733 ddi_dma_attr_t dma_attr;
1730 1734 ddi_dma_attr_t dma_attr_ro;
1731 1735 ddi_dma_attr_t dma_attr_1sg;
1732 1736 ddi_dma_attr_t dma_attr_fcip_rsp;
1733 1737
1734 1738 /* HBA Info */
1735 1739 emlxs_model_t model_info;
1736 1740 emlxs_vpd_t vpd; /* vital product data */
1737 1741 NAME_TYPE wwnn;
1738 1742 NAME_TYPE wwpn;
1739 1743 char snn[256];
1740 1744 char spn[256];
1741 1745 PROG_ID load_list[MAX_LOAD_ENTRY];
1742 1746 WAKE_UP_PARMS wakeup_parms;
1743 1747 uint32_t max_nodes;
1744 1748 uint32_t io_throttle;
1745 1749 uint32_t io_active;
1746 1750 uint32_t bus_type;
1747 1751 #define PCI_FC 0
1748 1752 #define SBUS_FC 1
1749 1753 uint32_t sli_intf;
1750 1754 #define SLI_INTF_VALID_MASK 0xe0000000
1751 1755 #define SLI_INTF_VALID 0xc0000000
1752 1756
1753 1757 #define SLI_INTF_HINT2_MASK 0x1f000000
1754 1758 #define SLI_INTF_HINT2_0 0x00000000
1755 1759
1756 1760 #define SLI_INTF_HINT1_MASK 0x00ff0000
1757 1761 #define SLI_INTF_HINT1_0 0x00000000
1758 1762 #define SLI_INTF_HINT1_1 0x00010000
1759 1763 #define SLI_INTF_HINT1_2 0x00020000
1760 1764
1761 1765 #define SLI_INTF_IF_TYPE_MASK 0x0000f000
1762 1766 #define SLI_INTF_IF_TYPE_0 0x00000000
1763 1767 #define SLI_INTF_IF_TYPE_1 0x00001000
1764 1768 #define SLI_INTF_IF_TYPE_2 0x00002000
1765 1769 #define SLI_INTF_IF_TYPE_3 0x00003000
1766 1770
1767 1771 #define SLI_INTF_FAMILY_MASK 0x00000f00
1768 1772 #define SLI_INTF_FAMILY_BE2 0x00000000
1769 1773 #define SLI_INTF_FAMILY_BE3 0x00000100
1770 1774 #define SLI_INTF_FAMILY_LANCER_A 0x00000a00
1771 1775 #define SLI_INTF_FAMILY_LANCER_B 0x00000b00
1772 1776
1773 1777 #define SLI_INTF_SLI_REV_MASK 0x000000f0
1774 1778 #define SLI_INTF_SLI_REV_NONE 0x00000000
1775 1779 #define SLI_INTF_SLI_REV_3 0x00000030
1776 1780 #define SLI_INTF_SLI_REV_4 0x00000040
1777 1781
1778 1782 #define SLI_INTF_RESERVED1 0x0000000e
1779 1783
1780 1784 #define SLI_INTF_FUNC_TYPE_MASK 0x00000001
1781 1785 #define SLI_INTF_FUNC_PF 0x00000000
1782 1786 #define SLI_INTF_FUNC_VF 0x00000001
1783 1787
1784 1788 /* Link management */
1785 1789 uint32_t link_event_tag;
1786 1790 uint8_t topology;
1787 1791 uint8_t linkspeed;
1788 1792 uint16_t qos_linkspeed;
1789 1793 uint32_t linkup_wait_flag;
1790 1794 kcondvar_t linkup_lock_cv;
1791 1795 kmutex_t linkup_lock;
1792 1796
1793 1797 /* Memory Pool management */
1794 1798 emlxs_memseg_t memseg[FC_MAX_SEG]; /* memory for buffer */
1795 1799 /* structures */
1796 1800 kmutex_t memget_lock; /* locks all memory pools get */
1797 1801 kmutex_t memput_lock; /* locks all memory pools put */
1798 1802 uint32_t mem_timer;
1799 1803
1800 1804 /* Fibre Channel Service Parameters */
1801 1805 SERV_PARM sparam;
1802 1806 uint32_t fc_edtov; /* E_D_TOV timer value */
1803 1807 uint32_t fc_arbtov; /* ARB_TOV timer value */
1804 1808 uint32_t fc_ratov; /* R_A_TOV timer value */
1805 1809 uint32_t fc_rttov; /* R_T_TOV timer value */
1806 1810 uint32_t fc_altov; /* AL_TOV timer value */
1807 1811 uint32_t fc_crtov; /* C_R_TOV timer value */
1808 1812 uint32_t fc_citov; /* C_I_TOV timer value */
1809 1813
1810 1814 /* Adapter State management */
1811 1815 int32_t state;
1812 1816 #define FC_ERROR 0x01 /* Adapter shutdown */
1813 1817 #define FC_KILLED 0x02 /* Adapter interlocked/killed */
1814 1818 #define FC_WARM_START 0x03 /* Adapter reset, but not restarted */
1815 1819 #define FC_INIT_START 0x10 /* Adapter restarted */
1816 1820 #define FC_INIT_NVPARAMS 0x11
1817 1821 #define FC_INIT_REV 0x12
1818 1822 #define FC_INIT_CFGPORT 0x13
1819 1823 #define FC_INIT_CFGRING 0x14
1820 1824 #define FC_INIT_INITLINK 0x15
1821 1825 #define FC_LINK_DOWN 0x20
1822 1826 #define FC_LINK_DOWN_PERSIST 0x21
1823 1827 #define FC_LINK_UP 0x30
1824 1828 #define FC_CLEAR_LA 0x31
1825 1829 #define FC_READY 0x40
1826 1830
1827 1831 uint32_t flag;
1828 1832 #define FC_ONLINING_MODE 0x00000001
1829 1833 #define FC_ONLINE_MODE 0x00000002
1830 1834 #define FC_OFFLINING_MODE 0x00000004
1831 1835 #define FC_OFFLINE_MODE 0x00000008
1832 1836
1833 1837 #define FC_NPIV_ENABLED 0x00000010 /* NPIV enabled on adapter */
1834 1838 #define FC_NPIV_SUPPORTED 0x00000020 /* NPIV supported on fabric */
1835 1839 #define FC_NPIV_UNSUPPORTED 0x00000040 /* NPIV unsupported on fabric */
1836 1840 #define FC_NPIV_LINKUP 0x00000100 /* NPIV enabled, supported, */
1837 1841 /* and link is ready */
1838 1842 #define FC_NPIV_DELAY_REQUIRED 0x00000200 /* Delay issuing FLOGI/FDISC */
1839 1843 /* and NameServer cmds */
1840 1844
1841 1845 #define FC_BOOTSTRAPMB_INIT 0x00000400
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1842 1846 #define FC_FIP_SUPPORTED 0x00000800 /* FIP supported */
1843 1847
1844 1848 #define FC_FABRIC_ATTACHED 0x00001000
1845 1849 #define FC_PT_TO_PT 0x00002000
1846 1850 #define FC_BYPASSED_MODE 0x00004000
1847 1851 #define FC_MENLO_MODE 0x00008000 /* Menlo maintenance mode */
1848 1852
1849 1853 #define FC_DUMP_SAFE 0x00010000 /* Safe to DUMP */
1850 1854 #define FC_DUMP_ACTIVE 0x00020000 /* DUMP in progress */
1851 1855 #define FC_NEW_FABRIC 0x00040000
1856 +#define FC_GPIO_LINK_UP 0x00080000
1852 1857
1853 1858 #define FC_SLIM2_MODE 0x00100000 /* SLIM in host memory */
1854 1859 #define FC_INTERLOCKED 0x00200000
1855 1860 #define FC_HBQ_ENABLED 0x00400000
1856 1861 #define FC_ASYNC_EVENTS 0x00800000
1857 1862
1858 1863 #define FC_ILB_MODE 0x01000000
1859 1864 #define FC_ELB_MODE 0x02000000
1860 1865 #define FC_LOOPBACK_MODE 0x03000000 /* Loopback Mode Mask */
1861 1866 #define FC_DUMP 0x04000000 /* DUMP in progress */
1862 1867 #define FC_SHUTDOWN 0x08000000 /* SHUTDOWN in progress */
1863 1868
1864 1869 #define FC_OVERTEMP_EVENT 0x10000000 /* FC_ERROR reason: */
1865 1870 /* over temperature event */
1866 1871 #define FC_MBOX_TIMEOUT 0x20000000 /* FC_ERROR reason: */
1867 1872 /* mailbox timeout event */
1868 1873 #define FC_DMA_CHECK_ERROR 0x40000000 /* Shared memory (slim,..) */
1869 1874 /* DMA handle went bad */
1870 1875 #define FC_HARDWARE_ERROR 0x80000000 /* FC_ERROR state triggered */
1871 1876
1872 1877 #define FC_RESET_MASK 0x00030C1F /* Bits to protect during */
1873 1878 /* a hard reset */
1874 1879 #define FC_LINKDOWN_MASK 0xFFF30C1F /* Bits to protect during */
1875 1880 /* a linkdown */
1876 1881
1877 1882 uint32_t fw_timer;
1878 1883 uint32_t fw_flag;
1879 1884 #define FW_UPDATE_NEEDED 0x00000001
1880 1885 #define FW_UPDATE_KERNEL 0x00000002
1881 1886
1882 1887 uint32_t temperature; /* Last reported temperature */
1883 1888
1884 1889 /* SBUS adapter management */
1885 1890 caddr_t sbus_pci_addr; /* Virt addr of TITAN */
1886 1891 /* pci config */
1887 1892 ddi_acc_handle_t sbus_pci_handle;
1888 1893
1889 1894 /* PCI BUS adapter management */
1890 1895 caddr_t pci_addr;
1891 1896 ddi_acc_handle_t pci_acc_handle;
1892 1897
1893 1898 uint32_t sli_mode;
1894 1899 #define EMLXS_HBA_SLI1_MODE 1
1895 1900 #define EMLXS_HBA_SLI2_MODE 2
1896 1901 #define EMLXS_HBA_SLI3_MODE 3
1897 1902 #define EMLXS_HBA_SLI4_MODE 4
1898 1903
1899 1904 /* SLI private data */
1900 1905 union {
1901 1906 emlxs_sli3_t sli3;
1902 1907 emlxs_sli4_t sli4;
1903 1908 } sli;
1904 1909
1905 1910 /* SLI API entry point routines */
1906 1911 emlxs_sli_api_t sli_api;
1907 1912
1908 1913 uint32_t io_poll_count; /* Number of poll commands */
1909 1914 /* in progress */
1910 1915
1911 1916 /* IO Completion management */
1912 1917 uint32_t iodone_count; /* Number of IO's on done Q */
1913 1918 /* Protected by EMLXS_PORT_LOCK */
1914 1919 emlxs_buf_t *iodone_list; /* fc_packet being deferred */
1915 1920 emlxs_buf_t *iodone_tail; /* fc_packet being deferred */
1916 1921 emlxs_thread_t iodone_thread;
1917 1922 emlxs_thread_t *spawn_thread_head;
1918 1923 emlxs_thread_t *spawn_thread_tail;
1919 1924 kmutex_t spawn_lock;
1920 1925 uint32_t spawn_open;
1921 1926
1922 1927 /* IO Channel management */
1923 1928 int32_t chan_count;
1924 1929 emlxs_channel_t chan[MAX_CHANNEL];
1925 1930 kmutex_t channel_tx_lock;
1926 1931 uint8_t channel_fcp; /* Default channel to use for FCP IO */
1927 1932 #define CHANNEL_FCT channel_fcp
1928 1933 uint8_t channel_ip; /* Default channel to use for IP IO */
1929 1934 uint8_t channel_els; /* Default channel to use for ELS IO */
1930 1935 uint8_t channel_ct; /* Default channel to use for CT IO */
1931 1936
1932 1937 /* IOTag management */
1933 1938 emlxs_buf_t **fc_table; /* sc_buf pointers indexed by */
1934 1939 /* iotag */
1935 1940 uint16_t fc_iotag; /* used to identify I/Os */
1936 1941 uint16_t fc_oor_iotag; /* OutOfRange (fc_table) iotags */
1937 1942 /* typically used for Abort/close */
1938 1943 #define EMLXS_MAX_ABORT_TAG 0x7fff
1939 1944 uint16_t max_iotag; /* ALL IOCBs except aborts */
1940 1945 kmutex_t iotag_lock;
1941 1946 uint32_t io_count; /* No of IO holding */
1942 1947 /* regular iotag */
1943 1948 uint32_t channel_tx_count; /* No of IO on tx Q */
1944 1949
1945 1950 /* Mailbox Management */
1946 1951 uint32_t mbox_queue_flag;
1947 1952 emlxs_queue_t mbox_queue;
1948 1953 void *mbox_mqe; /* active mbox mqe */
1949 1954 void *mbox_mbq; /* active MAILBOXQ */
1950 1955 kcondvar_t mbox_lock_cv; /* MBX_SLEEP */
1951 1956 kmutex_t mbox_lock; /* MBX_SLEEP */
1952 1957 uint32_t mbox_timer;
1953 1958
1954 1959 /* Interrupt management */
1955 1960 void *intr_arg;
1956 1961 uint32_t intr_unclaimed;
1957 1962 uint32_t intr_autoClear;
1958 1963 uint32_t intr_busy_cnt;
1959 1964
1960 1965 uint32_t intr_flags;
1961 1966 #define EMLXS_INTX_INITED 0x0001
1962 1967 #define EMLXS_INTX_ADDED 0x0002
1963 1968 #define EMLXS_MSI_ENABLED 0x0010
1964 1969 #define EMLXS_MSI_INITED 0x0020
1965 1970 #define EMLXS_MSI_ADDED 0x0040
1966 1971 #define EMLXS_INTR_INITED (EMLXS_INTX_INITED|EMLXS_MSI_INITED)
1967 1972 #define EMLXS_INTR_ADDED (EMLXS_INTX_ADDED|EMLXS_MSI_ADDED)
1968 1973
1969 1974 #ifdef MSI_SUPPORT
1970 1975 ddi_intr_handle_t *intr_htable;
1971 1976 uint32_t *intr_pri;
1972 1977 int32_t *intr_cap;
1973 1978 uint32_t intr_count;
1974 1979 uint32_t intr_type;
1975 1980 uint32_t intr_cond;
1976 1981 uint32_t intr_map[EMLXS_MSI_MAX_INTRS];
1977 1982 uint32_t intr_mask;
1978 1983
1979 1984 kmutex_t msiid_lock; /* for last_msiid */
1980 1985 int last_msiid;
1981 1986
1982 1987 kmutex_t intr_lock[EMLXS_MSI_MAX_INTRS];
1983 1988 int chan2msi[MAX_CHANNEL];
1984 1989 /* Index is the channel id */
1985 1990 int msi2chan[EMLXS_MSI_MAX_INTRS];
1986 1991 /* Index is the MSX-X msg id */
1987 1992 #endif /* MSI_SUPPORT */
1988 1993
1989 1994 uint32_t heartbeat_timer;
1990 1995 uint32_t heartbeat_flag;
1991 1996 uint32_t heartbeat_active;
1992 1997
1993 1998 /* IOCTL management */
1994 1999 kmutex_t ioctl_lock;
1995 2000 uint32_t ioctl_flags;
1996 2001 #define EMLXS_OPEN 0x00000001
1997 2002 #define EMLXS_OPEN_EXCLUSIVE 0x00000002
1998 2003
1999 2004 /* Timer management */
2000 2005 kcondvar_t timer_lock_cv;
2001 2006 kmutex_t timer_lock;
2002 2007 timeout_id_t timer_id;
2003 2008 uint32_t timer_tics;
2004 2009 uint32_t timer_flags;
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2005 2010 #define EMLXS_TIMER_STARTED 0x0000001
2006 2011 #define EMLXS_TIMER_BUSY 0x0000002
2007 2012 #define EMLXS_TIMER_KILL 0x0000004
2008 2013 #define EMLXS_TIMER_ENDED 0x0000008
2009 2014
2010 2015 /* Misc Timers */
2011 2016 uint32_t linkup_timer;
2012 2017 uint32_t discovery_timer;
2013 2018 uint32_t pkt_timer;
2014 2019
2020 + /* GPIO Management */
2021 + uint8_t gpio_desired;
2022 + uint8_t gpio_current;
2023 + uint8_t gpio_bit;
2024 +#define EMLXS_GPIO_LO 0x01
2025 +#define EMLXS_GPIO_HI 0x02
2026 +#define EMLXS_GPIO_ACT 0x04
2027 +#define EMLXS_GPIO_LASER 0x08
2028 +#define EMLXS_GPIO_LOC 0x10
2029 +
2030 + uint8_t gpio_pin[4];
2031 +
2032 +#define EMLXS_GPIO_PIN_LO 0
2033 +#define EMLXS_GPIO_PIN_HI 1
2034 +#define EMLXS_GPIO_PIN_ACT 2
2035 +#define EMLXS_GPIO_PIN_LASER 3
2036 +
2037 + kmutex_t gpio_lock; /* Timer lock */
2038 + timeout_id_t gpio_timer;
2039 +
2015 2040 /* Power Management */
2016 2041 uint32_t pm_state;
2017 2042 /* pm_state */
2018 2043 #define EMLXS_PM_IN_ATTACH 0x00000001
2019 2044 #define EMLXS_PM_IN_DETACH 0x00000002
2020 2045 #define EMLXS_PM_IN_SOL_CB 0x00000010
2021 2046 #define EMLXS_PM_IN_UNSOL_CB 0x00000020
2022 2047 #define EMLXS_PM_IN_LINK_RESET 0x00000100
2023 2048 #define EMLXS_PM_IN_HARD_RESET 0x00000200
2024 2049 #define EMLXS_PM_SUSPENDED 0x01000000
2025 2050
2026 2051 uint32_t pm_level;
2027 2052 /* pm_level */
2028 2053 #define EMLXS_PM_ADAPTER_DOWN 0
2029 2054 #define EMLXS_PM_ADAPTER_UP 1
2030 2055
2031 2056 uint32_t pm_busy;
2032 2057 kmutex_t pm_lock;
2033 2058 uint8_t pm_config[PCI_CONFIG_SIZE];
2034 2059 #ifdef IDLE_TIMER
2035 2060 uint32_t pm_idle_timer;
2036 2061 uint32_t pm_active; /* Only used by timer */
2037 2062 #endif /* IDLE_TIMER */
2038 2063
2039 2064 /* Loopback management */
2040 2065 uint32_t loopback_tics;
2041 2066 void *loopback_pkt;
2042 2067
2043 2068 /* Event management */
2044 2069 emlxs_event_queue_t event_queue;
2045 2070 uint32_t event_mask;
2046 2071 uint32_t event_timer;
2047 2072 emlxs_dfc_event_t dfc_event[MAX_DFC_EVENTS];
2048 2073 emlxs_hba_event_t hba_event;
2049 2074
2050 2075 /* Parameter management */
2051 2076 emlxs_config_t config[NUM_CFG_PARAM];
2052 2077
2053 2078 /* Driver stat management */
2054 2079 kstat_t *kstat;
2055 2080 emlxs_stats_t stats;
2056 2081
2057 2082 /* Log management */
2058 2083 emlxs_msg_log_t log;
2059 2084
2060 2085 /* Port managment */
2061 2086 uint32_t vpi_max;
2062 2087 uint32_t vpi_high;
2063 2088 uint32_t num_of_ports;
2064 2089
2065 2090 kmutex_t port_lock; /* locks port, nodes, rings */
2066 2091 emlxs_port_t port[MAX_VPORTS + 1]; /* port specific info */
2067 2092 /* Last one is for */
2068 2093 /* NPIV ready test */
2069 2094
2070 2095 #ifdef DHCHAP_SUPPORT
2071 2096 kmutex_t dhc_lock;
2072 2097 kmutex_t auth_lock;
2073 2098 emlxs_auth_cfg_t auth_cfg; /* Default auth_cfg. */
2074 2099 /* Points to list of entries. */
2075 2100 /* Protected by auth_lock */
2076 2101 uint32_t auth_cfg_count;
2077 2102 emlxs_auth_key_t auth_key; /* Default auth_key. */
2078 2103 /* Points to list of entries. */
2079 2104 /* Protected by auth_lock */
2080 2105 uint32_t auth_key_count;
2081 2106 uint32_t rdn_flag;
2082 2107 #endif /* DHCHAP_SUPPORT */
2083 2108
2084 2109 #ifdef TEST_SUPPORT
2085 2110 uint32_t underrun_counter;
2086 2111 #endif /* TEST_SUPPORT */
2087 2112
2088 2113 #ifdef MODFW_SUPPORT
2089 2114 ddi_modhandle_t fw_modhandle;
2090 2115 #endif /* MODFW_SUPPORT */
2091 2116
2092 2117 #ifdef DUMP_SUPPORT
2093 2118 emlxs_file_t dump_txtfile;
2094 2119 emlxs_file_t dump_dmpfile;
2095 2120 emlxs_file_t dump_ceefile;
2096 2121 kmutex_t dump_lock;
2097 2122 #define EMLXS_DUMP_LOCK hba->dump_lock
2098 2123 #define EMLXS_TXT_FILE 1
2099 2124 #define EMLXS_DMP_FILE 2
2100 2125 #define EMLXS_CEE_FILE 3
2101 2126
2102 2127 #define EMLXS_DRV_DUMP 0
2103 2128 #define EMLXS_TEMP_DUMP 1
2104 2129 #define EMLXS_USER_DUMP 2
2105 2130
2106 2131 #endif /* DUMP_SUPPORT */
2107 2132
2108 2133 uint32_t reset_request;
2109 2134 #define FC_LINK_RESET 1
2110 2135 #define FC_PORT_RESET 2
2111 2136
2112 2137 uint32_t reset_state;
2113 2138 #define FC_LINK_RESET_INP 1
2114 2139 #define FC_PORT_RESET_INP 2
2115 2140
2116 2141 } emlxs_hba_t;
2117 2142
2118 2143 #define EMLXS_SLI_MAP_HDW (hba->sli_api.sli_map_hdw)
2119 2144 #define EMLXS_SLI_UNMAP_HDW (hba->sli_api.sli_unmap_hdw)
2120 2145 #define EMLXS_SLI_ONLINE (hba->sli_api.sli_online)
2121 2146 #define EMLXS_SLI_OFFLINE (hba->sli_api.sli_offline)
2122 2147 #define EMLXS_SLI_HBA_RESET (hba->sli_api.sli_hba_reset)
2123 2148 #define EMLXS_SLI_HBA_KILL (hba->sli_api.sli_hba_kill)
2124 2149 #define EMLXS_SLI_ISSUE_IOCB_CMD (hba->sli_api.sli_issue_iocb_cmd)
2125 2150 #define EMLXS_SLI_ISSUE_MBOX_CMD (hba->sli_api.sli_issue_mbox_cmd)
2126 2151 #define EMLXS_SLI_PREP_FCT_IOCB (hba->sli_api.sli_prep_fct_iocb)
2127 2152 #define EMLXS_SLI_PREP_FCP_IOCB (hba->sli_api.sli_prep_fcp_iocb)
2128 2153 #define EMLXS_SLI_PREP_IP_IOCB (hba->sli_api.sli_prep_ip_iocb)
2129 2154 #define EMLXS_SLI_PREP_ELS_IOCB (hba->sli_api.sli_prep_els_iocb)
2130 2155 #define EMLXS_SLI_PREP_CT_IOCB (hba->sli_api.sli_prep_ct_iocb)
2131 2156 #define EMLXS_SLI_POLL_INTR (hba->sli_api.sli_poll_intr)
2132 2157 #define EMLXS_SLI_INTX_INTR (hba->sli_api.sli_intx_intr)
2133 2158 #define EMLXS_SLI_MSI_INTR (hba->sli_api.sli_msi_intr)
2134 2159 #define EMLXS_SLI_DISABLE_INTR (hba->sli_api.sli_disable_intr)
2135 2160 #define EMLXS_SLI_TIMER (hba->sli_api.sli_timer)
2136 2161 #define EMLXS_SLI_POLL_ERRATT (hba->sli_api.sli_poll_erratt)
2137 2162 #define EMLXS_SLI_REG_DID (hba->sli_api.sli_reg_did)
2138 2163 #define EMLXS_SLI_UNREG_NODE (hba->sli_api.sli_unreg_node)
2139 2164
2140 2165 #define EMLXS_HBA_T 1 /* flag emlxs_hba_t is already typedefed */
2141 2166
2142 2167 #ifdef MSI_SUPPORT
2143 2168 #define EMLXS_INTR_INIT(_hba, _m) emlxs_msi_init(_hba, _m)
2144 2169 #define EMLXS_INTR_UNINIT(_hba) emlxs_msi_uninit(_hba)
2145 2170 #define EMLXS_INTR_ADD(_hba) emlxs_msi_add(_hba)
2146 2171 #define EMLXS_INTR_REMOVE(_hba) emlxs_msi_remove(_hba)
2147 2172 #else
2148 2173 #define EMLXS_INTR_INIT(_hba, _m) emlxs_intx_init(_hba, _m)
2149 2174 #define EMLXS_INTR_UNINIT(_hba) emlxs_intx_uninit(_hba)
2150 2175 #define EMLXS_INTR_ADD(_hba) emlxs_intx_add(_hba)
2151 2176 #define EMLXS_INTR_REMOVE(_hba) emlxs_intx_remove(_hba)
2152 2177 #endif /* MSI_SUPPORT */
2153 2178
2154 2179
2155 2180 /* Power Management Component */
2156 2181 #define EMLXS_PM_ADAPTER 0
2157 2182
2158 2183
2159 2184 #define DRV_TIME (uint32_t)(ddi_get_time() - emlxs_device.drv_timestamp)
2160 2185
2161 2186 #define HBA port->hba
2162 2187 #define PPORT hba->port[0]
2163 2188 #define VPORT(x) hba->port[x]
2164 2189 #define EMLXS_TIMER_LOCK hba->timer_lock
2165 2190 #define VPD hba->vpd
2166 2191 #define CFG hba->config[0]
2167 2192 #define LOG hba->log
2168 2193 #define EVENTQ hba->event_queue
2169 2194 #define EMLXS_MBOX_LOCK hba->mbox_lock
2170 2195 #define EMLXS_MBOX_CV hba->mbox_lock_cv
2171 2196 #define EMLXS_LINKUP_LOCK hba->linkup_lock
2172 2197 #define EMLXS_LINKUP_CV hba->linkup_lock_cv
2173 2198 #define EMLXS_TX_CHANNEL_LOCK hba->channel_tx_lock /* ring txq lock */
2174 2199 #define EMLXS_MEMGET_LOCK hba->memget_lock /* mempool get lock */
2175 2200 #define EMLXS_MEMPUT_LOCK hba->memput_lock /* mempool put lock */
2176 2201 #define EMLXS_IOCTL_LOCK hba->ioctl_lock /* ioctl lock */
2177 2202 #define EMLXS_SPAWN_LOCK hba->spawn_lock /* spawn lock */
2178 2203 #define EMLXS_PM_LOCK hba->pm_lock /* pm lock */
2179 2204 #define HBASTATS hba->stats
2180 2205 #define EMLXS_CMD_RING_LOCK(n) hba->sli.sli3.ring_cmd_lock[n]
2181 2206
2182 2207 #define EMLXS_QUE_LOCK(n) hba->sli.sli4.que_lock[n]
2183 2208 #define EMLXS_MSIID_LOCK hba->msiid_lock
2184 2209
2185 2210 #define EMLXS_FCTAB_LOCK hba->iotag_lock
2186 2211
2187 2212 #define EMLXS_FCF_LOCK hba->sli.sli4.fcf_lock
2188 2213
2189 2214 #define EMLXS_PORT_LOCK hba->port_lock /* locks ports, */
2190 2215 /* nodes, rings */
2191 2216 #define EMLXS_INTR_LOCK(_id) hba->intr_lock[_id] /* locks intr threads */
2192 2217
2193 2218 #define EMLXS_PKT_LOCK port->pkt_lock /* used for pkt */
2194 2219 /* polling */
2195 2220 #define EMLXS_PKT_CV port->pkt_lock_cv /* Used for pkt */
2196 2221 /* polling */
2197 2222 #define EMLXS_UB_LOCK port->ub_lock /* locks unsolicited */
2198 2223 /* buffer pool */
2199 2224
2200 2225 /* These SWAPs will swap on any platform */
2201 2226 #define SWAP32_BUFFER(_b, _c) emlxs_swap32_buffer(_b, _c)
2202 2227 #define SWAP32_BCOPY(_s, _d, _c) emlxs_swap32_bcopy(_s, _d, _c)
2203 2228
2204 2229 #define SWAP64(_x) ((((uint64_t)(_x) & 0xFF)<<56) | \
2205 2230 (((uint64_t)(_x) & 0xFF00)<<40) | \
2206 2231 (((uint64_t)(_x) & 0xFF0000)<<24) | \
2207 2232 (((uint64_t)(_x) & 0xFF000000)<<8) | \
2208 2233 (((uint64_t)(_x) & 0xFF00000000)>>8) | \
2209 2234 (((uint64_t)(_x) & 0xFF0000000000)>>24) | \
2210 2235 (((uint64_t)(_x) & 0xFF000000000000)>>40) | \
2211 2236 (((uint64_t)(_x) & 0xFF00000000000000)>>56))
2212 2237
2213 2238 #define SWAP32(_x) ((((uint32_t)(_x) & 0xFF)<<24) | \
2214 2239 (((uint32_t)(_x) & 0xFF00)<<8) | \
2215 2240 (((uint32_t)(_x) & 0xFF0000)>>8) | \
2216 2241 (((uint32_t)(_x) & 0xFF000000)>>24))
2217 2242
2218 2243 #define SWAP16(_x) ((((uint16_t)(_x) & 0xFF)<<8) | \
2219 2244 (((uint16_t)(_x) & 0xFF00)>>8))
2220 2245
2221 2246 #define SWAP24_LO(_x) ((((uint32_t)(_x) & 0xFF)<<16) | \
2222 2247 ((uint32_t)(_x) & 0xFF00FF00) | \
2223 2248 (((uint32_t)(_x) & 0x00FF0000)>>16))
2224 2249
2225 2250 #define SWAP24_HI(_x) (((uint32_t)(_x) & 0x00FF00FF) | \
2226 2251 (((uint32_t)(_x) & 0x0000FF00)<<16) | \
2227 2252 (((uint32_t)(_x) & 0xFF000000)>>16))
2228 2253
2229 2254 /* These LE_SWAPs will only swap on a LE platform */
2230 2255 #ifdef EMLXS_LITTLE_ENDIAN
2231 2256 #define LE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c)
2232 2257 #define LE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c)
2233 2258 #define LE_SWAP64(_x) SWAP64(_x)
2234 2259 #define LE_SWAP32(_x) SWAP32(_x)
2235 2260 #define LE_SWAP16(_x) SWAP16(_x)
2236 2261 #define LE_SWAP24_LO(_x) SWAP24_LO(X)
2237 2262 #define LE_SWAP24_HI(_x) SWAP24_HI(X)
2238 2263
2239 2264 #if (EMLXS_MODREVX == EMLXS_MODREV2X)
2240 2265 #undef LE_SWAP24_LO
2241 2266 #define LE_SWAP24_LO(_x) (_x)
2242 2267 #undef LE_SWAP24_HI
2243 2268 #define LE_SWAP24_HI(_x) (_x)
2244 2269 #endif /* EMLXS_MODREV2X */
2245 2270
2246 2271 #else /* BIG ENDIAN */
2247 2272 #define LE_SWAP32_BUFFER(_b, _c)
2248 2273 #define LE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c)
2249 2274 #define LE_SWAP64(_x) (_x)
2250 2275 #define LE_SWAP32(_x) (_x)
2251 2276 #define LE_SWAP16(_x) (_x)
2252 2277 #define LE_SWAP24_LO(_x) (_x)
2253 2278 #define LE_SWAP24_HI(_x) (_x)
2254 2279 #endif /* EMLXS_LITTLE_ENDIAN */
2255 2280
2256 2281 /* These BE_SWAPs will only swap on a BE platform */
2257 2282 #ifdef EMLXS_BIG_ENDIAN
2258 2283 #define BE_SWAP32_BUFFER(_b, _c) SWAP32_BUFFER(_b, _c)
2259 2284 #define BE_SWAP32_BCOPY(_s, _d, _c) SWAP32_BCOPY(_s, _d, _c)
2260 2285 #define BE_SWAP64(_x) SWAP64(_x)
2261 2286 #define BE_SWAP32(_x) SWAP32(_x)
2262 2287 #define BE_SWAP16(_x) SWAP16(_x)
2263 2288 #else /* LITTLE ENDIAN */
2264 2289 #define BE_SWAP32_BUFFER(_b, _c)
2265 2290 #define BE_SWAP32_BCOPY(_s, _d, _c) bcopy(_s, _d, _c)
2266 2291 #define BE_SWAP64(_x) (_x)
2267 2292 #define BE_SWAP32(_x) (_x)
2268 2293 #define BE_SWAP16(_x) (_x)
2269 2294 #endif /* EMLXS_BIG_ENDIAN */
2270 2295
2271 2296 #define EMLXS_DFC_RESET_ALL 0x10
2272 2297 #define EMLXS_DFC_RESET_ALL_FORCE_DUMP 0x11
2273 2298
2274 2299 #ifdef __cplusplus
2275 2300 }
2276 2301 #endif
2277 2302
2278 2303 #endif /* _EMLXS_FC_H */
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