5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _EMLXS_FC_H
28 #define _EMLXS_FC_H
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 typedef struct emlxs_buf
35 {
36 fc_packet_t *pkt; /* scsi_pkt reference */
37 struct emlxs_port *port; /* pointer to port */
38 void *bmp; /* Save the buffer pointer */
39 /* list for later use. */
40 struct emlxs_buf *fc_fwd; /* Use it by chip_Q */
41 struct emlxs_buf *fc_bkwd; /* Use it by chip_Q */
42 struct emlxs_buf *next; /* Use it when the iodone */
43 struct emlxs_node *node;
44 void *channel; /* Save channel and used by */
477
478
479 #define NADDR_LEN 6 /* MAC network address length */
480 typedef struct emlxs_fcip_nethdr
481 {
482 NAME_TYPE fc_destname; /* destination port name */
483 NAME_TYPE fc_srcname; /* source port name */
484 } emlxs_fcip_nethdr_t;
485 typedef emlxs_fcip_nethdr_t NETHDR;
486
487
488 #define MEM_NLP 0 /* memory segment to hold node list entries */
489 #define MEM_IOCB 1 /* memory segment to hold iocb commands */
490 #define MEM_MBOX 2 /* memory segment to hold mailbox cmds */
491 #define MEM_BPL 3 /* and to hold buffer ptr lists - SLI2 */
492 #define MEM_BUF 4 /* memory segment to hold buffer data */
493 #define MEM_ELSBUF 4 /* memory segment to hold buffer data */
494 #define MEM_IPBUF 5 /* memory segment to hold IP buffer data */
495 #define MEM_CTBUF 6 /* memory segment to hold CT buffer data */
496 #define MEM_FCTBUF 7 /* memory segment to hold FCT buffer data */
497
498 #ifdef SFCT_SUPPORT
499 #define FC_MAX_SEG 8
500 #define MEM_FCTSEG 10 /* must be greater than FC_MAX_SEG */
501 #else
502 #define FC_MAX_SEG 7
503 #endif /* SFCT_SUPPORT */
504
505
506 /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
507 #define BPL_TO_SGLLEN(_bpl) ((_bpl/12)-2)
508 #define MEM_BPL_SIZE 36 /* Default size */
509
510 /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
511 #define SGL_TO_SGLLEN(_sgl) ((_sgl/16)-2)
512 #define MEM_SGL_SIZE 4096 /* Default size */
513
514 #define MEM_BUF_SIZE 1024
515 #define MEM_BUF_COUNT 64
516
517 #define MEM_ELSBUF_SIZE MEM_BUF_SIZE
518 #define MEM_ELSBUF_COUNT hba->max_nodes
519 #define MEM_IPBUF_SIZE 65535
520 #define MEM_IPBUF_COUNT 60
521 #define MEM_CTBUF_SIZE MAX_CT_PAYLOAD /* (1024*320) */
522 #define MEM_CTBUF_COUNT 8
1832
1833 #define FC_NPIV_ENABLED 0x00000010 /* NPIV enabled on adapter */
1834 #define FC_NPIV_SUPPORTED 0x00000020 /* NPIV supported on fabric */
1835 #define FC_NPIV_UNSUPPORTED 0x00000040 /* NPIV unsupported on fabric */
1836 #define FC_NPIV_LINKUP 0x00000100 /* NPIV enabled, supported, */
1837 /* and link is ready */
1838 #define FC_NPIV_DELAY_REQUIRED 0x00000200 /* Delay issuing FLOGI/FDISC */
1839 /* and NameServer cmds */
1840
1841 #define FC_BOOTSTRAPMB_INIT 0x00000400
1842 #define FC_FIP_SUPPORTED 0x00000800 /* FIP supported */
1843
1844 #define FC_FABRIC_ATTACHED 0x00001000
1845 #define FC_PT_TO_PT 0x00002000
1846 #define FC_BYPASSED_MODE 0x00004000
1847 #define FC_MENLO_MODE 0x00008000 /* Menlo maintenance mode */
1848
1849 #define FC_DUMP_SAFE 0x00010000 /* Safe to DUMP */
1850 #define FC_DUMP_ACTIVE 0x00020000 /* DUMP in progress */
1851 #define FC_NEW_FABRIC 0x00040000
1852
1853 #define FC_SLIM2_MODE 0x00100000 /* SLIM in host memory */
1854 #define FC_INTERLOCKED 0x00200000
1855 #define FC_HBQ_ENABLED 0x00400000
1856 #define FC_ASYNC_EVENTS 0x00800000
1857
1858 #define FC_ILB_MODE 0x01000000
1859 #define FC_ELB_MODE 0x02000000
1860 #define FC_LOOPBACK_MODE 0x03000000 /* Loopback Mode Mask */
1861 #define FC_DUMP 0x04000000 /* DUMP in progress */
1862 #define FC_SHUTDOWN 0x08000000 /* SHUTDOWN in progress */
1863
1864 #define FC_OVERTEMP_EVENT 0x10000000 /* FC_ERROR reason: */
1865 /* over temperature event */
1866 #define FC_MBOX_TIMEOUT 0x20000000 /* FC_ERROR reason: */
1867 /* mailbox timeout event */
1868 #define FC_DMA_CHECK_ERROR 0x40000000 /* Shared memory (slim,..) */
1869 /* DMA handle went bad */
1870 #define FC_HARDWARE_ERROR 0x80000000 /* FC_ERROR state triggered */
1871
1995 uint32_t ioctl_flags;
1996 #define EMLXS_OPEN 0x00000001
1997 #define EMLXS_OPEN_EXCLUSIVE 0x00000002
1998
1999 /* Timer management */
2000 kcondvar_t timer_lock_cv;
2001 kmutex_t timer_lock;
2002 timeout_id_t timer_id;
2003 uint32_t timer_tics;
2004 uint32_t timer_flags;
2005 #define EMLXS_TIMER_STARTED 0x0000001
2006 #define EMLXS_TIMER_BUSY 0x0000002
2007 #define EMLXS_TIMER_KILL 0x0000004
2008 #define EMLXS_TIMER_ENDED 0x0000008
2009
2010 /* Misc Timers */
2011 uint32_t linkup_timer;
2012 uint32_t discovery_timer;
2013 uint32_t pkt_timer;
2014
2015 /* Power Management */
2016 uint32_t pm_state;
2017 /* pm_state */
2018 #define EMLXS_PM_IN_ATTACH 0x00000001
2019 #define EMLXS_PM_IN_DETACH 0x00000002
2020 #define EMLXS_PM_IN_SOL_CB 0x00000010
2021 #define EMLXS_PM_IN_UNSOL_CB 0x00000020
2022 #define EMLXS_PM_IN_LINK_RESET 0x00000100
2023 #define EMLXS_PM_IN_HARD_RESET 0x00000200
2024 #define EMLXS_PM_SUSPENDED 0x01000000
2025
2026 uint32_t pm_level;
2027 /* pm_level */
2028 #define EMLXS_PM_ADAPTER_DOWN 0
2029 #define EMLXS_PM_ADAPTER_UP 1
2030
2031 uint32_t pm_busy;
2032 kmutex_t pm_lock;
2033 uint8_t pm_config[PCI_CONFIG_SIZE];
2034 #ifdef IDLE_TIMER
|
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
26 */
27
28 #ifndef _EMLXS_FC_H
29 #define _EMLXS_FC_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 typedef struct emlxs_buf
36 {
37 fc_packet_t *pkt; /* scsi_pkt reference */
38 struct emlxs_port *port; /* pointer to port */
39 void *bmp; /* Save the buffer pointer */
40 /* list for later use. */
41 struct emlxs_buf *fc_fwd; /* Use it by chip_Q */
42 struct emlxs_buf *fc_bkwd; /* Use it by chip_Q */
43 struct emlxs_buf *next; /* Use it when the iodone */
44 struct emlxs_node *node;
45 void *channel; /* Save channel and used by */
478
479
480 #define NADDR_LEN 6 /* MAC network address length */
481 typedef struct emlxs_fcip_nethdr
482 {
483 NAME_TYPE fc_destname; /* destination port name */
484 NAME_TYPE fc_srcname; /* source port name */
485 } emlxs_fcip_nethdr_t;
486 typedef emlxs_fcip_nethdr_t NETHDR;
487
488
489 #define MEM_NLP 0 /* memory segment to hold node list entries */
490 #define MEM_IOCB 1 /* memory segment to hold iocb commands */
491 #define MEM_MBOX 2 /* memory segment to hold mailbox cmds */
492 #define MEM_BPL 3 /* and to hold buffer ptr lists - SLI2 */
493 #define MEM_BUF 4 /* memory segment to hold buffer data */
494 #define MEM_ELSBUF 4 /* memory segment to hold buffer data */
495 #define MEM_IPBUF 5 /* memory segment to hold IP buffer data */
496 #define MEM_CTBUF 6 /* memory segment to hold CT buffer data */
497 #define MEM_FCTBUF 7 /* memory segment to hold FCT buffer data */
498 #define MEM_SGL1K 8 /* memory segment to hold 1K SGL entries */
499 #define MEM_SGL2K 9 /* memory segment to hold 2K SGL entries */
500 #define MEM_SGL4K 10 /* memory segment to hold 4K SGL entries */
501
502 #ifdef SFCT_SUPPORT
503 #define FC_MAX_SEG 11
504 #define MEM_FCTSEG 13 /* must be greater than FC_MAX_SEG */
505 #else
506 #define FC_MAX_SEG 10
507 #endif /* SFCT_SUPPORT */
508
509
510 /* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
511 #define BPL_TO_SGLLEN(_bpl) ((_bpl/12)-2)
512 #define MEM_BPL_SIZE 36 /* Default size */
513
514 /* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
515 #define SGL_TO_SGLLEN(_sgl) ((_sgl/16)-2)
516 #define MEM_SGL_SIZE 4096 /* Default size */
517
518 #define MEM_BUF_SIZE 1024
519 #define MEM_BUF_COUNT 64
520
521 #define MEM_ELSBUF_SIZE MEM_BUF_SIZE
522 #define MEM_ELSBUF_COUNT hba->max_nodes
523 #define MEM_IPBUF_SIZE 65535
524 #define MEM_IPBUF_COUNT 60
525 #define MEM_CTBUF_SIZE MAX_CT_PAYLOAD /* (1024*320) */
526 #define MEM_CTBUF_COUNT 8
1836
1837 #define FC_NPIV_ENABLED 0x00000010 /* NPIV enabled on adapter */
1838 #define FC_NPIV_SUPPORTED 0x00000020 /* NPIV supported on fabric */
1839 #define FC_NPIV_UNSUPPORTED 0x00000040 /* NPIV unsupported on fabric */
1840 #define FC_NPIV_LINKUP 0x00000100 /* NPIV enabled, supported, */
1841 /* and link is ready */
1842 #define FC_NPIV_DELAY_REQUIRED 0x00000200 /* Delay issuing FLOGI/FDISC */
1843 /* and NameServer cmds */
1844
1845 #define FC_BOOTSTRAPMB_INIT 0x00000400
1846 #define FC_FIP_SUPPORTED 0x00000800 /* FIP supported */
1847
1848 #define FC_FABRIC_ATTACHED 0x00001000
1849 #define FC_PT_TO_PT 0x00002000
1850 #define FC_BYPASSED_MODE 0x00004000
1851 #define FC_MENLO_MODE 0x00008000 /* Menlo maintenance mode */
1852
1853 #define FC_DUMP_SAFE 0x00010000 /* Safe to DUMP */
1854 #define FC_DUMP_ACTIVE 0x00020000 /* DUMP in progress */
1855 #define FC_NEW_FABRIC 0x00040000
1856 #define FC_GPIO_LINK_UP 0x00080000
1857
1858 #define FC_SLIM2_MODE 0x00100000 /* SLIM in host memory */
1859 #define FC_INTERLOCKED 0x00200000
1860 #define FC_HBQ_ENABLED 0x00400000
1861 #define FC_ASYNC_EVENTS 0x00800000
1862
1863 #define FC_ILB_MODE 0x01000000
1864 #define FC_ELB_MODE 0x02000000
1865 #define FC_LOOPBACK_MODE 0x03000000 /* Loopback Mode Mask */
1866 #define FC_DUMP 0x04000000 /* DUMP in progress */
1867 #define FC_SHUTDOWN 0x08000000 /* SHUTDOWN in progress */
1868
1869 #define FC_OVERTEMP_EVENT 0x10000000 /* FC_ERROR reason: */
1870 /* over temperature event */
1871 #define FC_MBOX_TIMEOUT 0x20000000 /* FC_ERROR reason: */
1872 /* mailbox timeout event */
1873 #define FC_DMA_CHECK_ERROR 0x40000000 /* Shared memory (slim,..) */
1874 /* DMA handle went bad */
1875 #define FC_HARDWARE_ERROR 0x80000000 /* FC_ERROR state triggered */
1876
2000 uint32_t ioctl_flags;
2001 #define EMLXS_OPEN 0x00000001
2002 #define EMLXS_OPEN_EXCLUSIVE 0x00000002
2003
2004 /* Timer management */
2005 kcondvar_t timer_lock_cv;
2006 kmutex_t timer_lock;
2007 timeout_id_t timer_id;
2008 uint32_t timer_tics;
2009 uint32_t timer_flags;
2010 #define EMLXS_TIMER_STARTED 0x0000001
2011 #define EMLXS_TIMER_BUSY 0x0000002
2012 #define EMLXS_TIMER_KILL 0x0000004
2013 #define EMLXS_TIMER_ENDED 0x0000008
2014
2015 /* Misc Timers */
2016 uint32_t linkup_timer;
2017 uint32_t discovery_timer;
2018 uint32_t pkt_timer;
2019
2020 /* GPIO Management */
2021 uint8_t gpio_desired;
2022 uint8_t gpio_current;
2023 uint8_t gpio_bit;
2024 #define EMLXS_GPIO_LO 0x01
2025 #define EMLXS_GPIO_HI 0x02
2026 #define EMLXS_GPIO_ACT 0x04
2027 #define EMLXS_GPIO_LASER 0x08
2028 #define EMLXS_GPIO_LOC 0x10
2029
2030 uint8_t gpio_pin[4];
2031
2032 #define EMLXS_GPIO_PIN_LO 0
2033 #define EMLXS_GPIO_PIN_HI 1
2034 #define EMLXS_GPIO_PIN_ACT 2
2035 #define EMLXS_GPIO_PIN_LASER 3
2036
2037 kmutex_t gpio_lock; /* Timer lock */
2038 timeout_id_t gpio_timer;
2039
2040 /* Power Management */
2041 uint32_t pm_state;
2042 /* pm_state */
2043 #define EMLXS_PM_IN_ATTACH 0x00000001
2044 #define EMLXS_PM_IN_DETACH 0x00000002
2045 #define EMLXS_PM_IN_SOL_CB 0x00000010
2046 #define EMLXS_PM_IN_UNSOL_CB 0x00000020
2047 #define EMLXS_PM_IN_LINK_RESET 0x00000100
2048 #define EMLXS_PM_IN_HARD_RESET 0x00000200
2049 #define EMLXS_PM_SUSPENDED 0x01000000
2050
2051 uint32_t pm_level;
2052 /* pm_level */
2053 #define EMLXS_PM_ADAPTER_DOWN 0
2054 #define EMLXS_PM_ADAPTER_UP 1
2055
2056 uint32_t pm_busy;
2057 kmutex_t pm_lock;
2058 uint8_t pm_config[PCI_CONFIG_SIZE];
2059 #ifdef IDLE_TIMER
|