MFV: illumos-gate@2aba3acda67326648fd60aaf2bfb4e18ee8c04ed
9816 Multi-TRB xhci transfers should use event data
9817 xhci needs to always set slot context
8550 increase xhci bulk transfer sgl count
9818 xhci_transfer_get_tdsize can return values that are too large
Reviewed by: Alex Wilson <alex.wilson@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Approved by: Joshua M. Clulow <josh@sysmgr.org>
Author: Robert Mustacchi <rm@joyent.com>

*** 8,18 ****
   * source.  A copy of the CDDL is also available via the Internet at
   * http://www.illumos.org/license/CDDL.
   */
  
  /*
!  * Copyright 2016 Joyent, Inc.
   */
  
  /*
   * -----------------------------
   * xHCI Ring Management Routines
--- 8,18 ----
   * source.  A copy of the CDDL is also available via the Internet at
   * http://www.illumos.org/license/CDDL.
   */
  
  /*
!  * Copyright (c) 2018, Joyent, Inc.
   */
  
  /*
   * -----------------------------
   * xHCI Ring Management Routines
*** 286,296 ****
   * advance, otherwise we leave the existing cycle bit untouched so the system
   * doesn't accidentally advance until we have everything filled in.
   */
  void
  xhci_ring_trb_fill(xhci_ring_t *xrp, uint_t trboff, xhci_trb_t *host_trb,
!     boolean_t put_cycle)
  {
          uint_t i;
          uint32_t flags;
          uint_t ent = xrp->xr_head;
          uint8_t cycle = xrp->xr_cycle;
--- 286,296 ----
   * advance, otherwise we leave the existing cycle bit untouched so the system
   * doesn't accidentally advance until we have everything filled in.
   */
  void
  xhci_ring_trb_fill(xhci_ring_t *xrp, uint_t trboff, xhci_trb_t *host_trb,
!     uint64_t *trb_pap, boolean_t put_cycle)
  {
          uint_t i;
          uint32_t flags;
          uint_t ent = xrp->xr_head;
          uint8_t cycle = xrp->xr_cycle;
*** 322,331 ****
--- 322,345 ----
          } else {
                  flags |= LE_32(XHCI_TRB_CYCLE);
          }
  
          trb->trb_flags = flags;
+ 
+         if (trb_pap != NULL) {
+                 uint64_t pa;
+ 
+                 /*
+                  * This logic only works if we have a single cookie address.
+                  * However, this is prettty tightly assumed for rings through
+                  * the xhci driver at this time.
+                  */
+                 ASSERT3U(xrp->xr_dma.xdb_ncookies, ==, 1);
+                 pa = xrp->xr_dma.xdb_cookies[0].dmac_laddress;
+                 pa += ((uintptr_t)trb - (uintptr_t)&xrp->xr_trb[0]);
+                 *trb_pap = pa;
+         }
  }
  
  /*
   * Update our metadata for the ring and verify the cycle bit is correctly set
   * for the first trb. It is expected that it is incorrectly set.
*** 378,388 ****
   * likely to mess up some of the required semantics.
   */
  void
  xhci_ring_trb_put(xhci_ring_t *xrp, xhci_trb_t *trb)
  {
!         xhci_ring_trb_fill(xrp, 0U, trb, B_FALSE);
          xhci_ring_trb_produce(xrp, 1U);
  }
  
  /*
   * Update the tail pointer for a ring based on the DMA address of a consumed
--- 392,402 ----
   * likely to mess up some of the required semantics.
   */
  void
  xhci_ring_trb_put(xhci_ring_t *xrp, xhci_trb_t *trb)
  {
!         xhci_ring_trb_fill(xrp, 0U, trb, NULL, B_FALSE);
          xhci_ring_trb_produce(xrp, 1U);
  }
  
  /*
   * Update the tail pointer for a ring based on the DMA address of a consumed