1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * EHCI Host Controller Driver (EHCI)
28 *
29 * The EHCI driver is a software driver which interfaces to the Universal
30 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to
31 * the Host Controller is defined by the EHCI Host Controller Interface.
32 *
33 * This module contains the main EHCI driver code which handles all USB
34 * transfers, bandwidth allocations and other general functionalities.
35 */
36
37 #include <sys/usb/hcd/ehci/ehcid.h>
38 #include <sys/usb/hcd/ehci/ehci_isoch.h>
39 #include <sys/usb/hcd/ehci/ehci_xfer.h>
40
41 /*
42 * EHCI MSI tunable:
43 *
44 * By default MSI is enabled on all supported platforms except for the
45 * EHCI controller of ULI1575 South bridge.
46 */
47 boolean_t ehci_enable_msi = B_TRUE;
48
49 /* Pointer to the state structure */
50 extern void *ehci_statep;
51
52 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *);
53
54 extern uint_t ehci_vt62x2_workaround;
55 extern int force_ehci_off;
56
57 /* Adjustable variables for the size of the pools */
58 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE;
59 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE;
60
61 /*
62 * Initialize the values which the order of 32ms intr qh are executed
63 * by the host controller in the lattice tree.
64 */
65 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] =
66 {0x00, 0x10, 0x08, 0x18,
67 0x04, 0x14, 0x0c, 0x1c,
68 0x02, 0x12, 0x0a, 0x1a,
69 0x06, 0x16, 0x0e, 0x1e,
70 0x01, 0x11, 0x09, 0x19,
71 0x05, 0x15, 0x0d, 0x1d,
72 0x03, 0x13, 0x0b, 0x1b,
73 0x07, 0x17, 0x0f, 0x1f};
74
75 /*
76 * Initialize the values which are used to calculate start split mask
77 * for the low/full/high speed interrupt and isochronous endpoints.
78 */
79 static uint_t ehci_start_split_mask[15] = {
80 /*
81 * For high/full/low speed usb devices. For high speed
82 * device with polling interval greater than or equal
83 * to 8us (125us).
84 */
85 0x01, /* 00000001 */
86 0x02, /* 00000010 */
87 0x04, /* 00000100 */
88 0x08, /* 00001000 */
89 0x10, /* 00010000 */
90 0x20, /* 00100000 */
91 0x40, /* 01000000 */
92 0x80, /* 10000000 */
93
94 /* Only for high speed devices with polling interval 4us */
95 0x11, /* 00010001 */
96 0x22, /* 00100010 */
97 0x44, /* 01000100 */
98 0x88, /* 10001000 */
99
100 /* Only for high speed devices with polling interval 2us */
101 0x55, /* 01010101 */
102 0xaa, /* 10101010 */
103
104 /* Only for high speed devices with polling interval 1us */
105 0xff /* 11111111 */
106 };
107
108 /*
109 * Initialize the values which are used to calculate complete split mask
110 * for the low/full speed interrupt and isochronous endpoints.
111 */
112 static uint_t ehci_intr_complete_split_mask[7] = {
113 /* Only full/low speed devices */
114 0x1c, /* 00011100 */
115 0x38, /* 00111000 */
116 0x70, /* 01110000 */
117 0xe0, /* 11100000 */
118 0x00, /* Need FSTN feature */
119 0x00, /* Need FSTN feature */
120 0x00 /* Need FSTN feature */
121 };
122
123
124 /*
125 * EHCI Internal Function Prototypes
126 */
127
128 /* Host Controller Driver (HCD) initialization functions */
129 void ehci_set_dma_attributes(ehci_state_t *ehcip);
130 int ehci_allocate_pools(ehci_state_t *ehcip);
131 void ehci_decode_ddi_dma_addr_bind_handle_result(
132 ehci_state_t *ehcip,
133 int result);
134 int ehci_map_regs(ehci_state_t *ehcip);
135 int ehci_register_intrs_and_init_mutex(
136 ehci_state_t *ehcip);
137 static int ehci_add_intrs(ehci_state_t *ehcip,
138 int intr_type);
139 int ehci_init_ctlr(ehci_state_t *ehcip,
140 int init_type);
141 static int ehci_take_control(ehci_state_t *ehcip);
142 static int ehci_init_periodic_frame_lst_table(
143 ehci_state_t *ehcip);
144 static void ehci_build_interrupt_lattice(
145 ehci_state_t *ehcip);
146 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip);
147
148 /* Host Controller Driver (HCD) deinitialization functions */
149 int ehci_cleanup(ehci_state_t *ehcip);
150 static void ehci_rem_intrs(ehci_state_t *ehcip);
151 int ehci_cpr_suspend(ehci_state_t *ehcip);
152 int ehci_cpr_resume(ehci_state_t *ehcip);
153
154 /* Bandwidth Allocation functions */
155 int ehci_allocate_bandwidth(ehci_state_t *ehcip,
156 usba_pipe_handle_data_t *ph,
157 uint_t *pnode,
158 uchar_t *smask,
159 uchar_t *cmask);
160 static int ehci_allocate_high_speed_bandwidth(
161 ehci_state_t *ehcip,
162 usba_pipe_handle_data_t *ph,
163 uint_t *hnode,
164 uchar_t *smask,
165 uchar_t *cmask);
166 static int ehci_allocate_classic_tt_bandwidth(
167 ehci_state_t *ehcip,
168 usba_pipe_handle_data_t *ph,
169 uint_t pnode);
170 void ehci_deallocate_bandwidth(ehci_state_t *ehcip,
171 usba_pipe_handle_data_t *ph,
172 uint_t pnode,
173 uchar_t smask,
174 uchar_t cmask);
175 static void ehci_deallocate_high_speed_bandwidth(
176 ehci_state_t *ehcip,
177 usba_pipe_handle_data_t *ph,
178 uint_t hnode,
179 uchar_t smask,
180 uchar_t cmask);
181 static void ehci_deallocate_classic_tt_bandwidth(
182 ehci_state_t *ehcip,
183 usba_pipe_handle_data_t *ph,
184 uint_t pnode);
185 static int ehci_compute_high_speed_bandwidth(
186 ehci_state_t *ehcip,
187 usb_ep_descr_t *endpoint,
188 usb_port_status_t port_status,
189 uint_t *sbandwidth,
190 uint_t *cbandwidth);
191 static int ehci_compute_classic_bandwidth(
192 usb_ep_descr_t *endpoint,
193 usb_port_status_t port_status,
194 uint_t *bandwidth);
195 int ehci_adjust_polling_interval(
196 ehci_state_t *ehcip,
197 usb_ep_descr_t *endpoint,
198 usb_port_status_t port_status);
199 static int ehci_adjust_high_speed_polling_interval(
200 ehci_state_t *ehcip,
201 usb_ep_descr_t *endpoint);
202 static uint_t ehci_lattice_height(uint_t interval);
203 static uint_t ehci_lattice_parent(uint_t node);
204 static uint_t ehci_find_periodic_node(
205 uint_t leaf,
206 int interval);
207 static uint_t ehci_leftmost_leaf(uint_t node,
208 uint_t height);
209 static uint_t ehci_pow_2(uint_t x);
210 static uint_t ehci_log_2(uint_t x);
211 static int ehci_find_bestfit_hs_mask(
212 ehci_state_t *ehcip,
213 uchar_t *smask,
214 uint_t *pnode,
215 usb_ep_descr_t *endpoint,
216 uint_t bandwidth,
217 int interval);
218 static int ehci_find_bestfit_ls_intr_mask(
219 ehci_state_t *ehcip,
220 uchar_t *smask,
221 uchar_t *cmask,
222 uint_t *pnode,
223 uint_t sbandwidth,
224 uint_t cbandwidth,
225 int interval);
226 static int ehci_find_bestfit_sitd_in_mask(
227 ehci_state_t *ehcip,
228 uchar_t *smask,
229 uchar_t *cmask,
230 uint_t *pnode,
231 uint_t sbandwidth,
232 uint_t cbandwidth,
233 int interval);
234 static int ehci_find_bestfit_sitd_out_mask(
235 ehci_state_t *ehcip,
236 uchar_t *smask,
237 uint_t *pnode,
238 uint_t sbandwidth,
239 int interval);
240 static uint_t ehci_calculate_bw_availability_mask(
241 ehci_state_t *ehcip,
242 uint_t bandwidth,
243 int leaf,
244 int leaf_count,
245 uchar_t *bw_mask);
246 static void ehci_update_bw_availability(
247 ehci_state_t *ehcip,
248 int bandwidth,
249 int leftmost_leaf,
250 int leaf_count,
251 uchar_t mask);
252
253 /* Miscellaneous functions */
254 ehci_state_t *ehci_obtain_state(
255 dev_info_t *dip);
256 int ehci_state_is_operational(
257 ehci_state_t *ehcip);
258 int ehci_do_soft_reset(
259 ehci_state_t *ehcip);
260 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip,
261 ehci_pipe_private_t *pp,
262 ehci_trans_wrapper_t *tw);
263 usb_frame_number_t ehci_get_current_frame_number(
264 ehci_state_t *ehcip);
265 static void ehci_cpr_cleanup(
266 ehci_state_t *ehcip);
267 int ehci_wait_for_sof(
268 ehci_state_t *ehcip);
269 void ehci_toggle_scheduler(
270 ehci_state_t *ehcip);
271 void ehci_print_caps(ehci_state_t *ehcip);
272 void ehci_print_regs(ehci_state_t *ehcip);
273 void ehci_print_qh(ehci_state_t *ehcip,
274 ehci_qh_t *qh);
275 void ehci_print_qtd(ehci_state_t *ehcip,
276 ehci_qtd_t *qtd);
277 void ehci_create_stats(ehci_state_t *ehcip);
278 void ehci_destroy_stats(ehci_state_t *ehcip);
279 void ehci_do_intrs_stats(ehci_state_t *ehcip,
280 int val);
281 void ehci_do_byte_stats(ehci_state_t *ehcip,
282 size_t len,
283 uint8_t attr,
284 uint8_t addr);
285
286 /*
287 * check if this ehci controller can support PM
288 */
289 int
290 ehci_hcdi_pm_support(dev_info_t *dip)
291 {
292 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep,
293 ddi_get_instance(dip));
294
295 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) &&
296 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) ||
297
298 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) &&
299 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) ||
300
301 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) {
302
303 return (USB_SUCCESS);
304 }
305
306 return (USB_FAILURE);
307 }
308
309 void
310 ehci_dma_attr_workaround(ehci_state_t *ehcip)
311 {
312 /*
313 * Some Nvidia chips can not handle qh dma address above 2G.
314 * The bit 31 of the dma address might be omitted and it will
315 * cause system crash or other unpredicable result. So force
316 * the dma address allocated below 2G to make ehci work.
317 */
318 if (PCI_VENDOR_NVIDIA == ehcip->ehci_vendor_id) {
319 switch (ehcip->ehci_device_id) {
320 case PCI_DEVICE_NVIDIA_CK804:
321 case PCI_DEVICE_NVIDIA_MCP04:
322 USB_DPRINTF_L2(PRINT_MASK_ATTA,
323 ehcip->ehci_log_hdl,
324 "ehci_dma_attr_workaround: NVIDIA dma "
325 "workaround enabled, force dma address "
326 "to be allocated below 2G");
327 ehcip->ehci_dma_attr.dma_attr_addr_hi =
328 0x7fffffffull;
329 break;
330 default:
331 break;
332
333 }
334 }
335 }
336
337 /*
338 * Host Controller Driver (HCD) initialization functions
339 */
340
341 /*
342 * ehci_set_dma_attributes:
343 *
344 * Set the limits in the DMA attributes structure. Most of the values used
345 * in the DMA limit structures are the default values as specified by the
346 * Writing PCI device drivers document.
347 */
348 void
349 ehci_set_dma_attributes(ehci_state_t *ehcip)
350 {
351 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
352 "ehci_set_dma_attributes:");
353
354 /* Initialize the DMA attributes */
355 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0;
356 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull;
357 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull;
358
359 /* 32 bit addressing */
360 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX;
361
362 /* Byte alignment */
363 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT;
364
365 /*
366 * Since PCI specification is byte alignment, the
367 * burst size field should be set to 1 for PCI devices.
368 */
369 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1;
370
371 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1;
372 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER;
373 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull;
374 ehcip->ehci_dma_attr.dma_attr_sgllen = 1;
375 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR;
376 ehcip->ehci_dma_attr.dma_attr_flags = 0;
377 ehci_dma_attr_workaround(ehcip);
378 }
379
380
381 /*
382 * ehci_allocate_pools:
383 *
384 * Allocate the system memory for the Endpoint Descriptor (QH) and for the
385 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned
386 * to a 16 byte boundary.
387 */
388 int
389 ehci_allocate_pools(ehci_state_t *ehcip)
390 {
391 ddi_device_acc_attr_t dev_attr;
392 size_t real_length;
393 int result;
394 uint_t ccount;
395 int i;
396
397 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
398 "ehci_allocate_pools:");
399
400 /* The host controller will be little endian */
401 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
402 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
403 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
404
405 /* Byte alignment */
406 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT;
407
408 /* Allocate the QTD pool DMA handle */
409 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr,
410 DDI_DMA_SLEEP, 0,
411 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) {
412
413 goto failure;
414 }
415
416 /* Allocate the memory for the QTD pool */
417 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle,
418 ehci_qtd_pool_size * sizeof (ehci_qtd_t),
419 &dev_attr,
420 DDI_DMA_CONSISTENT,
421 DDI_DMA_SLEEP,
422 0,
423 (caddr_t *)&ehcip->ehci_qtd_pool_addr,
424 &real_length,
425 &ehcip->ehci_qtd_pool_mem_handle)) {
426
427 goto failure;
428 }
429
430 /* Map the QTD pool into the I/O address space */
431 result = ddi_dma_addr_bind_handle(
432 ehcip->ehci_qtd_pool_dma_handle,
433 NULL,
434 (caddr_t)ehcip->ehci_qtd_pool_addr,
435 real_length,
436 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
437 DDI_DMA_SLEEP,
438 NULL,
439 &ehcip->ehci_qtd_pool_cookie,
440 &ccount);
441
442 bzero((void *)ehcip->ehci_qtd_pool_addr,
443 ehci_qtd_pool_size * sizeof (ehci_qtd_t));
444
445 /* Process the result */
446 if (result == DDI_DMA_MAPPED) {
447 /* The cookie count should be 1 */
448 if (ccount != 1) {
449 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
450 "ehci_allocate_pools: More than 1 cookie");
451
452 goto failure;
453 }
454 } else {
455 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
456 "ehci_allocate_pools: Result = %d", result);
457
458 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result);
459
460 goto failure;
461 }
462
463 /*
464 * DMA addresses for QTD pools are bound
465 */
466 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND;
467
468 /* Initialize the QTD pool */
469 for (i = 0; i < ehci_qtd_pool_size; i ++) {
470 Set_QTD(ehcip->ehci_qtd_pool_addr[i].
471 qtd_state, EHCI_QTD_FREE);
472 }
473
474 /* Allocate the QTD pool DMA handle */
475 if (ddi_dma_alloc_handle(ehcip->ehci_dip,
476 &ehcip->ehci_dma_attr,
477 DDI_DMA_SLEEP,
478 0,
479 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) {
480 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
481 "ehci_allocate_pools: ddi_dma_alloc_handle failed");
482
483 goto failure;
484 }
485
486 /* Allocate the memory for the QH pool */
487 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle,
488 ehci_qh_pool_size * sizeof (ehci_qh_t),
489 &dev_attr,
490 DDI_DMA_CONSISTENT,
491 DDI_DMA_SLEEP,
492 0,
493 (caddr_t *)&ehcip->ehci_qh_pool_addr,
494 &real_length,
495 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) {
496 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
497 "ehci_allocate_pools: ddi_dma_mem_alloc failed");
498
499 goto failure;
500 }
501
502 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle,
503 NULL,
504 (caddr_t)ehcip->ehci_qh_pool_addr,
505 real_length,
506 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
507 DDI_DMA_SLEEP,
508 NULL,
509 &ehcip->ehci_qh_pool_cookie,
510 &ccount);
511
512 bzero((void *)ehcip->ehci_qh_pool_addr,
513 ehci_qh_pool_size * sizeof (ehci_qh_t));
514
515 /* Process the result */
516 if (result == DDI_DMA_MAPPED) {
517 /* The cookie count should be 1 */
518 if (ccount != 1) {
519 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
520 "ehci_allocate_pools: More than 1 cookie");
521
522 goto failure;
523 }
524 } else {
525 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result);
526
527 goto failure;
528 }
529
530 /*
531 * DMA addresses for QH pools are bound
532 */
533 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND;
534
535 /* Initialize the QH pool */
536 for (i = 0; i < ehci_qh_pool_size; i ++) {
537 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE);
538 }
539
540 /* Byte alignment */
541 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT;
542
543 return (DDI_SUCCESS);
544
545 failure:
546 /* Byte alignment */
547 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT;
548
549 return (DDI_FAILURE);
550 }
551
552
553 /*
554 * ehci_decode_ddi_dma_addr_bind_handle_result:
555 *
556 * Process the return values of ddi_dma_addr_bind_handle()
557 */
558 void
559 ehci_decode_ddi_dma_addr_bind_handle_result(
560 ehci_state_t *ehcip,
561 int result)
562 {
563 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl,
564 "ehci_decode_ddi_dma_addr_bind_handle_result:");
565
566 switch (result) {
567 case DDI_DMA_PARTIAL_MAP:
568 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl,
569 "Partial transfers not allowed");
570 break;
571 case DDI_DMA_INUSE:
572 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl,
573 "Handle is in use");
574 break;
575 case DDI_DMA_NORESOURCES:
576 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl,
577 "No resources");
578 break;
579 case DDI_DMA_NOMAPPING:
580 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl,
581 "No mapping");
582 break;
583 case DDI_DMA_TOOBIG:
584 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl,
585 "Object is too big");
586 break;
587 default:
588 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl,
589 "Unknown dma error");
590 }
591 }
592
593
594 /*
595 * ehci_map_regs:
596 *
597 * The Host Controller (HC) contains a set of on-chip operational registers
598 * and which should be mapped into a non-cacheable portion of the system
599 * addressable space.
600 */
601 int
602 ehci_map_regs(ehci_state_t *ehcip)
603 {
604 ddi_device_acc_attr_t attr;
605 uint16_t cmd_reg;
606 uint_t length;
607
608 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:");
609
610 /* Check to make sure we have memory access */
611 if (pci_config_setup(ehcip->ehci_dip,
612 &ehcip->ehci_config_handle) != DDI_SUCCESS) {
613
614 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
615 "ehci_map_regs: Config error");
616
617 return (DDI_FAILURE);
618 }
619
620 /* Make sure Memory Access Enable is set */
621 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM);
622
623 if (!(cmd_reg & PCI_COMM_MAE)) {
624
625 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
626 "ehci_map_regs: Memory base address access disabled");
627
628 return (DDI_FAILURE);
629 }
630
631 /* The host controller will be little endian */
632 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
633 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
634 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
635
636 /* Map in EHCI Capability registers */
637 if (ddi_regs_map_setup(ehcip->ehci_dip, 1,
638 (caddr_t *)&ehcip->ehci_capsp, 0,
639 sizeof (ehci_caps_t), &attr,
640 &ehcip->ehci_caps_handle) != DDI_SUCCESS) {
641
642 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
643 "ehci_map_regs: Map setup error");
644
645 return (DDI_FAILURE);
646 }
647
648 length = ddi_get8(ehcip->ehci_caps_handle,
649 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length);
650
651 /* Free the original mapping */
652 ddi_regs_map_free(&ehcip->ehci_caps_handle);
653
654 /* Re-map in EHCI Capability and Operational registers */
655 if (ddi_regs_map_setup(ehcip->ehci_dip, 1,
656 (caddr_t *)&ehcip->ehci_capsp, 0,
657 length + sizeof (ehci_regs_t), &attr,
658 &ehcip->ehci_caps_handle) != DDI_SUCCESS) {
659
660 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
661 "ehci_map_regs: Map setup error");
662
663 return (DDI_FAILURE);
664 }
665
666 /* Get the pointer to EHCI Operational Register */
667 ehcip->ehci_regsp = (ehci_regs_t *)
668 ((uintptr_t)ehcip->ehci_capsp + length);
669
670 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
671 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n",
672 (void *)ehcip->ehci_capsp, (void *)ehcip->ehci_regsp);
673
674 return (DDI_SUCCESS);
675 }
676
677 /*
678 * The following simulated polling is for debugging purposes only.
679 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf.
680 */
681 static int
682 ehci_is_polled(dev_info_t *dip)
683 {
684 int ret;
685 char *propval;
686
687 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
688 "usb-polling", &propval) != DDI_SUCCESS)
689
690 return (0);
691
692 ret = (strcmp(propval, "true") == 0);
693 ddi_prop_free(propval);
694
695 return (ret);
696 }
697
698 static void
699 ehci_poll_intr(void *arg)
700 {
701 /* poll every msec */
702 for (;;) {
703 (void) ehci_intr(arg, NULL);
704 delay(drv_usectohz(1000));
705 }
706 }
707
708 /*
709 * ehci_register_intrs_and_init_mutex:
710 *
711 * Register interrupts and initialize each mutex and condition variables
712 */
713 int
714 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip)
715 {
716 int intr_types;
717
718 #if defined(__x86)
719 uint8_t iline;
720 #endif
721
722 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
723 "ehci_register_intrs_and_init_mutex:");
724
725 /*
726 * There is a known MSI hardware bug with the EHCI controller
727 * of ULI1575 southbridge. Hence MSI is disabled for this chip.
728 */
729 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) &&
730 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) {
731 ehcip->ehci_msi_enabled = B_FALSE;
732 } else {
733 /* Set the MSI enable flag from the global EHCI MSI tunable */
734 ehcip->ehci_msi_enabled = ehci_enable_msi;
735 }
736
737 /* launch polling thread instead of enabling pci interrupt */
738 if (ehci_is_polled(ehcip->ehci_dip)) {
739 extern pri_t maxclsyspri;
740
741 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
742 "ehci_register_intrs_and_init_mutex: "
743 "running in simulated polled mode");
744
745 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0,
746 TS_RUN, maxclsyspri);
747
748 goto skip_intr;
749 }
750
751 #if defined(__x86)
752 /*
753 * Make sure that the interrupt pin is connected to the
754 * interrupt controller on x86. Interrupt line 255 means
755 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43).
756 * If we would return failure when interrupt line equals 255, then
757 * high speed devices will be routed to companion host controllers.
758 * However, it is not necessary to return failure here, and
759 * o/uhci codes don't check the interrupt line either.
760 * But it's good to log a message here for debug purposes.
761 */
762 iline = pci_config_get8(ehcip->ehci_config_handle,
763 PCI_CONF_ILINE);
764
765 if (iline == 255) {
766 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
767 "ehci_register_intrs_and_init_mutex: "
768 "interrupt line value out of range (%d)",
769 iline);
770 }
771 #endif /* __x86 */
772
773 /* Get supported interrupt types */
774 if (ddi_intr_get_supported_types(ehcip->ehci_dip,
775 &intr_types) != DDI_SUCCESS) {
776 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
777 "ehci_register_intrs_and_init_mutex: "
778 "ddi_intr_get_supported_types failed");
779
780 return (DDI_FAILURE);
781 }
782
783 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
784 "ehci_register_intrs_and_init_mutex: "
785 "supported interrupt types 0x%x", intr_types);
786
787 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) {
788 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI)
789 != DDI_SUCCESS) {
790 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
791 "ehci_register_intrs_and_init_mutex: MSI "
792 "registration failed, trying FIXED interrupt \n");
793 } else {
794 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
795 "ehci_register_intrs_and_init_mutex: "
796 "Using MSI interrupt type\n");
797
798 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI;
799 ehcip->ehci_flags |= EHCI_INTR;
800 }
801 }
802
803 if ((!(ehcip->ehci_flags & EHCI_INTR)) &&
804 (intr_types & DDI_INTR_TYPE_FIXED)) {
805 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED)
806 != DDI_SUCCESS) {
807 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
808 "ehci_register_intrs_and_init_mutex: "
809 "FIXED interrupt registration failed\n");
810
811 return (DDI_FAILURE);
812 }
813
814 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
815 "ehci_register_intrs_and_init_mutex: "
816 "Using FIXED interrupt type\n");
817
818 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED;
819 ehcip->ehci_flags |= EHCI_INTR;
820 }
821
822 skip_intr:
823 /* Create prototype for advance on async schedule */
824 cv_init(&ehcip->ehci_async_schedule_advance_cv,
825 NULL, CV_DRIVER, NULL);
826
827 return (DDI_SUCCESS);
828 }
829
830
831 /*
832 * ehci_add_intrs:
833 *
834 * Register FIXED or MSI interrupts.
835 */
836 static int
837 ehci_add_intrs(ehci_state_t *ehcip,
838 int intr_type)
839 {
840 int actual, avail, intr_size, count = 0;
841 int i, flag, ret;
842
843 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
844 "ehci_add_intrs: interrupt type 0x%x", intr_type);
845
846 /* Get number of interrupts */
847 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count);
848 if ((ret != DDI_SUCCESS) || (count == 0)) {
849 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
850 "ehci_add_intrs: ddi_intr_get_nintrs() failure, "
851 "ret: %d, count: %d", ret, count);
852
853 return (DDI_FAILURE);
854 }
855
856 /* Get number of available interrupts */
857 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail);
858 if ((ret != DDI_SUCCESS) || (avail == 0)) {
859 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
860 "ehci_add_intrs: ddi_intr_get_navail() failure, "
861 "ret: %d, count: %d", ret, count);
862
863 return (DDI_FAILURE);
864 }
865
866 if (avail < count) {
867 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
868 "ehci_add_intrs: ehci_add_intrs: nintrs () "
869 "returned %d, navail returned %d\n", count, avail);
870 }
871
872 /* Allocate an array of interrupt handles */
873 intr_size = count * sizeof (ddi_intr_handle_t);
874 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP);
875
876 flag = (intr_type == DDI_INTR_TYPE_MSI) ?
877 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL;
878
879 /* call ddi_intr_alloc() */
880 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable,
881 intr_type, 0, count, &actual, flag);
882
883 if ((ret != DDI_SUCCESS) || (actual == 0)) {
884 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
885 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret);
886
887 kmem_free(ehcip->ehci_htable, intr_size);
888
889 return (DDI_FAILURE);
890 }
891
892 if (actual < count) {
893 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
894 "ehci_add_intrs: Requested: %d, Received: %d\n",
895 count, actual);
896
897 for (i = 0; i < actual; i++)
898 (void) ddi_intr_free(ehcip->ehci_htable[i]);
899
900 kmem_free(ehcip->ehci_htable, intr_size);
901
902 return (DDI_FAILURE);
903 }
904
905 ehcip->ehci_intr_cnt = actual;
906
907 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0],
908 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) {
909 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
910 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret);
911
912 for (i = 0; i < actual; i++)
913 (void) ddi_intr_free(ehcip->ehci_htable[i]);
914
915 kmem_free(ehcip->ehci_htable, intr_size);
916
917 return (DDI_FAILURE);
918 }
919
920 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
921 "ehci_add_intrs: Supported Interrupt priority 0x%x",
922 ehcip->ehci_intr_pri);
923
924 /* Test for high level mutex */
925 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) {
926 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
927 "ehci_add_intrs: Hi level interrupt not supported");
928
929 for (i = 0; i < actual; i++)
930 (void) ddi_intr_free(ehcip->ehci_htable[i]);
931
932 kmem_free(ehcip->ehci_htable, intr_size);
933
934 return (DDI_FAILURE);
935 }
936
937 /* Initialize the mutex */
938 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER,
939 DDI_INTR_PRI(ehcip->ehci_intr_pri));
940
941 /* Call ddi_intr_add_handler() */
942 for (i = 0; i < actual; i++) {
943 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i],
944 ehci_intr, (caddr_t)ehcip,
945 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
946 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
947 "ehci_add_intrs:ddi_intr_add_handler() "
948 "failed %d", ret);
949
950 for (i = 0; i < actual; i++)
951 (void) ddi_intr_free(ehcip->ehci_htable[i]);
952
953 mutex_destroy(&ehcip->ehci_int_mutex);
954 kmem_free(ehcip->ehci_htable, intr_size);
955
956 return (DDI_FAILURE);
957 }
958 }
959
960 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0],
961 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) {
962 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
963 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret);
964
965 for (i = 0; i < actual; i++) {
966 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]);
967 (void) ddi_intr_free(ehcip->ehci_htable[i]);
968 }
969
970 mutex_destroy(&ehcip->ehci_int_mutex);
971 kmem_free(ehcip->ehci_htable, intr_size);
972
973 return (DDI_FAILURE);
974 }
975
976 /* Enable all interrupts */
977 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) {
978 /* Call ddi_intr_block_enable() for MSI interrupts */
979 (void) ddi_intr_block_enable(ehcip->ehci_htable,
980 ehcip->ehci_intr_cnt);
981 } else {
982 /* Call ddi_intr_enable for MSI or FIXED interrupts */
983 for (i = 0; i < ehcip->ehci_intr_cnt; i++)
984 (void) ddi_intr_enable(ehcip->ehci_htable[i]);
985 }
986
987 return (DDI_SUCCESS);
988 }
989
990
991 /*
992 * ehci_init_hardware
993 *
994 * take control from BIOS, reset EHCI host controller, and check version, etc.
995 */
996 int
997 ehci_init_hardware(ehci_state_t *ehcip)
998 {
999 int revision;
1000 uint16_t cmd_reg;
1001 int abort_on_BIOS_take_over_failure;
1002
1003 /* Take control from the BIOS */
1004 if (ehci_take_control(ehcip) != USB_SUCCESS) {
1005
1006 /* read .conf file properties */
1007 abort_on_BIOS_take_over_failure =
1008 ddi_prop_get_int(DDI_DEV_T_ANY,
1009 ehcip->ehci_dip, DDI_PROP_DONTPASS,
1010 "abort-on-BIOS-take-over-failure", 0);
1011
1012 if (abort_on_BIOS_take_over_failure) {
1013
1014 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1015 "Unable to take control from BIOS.");
1016
1017 return (DDI_FAILURE);
1018 }
1019
1020 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1021 "Unable to take control from BIOS. Failure is ignored.");
1022 }
1023
1024 /* set Memory Master Enable */
1025 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM);
1026 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME);
1027 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg);
1028
1029 /* Reset the EHCI host controller */
1030 Set_OpReg(ehci_command,
1031 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET);
1032
1033 /* Wait 10ms for reset to complete */
1034 drv_usecwait(EHCI_RESET_TIMEWAIT);
1035
1036 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED);
1037
1038 /* Verify the version number */
1039 revision = Get_16Cap(ehci_version);
1040
1041 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1042 "ehci_init_hardware: Revision 0x%x", revision);
1043
1044 /*
1045 * EHCI driver supports EHCI host controllers compliant to
1046 * 0.95 and higher revisions of EHCI specifications.
1047 */
1048 if (revision < EHCI_REVISION_0_95) {
1049
1050 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1051 "Revision 0x%x is not supported", revision);
1052
1053 return (DDI_FAILURE);
1054 }
1055
1056 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) {
1057
1058 /* Initialize the Frame list base address area */
1059 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) {
1060
1061 return (DDI_FAILURE);
1062 }
1063
1064 /*
1065 * For performance reasons, do not insert anything into the
1066 * asynchronous list or activate the asynch list schedule until
1067 * there is a valid QH.
1068 */
1069 ehcip->ehci_head_of_async_sched_list = NULL;
1070
1071 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) &&
1072 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) {
1073 /*
1074 * The driver is unable to reliably stop the asynch
1075 * list schedule on VIA VT6202 controllers, so we
1076 * always keep a dummy QH on the list.
1077 */
1078 ehci_qh_t *dummy_async_qh =
1079 ehci_alloc_qh(ehcip, NULL, NULL);
1080
1081 Set_QH(dummy_async_qh->qh_link_ptr,
1082 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) &
1083 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH));
1084
1085 /* Set this QH to be the "head" of the circular list */
1086 Set_QH(dummy_async_qh->qh_ctrl,
1087 Get_QH(dummy_async_qh->qh_ctrl) |
1088 EHCI_QH_CTRL_RECLAIM_HEAD);
1089
1090 Set_QH(dummy_async_qh->qh_next_qtd,
1091 EHCI_QH_NEXT_QTD_PTR_VALID);
1092 Set_QH(dummy_async_qh->qh_alt_next_qtd,
1093 EHCI_QH_ALT_NEXT_QTD_PTR_VALID);
1094
1095 ehcip->ehci_head_of_async_sched_list = dummy_async_qh;
1096 ehcip->ehci_open_async_count++;
1097 ehcip->ehci_async_req_count++;
1098 }
1099 }
1100
1101 return (DDI_SUCCESS);
1102 }
1103
1104
1105 /*
1106 * ehci_init_workaround
1107 *
1108 * some workarounds during initializing ehci
1109 */
1110 int
1111 ehci_init_workaround(ehci_state_t *ehcip)
1112 {
1113 /*
1114 * Acer Labs Inc. M5273 EHCI controller does not send
1115 * interrupts unless the Root hub ports are routed to the EHCI
1116 * host controller; so route the ports now, before we test for
1117 * the presence of SOFs interrupts.
1118 */
1119 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) {
1120 /* Route all Root hub ports to EHCI host controller */
1121 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI);
1122 }
1123
1124 /*
1125 * VIA chips have some issues and may not work reliably.
1126 * Revisions >= 0x80 are part of a southbridge and appear
1127 * to be reliable with the workaround.
1128 * For revisions < 0x80, if we were bound using class
1129 * complain, else proceed. This will allow the user to
1130 * bind ehci specifically to this chip and not have the
1131 * warnings
1132 */
1133 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) {
1134
1135 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) {
1136
1137 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1138 "ehci_init_workaround: Applying VIA workarounds "
1139 "for the 6212 chip.");
1140
1141 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name,
1142 "pciclass,0c0320") == 0) {
1143
1144 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1145 "Due to recently discovered incompatibilities");
1146 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1147 "with this USB controller, USB2.x transfer");
1148 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1149 "support has been disabled. This device will");
1150 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1151 "continue to function as a USB1.x controller.");
1152 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1153 "If you are interested in enabling USB2.x");
1154 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1155 "support please, refer to the ehci(7D) man page.");
1156 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1157 "Please also refer to www.sun.com/io for");
1158 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1159 "Solaris Ready products and to");
1160 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1161 "www.sun.com/bigadmin/hcl for additional");
1162 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1163 "compatible USB products.");
1164
1165 return (DDI_FAILURE);
1166
1167 } else if (ehci_vt62x2_workaround) {
1168
1169 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1170 "Applying VIA workarounds");
1171 }
1172 }
1173
1174 return (DDI_SUCCESS);
1175 }
1176
1177
1178 /*
1179 * ehci_init_check_status
1180 *
1181 * Check if EHCI host controller is running
1182 */
1183 int
1184 ehci_init_check_status(ehci_state_t *ehcip)
1185 {
1186 clock_t sof_time_wait;
1187
1188 /*
1189 * Get the number of clock ticks to wait.
1190 * This is based on the maximum time it takes for a frame list rollover
1191 * and maximum time wait for SOFs to begin.
1192 */
1193 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) +
1194 EHCI_SOF_TIMEWAIT);
1195
1196 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */
1197 ehcip->ehci_flags |= EHCI_CV_INTR;
1198
1199 /* We need to add a delay to allow the chip time to start running */
1200 (void) cv_reltimedwait(&ehcip->ehci_async_schedule_advance_cv,
1201 &ehcip->ehci_int_mutex, sof_time_wait, TR_CLOCK_TICK);
1202
1203 /*
1204 * Check EHCI host controller is running, otherwise return failure.
1205 */
1206 if ((ehcip->ehci_flags & EHCI_CV_INTR) ||
1207 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) {
1208
1209 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1210 "No SOF interrupts have been received, this USB EHCI host"
1211 "controller is unusable");
1212
1213 /*
1214 * Route all Root hub ports to Classic host
1215 * controller, in case this is an unusable ALI M5273
1216 * EHCI controller.
1217 */
1218 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) {
1219 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC);
1220 }
1221
1222 return (DDI_FAILURE);
1223 }
1224
1225 return (DDI_SUCCESS);
1226 }
1227
1228
1229 /*
1230 * ehci_init_ctlr:
1231 *
1232 * Initialize the Host Controller (HC).
1233 */
1234 int
1235 ehci_init_ctlr(ehci_state_t *ehcip,
1236 int init_type)
1237 {
1238 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:");
1239
1240 if (init_type == EHCI_NORMAL_INITIALIZATION) {
1241
1242 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) {
1243
1244 return (DDI_FAILURE);
1245 }
1246 }
1247
1248 /*
1249 * Check for Asynchronous schedule park capability feature. If this
1250 * feature is supported, then, program ehci command register with
1251 * appropriate values..
1252 */
1253 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) {
1254
1255 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1256 "ehci_init_ctlr: Async park mode is supported");
1257
1258 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) |
1259 (EHCI_CMD_ASYNC_PARK_ENABLE |
1260 EHCI_CMD_ASYNC_PARK_COUNT_3)));
1261 }
1262
1263 /*
1264 * Check for programmable periodic frame list feature. If this
1265 * feature is supported, then, program ehci command register with
1266 * 1024 frame list value.
1267 */
1268 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) {
1269
1270 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1271 "ehci_init_ctlr: Variable programmable periodic "
1272 "frame list is supported");
1273
1274 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) |
1275 EHCI_CMD_FRAME_1024_SIZE));
1276 }
1277
1278 /*
1279 * Currently EHCI driver doesn't support 64 bit addressing.
1280 *
1281 * If we are using 64 bit addressing capability, then, program
1282 * ehci_ctrl_segment register with 4 Gigabyte segment where all
1283 * of the interface data structures are allocated.
1284 */
1285 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) {
1286
1287 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1288 "ehci_init_ctlr: EHCI driver doesn't support "
1289 "64 bit addressing");
1290 }
1291
1292 /* 64 bit addressing is not support */
1293 Set_OpReg(ehci_ctrl_segment, 0x00000000);
1294
1295 /* Turn on/off the schedulers */
1296 ehci_toggle_scheduler(ehcip);
1297
1298 /* Set host controller soft state to operational */
1299 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE;
1300
1301 /*
1302 * Set the Periodic Frame List Base Address register with the
1303 * starting physical address of the Periodic Frame List.
1304 */
1305 Set_OpReg(ehci_periodic_list_base,
1306 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address &
1307 EHCI_PERIODIC_LIST_BASE));
1308
1309 /*
1310 * Set ehci_interrupt to enable all interrupts except Root
1311 * Hub Status change interrupt.
1312 */
1313 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR |
1314 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR |
1315 EHCI_INTR_USB);
1316
1317 /*
1318 * Set the desired interrupt threshold and turn on EHCI host controller.
1319 */
1320 Set_OpReg(ehci_command,
1321 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) |
1322 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN)));
1323
1324 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN);
1325
1326 if (init_type == EHCI_NORMAL_INITIALIZATION) {
1327
1328 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) {
1329
1330 /* Set host controller soft state to error */
1331 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE;
1332
1333 return (DDI_FAILURE);
1334 }
1335
1336 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) {
1337
1338 /* Set host controller soft state to error */
1339 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE;
1340
1341 return (DDI_FAILURE);
1342 }
1343
1344 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1345 "ehci_init_ctlr: SOF's have started");
1346 }
1347
1348 /* Route all Root hub ports to EHCI host controller */
1349 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI);
1350
1351 return (DDI_SUCCESS);
1352 }
1353
1354 /*
1355 * ehci_take_control:
1356 *
1357 * Handshake to take EHCI control from BIOS if necessary. Its only valid for
1358 * x86 machines, because sparc doesn't have a BIOS.
1359 * On x86 machine, the take control process includes
1360 * o get the base address of the extended capability list
1361 * o find out the capability for handoff synchronization in the list.
1362 * o check if BIOS has owned the host controller.
1363 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership.
1364 * o wait for a constant time and check if BIOS has relinquished control.
1365 */
1366 /* ARGSUSED */
1367 static int
1368 ehci_take_control(ehci_state_t *ehcip)
1369 {
1370 #if defined(__x86)
1371 uint32_t extended_cap;
1372 uint32_t extended_cap_offset;
1373 uint32_t extended_cap_id;
1374 uint_t retry;
1375
1376 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1377 "ehci_take_control:");
1378
1379 /*
1380 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS
1381 * register.
1382 */
1383 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >>
1384 EHCI_HCC_EECP_SHIFT;
1385
1386 /*
1387 * According EHCI Spec 2.2.4, if the extended capability offset is
1388 * less than 40h then its not valid. This means we don't need to
1389 * worry about BIOS handoff.
1390 */
1391 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) {
1392
1393 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1394 "ehci_take_control: Hardware doesn't support legacy.");
1395
1396 goto success;
1397 }
1398
1399 /*
1400 * According EHCI Spec 2.1.7, A zero offset indicates the
1401 * end of the extended capability list.
1402 */
1403 while (extended_cap_offset) {
1404
1405 /* Get the extended capability value. */
1406 extended_cap = pci_config_get32(ehcip->ehci_config_handle,
1407 extended_cap_offset);
1408
1409 /* Get the capability ID */
1410 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >>
1411 EHCI_EX_CAP_ID_SHIFT;
1412
1413 /* Check if the card support legacy */
1414 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) {
1415 break;
1416 }
1417
1418 /* Get the offset of the next capability */
1419 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >>
1420 EHCI_EX_CAP_NEXT_PTR_SHIFT;
1421 }
1422
1423 /*
1424 * Unable to find legacy support in hardware's extended capability list.
1425 * This means we don't need to worry about BIOS handoff.
1426 */
1427 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) {
1428
1429 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1430 "ehci_take_control: Hardware doesn't support legacy");
1431
1432 goto success;
1433 }
1434
1435 /* Check if BIOS has owned it. */
1436 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) {
1437
1438 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1439 "ehci_take_control: BIOS does not own EHCI");
1440
1441 goto success;
1442 }
1443
1444 /*
1445 * According EHCI Spec 5.1, The OS driver initiates an ownership
1446 * request by setting the OS Owned semaphore to a one. The OS
1447 * waits for the BIOS Owned bit to go to a zero before attempting
1448 * to use the EHCI controller. The time that OS must wait for BIOS
1449 * to respond to the request for ownership is beyond the scope of
1450 * this specification.
1451 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms
1452 * for BIOS to release the ownership.
1453 */
1454 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM;
1455 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset,
1456 extended_cap);
1457
1458 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) {
1459
1460 /* wait a special interval */
1461 #ifndef __lock_lint
1462 delay(drv_usectohz(EHCI_TAKEOVER_DELAY));
1463 #endif
1464 /* Check to see if the BIOS has released the ownership */
1465 extended_cap = pci_config_get32(
1466 ehcip->ehci_config_handle, extended_cap_offset);
1467
1468 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) {
1469
1470 USB_DPRINTF_L3(PRINT_MASK_ATTA,
1471 ehcip->ehci_log_hdl,
1472 "ehci_take_control: BIOS has released "
1473 "the ownership. retry = %d", retry);
1474
1475 goto success;
1476 }
1477
1478 }
1479
1480 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1481 "ehci_take_control: take control from BIOS failed.");
1482
1483 return (USB_FAILURE);
1484
1485 success:
1486
1487 #endif /* __x86 */
1488 return (USB_SUCCESS);
1489 }
1490
1491
1492 /*
1493 * ehci_init_periodic_frame_list_table :
1494 *
1495 * Allocate the system memory and initialize Host Controller
1496 * Periodic Frame List table area. The starting of the Periodic
1497 * Frame List Table area must be 4096 byte aligned.
1498 */
1499 static int
1500 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip)
1501 {
1502 ddi_device_acc_attr_t dev_attr;
1503 size_t real_length;
1504 uint_t ccount;
1505 int result;
1506
1507 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
1508
1509 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1510 "ehci_init_periodic_frame_lst_table:");
1511
1512 /* The host controller will be little endian */
1513 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1514 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
1515 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1516
1517 /* Force the required 4K restrictive alignment */
1518 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT;
1519
1520 /* Create space for the Periodic Frame List */
1521 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr,
1522 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) {
1523
1524 goto failure;
1525 }
1526
1527 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle,
1528 sizeof (ehci_periodic_frame_list_t),
1529 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
1530 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep,
1531 &real_length, &ehcip->ehci_pflt_mem_handle)) {
1532
1533 goto failure;
1534 }
1535
1536 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1537 "ehci_init_periodic_frame_lst_table: "
1538 "Real length %lu", real_length);
1539
1540 /* Map the whole Periodic Frame List into the I/O address space */
1541 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle,
1542 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep,
1543 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1544 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount);
1545
1546 if (result == DDI_DMA_MAPPED) {
1547 /* The cookie count should be 1 */
1548 if (ccount != 1) {
1549 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1550 "ehci_init_periodic_frame_lst_table: "
1551 "More than 1 cookie");
1552
1553 goto failure;
1554 }
1555 } else {
1556 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result);
1557
1558 goto failure;
1559 }
1560
1561 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1562 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x",
1563 (void *)ehcip->ehci_periodic_frame_list_tablep,
1564 ehcip->ehci_pflt_cookie.dmac_address);
1565
1566 /*
1567 * DMA addresses for Periodic Frame List are bound.
1568 */
1569 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND;
1570
1571 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length);
1572
1573 /* Initialize the Periodic Frame List */
1574 ehci_build_interrupt_lattice(ehcip);
1575
1576 /* Reset Byte Alignment to Default */
1577 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT;
1578
1579 return (DDI_SUCCESS);
1580 failure:
1581 /* Byte alignment */
1582 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT;
1583
1584 return (DDI_FAILURE);
1585 }
1586
1587
1588 /*
1589 * ehci_build_interrupt_lattice:
1590 *
1591 * Construct the interrupt lattice tree using static Endpoint Descriptors
1592 * (QH). This interrupt lattice tree will have total of 32 interrupt QH
1593 * lists and the Host Controller (HC) processes one interrupt QH list in
1594 * every frame. The Host Controller traverses the periodic schedule by
1595 * constructing an array offset reference from the Periodic List Base Address
1596 * register and bits 12 to 3 of Frame Index register. It fetches the element
1597 * and begins traversing the graph of linked schedule data structures.
1598 */
1599 static void
1600 ehci_build_interrupt_lattice(ehci_state_t *ehcip)
1601 {
1602 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr;
1603 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS];
1604 ehci_periodic_frame_list_t *periodic_frame_list =
1605 ehcip->ehci_periodic_frame_list_tablep;
1606 ushort_t *temp, num_of_nodes;
1607 uintptr_t addr;
1608 int i, j, k;
1609
1610 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1611 "ehci_build_interrupt_lattice:");
1612
1613 /*
1614 * Reserve the first 63 Endpoint Descriptor (QH) structures
1615 * in the pool as static endpoints & these are required for
1616 * constructing interrupt lattice tree.
1617 */
1618 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) {
1619 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC);
1620 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED);
1621 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID);
1622 Set_QH(list_array[i].qh_alt_next_qtd,
1623 EHCI_QH_ALT_NEXT_QTD_PTR_VALID);
1624 }
1625
1626 /*
1627 * Make sure that last Endpoint on the periodic frame list terminates
1628 * periodic schedule.
1629 */
1630 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID);
1631
1632 /* Build the interrupt lattice tree */
1633 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) {
1634 /*
1635 * The next pointer in the host controller endpoint
1636 * descriptor must contain an iommu address. Calculate
1637 * the offset into the cpu address and add this to the
1638 * starting iommu address.
1639 */
1640 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]);
1641
1642 Set_QH(list_array[2*i + 1].qh_link_ptr,
1643 addr | EHCI_QH_LINK_REF_QH);
1644 Set_QH(list_array[2*i + 2].qh_link_ptr,
1645 addr | EHCI_QH_LINK_REF_QH);
1646 }
1647
1648 /* Build the tree bottom */
1649 temp = (unsigned short *)
1650 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP);
1651
1652 num_of_nodes = 1;
1653
1654 /*
1655 * Initialize the values which are used for setting up head pointers
1656 * for the 32ms scheduling lists which starts from the Periodic Frame
1657 * List.
1658 */
1659 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) {
1660 for (j = 0, k = 0; k < num_of_nodes; k++, j++) {
1661 ehci_index[j++] = temp[k];
1662 ehci_index[j] = temp[k] + ehci_pow_2(i);
1663 }
1664
1665 num_of_nodes *= 2;
1666 for (k = 0; k < num_of_nodes; k++)
1667 temp[k] = ehci_index[k];
1668 }
1669
1670 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2));
1671
1672 /*
1673 * Initialize the interrupt list in the Periodic Frame List Table
1674 * so that it points to the bottom of the tree.
1675 */
1676 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) {
1677 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)
1678 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1]));
1679
1680 ASSERT(addr);
1681
1682 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) {
1683 Set_PFLT(periodic_frame_list->
1684 ehci_periodic_frame_list_table[ehci_index[j++]],
1685 (uint32_t)(addr | EHCI_QH_LINK_REF_QH));
1686 }
1687 }
1688 }
1689
1690
1691 /*
1692 * ehci_alloc_hcdi_ops:
1693 *
1694 * The HCDI interfaces or entry points are the software interfaces used by
1695 * the Universal Serial Bus Driver (USBA) to access the services of the
1696 * Host Controller Driver (HCD). During HCD initialization, inform USBA
1697 * about all available HCDI interfaces or entry points.
1698 */
1699 usba_hcdi_ops_t *
1700 ehci_alloc_hcdi_ops(ehci_state_t *ehcip)
1701 {
1702 usba_hcdi_ops_t *usba_hcdi_ops;
1703
1704 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1705 "ehci_alloc_hcdi_ops:");
1706
1707 usba_hcdi_ops = usba_alloc_hcdi_ops();
1708
1709 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION;
1710
1711 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support;
1712 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open;
1713 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close;
1714
1715 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset;
1716 usba_hcdi_ops->usba_hcdi_pipe_reset_data_toggle =
1717 ehci_hcdi_pipe_reset_data_toggle;
1718
1719 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer;
1720 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer;
1721 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer;
1722 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer;
1723
1724 usba_hcdi_ops->usba_hcdi_bulk_transfer_size =
1725 ehci_hcdi_bulk_transfer_size;
1726
1727 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling =
1728 ehci_hcdi_pipe_stop_intr_polling;
1729 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling =
1730 ehci_hcdi_pipe_stop_isoc_polling;
1731
1732 usba_hcdi_ops->usba_hcdi_get_current_frame_number =
1733 ehci_hcdi_get_current_frame_number;
1734 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts =
1735 ehci_hcdi_get_max_isoc_pkts;
1736
1737 usba_hcdi_ops->usba_hcdi_console_input_init =
1738 ehci_hcdi_polled_input_init;
1739 usba_hcdi_ops->usba_hcdi_console_input_enter =
1740 ehci_hcdi_polled_input_enter;
1741 usba_hcdi_ops->usba_hcdi_console_read =
1742 ehci_hcdi_polled_read;
1743 usba_hcdi_ops->usba_hcdi_console_input_exit =
1744 ehci_hcdi_polled_input_exit;
1745 usba_hcdi_ops->usba_hcdi_console_input_fini =
1746 ehci_hcdi_polled_input_fini;
1747
1748 usba_hcdi_ops->usba_hcdi_console_output_init =
1749 ehci_hcdi_polled_output_init;
1750 usba_hcdi_ops->usba_hcdi_console_output_enter =
1751 ehci_hcdi_polled_output_enter;
1752 usba_hcdi_ops->usba_hcdi_console_write =
1753 ehci_hcdi_polled_write;
1754 usba_hcdi_ops->usba_hcdi_console_output_exit =
1755 ehci_hcdi_polled_output_exit;
1756 usba_hcdi_ops->usba_hcdi_console_output_fini =
1757 ehci_hcdi_polled_output_fini;
1758 return (usba_hcdi_ops);
1759 }
1760
1761
1762 /*
1763 * Host Controller Driver (HCD) deinitialization functions
1764 */
1765
1766 /*
1767 * ehci_cleanup:
1768 *
1769 * Cleanup on attach failure or detach
1770 */
1771 int
1772 ehci_cleanup(ehci_state_t *ehcip)
1773 {
1774 ehci_trans_wrapper_t *tw;
1775 ehci_pipe_private_t *pp;
1776 ehci_qtd_t *qtd;
1777 int i, ctrl, rval;
1778 int flags = ehcip->ehci_flags;
1779
1780 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:");
1781
1782 if (flags & EHCI_RHREG) {
1783 /* Unload the root hub driver */
1784 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) {
1785
1786 return (DDI_FAILURE);
1787 }
1788 }
1789
1790 if (flags & EHCI_USBAREG) {
1791 /* Unregister this HCD instance with USBA */
1792 usba_hcdi_unregister(ehcip->ehci_dip);
1793 }
1794
1795 if (flags & EHCI_INTR) {
1796
1797 mutex_enter(&ehcip->ehci_int_mutex);
1798
1799 /* Disable all EHCI QH list processing */
1800 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) &
1801 ~(EHCI_CMD_ASYNC_SCHED_ENABLE |
1802 EHCI_CMD_PERIODIC_SCHED_ENABLE)));
1803
1804 /* Disable all EHCI interrupts */
1805 Set_OpReg(ehci_interrupt, 0);
1806
1807 /* wait for the next SOF */
1808 (void) ehci_wait_for_sof(ehcip);
1809
1810 /* Route all Root hub ports to Classic host controller */
1811 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC);
1812
1813 /* Stop the EHCI host controller */
1814 Set_OpReg(ehci_command,
1815 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN);
1816
1817 mutex_exit(&ehcip->ehci_int_mutex);
1818
1819 /* Wait for sometime */
1820 delay(drv_usectohz(EHCI_TIMEWAIT));
1821
1822 ehci_rem_intrs(ehcip);
1823 }
1824
1825 /* Unmap the EHCI registers */
1826 if (ehcip->ehci_caps_handle) {
1827 ddi_regs_map_free(&ehcip->ehci_caps_handle);
1828 }
1829
1830 if (ehcip->ehci_config_handle) {
1831 pci_config_teardown(&ehcip->ehci_config_handle);
1832 }
1833
1834 /* Free all the buffers */
1835 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) {
1836 for (i = 0; i < ehci_qtd_pool_size; i ++) {
1837 qtd = &ehcip->ehci_qtd_pool_addr[i];
1838 ctrl = Get_QTD(ehcip->
1839 ehci_qtd_pool_addr[i].qtd_state);
1840
1841 if ((ctrl != EHCI_QTD_FREE) &&
1842 (ctrl != EHCI_QTD_DUMMY) &&
1843 (qtd->qtd_trans_wrapper)) {
1844
1845 mutex_enter(&ehcip->ehci_int_mutex);
1846
1847 tw = (ehci_trans_wrapper_t *)
1848 EHCI_LOOKUP_ID((uint32_t)
1849 Get_QTD(qtd->qtd_trans_wrapper));
1850
1851 /* Obtain the pipe private structure */
1852 pp = tw->tw_pipe_private;
1853
1854 /* Stop the the transfer timer */
1855 ehci_stop_xfer_timer(ehcip, tw,
1856 EHCI_REMOVE_XFER_ALWAYS);
1857
1858 ehci_deallocate_tw(ehcip, pp, tw);
1859
1860 mutex_exit(&ehcip->ehci_int_mutex);
1861 }
1862 }
1863
1864 /*
1865 * If EHCI_QTD_POOL_BOUND flag is set, then unbind
1866 * the handle for QTD pools.
1867 */
1868 if ((ehcip->ehci_dma_addr_bind_flag &
1869 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) {
1870
1871 rval = ddi_dma_unbind_handle(
1872 ehcip->ehci_qtd_pool_dma_handle);
1873
1874 ASSERT(rval == DDI_SUCCESS);
1875 }
1876 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle);
1877 }
1878
1879 /* Free the QTD pool */
1880 if (ehcip->ehci_qtd_pool_dma_handle) {
1881 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle);
1882 }
1883
1884 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) {
1885 /*
1886 * If EHCI_QH_POOL_BOUND flag is set, then unbind
1887 * the handle for QH pools.
1888 */
1889 if ((ehcip->ehci_dma_addr_bind_flag &
1890 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) {
1891
1892 rval = ddi_dma_unbind_handle(
1893 ehcip->ehci_qh_pool_dma_handle);
1894
1895 ASSERT(rval == DDI_SUCCESS);
1896 }
1897
1898 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle);
1899 }
1900
1901 /* Free the QH pool */
1902 if (ehcip->ehci_qh_pool_dma_handle) {
1903 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle);
1904 }
1905
1906 /* Free the Periodic frame list table (PFLT) area */
1907 if (ehcip->ehci_periodic_frame_list_tablep &&
1908 ehcip->ehci_pflt_mem_handle) {
1909 /*
1910 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind
1911 * the handle for PFLT.
1912 */
1913 if ((ehcip->ehci_dma_addr_bind_flag &
1914 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) {
1915
1916 rval = ddi_dma_unbind_handle(
1917 ehcip->ehci_pflt_dma_handle);
1918
1919 ASSERT(rval == DDI_SUCCESS);
1920 }
1921
1922 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle);
1923 }
1924
1925 (void) ehci_isoc_cleanup(ehcip);
1926
1927 if (ehcip->ehci_pflt_dma_handle) {
1928 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle);
1929 }
1930
1931 if (flags & EHCI_INTR) {
1932 /* Destroy the mutex */
1933 mutex_destroy(&ehcip->ehci_int_mutex);
1934
1935 /* Destroy the async schedule advance condition variable */
1936 cv_destroy(&ehcip->ehci_async_schedule_advance_cv);
1937 }
1938
1939 /* clean up kstat structs */
1940 ehci_destroy_stats(ehcip);
1941
1942 /* Free ehci hcdi ops */
1943 if (ehcip->ehci_hcdi_ops) {
1944 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops);
1945 }
1946
1947 if (flags & EHCI_ZALLOC) {
1948
1949 usb_free_log_hdl(ehcip->ehci_log_hdl);
1950
1951 /* Remove all properties that might have been created */
1952 ddi_prop_remove_all(ehcip->ehci_dip);
1953
1954 /* Free the soft state */
1955 ddi_soft_state_free(ehci_statep,
1956 ddi_get_instance(ehcip->ehci_dip));
1957 }
1958
1959 return (DDI_SUCCESS);
1960 }
1961
1962
1963 /*
1964 * ehci_rem_intrs:
1965 *
1966 * Unregister FIXED or MSI interrupts
1967 */
1968 static void
1969 ehci_rem_intrs(ehci_state_t *ehcip)
1970 {
1971 int i;
1972
1973 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
1974 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type);
1975
1976 /* Disable all interrupts */
1977 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) {
1978 (void) ddi_intr_block_disable(ehcip->ehci_htable,
1979 ehcip->ehci_intr_cnt);
1980 } else {
1981 for (i = 0; i < ehcip->ehci_intr_cnt; i++) {
1982 (void) ddi_intr_disable(ehcip->ehci_htable[i]);
1983 }
1984 }
1985
1986 /* Call ddi_intr_remove_handler() */
1987 for (i = 0; i < ehcip->ehci_intr_cnt; i++) {
1988 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]);
1989 (void) ddi_intr_free(ehcip->ehci_htable[i]);
1990 }
1991
1992 kmem_free(ehcip->ehci_htable,
1993 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t));
1994 }
1995
1996
1997 /*
1998 * ehci_cpr_suspend
1999 */
2000 int
2001 ehci_cpr_suspend(ehci_state_t *ehcip)
2002 {
2003 int i;
2004
2005 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2006 "ehci_cpr_suspend:");
2007
2008 /* Call into the root hub and suspend it */
2009 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) {
2010
2011 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2012 "ehci_cpr_suspend: root hub fails to suspend");
2013
2014 return (DDI_FAILURE);
2015 }
2016
2017 /* Only root hub's intr pipe should be open at this time */
2018 mutex_enter(&ehcip->ehci_int_mutex);
2019
2020 ASSERT(ehcip->ehci_open_pipe_count == 0);
2021
2022 /* Just wait till all resources are reclaimed */
2023 i = 0;
2024 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) {
2025 ehci_handle_endpoint_reclaimation(ehcip);
2026 (void) ehci_wait_for_sof(ehcip);
2027 }
2028 ASSERT(ehcip->ehci_reclaim_list == NULL);
2029
2030 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2031 "ehci_cpr_suspend: Disable HC QH list processing");
2032
2033 /* Disable all EHCI QH list processing */
2034 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) &
2035 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)));
2036
2037 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2038 "ehci_cpr_suspend: Disable HC interrupts");
2039
2040 /* Disable all EHCI interrupts */
2041 Set_OpReg(ehci_interrupt, 0);
2042
2043 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2044 "ehci_cpr_suspend: Wait for the next SOF");
2045
2046 /* Wait for the next SOF */
2047 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) {
2048
2049 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2050 "ehci_cpr_suspend: ehci host controller suspend failed");
2051
2052 mutex_exit(&ehcip->ehci_int_mutex);
2053 return (DDI_FAILURE);
2054 }
2055
2056 /*
2057 * Stop the ehci host controller
2058 * if usb keyboard is not connected.
2059 */
2060 if (ehcip->ehci_polled_kbd_count == 0 || force_ehci_off != 0) {
2061 Set_OpReg(ehci_command,
2062 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN);
2063
2064 }
2065
2066 /* Set host controller soft state to suspend */
2067 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE;
2068
2069 mutex_exit(&ehcip->ehci_int_mutex);
2070
2071 return (DDI_SUCCESS);
2072 }
2073
2074
2075 /*
2076 * ehci_cpr_resume
2077 */
2078 int
2079 ehci_cpr_resume(ehci_state_t *ehcip)
2080 {
2081 mutex_enter(&ehcip->ehci_int_mutex);
2082
2083 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2084 "ehci_cpr_resume: Restart the controller");
2085
2086 /* Cleanup ehci specific information across cpr */
2087 ehci_cpr_cleanup(ehcip);
2088
2089 /* Restart the controller */
2090 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) {
2091
2092 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
2093 "ehci_cpr_resume: ehci host controller resume failed ");
2094
2095 mutex_exit(&ehcip->ehci_int_mutex);
2096
2097 return (DDI_FAILURE);
2098 }
2099
2100 mutex_exit(&ehcip->ehci_int_mutex);
2101
2102 /* Now resume the root hub */
2103 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) {
2104
2105 return (DDI_FAILURE);
2106 }
2107
2108 return (DDI_SUCCESS);
2109 }
2110
2111
2112 /*
2113 * Bandwidth Allocation functions
2114 */
2115
2116 /*
2117 * ehci_allocate_bandwidth:
2118 *
2119 * Figure out whether or not this interval may be supported. Return the index
2120 * into the lattice if it can be supported. Return allocation failure if it
2121 * can not be supported.
2122 */
2123 int
2124 ehci_allocate_bandwidth(
2125 ehci_state_t *ehcip,
2126 usba_pipe_handle_data_t *ph,
2127 uint_t *pnode,
2128 uchar_t *smask,
2129 uchar_t *cmask)
2130 {
2131 int error = USB_SUCCESS;
2132
2133 /* This routine is protected by the ehci_int_mutex */
2134 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
2135
2136 /* Reset the pnode to the last checked pnode */
2137 *pnode = 0;
2138
2139 /* Allocate high speed bandwidth */
2140 if ((error = ehci_allocate_high_speed_bandwidth(ehcip,
2141 ph, pnode, smask, cmask)) != USB_SUCCESS) {
2142
2143 return (error);
2144 }
2145
2146 /*
2147 * For low/full speed usb devices, allocate classic TT bandwidth
2148 * in additional to high speed bandwidth.
2149 */
2150 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) {
2151
2152 /* Allocate classic TT bandwidth */
2153 if ((error = ehci_allocate_classic_tt_bandwidth(
2154 ehcip, ph, *pnode)) != USB_SUCCESS) {
2155
2156 /* Deallocate high speed bandwidth */
2157 ehci_deallocate_high_speed_bandwidth(
2158 ehcip, ph, *pnode, *smask, *cmask);
2159 }
2160 }
2161
2162 return (error);
2163 }
2164
2165
2166 /*
2167 * ehci_allocate_high_speed_bandwidth:
2168 *
2169 * Allocate high speed bandwidth for the low/full/high speed interrupt and
2170 * isochronous endpoints.
2171 */
2172 static int
2173 ehci_allocate_high_speed_bandwidth(
2174 ehci_state_t *ehcip,
2175 usba_pipe_handle_data_t *ph,
2176 uint_t *pnode,
2177 uchar_t *smask,
2178 uchar_t *cmask)
2179 {
2180 uint_t sbandwidth, cbandwidth;
2181 int interval;
2182 usb_ep_descr_t *endpoint = &ph->p_ep;
2183 usba_device_t *child_ud;
2184 usb_port_status_t port_status;
2185 int error;
2186
2187 /* This routine is protected by the ehci_int_mutex */
2188 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
2189
2190 /* Get child's usba device structure */
2191 child_ud = ph->p_usba_device;
2192
2193 mutex_enter(&child_ud->usb_mutex);
2194
2195 /* Get the current usb device's port status */
2196 port_status = ph->p_usba_device->usb_port_status;
2197
2198 mutex_exit(&child_ud->usb_mutex);
2199
2200 /*
2201 * Calculate the length in bytes of a transaction on this
2202 * periodic endpoint. Return failure if maximum packet is
2203 * zero.
2204 */
2205 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint,
2206 port_status, &sbandwidth, &cbandwidth);
2207 if (error != USB_SUCCESS) {
2208
2209 return (error);
2210 }
2211
2212 /*
2213 * Adjust polling interval to be a power of 2.
2214 * If this interval can't be supported, return
2215 * allocation failure.
2216 */
2217 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status);
2218 if (interval == USB_FAILURE) {
2219
2220 return (USB_FAILURE);
2221 }
2222
2223 if (port_status == USBA_HIGH_SPEED_DEV) {
2224 /* Allocate bandwidth for high speed devices */
2225 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) ==
2226 USB_EP_ATTR_ISOCH) {
2227 error = USB_SUCCESS;
2228 } else {
2229
2230 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode,
2231 endpoint, sbandwidth, interval);
2232 }
2233
2234 *cmask = 0x00;
2235
2236 } else {
2237 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) ==
2238 USB_EP_ATTR_INTR) {
2239
2240 /* Allocate bandwidth for low speed interrupt */
2241 error = ehci_find_bestfit_ls_intr_mask(ehcip,
2242 smask, cmask, pnode, sbandwidth, cbandwidth,
2243 interval);
2244 } else {
2245 if ((endpoint->bEndpointAddress &
2246 USB_EP_DIR_MASK) == USB_EP_DIR_IN) {
2247
2248 /* Allocate bandwidth for sitd in */
2249 error = ehci_find_bestfit_sitd_in_mask(ehcip,
2250 smask, cmask, pnode, sbandwidth, cbandwidth,
2251 interval);
2252 } else {
2253
2254 /* Allocate bandwidth for sitd out */
2255 error = ehci_find_bestfit_sitd_out_mask(ehcip,
2256 smask, pnode, sbandwidth, interval);
2257 *cmask = 0x00;
2258 }
2259 }
2260 }
2261
2262 if (error != USB_SUCCESS) {
2263 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2264 "ehci_allocate_high_speed_bandwidth: Reached maximum "
2265 "bandwidth value and cannot allocate bandwidth for a "
2266 "given high-speed periodic endpoint");
2267
2268 return (USB_NO_BANDWIDTH);
2269 }
2270
2271 return (error);
2272 }
2273
2274
2275 /*
2276 * ehci_allocate_classic_tt_speed_bandwidth:
2277 *
2278 * Allocate classic TT bandwidth for the low/full speed interrupt and
2279 * isochronous endpoints.
2280 */
2281 static int
2282 ehci_allocate_classic_tt_bandwidth(
2283 ehci_state_t *ehcip,
2284 usba_pipe_handle_data_t *ph,
2285 uint_t pnode)
2286 {
2287 uint_t bandwidth, min;
2288 uint_t height, leftmost, list;
2289 usb_ep_descr_t *endpoint = &ph->p_ep;
2290 usba_device_t *child_ud, *parent_ud;
2291 usb_port_status_t port_status;
2292 int i, interval;
2293
2294 /* This routine is protected by the ehci_int_mutex */
2295 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
2296
2297 /* Get child's usba device structure */
2298 child_ud = ph->p_usba_device;
2299
2300 mutex_enter(&child_ud->usb_mutex);
2301
2302 /* Get the current usb device's port status */
2303 port_status = child_ud->usb_port_status;
2304
2305 /* Get the parent high speed hub's usba device structure */
2306 parent_ud = child_ud->usb_hs_hub_usba_dev;
2307
2308 mutex_exit(&child_ud->usb_mutex);
2309
2310 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2311 "ehci_allocate_classic_tt_bandwidth: "
2312 "child_ud 0x%p parent_ud 0x%p",
2313 (void *)child_ud, (void *)parent_ud);
2314
2315 /*
2316 * Calculate the length in bytes of a transaction on this
2317 * periodic endpoint. Return failure if maximum packet is
2318 * zero.
2319 */
2320 if (ehci_compute_classic_bandwidth(endpoint,
2321 port_status, &bandwidth) != USB_SUCCESS) {
2322
2323 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2324 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint "
2325 "with zero endpoint maximum packet size is not supported");
2326
2327 return (USB_NOT_SUPPORTED);
2328 }
2329
2330 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2331 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth);
2332
2333 mutex_enter(&parent_ud->usb_mutex);
2334
2335 /*
2336 * If the length in bytes plus the allocated bandwidth exceeds
2337 * the maximum, return bandwidth allocation failure.
2338 */
2339 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) >
2340 FS_PERIODIC_BANDWIDTH) {
2341
2342 mutex_exit(&parent_ud->usb_mutex);
2343
2344 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2345 "ehci_allocate_classic_tt_bandwidth: Reached maximum "
2346 "bandwidth value and cannot allocate bandwidth for a "
2347 "given low/full speed periodic endpoint");
2348
2349 return (USB_NO_BANDWIDTH);
2350 }
2351
2352 mutex_exit(&parent_ud->usb_mutex);
2353
2354 /* Adjust polling interval to be a power of 2 */
2355 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status);
2356
2357 /* Find the height in the tree */
2358 height = ehci_lattice_height(interval);
2359
2360 /* Find the leftmost leaf in the subtree specified by the node. */
2361 leftmost = ehci_leftmost_leaf(pnode, height);
2362
2363 mutex_enter(&parent_ud->usb_mutex);
2364
2365 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) {
2366 list = ehci_index[leftmost + i];
2367
2368 if ((parent_ud->usb_hs_hub_bandwidth[list] +
2369 bandwidth) > FS_PERIODIC_BANDWIDTH) {
2370
2371 mutex_exit(&parent_ud->usb_mutex);
2372
2373 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2374 "ehci_allocate_classic_tt_bandwidth: Reached "
2375 "maximum bandwidth value and cannot allocate "
2376 "bandwidth for low/full periodic endpoint");
2377
2378 return (USB_NO_BANDWIDTH);
2379 }
2380 }
2381
2382 /*
2383 * All the leaves for this node must be updated with the bandwidth.
2384 */
2385 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) {
2386 list = ehci_index[leftmost + i];
2387 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth;
2388 }
2389
2390 /* Find the leaf with the smallest allocated bandwidth */
2391 min = parent_ud->usb_hs_hub_bandwidth[0];
2392
2393 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) {
2394 if (parent_ud->usb_hs_hub_bandwidth[i] < min) {
2395 min = parent_ud->usb_hs_hub_bandwidth[i];
2396 }
2397 }
2398
2399 /* Save the minimum for later use */
2400 parent_ud->usb_hs_hub_min_bandwidth = min;
2401
2402 mutex_exit(&parent_ud->usb_mutex);
2403
2404 return (USB_SUCCESS);
2405 }
2406
2407
2408 /*
2409 * ehci_deallocate_bandwidth:
2410 *
2411 * Deallocate bandwidth for the given node in the lattice and the length
2412 * of transfer.
2413 */
2414 void
2415 ehci_deallocate_bandwidth(
2416 ehci_state_t *ehcip,
2417 usba_pipe_handle_data_t *ph,
2418 uint_t pnode,
2419 uchar_t smask,
2420 uchar_t cmask)
2421 {
2422 /* This routine is protected by the ehci_int_mutex */
2423 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
2424
2425 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask);
2426
2427 /*
2428 * For low/full speed usb devices, deallocate classic TT bandwidth
2429 * in additional to high speed bandwidth.
2430 */
2431 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) {
2432
2433 /* Deallocate classic TT bandwidth */
2434 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode);
2435 }
2436 }
2437
2438
2439 /*
2440 * ehci_deallocate_high_speed_bandwidth:
2441 *
2442 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint.
2443 */
2444 static void
2445 ehci_deallocate_high_speed_bandwidth(
2446 ehci_state_t *ehcip,
2447 usba_pipe_handle_data_t *ph,
2448 uint_t pnode,
2449 uchar_t smask,
2450 uchar_t cmask)
2451 {
2452 uint_t height, leftmost;
2453 uint_t list_count;
2454 uint_t sbandwidth, cbandwidth;
2455 int interval;
2456 usb_ep_descr_t *endpoint = &ph->p_ep;
2457 usba_device_t *child_ud;
2458 usb_port_status_t port_status;
2459
2460 /* This routine is protected by the ehci_int_mutex */
2461 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
2462
2463 /* Get child's usba device structure */
2464 child_ud = ph->p_usba_device;
2465
2466 mutex_enter(&child_ud->usb_mutex);
2467
2468 /* Get the current usb device's port status */
2469 port_status = ph->p_usba_device->usb_port_status;
2470
2471 mutex_exit(&child_ud->usb_mutex);
2472
2473 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint,
2474 port_status, &sbandwidth, &cbandwidth);
2475
2476 /* Adjust polling interval to be a power of 2 */
2477 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status);
2478
2479 /* Find the height in the tree */
2480 height = ehci_lattice_height(interval);
2481
2482 /*
2483 * Find the leftmost leaf in the subtree specified by the node
2484 */
2485 leftmost = ehci_leftmost_leaf(pnode, height);
2486
2487 list_count = EHCI_NUM_INTR_QH_LISTS/interval;
2488
2489 /* Delete the bandwidth from the appropriate lists */
2490 if (port_status == USBA_HIGH_SPEED_DEV) {
2491
2492 ehci_update_bw_availability(ehcip, -sbandwidth,
2493 leftmost, list_count, smask);
2494 } else {
2495 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) ==
2496 USB_EP_ATTR_INTR) {
2497
2498 ehci_update_bw_availability(ehcip, -sbandwidth,
2499 leftmost, list_count, smask);
2500 ehci_update_bw_availability(ehcip, -cbandwidth,
2501 leftmost, list_count, cmask);
2502 } else {
2503 if ((endpoint->bEndpointAddress &
2504 USB_EP_DIR_MASK) == USB_EP_DIR_IN) {
2505
2506 ehci_update_bw_availability(ehcip, -sbandwidth,
2507 leftmost, list_count, smask);
2508 ehci_update_bw_availability(ehcip,
2509 -MAX_UFRAME_SITD_XFER, leftmost,
2510 list_count, cmask);
2511 } else {
2512
2513 ehci_update_bw_availability(ehcip,
2514 -MAX_UFRAME_SITD_XFER, leftmost,
2515 list_count, smask);
2516 }
2517 }
2518 }
2519 }
2520
2521 /*
2522 * ehci_deallocate_classic_tt_bandwidth:
2523 *
2524 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint.
2525 */
2526 static void
2527 ehci_deallocate_classic_tt_bandwidth(
2528 ehci_state_t *ehcip,
2529 usba_pipe_handle_data_t *ph,
2530 uint_t pnode)
2531 {
2532 uint_t bandwidth, height, leftmost, list, min;
2533 int i, interval;
2534 usb_ep_descr_t *endpoint = &ph->p_ep;
2535 usba_device_t *child_ud, *parent_ud;
2536 usb_port_status_t port_status;
2537
2538 /* This routine is protected by the ehci_int_mutex */
2539 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
2540
2541 /* Get child's usba device structure */
2542 child_ud = ph->p_usba_device;
2543
2544 mutex_enter(&child_ud->usb_mutex);
2545
2546 /* Get the current usb device's port status */
2547 port_status = child_ud->usb_port_status;
2548
2549 /* Get the parent high speed hub's usba device structure */
2550 parent_ud = child_ud->usb_hs_hub_usba_dev;
2551
2552 mutex_exit(&child_ud->usb_mutex);
2553
2554 /* Obtain the bandwidth */
2555 (void) ehci_compute_classic_bandwidth(endpoint,
2556 port_status, &bandwidth);
2557
2558 /* Adjust polling interval to be a power of 2 */
2559 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status);
2560
2561 /* Find the height in the tree */
2562 height = ehci_lattice_height(interval);
2563
2564 /* Find the leftmost leaf in the subtree specified by the node */
2565 leftmost = ehci_leftmost_leaf(pnode, height);
2566
2567 mutex_enter(&parent_ud->usb_mutex);
2568
2569 /* Delete the bandwidth from the appropriate lists */
2570 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) {
2571 list = ehci_index[leftmost + i];
2572 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth;
2573 }
2574
2575 /* Find the leaf with the smallest allocated bandwidth */
2576 min = parent_ud->usb_hs_hub_bandwidth[0];
2577
2578 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) {
2579 if (parent_ud->usb_hs_hub_bandwidth[i] < min) {
2580 min = parent_ud->usb_hs_hub_bandwidth[i];
2581 }
2582 }
2583
2584 /* Save the minimum for later use */
2585 parent_ud->usb_hs_hub_min_bandwidth = min;
2586
2587 mutex_exit(&parent_ud->usb_mutex);
2588 }
2589
2590
2591 /*
2592 * ehci_compute_high_speed_bandwidth:
2593 *
2594 * Given a periodic endpoint (interrupt or isochronous) determine the total
2595 * bandwidth for one transaction. The EHCI host controller traverses the
2596 * endpoint descriptor lists on a first-come-first-serve basis. When the HC
2597 * services an endpoint, only a single transaction attempt is made. The HC
2598 * moves to the next Endpoint Descriptor after the first transaction attempt
2599 * rather than finishing the entire Transfer Descriptor. Therefore, when a
2600 * Transfer Descriptor is inserted into the lattice, we will only count the
2601 * number of bytes for one transaction.
2602 *
2603 * The following are the formulas used for calculating bandwidth in terms
2604 * bytes and it is for the single USB high speed transaction. The protocol
2605 * overheads will be different for each of type of USB transfer & all these
2606 * formulas & protocol overheads are derived from the 5.11.3 section of the
2607 * USB 2.0 Specification.
2608 *
2609 * High-Speed:
2610 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay
2611 *
2612 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub)
2613 *
2614 * Protocol overhead + Split transaction overhead +
2615 * ((MaxPktSz * 7)/6) + Host_Delay;
2616 */
2617 /* ARGSUSED */
2618 static int
2619 ehci_compute_high_speed_bandwidth(
2620 ehci_state_t *ehcip,
2621 usb_ep_descr_t *endpoint,
2622 usb_port_status_t port_status,
2623 uint_t *sbandwidth,
2624 uint_t *cbandwidth)
2625 {
2626 ushort_t maxpacketsize = endpoint->wMaxPacketSize;
2627
2628 /* Return failure if endpoint maximum packet is zero */
2629 if (maxpacketsize == 0) {
2630 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2631 "ehci_allocate_high_speed_bandwidth: Periodic endpoint "
2632 "with zero endpoint maximum packet size is not supported");
2633
2634 return (USB_NOT_SUPPORTED);
2635 }
2636
2637 /* Add bit-stuffing overhead */
2638 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6);
2639
2640 /* Add Host Controller specific delay to required bandwidth */
2641 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY;
2642
2643 /* Add xfer specific protocol overheads */
2644 if ((endpoint->bmAttributes &
2645 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) {
2646 /* High speed interrupt transaction */
2647 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD;
2648 } else {
2649 /* Isochronous transaction */
2650 *sbandwidth += HS_ISOC_PROTO_OVERHEAD;
2651 }
2652
2653 /*
2654 * For low/full speed devices, add split transaction specific
2655 * overheads.
2656 */
2657 if (port_status != USBA_HIGH_SPEED_DEV) {
2658 /*
2659 * Add start and complete split transaction
2660 * tokens overheads.
2661 */
2662 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD;
2663 *sbandwidth += START_SPLIT_OVERHEAD;
2664
2665 /* Add data overhead depending on data direction */
2666 if ((endpoint->bEndpointAddress &
2667 USB_EP_DIR_MASK) == USB_EP_DIR_IN) {
2668 *cbandwidth += maxpacketsize;
2669 } else {
2670 if ((endpoint->bmAttributes &
2671 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) {
2672 /* There is no compete splits for out */
2673 *cbandwidth = 0;
2674 }
2675 *sbandwidth += maxpacketsize;
2676 }
2677 } else {
2678 uint_t xactions;
2679
2680 /* Get the max transactions per microframe */
2681 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >>
2682 USB_EP_MAX_XACTS_SHIFT) + 1;
2683
2684 /* High speed transaction */
2685 *sbandwidth += maxpacketsize;
2686
2687 /* Calculate bandwidth per micro-frame */
2688 *sbandwidth *= xactions;
2689
2690 *cbandwidth = 0;
2691 }
2692
2693 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2694 "ehci_allocate_high_speed_bandwidth: "
2695 "Start split bandwidth %d Complete split bandwidth %d",
2696 *sbandwidth, *cbandwidth);
2697
2698 return (USB_SUCCESS);
2699 }
2700
2701
2702 /*
2703 * ehci_compute_classic_bandwidth:
2704 *
2705 * Given a periodic endpoint (interrupt or isochronous) determine the total
2706 * bandwidth for one transaction. The EHCI host controller traverses the
2707 * endpoint descriptor lists on a first-come-first-serve basis. When the HC
2708 * services an endpoint, only a single transaction attempt is made. The HC
2709 * moves to the next Endpoint Descriptor after the first transaction attempt
2710 * rather than finishing the entire Transfer Descriptor. Therefore, when a
2711 * Transfer Descriptor is inserted into the lattice, we will only count the
2712 * number of bytes for one transaction.
2713 *
2714 * The following are the formulas used for calculating bandwidth in terms
2715 * bytes and it is for the single USB high speed transaction. The protocol
2716 * overheads will be different for each of type of USB transfer & all these
2717 * formulas & protocol overheads are derived from the 5.11.3 section of the
2718 * USB 2.0 Specification.
2719 *
2720 * Low-Speed:
2721 * Protocol overhead + Hub LS overhead +
2722 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay
2723 *
2724 * Full-Speed:
2725 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay
2726 */
2727 /* ARGSUSED */
2728 static int
2729 ehci_compute_classic_bandwidth(
2730 usb_ep_descr_t *endpoint,
2731 usb_port_status_t port_status,
2732 uint_t *bandwidth)
2733 {
2734 ushort_t maxpacketsize = endpoint->wMaxPacketSize;
2735
2736 /*
2737 * If endpoint maximum packet is zero, then return immediately.
2738 */
2739 if (maxpacketsize == 0) {
2740
2741 return (USB_NOT_SUPPORTED);
2742 }
2743
2744 /* Add TT delay to required bandwidth */
2745 *bandwidth = TT_DELAY;
2746
2747 /* Add bit-stuffing overhead */
2748 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6);
2749
2750 switch (port_status) {
2751 case USBA_LOW_SPEED_DEV:
2752 /* Low speed interrupt transaction */
2753 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD +
2754 HUB_LOW_SPEED_PROTO_OVERHEAD +
2755 (LOW_SPEED_CLOCK * maxpacketsize));
2756 break;
2757 case USBA_FULL_SPEED_DEV:
2758 /* Full speed transaction */
2759 *bandwidth += maxpacketsize;
2760
2761 /* Add xfer specific protocol overheads */
2762 if ((endpoint->bmAttributes &
2763 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) {
2764 /* Full speed interrupt transaction */
2765 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD;
2766 } else {
2767 /* Isochronous and input transaction */
2768 if ((endpoint->bEndpointAddress &
2769 USB_EP_DIR_MASK) == USB_EP_DIR_IN) {
2770 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD;
2771 } else {
2772 /* Isochronous and output transaction */
2773 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD;
2774 }
2775 }
2776 break;
2777 }
2778
2779 return (USB_SUCCESS);
2780 }
2781
2782
2783 /*
2784 * ehci_adjust_polling_interval:
2785 *
2786 * Adjust bandwidth according usb device speed.
2787 */
2788 /* ARGSUSED */
2789 int
2790 ehci_adjust_polling_interval(
2791 ehci_state_t *ehcip,
2792 usb_ep_descr_t *endpoint,
2793 usb_port_status_t port_status)
2794 {
2795 uint_t interval;
2796 int i = 0;
2797
2798 /* Get the polling interval */
2799 interval = endpoint->bInterval;
2800
2801 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2802 "ehci_adjust_polling_interval: Polling interval 0x%x", interval);
2803
2804 /*
2805 * According USB 2.0 Specifications, a high-speed endpoint's
2806 * polling intervals are specified interms of 125us or micro
2807 * frame, where as full/low endpoint's polling intervals are
2808 * specified in milliseconds.
2809 *
2810 * A high speed interrupt/isochronous endpoints can specify
2811 * desired polling interval between 1 to 16 micro-frames,
2812 * where as full/low endpoints can specify between 1 to 255
2813 * milliseconds.
2814 */
2815 switch (port_status) {
2816 case USBA_LOW_SPEED_DEV:
2817 /*
2818 * Low speed endpoints are limited to specifying
2819 * only 8ms to 255ms in this driver. If a device
2820 * reports a polling interval that is less than 8ms,
2821 * it will use 8 ms instead.
2822 */
2823 if (interval < LS_MIN_POLL_INTERVAL) {
2824
2825 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2826 "Low speed endpoint's poll interval of %d ms "
2827 "is below threshold. Rounding up to %d ms",
2828 interval, LS_MIN_POLL_INTERVAL);
2829
2830 interval = LS_MIN_POLL_INTERVAL;
2831 }
2832
2833 /*
2834 * Return an error if the polling interval is greater
2835 * than 255ms.
2836 */
2837 if (interval > LS_MAX_POLL_INTERVAL) {
2838
2839 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2840 "Low speed endpoint's poll interval is "
2841 "greater than %d ms", LS_MAX_POLL_INTERVAL);
2842
2843 return (USB_FAILURE);
2844 }
2845 break;
2846
2847 case USBA_FULL_SPEED_DEV:
2848 /*
2849 * Return an error if the polling interval is less
2850 * than 1ms and greater than 255ms.
2851 */
2852 if ((interval < FS_MIN_POLL_INTERVAL) &&
2853 (interval > FS_MAX_POLL_INTERVAL)) {
2854
2855 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2856 "Full speed endpoint's poll interval must "
2857 "be between %d and %d ms", FS_MIN_POLL_INTERVAL,
2858 FS_MAX_POLL_INTERVAL);
2859
2860 return (USB_FAILURE);
2861 }
2862 break;
2863 case USBA_HIGH_SPEED_DEV:
2864 /*
2865 * Return an error if the polling interval is less 1
2866 * and greater than 16. Convert this value to 125us
2867 * units using 2^(bInterval -1). refer usb 2.0 spec
2868 * page 51 for details.
2869 */
2870 if ((interval < HS_MIN_POLL_INTERVAL) &&
2871 (interval > HS_MAX_POLL_INTERVAL)) {
2872
2873 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2874 "High speed endpoint's poll interval "
2875 "must be between %d and %d units",
2876 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL);
2877
2878 return (USB_FAILURE);
2879 }
2880
2881 /* Adjust high speed device polling interval */
2882 interval =
2883 ehci_adjust_high_speed_polling_interval(ehcip, endpoint);
2884
2885 break;
2886 }
2887
2888 /*
2889 * If polling interval is greater than 32ms,
2890 * adjust polling interval equal to 32ms.
2891 */
2892 if (interval > EHCI_NUM_INTR_QH_LISTS) {
2893 interval = EHCI_NUM_INTR_QH_LISTS;
2894 }
2895
2896 /*
2897 * Find the nearest power of 2 that's less
2898 * than interval.
2899 */
2900 while ((ehci_pow_2(i)) <= interval) {
2901 i++;
2902 }
2903
2904 return (ehci_pow_2((i - 1)));
2905 }
2906
2907
2908 /*
2909 * ehci_adjust_high_speed_polling_interval:
2910 */
2911 /* ARGSUSED */
2912 static int
2913 ehci_adjust_high_speed_polling_interval(
2914 ehci_state_t *ehcip,
2915 usb_ep_descr_t *endpoint)
2916 {
2917 uint_t interval;
2918
2919 /* Get the polling interval */
2920 interval = ehci_pow_2(endpoint->bInterval - 1);
2921
2922 /*
2923 * Convert polling interval from micro seconds
2924 * to milli seconds.
2925 */
2926 if (interval <= EHCI_MAX_UFRAMES) {
2927 interval = 1;
2928 } else {
2929 interval = interval/EHCI_MAX_UFRAMES;
2930 }
2931
2932 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
2933 "ehci_adjust_high_speed_polling_interval: "
2934 "High speed adjusted interval 0x%x", interval);
2935
2936 return (interval);
2937 }
2938
2939
2940 /*
2941 * ehci_lattice_height:
2942 *
2943 * Given the requested bandwidth, find the height in the tree at which the
2944 * nodes for this bandwidth fall. The height is measured as the number of
2945 * nodes from the leaf to the level specified by bandwidth The root of the
2946 * tree is at height TREE_HEIGHT.
2947 */
2948 static uint_t
2949 ehci_lattice_height(uint_t interval)
2950 {
2951 return (TREE_HEIGHT - (ehci_log_2(interval)));
2952 }
2953
2954
2955 /*
2956 * ehci_lattice_parent:
2957 *
2958 * Given a node in the lattice, find the index of the parent node
2959 */
2960 static uint_t
2961 ehci_lattice_parent(uint_t node)
2962 {
2963 if ((node % 2) == 0) {
2964
2965 return ((node/2) - 1);
2966 } else {
2967
2968 return ((node + 1)/2 - 1);
2969 }
2970 }
2971
2972
2973 /*
2974 * ehci_find_periodic_node:
2975 *
2976 * Based on the "real" array leaf node and interval, get the periodic node.
2977 */
2978 static uint_t
2979 ehci_find_periodic_node(uint_t leaf, int interval) {
2980 uint_t lattice_leaf;
2981 uint_t height = ehci_lattice_height(interval);
2982 uint_t pnode;
2983 int i;
2984
2985 /* Get the leaf number in the lattice */
2986 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1;
2987
2988 /* Get the node in the lattice based on the height and leaf */
2989 pnode = lattice_leaf;
2990 for (i = 0; i < height; i++) {
2991 pnode = ehci_lattice_parent(pnode);
2992 }
2993
2994 return (pnode);
2995 }
2996
2997
2998 /*
2999 * ehci_leftmost_leaf:
3000 *
3001 * Find the leftmost leaf in the subtree specified by the node. Height refers
3002 * to number of nodes from the bottom of the tree to the node, including the
3003 * node.
3004 *
3005 * The formula for a zero based tree is:
3006 * 2^H * Node + 2^H - 1
3007 * The leaf of the tree is an array, convert the number for the array.
3008 * Subtract the size of nodes not in the array
3009 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) =
3010 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS =
3011 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS
3012 * 0
3013 * 1 2
3014 * 0 1 2 3
3015 */
3016 static uint_t
3017 ehci_leftmost_leaf(
3018 uint_t node,
3019 uint_t height)
3020 {
3021 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS);
3022 }
3023
3024
3025 /*
3026 * ehci_pow_2:
3027 *
3028 * Compute 2 to the power
3029 */
3030 static uint_t
3031 ehci_pow_2(uint_t x)
3032 {
3033 if (x == 0) {
3034
3035 return (1);
3036 } else {
3037
3038 return (2 << (x - 1));
3039 }
3040 }
3041
3042
3043 /*
3044 * ehci_log_2:
3045 *
3046 * Compute log base 2 of x
3047 */
3048 static uint_t
3049 ehci_log_2(uint_t x)
3050 {
3051 int i = 0;
3052
3053 while (x != 1) {
3054 x = x >> 1;
3055 i++;
3056 }
3057
3058 return (i);
3059 }
3060
3061
3062 /*
3063 * ehci_find_bestfit_hs_mask:
3064 *
3065 * Find the smask and cmask in the bandwidth allocation, and update the
3066 * bandwidth allocation.
3067 */
3068 static int
3069 ehci_find_bestfit_hs_mask(
3070 ehci_state_t *ehcip,
3071 uchar_t *smask,
3072 uint_t *pnode,
3073 usb_ep_descr_t *endpoint,
3074 uint_t bandwidth,
3075 int interval)
3076 {
3077 int i;
3078 uint_t elements, index;
3079 int array_leaf, best_array_leaf;
3080 uint_t node_bandwidth, best_node_bandwidth;
3081 uint_t leaf_count;
3082 uchar_t bw_mask;
3083 uchar_t best_smask;
3084
3085 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
3086 "ehci_find_bestfit_hs_mask: ");
3087
3088 /* Get all the valid smasks */
3089 switch (ehci_pow_2(endpoint->bInterval - 1)) {
3090 case EHCI_INTR_1US_POLL:
3091 index = EHCI_1US_MASK_INDEX;
3092 elements = EHCI_INTR_1US_POLL;
3093 break;
3094 case EHCI_INTR_2US_POLL:
3095 index = EHCI_2US_MASK_INDEX;
3096 elements = EHCI_INTR_2US_POLL;
3097 break;
3098 case EHCI_INTR_4US_POLL:
3099 index = EHCI_4US_MASK_INDEX;
3100 elements = EHCI_INTR_4US_POLL;
3101 break;
3102 case EHCI_INTR_XUS_POLL:
3103 default:
3104 index = EHCI_XUS_MASK_INDEX;
3105 elements = EHCI_INTR_XUS_POLL;
3106 break;
3107 }
3108
3109 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval;
3110
3111 /*
3112 * Because of the way the leaves are setup, we will automatically
3113 * hit the leftmost leaf of every possible node with this interval.
3114 */
3115 best_smask = 0x00;
3116 best_node_bandwidth = 0;
3117 for (array_leaf = 0; array_leaf < interval; array_leaf++) {
3118 /* Find the bandwidth mask */
3119 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip,
3120 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask);
3121
3122 /*
3123 * If this node cannot support our requirements skip to the
3124 * next leaf.
3125 */
3126 if (bw_mask == 0x00) {
3127 continue;
3128 }
3129
3130 /*
3131 * Now make sure our bandwidth requirements can be
3132 * satisfied with one of smasks in this node.
3133 */
3134 *smask = 0x00;
3135 for (i = index; i < (index + elements); i++) {
3136 /* Check the start split mask value */
3137 if (ehci_start_split_mask[index] & bw_mask) {
3138 *smask = ehci_start_split_mask[index];
3139 break;
3140 }
3141 }
3142
3143 /*
3144 * If an appropriate smask is found save the information if:
3145 * o best_smask has not been found yet.
3146 * - or -
3147 * o This is the node with the least amount of bandwidth
3148 */
3149 if ((*smask != 0x00) &&
3150 ((best_smask == 0x00) ||
3151 (best_node_bandwidth > node_bandwidth))) {
3152
3153 best_node_bandwidth = node_bandwidth;
3154 best_array_leaf = array_leaf;
3155 best_smask = *smask;
3156 }
3157 }
3158
3159 /*
3160 * If we find node that can handle the bandwidth populate the
3161 * appropriate variables and return success.
3162 */
3163 if (best_smask) {
3164 *smask = best_smask;
3165 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf],
3166 interval);
3167 ehci_update_bw_availability(ehcip, bandwidth,
3168 ehci_index[best_array_leaf], leaf_count, best_smask);
3169
3170 return (USB_SUCCESS);
3171 }
3172
3173 return (USB_FAILURE);
3174 }
3175
3176
3177 /*
3178 * ehci_find_bestfit_ls_intr_mask:
3179 *
3180 * Find the smask and cmask in the bandwidth allocation.
3181 */
3182 static int
3183 ehci_find_bestfit_ls_intr_mask(
3184 ehci_state_t *ehcip,
3185 uchar_t *smask,
3186 uchar_t *cmask,
3187 uint_t *pnode,
3188 uint_t sbandwidth,
3189 uint_t cbandwidth,
3190 int interval)
3191 {
3192 int i;
3193 uint_t elements, index;
3194 int array_leaf, best_array_leaf;
3195 uint_t node_sbandwidth, node_cbandwidth;
3196 uint_t best_node_bandwidth;
3197 uint_t leaf_count;
3198 uchar_t bw_smask, bw_cmask;
3199 uchar_t best_smask, best_cmask;
3200
3201 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
3202 "ehci_find_bestfit_ls_intr_mask: ");
3203
3204 /* For low and full speed devices */
3205 index = EHCI_XUS_MASK_INDEX;
3206 elements = EHCI_INTR_4MS_POLL;
3207
3208 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval;
3209
3210 /*
3211 * Because of the way the leaves are setup, we will automatically
3212 * hit the leftmost leaf of every possible node with this interval.
3213 */
3214 best_smask = 0x00;
3215 best_node_bandwidth = 0;
3216 for (array_leaf = 0; array_leaf < interval; array_leaf++) {
3217 /* Find the bandwidth mask */
3218 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip,
3219 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask);
3220 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip,
3221 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask);
3222
3223 /*
3224 * If this node cannot support our requirements skip to the
3225 * next leaf.
3226 */
3227 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) {
3228 continue;
3229 }
3230
3231 /*
3232 * Now make sure our bandwidth requirements can be
3233 * satisfied with one of smasks in this node.
3234 */
3235 *smask = 0x00;
3236 *cmask = 0x00;
3237 for (i = index; i < (index + elements); i++) {
3238 /* Check the start split mask value */
3239 if ((ehci_start_split_mask[index] & bw_smask) &&
3240 (ehci_intr_complete_split_mask[index] & bw_cmask)) {
3241 *smask = ehci_start_split_mask[index];
3242 *cmask = ehci_intr_complete_split_mask[index];
3243 break;
3244 }
3245 }
3246
3247 /*
3248 * If an appropriate smask is found save the information if:
3249 * o best_smask has not been found yet.
3250 * - or -
3251 * o This is the node with the least amount of bandwidth
3252 */
3253 if ((*smask != 0x00) &&
3254 ((best_smask == 0x00) ||
3255 (best_node_bandwidth >
3256 (node_sbandwidth + node_cbandwidth)))) {
3257 best_node_bandwidth = node_sbandwidth + node_cbandwidth;
3258 best_array_leaf = array_leaf;
3259 best_smask = *smask;
3260 best_cmask = *cmask;
3261 }
3262 }
3263
3264 /*
3265 * If we find node that can handle the bandwidth populate the
3266 * appropriate variables and return success.
3267 */
3268 if (best_smask) {
3269 *smask = best_smask;
3270 *cmask = best_cmask;
3271 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf],
3272 interval);
3273 ehci_update_bw_availability(ehcip, sbandwidth,
3274 ehci_index[best_array_leaf], leaf_count, best_smask);
3275 ehci_update_bw_availability(ehcip, cbandwidth,
3276 ehci_index[best_array_leaf], leaf_count, best_cmask);
3277
3278 return (USB_SUCCESS);
3279 }
3280
3281 return (USB_FAILURE);
3282 }
3283
3284
3285 /*
3286 * ehci_find_bestfit_sitd_in_mask:
3287 *
3288 * Find the smask and cmask in the bandwidth allocation.
3289 */
3290 static int
3291 ehci_find_bestfit_sitd_in_mask(
3292 ehci_state_t *ehcip,
3293 uchar_t *smask,
3294 uchar_t *cmask,
3295 uint_t *pnode,
3296 uint_t sbandwidth,
3297 uint_t cbandwidth,
3298 int interval)
3299 {
3300 int i, uFrames, found;
3301 int array_leaf, best_array_leaf;
3302 uint_t node_sbandwidth, node_cbandwidth;
3303 uint_t best_node_bandwidth;
3304 uint_t leaf_count;
3305 uchar_t bw_smask, bw_cmask;
3306 uchar_t best_smask, best_cmask;
3307
3308 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
3309 "ehci_find_bestfit_sitd_in_mask: ");
3310
3311 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval;
3312
3313 /*
3314 * Because of the way the leaves are setup, we will automatically
3315 * hit the leftmost leaf of every possible node with this interval.
3316 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame.
3317 */
3318 /*
3319 * Need to add an additional 2 uFrames, if the "L"ast
3320 * complete split is before uFrame 6. See section
3321 * 11.8.4 in USB 2.0 Spec. Currently we do not support
3322 * the "Back Ptr" which means we support on IN of
3323 * ~4*MAX_UFRAME_SITD_XFER bandwidth/
3324 */
3325 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2;
3326 if (cbandwidth % MAX_UFRAME_SITD_XFER) {
3327 uFrames++;
3328 }
3329 if (uFrames > 6) {
3330
3331 return (USB_FAILURE);
3332 }
3333 *smask = 0x1;
3334 *cmask = 0x00;
3335 for (i = 0; i < uFrames; i++) {
3336 *cmask = *cmask << 1;
3337 *cmask |= 0x1;
3338 }
3339 /* cmask must start 2 frames after the smask */
3340 *cmask = *cmask << 2;
3341
3342 found = 0;
3343 best_smask = 0x00;
3344 best_node_bandwidth = 0;
3345 for (array_leaf = 0; array_leaf < interval; array_leaf++) {
3346 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip,
3347 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask);
3348 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip,
3349 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count,
3350 &bw_cmask);
3351
3352 /*
3353 * If this node cannot support our requirements skip to the
3354 * next leaf.
3355 */
3356 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) {
3357 continue;
3358 }
3359
3360 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) {
3361 if ((*smask & bw_smask) && (*cmask & bw_cmask)) {
3362 found = 1;
3363 break;
3364 }
3365 *smask = *smask << 1;
3366 *cmask = *cmask << 1;
3367 }
3368
3369 /*
3370 * If an appropriate smask is found save the information if:
3371 * o best_smask has not been found yet.
3372 * - or -
3373 * o This is the node with the least amount of bandwidth
3374 */
3375 if (found &&
3376 ((best_smask == 0x00) ||
3377 (best_node_bandwidth >
3378 (node_sbandwidth + node_cbandwidth)))) {
3379 best_node_bandwidth = node_sbandwidth + node_cbandwidth;
3380 best_array_leaf = array_leaf;
3381 best_smask = *smask;
3382 best_cmask = *cmask;
3383 }
3384 }
3385
3386 /*
3387 * If we find node that can handle the bandwidth populate the
3388 * appropriate variables and return success.
3389 */
3390 if (best_smask) {
3391 *smask = best_smask;
3392 *cmask = best_cmask;
3393 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf],
3394 interval);
3395 ehci_update_bw_availability(ehcip, sbandwidth,
3396 ehci_index[best_array_leaf], leaf_count, best_smask);
3397 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER,
3398 ehci_index[best_array_leaf], leaf_count, best_cmask);
3399
3400 return (USB_SUCCESS);
3401 }
3402
3403 return (USB_FAILURE);
3404 }
3405
3406
3407 /*
3408 * ehci_find_bestfit_sitd_out_mask:
3409 *
3410 * Find the smask in the bandwidth allocation.
3411 */
3412 static int
3413 ehci_find_bestfit_sitd_out_mask(
3414 ehci_state_t *ehcip,
3415 uchar_t *smask,
3416 uint_t *pnode,
3417 uint_t sbandwidth,
3418 int interval)
3419 {
3420 int i, uFrames, found;
3421 int array_leaf, best_array_leaf;
3422 uint_t node_sbandwidth;
3423 uint_t best_node_bandwidth;
3424 uint_t leaf_count;
3425 uchar_t bw_smask;
3426 uchar_t best_smask;
3427
3428 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
3429 "ehci_find_bestfit_sitd_out_mask: ");
3430
3431 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval;
3432
3433 /*
3434 * Because of the way the leaves are setup, we will automatically
3435 * hit the leftmost leaf of every possible node with this interval.
3436 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame.
3437 */
3438 *smask = 0x00;
3439 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER;
3440 if (sbandwidth % MAX_UFRAME_SITD_XFER) {
3441 uFrames++;
3442 }
3443 for (i = 0; i < uFrames; i++) {
3444 *smask = *smask << 1;
3445 *smask |= 0x1;
3446 }
3447
3448 found = 0;
3449 best_smask = 0x00;
3450 best_node_bandwidth = 0;
3451 for (array_leaf = 0; array_leaf < interval; array_leaf++) {
3452 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip,
3453 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count,
3454 &bw_smask);
3455
3456 /*
3457 * If this node cannot support our requirements skip to the
3458 * next leaf.
3459 */
3460 if (bw_smask == 0x00) {
3461 continue;
3462 }
3463
3464 /* You cannot have a start split on the 8th uFrame */
3465 for (i = 0; (*smask & 0x80) == 0; i++) {
3466 if (*smask & bw_smask) {
3467 found = 1;
3468 break;
3469 }
3470 *smask = *smask << 1;
3471 }
3472
3473 /*
3474 * If an appropriate smask is found save the information if:
3475 * o best_smask has not been found yet.
3476 * - or -
3477 * o This is the node with the least amount of bandwidth
3478 */
3479 if (found &&
3480 ((best_smask == 0x00) ||
3481 (best_node_bandwidth > node_sbandwidth))) {
3482 best_node_bandwidth = node_sbandwidth;
3483 best_array_leaf = array_leaf;
3484 best_smask = *smask;
3485 }
3486 }
3487
3488 /*
3489 * If we find node that can handle the bandwidth populate the
3490 * appropriate variables and return success.
3491 */
3492 if (best_smask) {
3493 *smask = best_smask;
3494 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf],
3495 interval);
3496 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER,
3497 ehci_index[best_array_leaf], leaf_count, best_smask);
3498
3499 return (USB_SUCCESS);
3500 }
3501
3502 return (USB_FAILURE);
3503 }
3504
3505
3506 /*
3507 * ehci_calculate_bw_availability_mask:
3508 *
3509 * Returns the "total bandwidth used" in this node.
3510 * Populates bw_mask with the uFrames that can support the bandwidth.
3511 *
3512 * If all the Frames cannot support this bandwidth, then bw_mask
3513 * will return 0x00 and the "total bandwidth used" will be invalid.
3514 */
3515 static uint_t
3516 ehci_calculate_bw_availability_mask(
3517 ehci_state_t *ehcip,
3518 uint_t bandwidth,
3519 int leaf,
3520 int leaf_count,
3521 uchar_t *bw_mask)
3522 {
3523 int i, j;
3524 uchar_t bw_uframe;
3525 int uframe_total;
3526 ehci_frame_bandwidth_t *fbp;
3527 uint_t total_bandwidth = 0;
3528
3529 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
3530 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d",
3531 leaf, leaf_count);
3532
3533 /* Start by saying all uFrames are available */
3534 *bw_mask = 0xFF;
3535
3536 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) {
3537 fbp = &ehcip->ehci_frame_bandwidth[leaf + i];
3538
3539 total_bandwidth += fbp->ehci_allocated_frame_bandwidth;
3540
3541 for (j = 0; j < EHCI_MAX_UFRAMES; j++) {
3542 /*
3543 * If the uFrame in bw_mask is available check to see if
3544 * it can support the additional bandwidth.
3545 */
3546 bw_uframe = (*bw_mask & (0x1 << j));
3547 uframe_total =
3548 fbp->ehci_micro_frame_bandwidth[j] +
3549 bandwidth;
3550 if ((bw_uframe) &&
3551 (uframe_total > HS_PERIODIC_BANDWIDTH)) {
3552 *bw_mask = *bw_mask & ~bw_uframe;
3553 }
3554 }
3555 }
3556
3557 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl,
3558 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x",
3559 *bw_mask);
3560
3561 return (total_bandwidth);
3562 }
3563
3564
3565 /*
3566 * ehci_update_bw_availability:
3567 *
3568 * The leftmost leaf needs to be in terms of array position and
3569 * not the actual lattice position.
3570 */
3571 static void
3572 ehci_update_bw_availability(
3573 ehci_state_t *ehcip,
3574 int bandwidth,
3575 int leftmost_leaf,
3576 int leaf_count,
3577 uchar_t mask)
3578 {
3579 int i, j;
3580 ehci_frame_bandwidth_t *fbp;
3581 int uFrame_bandwidth[8];
3582
3583 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
3584 "ehci_update_bw_availability: "
3585 "leaf %d count %d bandwidth 0x%x mask 0x%x",
3586 leftmost_leaf, leaf_count, bandwidth, mask);
3587
3588 ASSERT(leftmost_leaf < 32);
3589 ASSERT(leftmost_leaf >= 0);
3590
3591 for (j = 0; j < EHCI_MAX_UFRAMES; j++) {
3592 if (mask & 0x1) {
3593 uFrame_bandwidth[j] = bandwidth;
3594 } else {
3595 uFrame_bandwidth[j] = 0;
3596 }
3597
3598 mask = mask >> 1;
3599 }
3600
3601 /* Updated all the effected leafs with the bandwidth */
3602 for (i = 0; i < leaf_count; i++) {
3603 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i];
3604
3605 for (j = 0; j < EHCI_MAX_UFRAMES; j++) {
3606 fbp->ehci_micro_frame_bandwidth[j] +=
3607 uFrame_bandwidth[j];
3608 fbp->ehci_allocated_frame_bandwidth +=
3609 uFrame_bandwidth[j];
3610 }
3611 }
3612 }
3613
3614 /*
3615 * Miscellaneous functions
3616 */
3617
3618 /*
3619 * ehci_obtain_state:
3620 *
3621 * NOTE: This function is also called from POLLED MODE.
3622 */
3623 ehci_state_t *
3624 ehci_obtain_state(dev_info_t *dip)
3625 {
3626 int instance = ddi_get_instance(dip);
3627
3628 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance);
3629
3630 ASSERT(state != NULL);
3631
3632 return (state);
3633 }
3634
3635
3636 /*
3637 * ehci_state_is_operational:
3638 *
3639 * Check the Host controller state and return proper values.
3640 */
3641 int
3642 ehci_state_is_operational(ehci_state_t *ehcip)
3643 {
3644 int val;
3645
3646 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
3647
3648 switch (ehcip->ehci_hc_soft_state) {
3649 case EHCI_CTLR_INIT_STATE:
3650 case EHCI_CTLR_SUSPEND_STATE:
3651 val = USB_FAILURE;
3652 break;
3653 case EHCI_CTLR_OPERATIONAL_STATE:
3654 val = USB_SUCCESS;
3655 break;
3656 case EHCI_CTLR_ERROR_STATE:
3657 val = USB_HC_HARDWARE_ERROR;
3658 break;
3659 default:
3660 val = USB_FAILURE;
3661 break;
3662 }
3663
3664 return (val);
3665 }
3666
3667
3668 /*
3669 * ehci_do_soft_reset
3670 *
3671 * Do soft reset of ehci host controller.
3672 */
3673 int
3674 ehci_do_soft_reset(ehci_state_t *ehcip)
3675 {
3676 usb_frame_number_t before_frame_number, after_frame_number;
3677 ehci_regs_t *ehci_save_regs;
3678
3679 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
3680
3681 /* Increment host controller error count */
3682 ehcip->ehci_hc_error++;
3683
3684 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl,
3685 "ehci_do_soft_reset:"
3686 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error);
3687
3688 /*
3689 * Allocate space for saving current Host Controller
3690 * registers. Don't do any recovery if allocation
3691 * fails.
3692 */
3693 ehci_save_regs = (ehci_regs_t *)
3694 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP);
3695
3696 if (ehci_save_regs == NULL) {
3697 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl,
3698 "ehci_do_soft_reset: kmem_zalloc failed");
3699
3700 return (USB_FAILURE);
3701 }
3702
3703 /* Save current ehci registers */
3704 ehci_save_regs->ehci_command = Get_OpReg(ehci_command);
3705 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt);
3706 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment);
3707 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr);
3708 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag);
3709 ehci_save_regs->ehci_periodic_list_base =
3710 Get_OpReg(ehci_periodic_list_base);
3711
3712 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl,
3713 "ehci_do_soft_reset: Save reg = 0x%p", (void *)ehci_save_regs);
3714
3715 /* Disable all list processing and interrupts */
3716 Set_OpReg(ehci_command, Get_OpReg(ehci_command) &
3717 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE));
3718
3719 /* Disable all EHCI interrupts */
3720 Set_OpReg(ehci_interrupt, 0);
3721
3722 /* Wait for few milliseconds */
3723 drv_usecwait(EHCI_SOF_TIMEWAIT);
3724
3725 /* Do light soft reset of ehci host controller */
3726 Set_OpReg(ehci_command,
3727 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET);
3728
3729 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl,
3730 "ehci_do_soft_reset: Reset in progress");
3731
3732 /* Wait for reset to complete */
3733 drv_usecwait(EHCI_RESET_TIMEWAIT);
3734
3735 /*
3736 * Restore previous saved EHCI register value
3737 * into the current EHCI registers.
3738 */
3739 Set_OpReg(ehci_ctrl_segment, (uint32_t)
3740 ehci_save_regs->ehci_ctrl_segment);
3741
3742 Set_OpReg(ehci_periodic_list_base, (uint32_t)
3743 ehci_save_regs->ehci_periodic_list_base);
3744
3745 Set_OpReg(ehci_async_list_addr, (uint32_t)
3746 ehci_save_regs->ehci_async_list_addr);
3747
3748 /*
3749 * For some reason this register might get nulled out by
3750 * the Uli M1575 South Bridge. To workaround the hardware
3751 * problem, check the value after write and retry if the
3752 * last write fails.
3753 */
3754 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) &&
3755 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) &&
3756 (ehci_save_regs->ehci_async_list_addr !=
3757 Get_OpReg(ehci_async_list_addr))) {
3758 int retry = 0;
3759
3760 Set_OpRegRetry(ehci_async_list_addr, (uint32_t)
3761 ehci_save_regs->ehci_async_list_addr, retry);
3762 if (retry >= EHCI_MAX_RETRY) {
3763 USB_DPRINTF_L2(PRINT_MASK_ATTA,
3764 ehcip->ehci_log_hdl, "ehci_do_soft_reset:"
3765 " ASYNCLISTADDR write failed.");
3766
3767 return (USB_FAILURE);
3768 }
3769 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
3770 "ehci_do_soft_reset: ASYNCLISTADDR "
3771 "write failed, retry=%d", retry);
3772 }
3773
3774 Set_OpReg(ehci_config_flag, (uint32_t)
3775 ehci_save_regs->ehci_config_flag);
3776
3777 /* Enable both Asynchronous and Periodic Schedule if necessary */
3778 ehci_toggle_scheduler(ehcip);
3779
3780 /*
3781 * Set ehci_interrupt to enable all interrupts except Root
3782 * Hub Status change and frame list rollover interrupts.
3783 */
3784 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR |
3785 EHCI_INTR_FRAME_LIST_ROLLOVER |
3786 EHCI_INTR_USB_ERROR |
3787 EHCI_INTR_USB);
3788
3789 /*
3790 * Deallocate the space that allocated for saving
3791 * HC registers.
3792 */
3793 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t));
3794
3795 /*
3796 * Set the desired interrupt threshold, frame list size (if
3797 * applicable) and turn EHCI host controller.
3798 */
3799 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) &
3800 ~EHCI_CMD_INTR_THRESHOLD) |
3801 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN)));
3802
3803 /* Wait 10ms for EHCI to start sending SOF */
3804 drv_usecwait(EHCI_RESET_TIMEWAIT);
3805
3806 /*
3807 * Get the current usb frame number before waiting for
3808 * few milliseconds.
3809 */
3810 before_frame_number = ehci_get_current_frame_number(ehcip);
3811
3812 /* Wait for few milliseconds */
3813 drv_usecwait(EHCI_SOF_TIMEWAIT);
3814
3815 /*
3816 * Get the current usb frame number after waiting for
3817 * few milliseconds.
3818 */
3819 after_frame_number = ehci_get_current_frame_number(ehcip);
3820
3821 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl,
3822 "ehci_do_soft_reset: Before Frame Number 0x%llx "
3823 "After Frame Number 0x%llx",
3824 (unsigned long long)before_frame_number,
3825 (unsigned long long)after_frame_number);
3826
3827 if ((after_frame_number <= before_frame_number) &&
3828 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) {
3829
3830 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl,
3831 "ehci_do_soft_reset: Soft reset failed");
3832
3833 return (USB_FAILURE);
3834 }
3835
3836 return (USB_SUCCESS);
3837 }
3838
3839
3840 /*
3841 * ehci_get_xfer_attrs:
3842 *
3843 * Get the attributes of a particular xfer.
3844 *
3845 * NOTE: This function is also called from POLLED MODE.
3846 */
3847 usb_req_attrs_t
3848 ehci_get_xfer_attrs(
3849 ehci_state_t *ehcip,
3850 ehci_pipe_private_t *pp,
3851 ehci_trans_wrapper_t *tw)
3852 {
3853 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep;
3854 usb_req_attrs_t attrs = USB_ATTRS_NONE;
3855
3856 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
3857 "ehci_get_xfer_attrs:");
3858
3859 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) {
3860 case USB_EP_ATTR_CONTROL:
3861 attrs = ((usb_ctrl_req_t *)
3862 tw->tw_curr_xfer_reqp)->ctrl_attributes;
3863 break;
3864 case USB_EP_ATTR_BULK:
3865 attrs = ((usb_bulk_req_t *)
3866 tw->tw_curr_xfer_reqp)->bulk_attributes;
3867 break;
3868 case USB_EP_ATTR_INTR:
3869 attrs = ((usb_intr_req_t *)
3870 tw->tw_curr_xfer_reqp)->intr_attributes;
3871 break;
3872 }
3873
3874 return (attrs);
3875 }
3876
3877
3878 /*
3879 * ehci_get_current_frame_number:
3880 *
3881 * Get the current software based usb frame number.
3882 */
3883 usb_frame_number_t
3884 ehci_get_current_frame_number(ehci_state_t *ehcip)
3885 {
3886 usb_frame_number_t usb_frame_number;
3887 usb_frame_number_t ehci_fno, micro_frame_number;
3888
3889 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
3890
3891 ehci_fno = ehcip->ehci_fno;
3892 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF;
3893
3894 /*
3895 * Calculate current software based usb frame number.
3896 *
3897 * This code accounts for the fact that frame number is
3898 * updated by the Host Controller before the ehci driver
3899 * gets an FrameListRollover interrupt that will adjust
3900 * Frame higher part.
3901 *
3902 * Refer ehci specification 1.0, section 2.3.2, page 21.
3903 */
3904 micro_frame_number = ((micro_frame_number & 0x1FFF) |
3905 ehci_fno) + (((micro_frame_number & 0x3FFF) ^
3906 ehci_fno) & 0x2000);
3907
3908 /*
3909 * Micro Frame number is equivalent to 125 usec. Eight
3910 * Micro Frame numbers are equivalent to one millsecond
3911 * or one usb frame number.
3912 */
3913 usb_frame_number = micro_frame_number >>
3914 EHCI_uFRAMES_PER_USB_FRAME_SHIFT;
3915
3916 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
3917 "ehci_get_current_frame_number: "
3918 "Current usb uframe number = 0x%llx "
3919 "Current usb frame number = 0x%llx",
3920 (unsigned long long)micro_frame_number,
3921 (unsigned long long)usb_frame_number);
3922
3923 return (usb_frame_number);
3924 }
3925
3926
3927 /*
3928 * ehci_cpr_cleanup:
3929 *
3930 * Cleanup ehci state and other ehci specific informations across
3931 * Check Point Resume (CPR).
3932 */
3933 static void
3934 ehci_cpr_cleanup(ehci_state_t *ehcip)
3935 {
3936 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
3937
3938 /* Reset software part of usb frame number */
3939 ehcip->ehci_fno = 0;
3940 }
3941
3942
3943 /*
3944 * ehci_wait_for_sof:
3945 *
3946 * Wait for couple of SOF interrupts
3947 */
3948 int
3949 ehci_wait_for_sof(ehci_state_t *ehcip)
3950 {
3951 usb_frame_number_t before_frame_number, after_frame_number;
3952 int error = USB_SUCCESS;
3953
3954 USB_DPRINTF_L4(PRINT_MASK_LISTS,
3955 ehcip->ehci_log_hdl, "ehci_wait_for_sof");
3956
3957 ASSERT(mutex_owned(&ehcip->ehci_int_mutex));
3958
3959 error = ehci_state_is_operational(ehcip);
3960
3961 if (error != USB_SUCCESS) {
3962
3963 return (error);
3964 }
3965
3966 /* Get the current usb frame number before waiting for two SOFs */
3967 before_frame_number = ehci_get_current_frame_number(ehcip);
3968
3969 mutex_exit(&ehcip->ehci_int_mutex);
3970
3971 /* Wait for few milliseconds */
3972 delay(drv_usectohz(EHCI_SOF_TIMEWAIT));
3973
3974 mutex_enter(&ehcip->ehci_int_mutex);
3975
3976 /* Get the current usb frame number after woken up */
3977 after_frame_number = ehci_get_current_frame_number(ehcip);
3978
3979 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
3980 "ehci_wait_for_sof: framenumber: before 0x%llx "
3981 "after 0x%llx",
3982 (unsigned long long)before_frame_number,
3983 (unsigned long long)after_frame_number);
3984
3985 /* Return failure, if usb frame number has not been changed */
3986 if (after_frame_number <= before_frame_number) {
3987
3988 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) {
3989
3990 USB_DPRINTF_L0(PRINT_MASK_LISTS,
3991 ehcip->ehci_log_hdl, "No SOF interrupts");
3992
3993 /* Set host controller soft state to error */
3994 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE;
3995
3996 return (USB_FAILURE);
3997 }
3998
3999 }
4000
4001 return (USB_SUCCESS);
4002 }
4003
4004 /*
4005 * Toggle the async/periodic schedule based on opened pipe count.
4006 * During pipe cleanup(in pipe reset case), the pipe's QH is temporarily
4007 * disabled. But the TW on the pipe is not freed. In this case, we need
4008 * to disable async/periodic schedule for some non-compatible hardware.
4009 * Otherwise, the hardware will overwrite software's configuration of
4010 * the QH.
4011 */
4012 void
4013 ehci_toggle_scheduler_on_pipe(ehci_state_t *ehcip)
4014 {
4015 uint_t temp_reg, cmd_reg;
4016
4017 cmd_reg = Get_OpReg(ehci_command);
4018 temp_reg = cmd_reg;
4019
4020 /*
4021 * Enable/Disable asynchronous scheduler, and
4022 * turn on/off async list door bell
4023 */
4024 if (ehcip->ehci_open_async_count) {
4025 if ((ehcip->ehci_async_req_count > 0) &&
4026 ((cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE) == 0)) {
4027 /*
4028 * For some reason this address might get nulled out by
4029 * the ehci chip. Set it here just in case it is null.
4030 */
4031 Set_OpReg(ehci_async_list_addr,
4032 ehci_qh_cpu_to_iommu(ehcip,
4033 ehcip->ehci_head_of_async_sched_list));
4034
4035 /*
4036 * For some reason this register might get nulled out by
4037 * the Uli M1575 Southbridge. To workaround the HW
4038 * problem, check the value after write and retry if the
4039 * last write fails.
4040 *
4041 * If the ASYNCLISTADDR remains "stuck" after
4042 * EHCI_MAX_RETRY retries, then the M1575 is broken
4043 * and is stuck in an inconsistent state and is about
4044 * to crash the machine with a trn_oor panic when it
4045 * does a DMA read from 0x0. It is better to panic
4046 * now rather than wait for the trn_oor crash; this
4047 * way Customer Service will have a clean signature
4048 * that indicts the M1575 chip rather than a
4049 * mysterious and hard-to-diagnose trn_oor panic.
4050 */
4051 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) &&
4052 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) &&
4053 (ehci_qh_cpu_to_iommu(ehcip,
4054 ehcip->ehci_head_of_async_sched_list) !=
4055 Get_OpReg(ehci_async_list_addr))) {
4056 int retry = 0;
4057
4058 Set_OpRegRetry(ehci_async_list_addr,
4059 ehci_qh_cpu_to_iommu(ehcip,
4060 ehcip->ehci_head_of_async_sched_list),
4061 retry);
4062 if (retry >= EHCI_MAX_RETRY)
4063 cmn_err(CE_PANIC,
4064 "ehci_toggle_scheduler_on_pipe: "
4065 "ASYNCLISTADDR write failed.");
4066
4067 USB_DPRINTF_L2(PRINT_MASK_ATTA,
4068 ehcip->ehci_log_hdl,
4069 "ehci_toggle_scheduler_on_pipe:"
4070 " ASYNCLISTADDR write failed, retry=%d",
4071 retry);
4072 }
4073
4074 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE;
4075 }
4076 } else {
4077 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE;
4078 }
4079
4080 if (ehcip->ehci_open_periodic_count) {
4081 if ((ehcip->ehci_periodic_req_count > 0) &&
4082 ((cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE) == 0)) {
4083 /*
4084 * For some reason this address get's nulled out by
4085 * the ehci chip. Set it here just in case it is null.
4086 */
4087 Set_OpReg(ehci_periodic_list_base,
4088 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address &
4089 0xFFFFF000));
4090 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE;
4091 }
4092 } else {
4093 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE;
4094 }
4095
4096 /* Just an optimization */
4097 if (temp_reg != cmd_reg) {
4098 Set_OpReg(ehci_command, cmd_reg);
4099 }
4100 }
4101
4102
4103 /*
4104 * ehci_toggle_scheduler:
4105 *
4106 * Turn scheduler based on pipe open count.
4107 */
4108 void
4109 ehci_toggle_scheduler(ehci_state_t *ehcip)
4110 {
4111 uint_t temp_reg, cmd_reg;
4112
4113 /*
4114 * For performance optimization, we need to change the bits
4115 * if (async == 1||async == 0) OR (periodic == 1||periodic == 0)
4116 *
4117 * Related bits already enabled if
4118 * async and periodic req counts are > 1
4119 * OR async req count > 1 & no periodic pipe
4120 * OR periodic req count > 1 & no async pipe
4121 */
4122 if (((ehcip->ehci_async_req_count > 1) &&
4123 (ehcip->ehci_periodic_req_count > 1)) ||
4124 ((ehcip->ehci_async_req_count > 1) &&
4125 (ehcip->ehci_open_periodic_count == 0)) ||
4126 ((ehcip->ehci_periodic_req_count > 1) &&
4127 (ehcip->ehci_open_async_count == 0))) {
4128 USB_DPRINTF_L4(PRINT_MASK_ATTA,
4129 ehcip->ehci_log_hdl, "ehci_toggle_scheduler:"
4130 "async/periodic bits no need to change");
4131
4132 return;
4133 }
4134
4135 cmd_reg = Get_OpReg(ehci_command);
4136 temp_reg = cmd_reg;
4137
4138 /*
4139 * Enable/Disable asynchronous scheduler, and
4140 * turn on/off async list door bell
4141 */
4142 if (ehcip->ehci_async_req_count > 1) {
4143 /* we already enable the async bit */
4144 USB_DPRINTF_L4(PRINT_MASK_ATTA,
4145 ehcip->ehci_log_hdl, "ehci_toggle_scheduler:"
4146 "async bit already enabled: cmd_reg=0x%x", cmd_reg);
4147 } else if (ehcip->ehci_async_req_count == 1) {
4148 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) {
4149 /*
4150 * For some reason this address might get nulled out by
4151 * the ehci chip. Set it here just in case it is null.
4152 * If it's not null, we should not reset the
4153 * ASYNCLISTADDR, because it's updated by hardware to
4154 * point to the next queue head to be executed.
4155 */
4156 if (!Get_OpReg(ehci_async_list_addr)) {
4157 Set_OpReg(ehci_async_list_addr,
4158 ehci_qh_cpu_to_iommu(ehcip,
4159 ehcip->ehci_head_of_async_sched_list));
4160 }
4161
4162 /*
4163 * For some reason this register might get nulled out by
4164 * the Uli M1575 Southbridge. To workaround the HW
4165 * problem, check the value after write and retry if the
4166 * last write fails.
4167 *
4168 * If the ASYNCLISTADDR remains "stuck" after
4169 * EHCI_MAX_RETRY retries, then the M1575 is broken
4170 * and is stuck in an inconsistent state and is about
4171 * to crash the machine with a trn_oor panic when it
4172 * does a DMA read from 0x0. It is better to panic
4173 * now rather than wait for the trn_oor crash; this
4174 * way Customer Service will have a clean signature
4175 * that indicts the M1575 chip rather than a
4176 * mysterious and hard-to-diagnose trn_oor panic.
4177 */
4178 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) &&
4179 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) &&
4180 (ehci_qh_cpu_to_iommu(ehcip,
4181 ehcip->ehci_head_of_async_sched_list) !=
4182 Get_OpReg(ehci_async_list_addr))) {
4183 int retry = 0;
4184
4185 Set_OpRegRetry(ehci_async_list_addr,
4186 ehci_qh_cpu_to_iommu(ehcip,
4187 ehcip->ehci_head_of_async_sched_list),
4188 retry);
4189 if (retry >= EHCI_MAX_RETRY)
4190 cmn_err(CE_PANIC,
4191 "ehci_toggle_scheduler: "
4192 "ASYNCLISTADDR write failed.");
4193
4194 USB_DPRINTF_L3(PRINT_MASK_ATTA,
4195 ehcip->ehci_log_hdl,
4196 "ehci_toggle_scheduler: ASYNCLISTADDR "
4197 "write failed, retry=%d", retry);
4198 }
4199 }
4200 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE;
4201 } else {
4202 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE;
4203 }
4204
4205 if (ehcip->ehci_periodic_req_count > 1) {
4206 /* we already enable the periodic bit. */
4207 USB_DPRINTF_L4(PRINT_MASK_ATTA,
4208 ehcip->ehci_log_hdl, "ehci_toggle_scheduler:"
4209 "periodic bit already enabled: cmd_reg=0x%x", cmd_reg);
4210 } else if (ehcip->ehci_periodic_req_count == 1) {
4211 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) {
4212 /*
4213 * For some reason this address get's nulled out by
4214 * the ehci chip. Set it here just in case it is null.
4215 */
4216 Set_OpReg(ehci_periodic_list_base,
4217 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address &
4218 0xFFFFF000));
4219 }
4220 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE;
4221 } else {
4222 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE;
4223 }
4224
4225 /* Just an optimization */
4226 if (temp_reg != cmd_reg) {
4227 Set_OpReg(ehci_command, cmd_reg);
4228
4229 /* To make sure the command register is updated correctly */
4230 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) &&
4231 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) {
4232 int retry = 0;
4233
4234 Set_OpRegRetry(ehci_command, cmd_reg, retry);
4235 USB_DPRINTF_L3(PRINT_MASK_ATTA,
4236 ehcip->ehci_log_hdl,
4237 "ehci_toggle_scheduler: CMD write failed, retry=%d",
4238 retry);
4239 }
4240
4241 }
4242 }
4243
4244 /*
4245 * ehci print functions
4246 */
4247
4248 /*
4249 * ehci_print_caps:
4250 */
4251 void
4252 ehci_print_caps(ehci_state_t *ehcip)
4253 {
4254 uint_t i;
4255
4256 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4257 "\n\tUSB 2.0 Host Controller Characteristics\n");
4258
4259 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4260 "Caps Length: 0x%x Version: 0x%x\n",
4261 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version));
4262
4263 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4264 "Structural Parameters\n");
4265 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4266 "Port indicators: %s", (Get_Cap(ehci_hcs_params) &
4267 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No");
4268 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4269 "No of Classic host controllers: 0x%x",
4270 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS)
4271 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT);
4272 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4273 "No of ports per Classic host controller: 0x%x",
4274 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC)
4275 >> EHCI_HCS_NUM_PORTS_CC_SHIFT);
4276 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4277 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) &
4278 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No");
4279 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4280 "Port power control: %s", (Get_Cap(ehci_hcs_params) &
4281 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No");
4282 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4283 "No of root hub ports: 0x%x\n",
4284 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS);
4285
4286 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4287 "Capability Parameters\n");
4288 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4289 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) &
4290 EHCI_HCC_EECP) ? "Yes" : "No");
4291 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4292 "Isoch schedule threshold: 0x%x",
4293 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD);
4294 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4295 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) &
4296 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No");
4297 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4298 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) &
4299 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024");
4300 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4301 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) &
4302 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No");
4303
4304 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4305 "Classic Port Route Description");
4306
4307 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) {
4308 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4309 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i]));
4310 }
4311 }
4312
4313
4314 /*
4315 * ehci_print_regs:
4316 */
4317 void
4318 ehci_print_regs(ehci_state_t *ehcip)
4319 {
4320 uint_t i;
4321
4322 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4323 "\n\tEHCI%d Operational Registers\n",
4324 ddi_get_instance(ehcip->ehci_dip));
4325
4326 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4327 "Command: 0x%x Status: 0x%x",
4328 Get_OpReg(ehci_command), Get_OpReg(ehci_status));
4329 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4330 "Interrupt: 0x%x Frame Index: 0x%x",
4331 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index));
4332 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4333 "Control Segment: 0x%x Periodic List Base: 0x%x",
4334 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base));
4335 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4336 "Async List Addr: 0x%x Config Flag: 0x%x",
4337 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag));
4338
4339 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4340 "Root Hub Port Status");
4341
4342 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) {
4343 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl,
4344 "\tPort Status 0x%x: 0x%x ", i,
4345 Get_OpReg(ehci_rh_port_status[i]));
4346 }
4347 }
4348
4349
4350 /*
4351 * ehci_print_qh:
4352 */
4353 void
4354 ehci_print_qh(
4355 ehci_state_t *ehcip,
4356 ehci_qh_t *qh)
4357 {
4358 uint_t i;
4359
4360 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4361 "ehci_print_qh: qh = 0x%p", (void *)qh);
4362
4363 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4364 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr));
4365 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4366 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl));
4367 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4368 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl));
4369 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4370 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd));
4371 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4372 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd));
4373 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4374 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd));
4375 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4376 "\tqh_status: 0x%x ", Get_QH(qh->qh_status));
4377
4378 for (i = 0; i < 5; i++) {
4379 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4380 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i]));
4381 }
4382
4383 for (i = 0; i < 5; i++) {
4384 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4385 "\tqh_buf_high[%d]: 0x%x ",
4386 i, Get_QH(qh->qh_buf_high[i]));
4387 }
4388
4389 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4390 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd));
4391 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4392 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev));
4393 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4394 "\tqh_state: 0x%x ", Get_QH(qh->qh_state));
4395 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4396 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next));
4397 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4398 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame));
4399 }
4400
4401
4402 /*
4403 * ehci_print_qtd:
4404 */
4405 void
4406 ehci_print_qtd(
4407 ehci_state_t *ehcip,
4408 ehci_qtd_t *qtd)
4409 {
4410 uint_t i;
4411
4412 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4413 "ehci_print_qtd: qtd = 0x%p", (void *)qtd);
4414
4415 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4416 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd));
4417 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4418 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd));
4419 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4420 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl));
4421
4422 for (i = 0; i < 5; i++) {
4423 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4424 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i]));
4425 }
4426
4427 for (i = 0; i < 5; i++) {
4428 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4429 "\tqtd_buf_high[%d]: 0x%x ",
4430 i, Get_QTD(qtd->qtd_buf_high[i]));
4431 }
4432
4433 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4434 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper));
4435 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4436 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd));
4437 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4438 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next));
4439 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4440 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev));
4441 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4442 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state));
4443 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4444 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase));
4445 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4446 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs));
4447 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl,
4448 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len));
4449 }
4450
4451 /*
4452 * ehci kstat functions
4453 */
4454
4455 /*
4456 * ehci_create_stats:
4457 *
4458 * Allocate and initialize the ehci kstat structures
4459 */
4460 void
4461 ehci_create_stats(ehci_state_t *ehcip)
4462 {
4463 char kstatname[KSTAT_STRLEN];
4464 const char *dname = ddi_driver_name(ehcip->ehci_dip);
4465 char *usbtypes[USB_N_COUNT_KSTATS] =
4466 {"ctrl", "isoch", "bulk", "intr"};
4467 uint_t instance = ehcip->ehci_instance;
4468 ehci_intrs_stats_t *isp;
4469 int i;
4470
4471 if (EHCI_INTRS_STATS(ehcip) == NULL) {
4472 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs",
4473 dname, instance);
4474 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance,
4475 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED,
4476 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t),
4477 KSTAT_FLAG_PERSISTENT);
4478
4479 if (EHCI_INTRS_STATS(ehcip)) {
4480 isp = EHCI_INTRS_STATS_DATA(ehcip);
4481 kstat_named_init(&isp->ehci_sts_total,
4482 "Interrupts Total", KSTAT_DATA_UINT64);
4483 kstat_named_init(&isp->ehci_sts_not_claimed,
4484 "Not Claimed", KSTAT_DATA_UINT64);
4485 kstat_named_init(&isp->ehci_sts_async_sched_status,
4486 "Async schedule status", KSTAT_DATA_UINT64);
4487 kstat_named_init(&isp->ehci_sts_periodic_sched_status,
4488 "Periodic sched status", KSTAT_DATA_UINT64);
4489 kstat_named_init(&isp->ehci_sts_empty_async_schedule,
4490 "Empty async schedule", KSTAT_DATA_UINT64);
4491 kstat_named_init(&isp->ehci_sts_host_ctrl_halted,
4492 "Host controller Halted", KSTAT_DATA_UINT64);
4493 kstat_named_init(&isp->ehci_sts_async_advance_intr,
4494 "Intr on async advance", KSTAT_DATA_UINT64);
4495 kstat_named_init(&isp->ehci_sts_host_system_error_intr,
4496 "Host system error", KSTAT_DATA_UINT64);
4497 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr,
4498 "Frame list rollover", KSTAT_DATA_UINT64);
4499 kstat_named_init(&isp->ehci_sts_rh_port_change_intr,
4500 "Port change detect", KSTAT_DATA_UINT64);
4501 kstat_named_init(&isp->ehci_sts_usb_error_intr,
4502 "USB error interrupt", KSTAT_DATA_UINT64);
4503 kstat_named_init(&isp->ehci_sts_usb_intr,
4504 "USB interrupt", KSTAT_DATA_UINT64);
4505
4506 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip;
4507 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev;
4508 kstat_install(EHCI_INTRS_STATS(ehcip));
4509 }
4510 }
4511
4512 if (EHCI_TOTAL_STATS(ehcip) == NULL) {
4513 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total",
4514 dname, instance);
4515 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance,
4516 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1,
4517 KSTAT_FLAG_PERSISTENT);
4518
4519 if (EHCI_TOTAL_STATS(ehcip)) {
4520 kstat_install(EHCI_TOTAL_STATS(ehcip));
4521 }
4522 }
4523
4524 for (i = 0; i < USB_N_COUNT_KSTATS; i++) {
4525 if (ehcip->ehci_count_stats[i] == NULL) {
4526 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s",
4527 dname, instance, usbtypes[i]);
4528 ehcip->ehci_count_stats[i] = kstat_create("usba",
4529 instance, kstatname, "usb_byte_count",
4530 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT);
4531
4532 if (ehcip->ehci_count_stats[i]) {
4533 kstat_install(ehcip->ehci_count_stats[i]);
4534 }
4535 }
4536 }
4537 }
4538
4539
4540 /*
4541 * ehci_destroy_stats:
4542 *
4543 * Clean up ehci kstat structures
4544 */
4545 void
4546 ehci_destroy_stats(ehci_state_t *ehcip)
4547 {
4548 int i;
4549
4550 if (EHCI_INTRS_STATS(ehcip)) {
4551 kstat_delete(EHCI_INTRS_STATS(ehcip));
4552 EHCI_INTRS_STATS(ehcip) = NULL;
4553 }
4554
4555 if (EHCI_TOTAL_STATS(ehcip)) {
4556 kstat_delete(EHCI_TOTAL_STATS(ehcip));
4557 EHCI_TOTAL_STATS(ehcip) = NULL;
4558 }
4559
4560 for (i = 0; i < USB_N_COUNT_KSTATS; i++) {
4561 if (ehcip->ehci_count_stats[i]) {
4562 kstat_delete(ehcip->ehci_count_stats[i]);
4563 ehcip->ehci_count_stats[i] = NULL;
4564 }
4565 }
4566 }
4567
4568
4569 /*
4570 * ehci_do_intrs_stats:
4571 *
4572 * ehci status information
4573 */
4574 void
4575 ehci_do_intrs_stats(
4576 ehci_state_t *ehcip,
4577 int val)
4578 {
4579 if (EHCI_INTRS_STATS(ehcip)) {
4580 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++;
4581 switch (val) {
4582 case EHCI_STS_ASYNC_SCHED_STATUS:
4583 EHCI_INTRS_STATS_DATA(ehcip)->
4584 ehci_sts_async_sched_status.value.ui64++;
4585 break;
4586 case EHCI_STS_PERIODIC_SCHED_STATUS:
4587 EHCI_INTRS_STATS_DATA(ehcip)->
4588 ehci_sts_periodic_sched_status.value.ui64++;
4589 break;
4590 case EHCI_STS_EMPTY_ASYNC_SCHEDULE:
4591 EHCI_INTRS_STATS_DATA(ehcip)->
4592 ehci_sts_empty_async_schedule.value.ui64++;
4593 break;
4594 case EHCI_STS_HOST_CTRL_HALTED:
4595 EHCI_INTRS_STATS_DATA(ehcip)->
4596 ehci_sts_host_ctrl_halted.value.ui64++;
4597 break;
4598 case EHCI_STS_ASYNC_ADVANCE_INTR:
4599 EHCI_INTRS_STATS_DATA(ehcip)->
4600 ehci_sts_async_advance_intr.value.ui64++;
4601 break;
4602 case EHCI_STS_HOST_SYSTEM_ERROR_INTR:
4603 EHCI_INTRS_STATS_DATA(ehcip)->
4604 ehci_sts_host_system_error_intr.value.ui64++;
4605 break;
4606 case EHCI_STS_FRM_LIST_ROLLOVER_INTR:
4607 EHCI_INTRS_STATS_DATA(ehcip)->
4608 ehci_sts_frm_list_rollover_intr.value.ui64++;
4609 break;
4610 case EHCI_STS_RH_PORT_CHANGE_INTR:
4611 EHCI_INTRS_STATS_DATA(ehcip)->
4612 ehci_sts_rh_port_change_intr.value.ui64++;
4613 break;
4614 case EHCI_STS_USB_ERROR_INTR:
4615 EHCI_INTRS_STATS_DATA(ehcip)->
4616 ehci_sts_usb_error_intr.value.ui64++;
4617 break;
4618 case EHCI_STS_USB_INTR:
4619 EHCI_INTRS_STATS_DATA(ehcip)->
4620 ehci_sts_usb_intr.value.ui64++;
4621 break;
4622 default:
4623 EHCI_INTRS_STATS_DATA(ehcip)->
4624 ehci_sts_not_claimed.value.ui64++;
4625 break;
4626 }
4627 }
4628 }
4629
4630
4631 /*
4632 * ehci_do_byte_stats:
4633 *
4634 * ehci data xfer information
4635 */
4636 void
4637 ehci_do_byte_stats(
4638 ehci_state_t *ehcip,
4639 size_t len,
4640 uint8_t attr,
4641 uint8_t addr)
4642 {
4643 uint8_t type = attr & USB_EP_ATTR_MASK;
4644 uint8_t dir = addr & USB_EP_DIR_MASK;
4645
4646 if (dir == USB_EP_DIR_IN) {
4647 EHCI_TOTAL_STATS_DATA(ehcip)->reads++;
4648 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len;
4649 switch (type) {
4650 case USB_EP_ATTR_CONTROL:
4651 EHCI_CTRL_STATS(ehcip)->reads++;
4652 EHCI_CTRL_STATS(ehcip)->nread += len;
4653 break;
4654 case USB_EP_ATTR_BULK:
4655 EHCI_BULK_STATS(ehcip)->reads++;
4656 EHCI_BULK_STATS(ehcip)->nread += len;
4657 break;
4658 case USB_EP_ATTR_INTR:
4659 EHCI_INTR_STATS(ehcip)->reads++;
4660 EHCI_INTR_STATS(ehcip)->nread += len;
4661 break;
4662 case USB_EP_ATTR_ISOCH:
4663 EHCI_ISOC_STATS(ehcip)->reads++;
4664 EHCI_ISOC_STATS(ehcip)->nread += len;
4665 break;
4666 }
4667 } else if (dir == USB_EP_DIR_OUT) {
4668 EHCI_TOTAL_STATS_DATA(ehcip)->writes++;
4669 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len;
4670 switch (type) {
4671 case USB_EP_ATTR_CONTROL:
4672 EHCI_CTRL_STATS(ehcip)->writes++;
4673 EHCI_CTRL_STATS(ehcip)->nwritten += len;
4674 break;
4675 case USB_EP_ATTR_BULK:
4676 EHCI_BULK_STATS(ehcip)->writes++;
4677 EHCI_BULK_STATS(ehcip)->nwritten += len;
4678 break;
4679 case USB_EP_ATTR_INTR:
4680 EHCI_INTR_STATS(ehcip)->writes++;
4681 EHCI_INTR_STATS(ehcip)->nwritten += len;
4682 break;
4683 case USB_EP_ATTR_ISOCH:
4684 EHCI_ISOC_STATS(ehcip)->writes++;
4685 EHCI_ISOC_STATS(ehcip)->nwritten += len;
4686 break;
4687 }
4688 }
4689 }