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MFV: illumos-gate@fd6d41c5025e9fb45a115fc82d86e9983d1e9fd6
9815 Want basic AHCI enclosure services
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
Reviewed by: Rob Johnston <rob.johnston@joyent.com>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Approved by: Dan McDonald <danmcd@joyent.com>
Author: Robert Mustacchi <rm@joyent.com>
Conflicts:
usr/src/cmd/Makefile
9772 Panic in ahci when the failed slot spkt is NULL
Reviewed by: Andy Stormont <astormont@racktopsystems.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Robert Mustacchi <rm@joyent.com>
NEX-17502 Slow crash dumps, significantly slower than live core
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
re #12164 Marvell 88SE9128: Appliance hard hangs on boot probing duplicated ahci device
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--- old/usr/src/uts/common/io/sata/adapters/ahci/ahci.c
+++ new/usr/src/uts/common/io/sata/adapters/ahci/ahci.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
24 - * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
24 + * Copyright 2018 Nexenta Systems, Inc. All rights reserved.
25 + * Copyright (c) 2018, Joyent, Inc.
26 + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
25 27 */
26 28
27 29 /*
28 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver
29 31 *
30 32 * Power Management Support
31 33 * ------------------------
32 34 *
33 35 * At the moment, the ahci driver only implements suspend/resume to
34 36 * support Suspend to RAM on X86 feature. Device power management isn't
35 37 * implemented, link power management is disabled, and hot plug isn't
36 38 * allowed during the period from suspend to resume.
37 39 *
38 40 * For s/r support, the ahci driver only need to implement DDI_SUSPEND
39 41 * and DDI_RESUME entries, and don't need to take care of new requests
40 42 * sent down after suspend because the target driver (sd) has already
41 43 * handled these conditions, and blocked these requests. For the detailed
42 44 * information, please check with sdopen, sdclose and sdioctl routines.
43 45 *
46 + *
47 + * Enclosure Management Support
48 + * ----------------------------
49 + *
50 + * The ahci driver has basic support for AHCI Enclosure Management (EM)
51 + * services. The AHCI specification provides an area in the primary ahci BAR for
52 + * posting data to send out to the enclosure management and provides a register
53 + * that provides both information and control about this. While the
54 + * specification allows for multiple forms of enclosure management, the only
55 + * supported, and commonly found form, is the AHCI specified LED format. The LED
56 + * format is often implemented as a one-way communication mechanism. Software
57 + * can write out what it cares about into the aforementioned data buffer and
58 + * then we wait for the transmission to be sent.
59 + *
60 + * This has some drawbacks. It means that we cannot know whether or not it has
61 + * succeeded. This means we cannot ask hardware what it thinks the LEDs are
62 + * set to. There's also the added unfortunate reality that firmware on the
63 + * microcontroller driving this will often not show the LEDs if no drive is
64 + * present and that actions taken may potentially cause this to get out of sync
65 + * with what we expect it to be. For example, the specification does not
66 + * describe what should happen if a drive is removed from the enclosure while
67 + * this is set and what should happen when it returns. We can only infer that it
68 + * should be the same.
69 + *
70 + * Because only a single command can be sent at any time and we don't want to
71 + * interfere with controller I/O, we create a taskq dedicated to this that has a
72 + * single thread. Both resets (which occur on attach and resume) and normal
73 + * changes to the LED state will be driven through this taskq. Because the taskq
74 + * has a single thread, this guarantees serial processing.
75 + *
76 + * Each userland-submitted task (basically not resets) has a reference counted
77 + * task structure. This allows the thread that called it to be cancelled and
78 + * have the system clean itself up. The user thread in ioctl blocks on a CV that
79 + * can receive signals as it waits for completion. Note, there is no guarantee
80 + * provided by the kernel that the first thread to enter the kernel will be the
81 + * first one to change state.
44 82 */
45 83
46 84 #include <sys/note.h>
47 85 #include <sys/scsi/scsi.h>
48 86 #include <sys/pci.h>
49 87 #include <sys/disp.h>
50 88 #include <sys/sata/sata_hba.h>
51 89 #include <sys/sata/adapters/ahci/ahcireg.h>
52 90 #include <sys/sata/adapters/ahci/ahcivar.h>
53 91
54 92 /*
55 93 * FMA header files
56 94 */
57 95 #include <sys/ddifm.h>
58 96 #include <sys/fm/protocol.h>
59 97 #include <sys/fm/util.h>
60 98 #include <sys/fm/io/ddi.h>
61 99
62 100 /*
101 + * EM Control header files
102 + */
103 +#include <sys/types.h>
104 +#include <sys/file.h>
105 +#include <sys/errno.h>
106 +#include <sys/open.h>
107 +#include <sys/cred.h>
108 +#include <sys/ddi.h>
109 +#include <sys/sunddi.h>
110 +
111 +/*
63 112 * This is the string displayed by modinfo, etc.
64 113 */
65 114 static char ahci_ident[] = "ahci driver";
66 115
67 116 /*
68 117 * Function prototypes for driver entry points
69 118 */
70 119 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t);
71 120 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t);
72 121 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
73 122 static int ahci_quiesce(dev_info_t *);
74 123
75 124 /*
76 125 * Function prototypes for SATA Framework interfaces
77 126 */
78 127 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t);
79 128 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *);
80 129
81 130 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *);
82 131 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt);
83 132 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int);
84 133 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *);
85 134 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *);
86 135 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *);
87 136 #if defined(__lock_lint)
88 137 static int ahci_selftest(dev_info_t *, sata_device_t *);
89 138 #endif
90 139
91 140 /*
92 141 * FMA Prototypes
93 142 */
94 143 static void ahci_fm_init(ahci_ctl_t *);
95 144 static void ahci_fm_fini(ahci_ctl_t *);
96 145 static int ahci_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void*);
97 146 int ahci_check_acc_handle(ddi_acc_handle_t);
98 147 int ahci_check_dma_handle(ddi_dma_handle_t);
99 148 void ahci_fm_ereport(ahci_ctl_t *, char *);
100 149 static int ahci_check_all_handle(ahci_ctl_t *);
101 150 static int ahci_check_ctl_handle(ahci_ctl_t *);
102 151 static int ahci_check_port_handle(ahci_ctl_t *, int);
103 152 static int ahci_check_slot_handle(ahci_port_t *, int);
104 153
105 154 /*
106 155 * Local function prototypes
107 156 */
108 157 static int ahci_setup_port_base_addresses(ahci_ctl_t *, ahci_port_t *);
109 158 static int ahci_alloc_ports_state(ahci_ctl_t *);
110 159 static void ahci_dealloc_ports_state(ahci_ctl_t *);
111 160 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t);
112 161 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t);
113 162 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *);
114 163 static void ahci_dealloc_rcvd_fis(ahci_port_t *);
115 164 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *);
116 165 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *);
117 166 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *);
118 167 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *);
119 168 static void ahci_alloc_pmult(ahci_ctl_t *, ahci_port_t *);
120 169 static void ahci_dealloc_pmult(ahci_ctl_t *, ahci_port_t *);
121 170
122 171 static int ahci_initialize_controller(ahci_ctl_t *);
123 172 static void ahci_uninitialize_controller(ahci_ctl_t *);
124 173 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
125 174 static int ahci_config_space_init(ahci_ctl_t *);
126 175 static void ahci_staggered_spin_up(ahci_ctl_t *, uint8_t);
127 176
128 177 static void ahci_drain_ports_taskq(ahci_ctl_t *);
129 178 static int ahci_rdwr_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t *,
130 179 uint8_t);
131 180 static int ahci_read_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t *);
132 181 static int ahci_write_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t);
133 182 static int ahci_update_pmult_pscr(ahci_ctl_t *, ahci_addr_t *,
134 183 sata_device_t *);
135 184 static int ahci_update_pmult_gscr(ahci_ctl_t *, ahci_addr_t *,
136 185 sata_pmult_gscr_t *);
137 186 static int ahci_initialize_pmult(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *,
138 187 sata_device_t *);
139 188 static int ahci_initialize_pmport(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
140 189 static int ahci_probe_pmult(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
141 190 static int ahci_probe_pmport(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *,
142 191 sata_device_t *);
143 192
144 193 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t);
145 194 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t);
146 195 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *,
147 196 ahci_addr_t *);
148 197 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *);
149 198 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *,
150 199 ahci_addr_t *, sata_pkt_t *);
151 200 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *,
152 201 ahci_addr_t *, sata_pkt_t *);
153 202 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *,
154 203 ahci_addr_t *, int);
155 204 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *);
156 205 static void ahci_copy_ncq_err_page(sata_cmd_t *,
157 206 struct sata_ncq_error_recovery_page *);
158 207 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *);
159 208 static void ahci_add_doneq(ahci_port_t *, sata_pkt_t *, int);
160 209 static void ahci_flush_doneq(ahci_port_t *);
161 210
162 211 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
163 212 static int ahci_hba_reset(ahci_ctl_t *);
164 213 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
165 214 static int ahci_pmport_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
166 215 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t);
167 216 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *,
168 217 ahci_addr_t *);
169 218 static int ahci_reset_pmdevice_reject_pkts(ahci_ctl_t *, ahci_port_t *,
170 219 ahci_addr_t *);
171 220 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *,
172 221 ahci_addr_t *);
173 222 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *);
174 223 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *,
175 224 uint8_t);
176 225 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *,
177 226 uint8_t, int, int *);
178 227 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t,
179 228 uint32_t, uint32_t, uint32_t, uint32_t);
180 229 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t);
181 230 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *,
182 231 uint8_t, sata_pkt_t *);
183 232 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *,
184 233 ahci_addr_t *, uint32_t);
185 234 static void ahci_pmult_error_recovery_handler(ahci_ctl_t *, ahci_port_t *,
186 235 uint8_t, uint32_t);
187 236 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *,
188 237 uint8_t, uint32_t);
189 238 static void ahci_events_handler(void *);
190 239 static void ahci_watchdog_handler(ahci_ctl_t *);
191 240
192 241 static uint_t ahci_intr(caddr_t, caddr_t);
193 242 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t);
194 243 static int ahci_add_intrs(ahci_ctl_t *, int);
195 244 static void ahci_rem_intrs(ahci_ctl_t *);
196 245 static void ahci_enable_all_intrs(ahci_ctl_t *);
197 246 static void ahci_disable_all_intrs(ahci_ctl_t *);
198 247 static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t);
199 248 static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t);
200 249
201 250 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t);
202 251 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t);
203 252 static int ahci_intr_ncq_events(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
204 253 static int ahci_intr_pmult_sntf_events(ahci_ctl_t *, ahci_port_t *, uint8_t);
205 254 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t);
206 255 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *,
207 256 ahci_port_t *, uint8_t);
208 257 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t);
209 258 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *,
210 259 uint8_t, uint32_t);
211 260 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *,
212 261 uint8_t, uint32_t);
213 262 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t);
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214 263
215 264 static void ahci_get_ahci_addr(ahci_ctl_t *, sata_device_t *, ahci_addr_t *);
216 265 static int ahci_get_num_implemented_ports(uint32_t);
217 266 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t, uint32_t);
218 267 static void ahci_dump_commands(ahci_ctl_t *, uint8_t, uint32_t);
219 268 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int);
220 269 #if AHCI_DEBUG
221 270 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...);
222 271 #endif
223 272
273 +static boolean_t ahci_em_init(ahci_ctl_t *);
274 +static void ahci_em_fini(ahci_ctl_t *);
275 +static void ahci_em_suspend(ahci_ctl_t *);
276 +static void ahci_em_resume(ahci_ctl_t *);
277 +static int ahci_em_ioctl(dev_info_t *, int, intptr_t);
224 278
279 +
225 280 /*
226 281 * DMA attributes for the data buffer
227 282 *
228 283 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
229 284 * does not support 64-bit addressing
230 285 */
231 286 static ddi_dma_attr_t buffer_dma_attr = {
232 287 DMA_ATTR_V0, /* dma_attr_version */
233 288 0x0ull, /* dma_attr_addr_lo: lowest bus address */
234 289 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
235 290 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */
236 291 0x2ull, /* dma_attr_align: word aligned */
237 292 1, /* dma_attr_burstsizes */
238 293 1, /* dma_attr_minxfer */
239 294 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
240 295 0xffffffffull, /* dma_attr_seg */
241 296 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */
242 297 512, /* dma_attr_granular */
243 298 0, /* dma_attr_flags */
244 299 };
245 300
246 301 /*
247 302 * DMA attributes for the rcvd FIS
248 303 *
249 304 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
250 305 * does not support 64-bit addressing
251 306 */
252 307 static ddi_dma_attr_t rcvd_fis_dma_attr = {
253 308 DMA_ATTR_V0, /* dma_attr_version */
254 309 0x0ull, /* dma_attr_addr_lo: lowest bus address */
255 310 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
256 311 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
257 312 0x100ull, /* dma_attr_align: 256-byte aligned */
258 313 1, /* dma_attr_burstsizes */
259 314 1, /* dma_attr_minxfer */
260 315 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
261 316 0xffffffffull, /* dma_attr_seg */
262 317 1, /* dma_attr_sgllen */
263 318 1, /* dma_attr_granular */
264 319 0, /* dma_attr_flags */
265 320 };
266 321
267 322 /*
268 323 * DMA attributes for the command list
269 324 *
270 325 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
271 326 * does not support 64-bit addressing
272 327 */
273 328 static ddi_dma_attr_t cmd_list_dma_attr = {
274 329 DMA_ATTR_V0, /* dma_attr_version */
275 330 0x0ull, /* dma_attr_addr_lo: lowest bus address */
276 331 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
277 332 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
278 333 0x400ull, /* dma_attr_align: 1K-byte aligned */
279 334 1, /* dma_attr_burstsizes */
280 335 1, /* dma_attr_minxfer */
281 336 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
282 337 0xffffffffull, /* dma_attr_seg */
283 338 1, /* dma_attr_sgllen */
284 339 1, /* dma_attr_granular */
285 340 0, /* dma_attr_flags */
286 341 };
287 342
288 343 /*
289 344 * DMA attributes for cmd tables
290 345 *
291 346 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
292 347 * does not support 64-bit addressing
293 348 */
294 349 static ddi_dma_attr_t cmd_table_dma_attr = {
295 350 DMA_ATTR_V0, /* dma_attr_version */
296 351 0x0ull, /* dma_attr_addr_lo: lowest bus address */
297 352 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
298 353 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
299 354 0x80ull, /* dma_attr_align: 128-byte aligned */
300 355 1, /* dma_attr_burstsizes */
301 356 1, /* dma_attr_minxfer */
302 357 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
303 358 0xffffffffull, /* dma_attr_seg */
304 359 1, /* dma_attr_sgllen */
305 360 1, /* dma_attr_granular */
306 361 0, /* dma_attr_flags */
307 362 };
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308 363
309 364
310 365 /* Device access attributes */
311 366 static ddi_device_acc_attr_t accattr = {
312 367 DDI_DEVICE_ATTR_V1,
313 368 DDI_STRUCTURE_LE_ACC,
314 369 DDI_STRICTORDER_ACC,
315 370 DDI_DEFAULT_ACC
316 371 };
317 372
318 -
319 373 static struct dev_ops ahcictl_dev_ops = {
320 374 DEVO_REV, /* devo_rev */
321 375 0, /* refcnt */
322 376 ahci_getinfo, /* info */
323 377 nulldev, /* identify */
324 378 nulldev, /* probe */
325 379 ahci_attach, /* attach */
326 380 ahci_detach, /* detach */
327 381 nodev, /* no reset */
328 - (struct cb_ops *)0, /* driver operations */
382 + NULL, /* driver operations */
329 383 NULL, /* bus operations */
330 384 NULL, /* power */
331 385 ahci_quiesce, /* quiesce */
332 386 };
333 387
334 388 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = {
335 389 SATA_TRAN_HOTPLUG_OPS_REV_1,
336 390 ahci_tran_hotplug_port_activate,
337 391 ahci_tran_hotplug_port_deactivate
338 392 };
339 393
340 394 extern struct mod_ops mod_driverops;
341 395
342 396 static struct modldrv modldrv = {
343 397 &mod_driverops, /* driverops */
344 398 ahci_ident, /* short description */
345 399 &ahcictl_dev_ops, /* driver ops */
346 400 };
347 401
348 402 static struct modlinkage modlinkage = {
349 403 MODREV_1,
350 404 &modldrv,
351 405 NULL
352 406 };
353 407
354 408 /* The following variables are watchdog handler related */
355 409 static clock_t ahci_watchdog_timeout = 5; /* 5 seconds */
356 410 static clock_t ahci_watchdog_tick;
357 411
358 412 /*
359 413 * This static variable indicates the size of command table,
360 414 * and it's changeable with prdt number, which ahci_dma_prdt_number
361 415 * indicates.
362 416 */
363 417 static size_t ahci_cmd_table_size;
364 418
365 419 /*
366 420 * The below global variables are tunable via /etc/system
367 421 *
368 422 * ahci_dma_prdt_number
369 423 * ahci_msi_enabled
370 424 * ahci_buf_64bit_dma
371 425 * ahci_commu_64bit_dma
372 426 */
373 427
374 428 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */
375 429 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER;
376 430
377 431 /* AHCI MSI is tunable */
378 432 boolean_t ahci_msi_enabled = B_TRUE;
379 433
380 434 /*
381 435 * 64-bit dma addressing for data buffer is tunable
382 436 *
383 437 * The variable controls only the below value:
384 438 * DBAU (upper 32-bits physical address of data block)
385 439 */
386 440 boolean_t ahci_buf_64bit_dma = B_TRUE;
387 441
388 442 /*
389 443 * 64-bit dma addressing for communication system descriptors is tunable
390 444 *
391 445 * The variable controls the below three values:
392 446 *
393 447 * PxCLBU (upper 32-bits for the command list base physical address)
394 448 * PxFBU (upper 32-bits for the received FIS base physical address)
395 449 * CTBAU (upper 32-bits of command table base)
396 450 */
397 451 boolean_t ahci_commu_64bit_dma = B_TRUE;
398 452
399 453 /*
400 454 * By default, 64-bit dma for data buffer will be disabled for AMD/ATI SB600
401 455 * chipset. If the users want to have a try with 64-bit dma, please change
402 456 * the below variable value to enable it.
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403 457 */
404 458 boolean_t sb600_buf_64bit_dma_disable = B_TRUE;
405 459
406 460 /*
407 461 * By default, 64-bit dma for command buffer will be disabled for AMD/ATI
408 462 * SB600/700/710/750/800. If the users want to have a try with 64-bit dma,
409 463 * please change the below value to enable it.
410 464 */
411 465 boolean_t sbxxx_commu_64bit_dma_disable = B_TRUE;
412 466
467 +/*
468 + * These values control the default delay and default number of times to wait
469 + * for an enclosure message to complete.
470 + */
471 +uint_t ahci_em_reset_delay_ms = 1;
472 +uint_t ahci_em_reset_delay_count = 1000;
473 +uint_t ahci_em_tx_delay_ms = 1;
474 +uint_t ahci_em_tx_delay_count = 1000;
413 475
476 +
414 477 /*
415 478 * End of global tunable variable definition
416 479 */
417 480
418 481 #if AHCI_DEBUG
419 482 uint32_t ahci_debug_flags = 0;
420 483 #else
421 484 uint32_t ahci_debug_flags = (AHCIDBG_ERRS|AHCIDBG_TIMEOUT);
422 485 #endif
423 486
424 487
425 488 #if AHCI_DEBUG
426 489 /* The following is needed for ahci_log() */
427 490 static kmutex_t ahci_log_mutex;
428 491 static char ahci_log_buf[512];
429 492 #endif
430 493
431 494 /* Opaque state pointer initialized by ddi_soft_state_init() */
432 495 static void *ahci_statep = NULL;
433 496
434 497 /*
435 498 * ahci module initialization.
436 499 */
437 500 int
438 501 _init(void)
439 502 {
440 503 int ret;
441 504
442 505 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0);
443 506 if (ret != 0) {
444 507 goto err_out;
445 508 }
446 509
447 510 #if AHCI_DEBUG
448 511 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL);
449 512 #endif
450 513
451 514 if ((ret = sata_hba_init(&modlinkage)) != 0) {
452 515 #if AHCI_DEBUG
453 516 mutex_destroy(&ahci_log_mutex);
454 517 #endif
455 518 ddi_soft_state_fini(&ahci_statep);
456 519 goto err_out;
457 520 }
458 521
459 522 /* watchdog tick */
460 523 ahci_watchdog_tick = drv_usectohz(
461 524 (clock_t)ahci_watchdog_timeout * 1000000);
462 525
463 526 ret = mod_install(&modlinkage);
464 527 if (ret != 0) {
465 528 sata_hba_fini(&modlinkage);
466 529 #if AHCI_DEBUG
467 530 mutex_destroy(&ahci_log_mutex);
468 531 #endif
469 532 ddi_soft_state_fini(&ahci_statep);
470 533 goto err_out;
471 534 }
472 535
473 536 return (ret);
474 537
475 538 err_out:
476 539 cmn_err(CE_WARN, "!ahci: Module init failed");
477 540 return (ret);
478 541 }
479 542
480 543 /*
481 544 * ahci module uninitialize.
482 545 */
483 546 int
484 547 _fini(void)
485 548 {
486 549 int ret;
487 550
488 551 ret = mod_remove(&modlinkage);
489 552 if (ret != 0) {
490 553 return (ret);
491 554 }
492 555
493 556 /* Remove the resources allocated in _init(). */
494 557 sata_hba_fini(&modlinkage);
495 558 #if AHCI_DEBUG
496 559 mutex_destroy(&ahci_log_mutex);
497 560 #endif
498 561 ddi_soft_state_fini(&ahci_statep);
499 562
500 563 return (ret);
501 564 }
502 565
503 566 /*
504 567 * _info entry point
505 568 */
506 569 int
507 570 _info(struct modinfo *modinfop)
508 571 {
509 572 return (mod_info(&modlinkage, modinfop));
510 573 }
511 574
512 575 /*
513 576 * The attach entry point for dev_ops.
514 577 */
515 578 static int
516 579 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
517 580 {
518 581 ahci_ctl_t *ahci_ctlp = NULL;
519 582 int instance = ddi_get_instance(dip);
520 583 int status;
521 584 int attach_state;
522 585 uint32_t cap_status, ahci_version;
523 586 uint32_t ghc_control;
524 587 int intr_types;
525 588 int i;
526 589 pci_regspec_t *regs;
527 590 int regs_length;
528 591 int rnumber;
529 592 #if AHCI_DEBUG
530 593 int speed;
531 594 #endif
532 595
533 596 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "ahci_attach enter",
534 597 NULL);
535 598
536 599 switch (cmd) {
537 600 case DDI_ATTACH:
538 601 break;
539 602
540 603 case DDI_RESUME:
541 604
542 605 /*
543 606 * During DDI_RESUME, the hardware state of the device
544 607 * (power may have been removed from the device) must be
545 608 * restored, allow pending requests to continue, and
546 609 * service new requests.
547 610 */
548 611 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
549 612 mutex_enter(&ahci_ctlp->ahcictl_mutex);
550 613
551 614 /*
552 615 * GHC.AE must be set to 1 before any other AHCI register
553 616 * is accessed
554 617 */
555 618 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
556 619 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
557 620 ghc_control |= AHCI_HBA_GHC_AE;
558 621 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
559 622 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
560 623
561 624 /* Restart watch thread */
562 625 if (ahci_ctlp->ahcictl_timeout_id == 0)
563 626 ahci_ctlp->ahcictl_timeout_id = timeout(
564 627 (void (*)(void *))ahci_watchdog_handler,
565 628 (caddr_t)ahci_ctlp, ahci_watchdog_tick);
566 629
567 630 mutex_exit(&ahci_ctlp->ahcictl_mutex);
568 631
569 632 /*
570 633 * Re-initialize the controller and enable the interrupts and
571 634 * restart all the ports.
572 635 *
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573 636 * Note that so far we don't support hot-plug during
574 637 * suspend/resume.
575 638 */
576 639 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) {
577 640 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp,
578 641 "Failed to initialize the controller "
579 642 "during DDI_RESUME", NULL);
580 643 return (DDI_FAILURE);
581 644 }
582 645
646 + /*
647 + * Reset the enclosure services.
648 + */
649 + ahci_em_resume(ahci_ctlp);
650 +
583 651 mutex_enter(&ahci_ctlp->ahcictl_mutex);
584 652 ahci_ctlp->ahcictl_flags &= ~AHCI_SUSPEND;
585 653 mutex_exit(&ahci_ctlp->ahcictl_mutex);
586 654
587 655 return (DDI_SUCCESS);
588 656
589 657 default:
590 658 return (DDI_FAILURE);
591 659 }
592 660
593 661 attach_state = AHCI_ATTACH_STATE_NONE;
594 662
595 663 /* Allocate soft state */
596 664 status = ddi_soft_state_zalloc(ahci_statep, instance);
597 665 if (status != DDI_SUCCESS) {
598 666 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state",
599 667 instance);
600 668 goto err_out;
601 669 }
602 670
603 671 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
604 672 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH;
605 673 ahci_ctlp->ahcictl_dip = dip;
606 674
607 675 /* Initialize the cport/port mapping */
608 676 for (i = 0; i < AHCI_MAX_PORTS; i++) {
609 677 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff;
610 678 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff;
611 679 }
612 680
613 681 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC;
614 682
615 683 /* Initialize FMA properties */
616 684 ahci_fm_init(ahci_ctlp);
617 685
618 686 attach_state |= AHCI_ATTACH_STATE_FMA;
619 687
620 688 /*
621 689 * Now map the AHCI base address; which includes global
622 690 * registers and port control registers
623 691 *
624 692 * According to the spec, the AHCI Base Address is BAR5,
625 693 * but BAR0-BAR4 are optional, so we need to check which
626 694 * rnumber is used for BAR5.
627 695 */
628 696
629 697 /*
630 698 * search through DDI "reg" property for the AHCI register set
631 699 */
632 700 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip,
633 701 DDI_PROP_DONTPASS, "reg", (int **)®s,
634 702 (uint_t *)®s_length) != DDI_PROP_SUCCESS) {
635 703 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property",
636 704 instance);
637 705 goto err_out;
638 706 }
639 707
640 708 /* AHCI Base Address is located at 0x24 offset */
641 709 for (rnumber = 0; rnumber < regs_length; ++rnumber) {
642 710 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M)
643 711 == AHCI_PCI_RNUM)
644 712 break;
645 713 }
646 714
647 715 ddi_prop_free(regs);
648 716
649 717 if (rnumber == regs_length) {
650 718 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set",
651 719 instance);
652 720 goto err_out;
653 721 }
654 722
655 723 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber);
656 724
657 725 status = ddi_regs_map_setup(dip,
658 726 rnumber,
659 727 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr,
660 728 0,
661 729 0,
662 730 &accattr,
663 731 &ahci_ctlp->ahcictl_ahci_acc_handle);
664 732 if (status != DDI_SUCCESS) {
665 733 cmn_err(CE_WARN, "!ahci%d: Cannot map register space",
666 734 instance);
667 735 goto err_out;
668 736 }
669 737
670 738 attach_state |= AHCI_ATTACH_STATE_REG_MAP;
671 739
672 740 /*
673 741 * GHC.AE must be set to 1 before any other AHCI register
674 742 * is accessed
675 743 */
676 744 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
677 745 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
678 746 ghc_control |= AHCI_HBA_GHC_AE;
679 747 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
680 748 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
681 749
682 750 /* Get the AHCI version information */
683 751 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
684 752 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp));
685 753
686 754 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance,
687 755 (ahci_version & 0xffff0000) >> 16,
688 756 ((ahci_version & 0x0000ff00) >> 4 |
689 757 (ahci_version & 0x000000ff)));
690 758
691 759 /* We don't support controllers whose versions are lower than 1.0 */
692 760 if (!(ahci_version & 0xffff0000)) {
693 761 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower "
694 762 "than version 1.0", instance);
695 763 goto err_out;
696 764 }
697 765
698 766 /* Get the HBA capabilities information */
699 767 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
700 768 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp));
701 769
702 770 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba capabilities = 0x%x",
703 771 cap_status);
704 772
705 773 /* CAP2 (HBA Capabilities Extended) is available since AHCI spec 1.2 */
706 774 if (ahci_version >= 0x00010200) {
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707 775 uint32_t cap2_status;
708 776
709 777 /* Get the HBA capabilities extended information */
710 778 cap2_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
711 779 (uint32_t *)AHCI_GLOBAL_CAP2(ahci_ctlp));
712 780
713 781 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
714 782 "hba capabilities extended = 0x%x", cap2_status);
715 783 }
716 784
785 + if (cap_status & AHCI_HBA_CAP_EMS) {
786 + ahci_ctlp->ahcictl_cap |= AHCI_CAP_EMS;
787 + ahci_ctlp->ahcictl_em_loc =
788 + ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
789 + (uint32_t *)AHCI_GLOBAL_EM_LOC(ahci_ctlp));
790 + ahci_ctlp->ahcictl_em_ctl =
791 + ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
792 + (uint32_t *)AHCI_GLOBAL_EM_CTL(ahci_ctlp));
793 + }
794 +
717 795 #if AHCI_DEBUG
718 796 /* Get the interface speed supported by the HBA */
719 797 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT;
720 798 if (speed == 0x01) {
721 799 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
722 800 "hba interface speed support: Gen 1 (1.5Gbps)", NULL);
723 801 } else if (speed == 0x10) {
724 802 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
725 803 "hba interface speed support: Gen 2 (3 Gbps)", NULL);
726 804 } else if (speed == 0x11) {
727 805 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
728 806 "hba interface speed support: Gen 3 (6 Gbps)", NULL);
729 807 }
730 808 #endif
731 809
732 810 /* Get the number of command slots supported by the HBA */
733 811 ahci_ctlp->ahcictl_num_cmd_slots =
734 812 ((cap_status & AHCI_HBA_CAP_NCS) >>
735 813 AHCI_HBA_CAP_NCS_SHIFT) + 1;
736 814
737 815 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d",
738 816 ahci_ctlp->ahcictl_num_cmd_slots);
739 817
740 818 /* Get the bit map which indicates ports implemented by the HBA */
741 819 ahci_ctlp->ahcictl_ports_implemented =
742 820 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
743 821 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp));
744 822
745 823 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x",
746 824 ahci_ctlp->ahcictl_ports_implemented);
747 825
748 826 /* Max port number implemented */
749 827 ahci_ctlp->ahcictl_num_ports =
750 828 ddi_fls(ahci_ctlp->ahcictl_ports_implemented);
751 829
752 830 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d",
753 831 (cap_status & AHCI_HBA_CAP_NP) + 1);
754 832
755 833 /* Get the number of implemented ports by the HBA */
756 834 ahci_ctlp->ahcictl_num_implemented_ports =
757 835 ahci_get_num_implemented_ports(
758 836 ahci_ctlp->ahcictl_ports_implemented);
759 837
760 838 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
761 839 "hba number of implemented ports: %d",
762 840 ahci_ctlp->ahcictl_num_implemented_ports);
763 841
764 842 /* Check whether HBA supports 64bit DMA addressing */
765 843 if (!(cap_status & AHCI_HBA_CAP_S64A)) {
766 844 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA;
767 845 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA;
768 846 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
769 847 "hba does not support 64-bit addressing", NULL);
770 848 }
771 849
772 850 /* Checking for the support of Port Multiplier */
773 851 if (cap_status & AHCI_HBA_CAP_SPM) {
774 852 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PMULT_CBSS;
775 853 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
776 854 "hba supports port multiplier (CBSS)", NULL);
777 855
778 856 /* Support FIS-based switching ? */
779 857 if (cap_status & AHCI_HBA_CAP_FBSS) {
780 858 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PMULT_FBSS;
781 859 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
782 860 "hba supports FIS-based switching (FBSS)", NULL);
783 861 }
784 862 }
785 863
786 864 /* Checking for Support Command List Override */
787 865 if (cap_status & AHCI_HBA_CAP_SCLO) {
788 866 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SCLO;
789 867 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
790 868 "hba supports command list override.", NULL);
791 869 }
792 870
793 871 /* Checking for Asynchronous Notification */
794 872 if (cap_status & AHCI_HBA_CAP_SSNTF) {
795 873 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SNTF;
796 874 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
797 875 "hba supports asynchronous notification.", NULL);
798 876 }
799 877
800 878 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle)
801 879 != DDI_SUCCESS) {
802 880 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space",
803 881 instance);
804 882 goto err_out;
805 883 }
806 884
807 885 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP;
808 886
809 887 /*
810 888 * Check the pci configuration space, and set caps. We also
811 889 * handle the hardware defect in this function.
812 890 *
813 891 * For example, force ATI SB600 to use 32-bit dma addressing
814 892 * since it doesn't support 64-bit dma though its CAP register
815 893 * declares it support.
816 894 */
817 895 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) {
818 896 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed",
819 897 instance);
820 898 goto err_out;
821 899 }
822 900
823 901 /*
824 902 * Disable the whole controller interrupts before adding
825 903 * interrupt handlers(s).
826 904 */
827 905 ahci_disable_all_intrs(ahci_ctlp);
828 906
829 907 /* Get supported interrupt types */
830 908 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
831 909 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed",
832 910 instance);
833 911 goto err_out;
834 912 }
835 913
836 914 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
837 915 "ddi_intr_get_supported_types() returned: 0x%x",
838 916 intr_types);
839 917
840 918 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) {
841 919 /*
842 920 * Try MSI first, but fall back to FIXED if failed
843 921 */
844 922 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_MSI) ==
845 923 DDI_SUCCESS) {
846 924 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI;
847 925 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
848 926 "Using MSI interrupt type", NULL);
849 927 goto intr_done;
850 928 }
851 929
852 930 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
853 931 "MSI registration failed, "
854 932 "trying FIXED interrupts", NULL);
855 933 }
856 934
857 935 if (intr_types & DDI_INTR_TYPE_FIXED) {
858 936 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_FIXED) ==
859 937 DDI_SUCCESS) {
860 938 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED;
861 939 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
862 940 "Using FIXED interrupt type", NULL);
863 941 goto intr_done;
864 942 }
865 943
866 944 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
867 945 "FIXED interrupt registration failed", NULL);
868 946 }
869 947
870 948 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance);
871 949
872 950 goto err_out;
873 951
874 952 intr_done:
875 953
876 954 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED;
877 955
878 956 /* Initialize the controller mutex */
879 957 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER,
880 958 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri);
881 959
882 960 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT;
883 961
884 962 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) {
885 963 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER;
886 964 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) {
887 965 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER;
888 966 }
889 967
890 968 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) +
891 969 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) *
892 970 sizeof (ahci_prdt_item_t));
893 971
894 972 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
895 973 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x,"
896 974 " ahci_cmd_table_size is 0x%x",
897 975 ahci_dma_prdt_number, ahci_cmd_table_size);
898 976
899 977 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER)
900 978 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen =
901 979 ahci_dma_prdt_number;
902 980
903 981 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr;
904 982 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr;
905 983 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr;
906 984 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr;
907 985
908 986 /*
909 987 * enable 64bit dma for data buffer for SB600 if
910 988 * sb600_buf_64bit_dma_disable is B_FALSE
911 989 */
912 990 if ((ahci_buf_64bit_dma == B_FALSE) ||
913 991 ((ahci_ctlp->ahcictl_cap & AHCI_CAP_BUF_32BIT_DMA) &&
914 992 !(sb600_buf_64bit_dma_disable == B_FALSE &&
915 993 ahci_ctlp->ahcictl_venid == 0x1002 &&
916 994 ahci_ctlp->ahcictl_devid == 0x4380))) {
917 995 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi =
918 996 0xffffffffull;
919 997 }
920 998
921 999 /*
922 1000 * enable 64bit dma for command buffer for SB600/700/710/800
923 1001 * if sbxxx_commu_64bit_dma_disable is B_FALSE
924 1002 */
925 1003 if ((ahci_commu_64bit_dma == B_FALSE) ||
926 1004 ((ahci_ctlp->ahcictl_cap & AHCI_CAP_COMMU_32BIT_DMA) &&
927 1005 !(sbxxx_commu_64bit_dma_disable == B_FALSE &&
928 1006 ahci_ctlp->ahcictl_venid == 0x1002 &&
929 1007 (ahci_ctlp->ahcictl_devid == 0x4380 ||
930 1008 ahci_ctlp->ahcictl_devid == 0x4391)))) {
931 1009 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi =
932 1010 0xffffffffull;
933 1011 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi =
934 1012 0xffffffffull;
935 1013 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi =
936 1014 0xffffffffull;
937 1015 }
938 1016
939 1017 /* Allocate the ports structure */
940 1018 status = ahci_alloc_ports_state(ahci_ctlp);
941 1019 if (status != AHCI_SUCCESS) {
942 1020 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure",
943 1021 instance);
944 1022 goto err_out;
945 1023 }
946 1024
947 1025 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC;
948 1026
949 1027 /*
950 1028 * Initialize the controller and ports.
951 1029 */
952 1030 status = ahci_initialize_controller(ahci_ctlp);
953 1031 if (status != AHCI_SUCCESS) {
954 1032 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed",
955 1033 instance);
956 1034 goto err_out;
957 1035 }
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958 1036
959 1037 attach_state |= AHCI_ATTACH_STATE_HW_INIT;
960 1038
961 1039 /* Start one thread to check packet timeouts */
962 1040 ahci_ctlp->ahcictl_timeout_id = timeout(
963 1041 (void (*)(void *))ahci_watchdog_handler,
964 1042 (caddr_t)ahci_ctlp, ahci_watchdog_tick);
965 1043
966 1044 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED;
967 1045
1046 + if (!ahci_em_init(ahci_ctlp)) {
1047 + cmn_err(CE_WARN, "!ahci%d: failed to initialize enclosure "
1048 + "services", instance);
1049 + goto err_out;
1050 + }
1051 + attach_state |= AHCI_ATTACH_STATE_ENCLOSURE;
1052 +
968 1053 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) {
969 1054 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed",
970 1055 instance);
971 1056 goto err_out;
972 1057 }
973 1058
974 1059 /* Check all handles at the end of the attach operation. */
975 1060 if (ahci_check_all_handle(ahci_ctlp) != DDI_SUCCESS) {
976 1061 cmn_err(CE_WARN, "!ahci%d: invalid dma/acc handles",
977 1062 instance);
978 1063 goto err_out;
979 1064 }
980 1065
981 1066 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH;
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982 1067
983 1068 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!", NULL);
984 1069
985 1070 return (DDI_SUCCESS);
986 1071
987 1072 err_out:
988 1073 /* FMA message */
989 1074 ahci_fm_ereport(ahci_ctlp, DDI_FM_DEVICE_NO_RESPONSE);
990 1075 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip, DDI_SERVICE_LOST);
991 1076
1077 + if (attach_state & AHCI_ATTACH_STATE_ENCLOSURE) {
1078 + ahci_em_fini(ahci_ctlp);
1079 + }
1080 +
992 1081 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) {
993 1082 mutex_enter(&ahci_ctlp->ahcictl_mutex);
994 1083 (void) untimeout(ahci_ctlp->ahcictl_timeout_id);
995 1084 ahci_ctlp->ahcictl_timeout_id = 0;
996 1085 mutex_exit(&ahci_ctlp->ahcictl_mutex);
997 1086 }
998 1087
999 1088 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) {
1000 1089 ahci_uninitialize_controller(ahci_ctlp);
1001 1090 }
1002 1091
1003 1092 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) {
1004 1093 ahci_dealloc_ports_state(ahci_ctlp);
1005 1094 }
1006 1095
1007 1096 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) {
1008 1097 mutex_destroy(&ahci_ctlp->ahcictl_mutex);
1009 1098 }
1010 1099
1011 1100 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) {
1012 1101 ahci_rem_intrs(ahci_ctlp);
1013 1102 }
1014 1103
1015 1104 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) {
1016 1105 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle);
1017 1106 }
1018 1107
1019 1108 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) {
1020 1109 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle);
1021 1110 }
1022 1111
1023 1112 if (attach_state & AHCI_ATTACH_STATE_FMA) {
1024 1113 ahci_fm_fini(ahci_ctlp);
1025 1114 }
1026 1115
1027 1116 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) {
1028 1117 ddi_soft_state_free(ahci_statep, instance);
1029 1118 }
1030 1119
1031 1120 return (DDI_FAILURE);
1032 1121 }
1033 1122
1034 1123 /*
1035 1124 * The detach entry point for dev_ops.
1036 1125 */
1037 1126 static int
1038 1127 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1039 1128 {
1040 1129 ahci_ctl_t *ahci_ctlp;
1041 1130 int instance;
1042 1131 int ret;
1043 1132
1044 1133 instance = ddi_get_instance(dip);
1045 1134 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
1046 1135
1047 1136 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter", NULL);
1048 1137
1049 1138 switch (cmd) {
1050 1139 case DDI_DETACH:
1051 1140
1052 1141 /* disable the interrupts for an uninterrupted detach */
1053 1142 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1054 1143 ahci_disable_all_intrs(ahci_ctlp);
1055 1144 mutex_exit(&ahci_ctlp->ahcictl_mutex);
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1056 1145
1057 1146 /* unregister from the sata framework. */
1058 1147 ret = ahci_unregister_sata_hba_tran(ahci_ctlp);
1059 1148 if (ret != AHCI_SUCCESS) {
1060 1149 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1061 1150 ahci_enable_all_intrs(ahci_ctlp);
1062 1151 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1063 1152 return (DDI_FAILURE);
1064 1153 }
1065 1154
1155 + ahci_em_fini(ahci_ctlp);
1156 +
1066 1157 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1067 1158
1068 1159 /* stop the watchdog handler */
1069 1160 (void) untimeout(ahci_ctlp->ahcictl_timeout_id);
1070 1161 ahci_ctlp->ahcictl_timeout_id = 0;
1071 1162
1072 1163 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1073 1164
1074 1165 /* uninitialize the controller */
1075 1166 ahci_uninitialize_controller(ahci_ctlp);
1076 1167
1077 1168 /* remove the interrupts */
1078 1169 ahci_rem_intrs(ahci_ctlp);
1079 1170
1080 1171 /* deallocate the ports structures */
1081 1172 ahci_dealloc_ports_state(ahci_ctlp);
1082 1173
1083 1174 /* destroy mutex */
1084 1175 mutex_destroy(&ahci_ctlp->ahcictl_mutex);
1085 1176
1086 1177 /* teardown the pci config */
1087 1178 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle);
1088 1179
1089 1180 /* remove the reg maps. */
1090 1181 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle);
1091 1182
1092 1183 /* release fma resource */
1093 1184 ahci_fm_fini(ahci_ctlp);
1094 1185
1095 1186 /* free the soft state. */
1096 1187 ddi_soft_state_free(ahci_statep, instance);
1097 1188
1098 1189 return (DDI_SUCCESS);
1099 1190
1100 1191 case DDI_SUSPEND:
1101 1192
1102 1193 /*
1103 1194 * The steps associated with suspension must include putting
1104 1195 * the underlying device into a quiescent state so that it
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1105 1196 * will not generate interrupts or modify or access memory.
1106 1197 */
1107 1198 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1108 1199 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) {
1109 1200 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1110 1201 return (DDI_SUCCESS);
1111 1202 }
1112 1203
1113 1204 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND;
1114 1205
1206 + ahci_em_suspend(ahci_ctlp);
1207 +
1115 1208 /* stop the watchdog handler */
1116 1209 if (ahci_ctlp->ahcictl_timeout_id) {
1117 1210 (void) untimeout(ahci_ctlp->ahcictl_timeout_id);
1118 1211 ahci_ctlp->ahcictl_timeout_id = 0;
1119 1212 }
1120 1213
1121 1214 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1122 1215
1123 1216 /*
1124 1217 * drain the taskq
1125 1218 */
1126 1219 ahci_drain_ports_taskq(ahci_ctlp);
1127 1220
1128 1221 /*
1129 1222 * Disable the interrupts and stop all the ports.
1130 1223 */
1131 1224 ahci_uninitialize_controller(ahci_ctlp);
1132 1225
1133 1226 return (DDI_SUCCESS);
1134 1227
1135 1228 default:
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1136 1229 return (DDI_FAILURE);
1137 1230 }
1138 1231 }
1139 1232
1140 1233 /*
1141 1234 * The info entry point for dev_ops.
1142 1235 *
1143 1236 */
1144 1237 static int
1145 1238 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd,
1146 - void *arg, void **result)
1239 + void *arg, void **result)
1147 1240 {
1148 1241 #ifndef __lock_lint
1149 1242 _NOTE(ARGUNUSED(dip))
1150 1243 #endif /* __lock_lint */
1151 1244
1152 1245 ahci_ctl_t *ahci_ctlp;
1153 1246 int instance;
1154 1247 dev_t dev;
1155 1248
1156 1249 dev = (dev_t)arg;
1157 1250 instance = getminor(dev);
1158 1251
1159 1252 switch (infocmd) {
1160 1253 case DDI_INFO_DEVT2DEVINFO:
1161 1254 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
1162 1255 if (ahci_ctlp != NULL) {
1163 1256 *result = ahci_ctlp->ahcictl_dip;
1164 1257 return (DDI_SUCCESS);
1165 1258 } else {
1166 1259 *result = NULL;
1167 1260 return (DDI_FAILURE);
1168 1261 }
1169 1262 case DDI_INFO_DEVT2INSTANCE:
1170 1263 *(int *)result = instance;
1171 1264 break;
1172 1265 default:
1173 1266 break;
1174 1267 }
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1175 1268
1176 1269 return (DDI_SUCCESS);
1177 1270 }
1178 1271
1179 1272 /*
1180 1273 * Registers the ahci with sata framework.
1181 1274 */
1182 1275 static int
1183 1276 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status)
1184 1277 {
1185 - struct sata_hba_tran *sata_hba_tran;
1278 + struct sata_hba_tran *sata_hba_tran;
1186 1279
1187 1280 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
1188 1281 "ahci_register_sata_hba_tran enter", NULL);
1189 1282
1190 1283 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1191 1284
1192 1285 /* Allocate memory for the sata_hba_tran */
1193 1286 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP);
1194 1287
1195 1288 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV;
1196 1289 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip;
1197 1290 sata_hba_tran->sata_tran_hba_dma_attr =
1198 1291 &ahci_ctlp->ahcictl_buffer_dma_attr;
1199 1292
1200 1293 /* Report the number of implemented ports */
1201 1294 sata_hba_tran->sata_tran_hba_num_cports =
1202 1295 ahci_ctlp->ahcictl_num_implemented_ports;
1203 1296
1204 1297 /* Support ATAPI device */
1205 1298 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI;
1206 1299
1207 1300 /* Get the data transfer capability for PIO command by the HBA */
1208 1301 if (cap_status & AHCI_HBA_CAP_PMD) {
1209 1302 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ;
1210 1303 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple "
1211 1304 "DRQ block data transfer for PIO command protocol", NULL);
1212 1305 }
1213 1306
1214 1307 /*
1215 1308 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set
1216 1309 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE
1217 1310 * QUEUED (EXT), and SERVICE commands). Queued operations are
1218 1311 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA
1219 1312 * QUEUED commands when the HBA and device support native command
1220 1313 * queuing(NCQ).
1221 1314 *
1222 1315 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the
1223 1316 * CAP register of the HBA indicates NCQ is supported.
1224 1317 *
1225 1318 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is
1226 1319 * set because the previous register content of PxCI can be re-written
1227 1320 * in the register write.
1228 1321 */
1229 1322 if ((cap_status & AHCI_HBA_CAP_SNCQ) &&
1230 1323 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) {
1231 1324 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ;
1232 1325 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ;
1233 1326 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native "
1234 1327 "Command Queuing", NULL);
1235 1328 }
1236 1329
1237 1330 /* Support port multiplier? */
1238 1331 if (cap_status & AHCI_HBA_CAP_SPM) {
1239 1332 sata_hba_tran->sata_tran_hba_features_support |=
1240 1333 SATA_CTLF_PORT_MULTIPLIER;
1241 1334
1242 1335 /* Support FIS-based switching for port multiplier? */
1243 1336 if (cap_status & AHCI_HBA_CAP_FBSS) {
1244 1337 sata_hba_tran->sata_tran_hba_features_support |=
1245 1338 SATA_CTLF_PMULT_FBS;
1246 1339 }
1247 1340 }
1248 1341
1249 1342 /* Report the number of command slots */
1250 1343 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots;
1251 1344
1252 1345 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port;
1253 1346 sata_hba_tran->sata_tran_start = ahci_tran_start;
1254 1347 sata_hba_tran->sata_tran_abort = ahci_tran_abort;
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1255 1348 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport;
1256 1349 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops;
1257 1350 #ifdef __lock_lint
1258 1351 sata_hba_tran->sata_tran_selftest = ahci_selftest;
1259 1352 #endif
1260 1353 /*
1261 1354 * When SATA framework adds support for pwrmgt the
1262 1355 * pwrmgt_ops needs to be updated
1263 1356 */
1264 1357 sata_hba_tran->sata_tran_pwrmgt_ops = NULL;
1265 - sata_hba_tran->sata_tran_ioctl = NULL;
1358 + sata_hba_tran->sata_tran_ioctl = ahci_em_ioctl;
1266 1359
1267 1360 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran;
1268 1361
1269 1362 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1270 1363
1271 1364 /* Attach it to SATA framework */
1272 1365 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH)
1273 1366 != DDI_SUCCESS) {
1274 1367 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t));
1275 1368 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1276 1369 ahci_ctlp->ahcictl_sata_hba_tran = NULL;
1277 1370 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1278 1371 return (AHCI_FAILURE);
1279 1372 }
1280 1373
1281 1374 return (AHCI_SUCCESS);
1282 1375 }
1283 1376
1284 1377 /*
1285 1378 * Unregisters the ahci with sata framework.
1286 1379 */
1287 1380 static int
1288 1381 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp)
1289 1382 {
1290 1383 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
1291 1384 "ahci_unregister_sata_hba_tran enter", NULL);
1292 1385
1293 1386 /* Detach from the SATA framework. */
1294 1387 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) !=
1295 1388 DDI_SUCCESS) {
1296 1389 return (AHCI_FAILURE);
1297 1390 }
1298 1391
1299 1392 /* Deallocate sata_hba_tran. */
1300 1393 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran,
1301 1394 sizeof (sata_hba_tran_t));
1302 1395
1303 1396 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1304 1397 ahci_ctlp->ahcictl_sata_hba_tran = NULL;
1305 1398 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1306 1399
1307 1400 return (AHCI_SUCCESS);
1308 1401 }
1309 1402
1310 1403 #define SET_PORTSTR(str, addrp) \
1311 1404 if (AHCI_ADDR_IS_PORT(addrp)) \
1312 1405 (void) sprintf((str), "%d", (addrp)->aa_port); \
1313 1406 else if (AHCI_ADDR_IS_PMULT(addrp)) \
1314 1407 (void) sprintf((str), "%d (pmult)", (addrp)->aa_port); \
1315 1408 else \
1316 1409 (void) sprintf((str), "%d:%d", (addrp)->aa_port, \
1317 1410 (addrp)->aa_pmport);
1318 1411
1319 1412 /*
1320 1413 * ahci_tran_probe_port is called by SATA framework. It returns port state,
1321 1414 * port status registers and an attached device type via sata_device
1322 1415 * structure.
1323 1416 *
1324 1417 * We return the cached information from a previous hardware probe. The
1325 1418 * actual hardware probing itself was done either from within
1326 1419 * ahci_initialize_controller() during the driver attach or from a phy
1327 1420 * ready change interrupt handler.
1328 1421 */
1329 1422 static int
1330 1423 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd)
1331 1424 {
1332 1425 ahci_ctl_t *ahci_ctlp;
1333 1426 ahci_port_t *ahci_portp;
1334 1427 ahci_addr_t addr, pmult_addr;
1335 1428 uint8_t cport = sd->satadev_addr.cport;
1336 1429 char portstr[10];
1337 1430 uint8_t device_type;
1338 1431 uint32_t port_state;
1339 1432 uint8_t port;
1340 1433 int rval = SATA_SUCCESS, rval_init;
1341 1434
1342 1435 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip));
1343 1436 port = ahci_ctlp->ahcictl_cport_to_port[cport];
1344 1437
1345 1438 ahci_portp = ahci_ctlp->ahcictl_ports[port];
1346 1439
1347 1440 mutex_enter(&ahci_portp->ahciport_mutex);
1348 1441
1349 1442 ahci_get_ahci_addr(ahci_ctlp, sd, &addr);
1350 1443 ASSERT(AHCI_ADDR_IS_VALID(&addr));
1351 1444 SET_PORTSTR(portstr, &addr);
1352 1445
1353 1446 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
1354 1447 "ahci_tran_probe_port enter: port %s", portstr);
1355 1448
1356 1449 if ((AHCI_ADDR_IS_PMULT(&addr) || AHCI_ADDR_IS_PMPORT(&addr)) &&
1357 1450 (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT ||
1358 1451 ahci_portp->ahciport_pmult_info == NULL)) {
1359 1452 /* port mutliplier is removed. */
1360 1453 AHCIDBG(AHCIDBG_PMULT, ahci_ctlp,
1361 1454 "ahci_tran_probe_port: "
1362 1455 "pmult is removed from port %s", portstr);
1363 1456 mutex_exit(&ahci_portp->ahciport_mutex);
1364 1457 return (SATA_FAILURE);
1365 1458 }
1366 1459
1367 1460 /*
1368 1461 * The sata_device may refer to
1369 1462 * 1. A controller port.
1370 1463 * A controller port should be ready here.
1371 1464 * 2. A port multiplier.
1372 1465 * SATA_ADDR_PMULT_SPEC - if it is not initialized yet, initialize
1373 1466 * it and register the port multiplier to the framework.
1374 1467 * SATA_ADDR_PMULT - check the status of all its device ports.
1375 1468 * 3. A port multiplier port.
1376 1469 * If it has not been initialized, initialized it.
1377 1470 *
1378 1471 * A port multiplier or a port multiplier port may require some
1379 1472 * initialization because we cannot do these time-consuming jobs in an
1380 1473 * interrupt context.
1381 1474 */
1382 1475 if (sd->satadev_addr.qual & SATA_ADDR_PMULT_SPEC) {
1383 1476 AHCI_ADDR_SET_PMULT(&pmult_addr, port);
1384 1477 /* Initialize registers on a port multiplier */
1385 1478 rval_init = ahci_initialize_pmult(ahci_ctlp,
1386 1479 ahci_portp, &pmult_addr, sd);
1387 1480 if (rval_init != AHCI_SUCCESS) {
1388 1481 AHCIDBG(AHCIDBG_PMULT, ahci_ctlp,
1389 1482 "ahci_tran_probe_port: "
1390 1483 "pmult initialization failed.", NULL);
1391 1484 mutex_exit(&ahci_portp->ahciport_mutex);
1392 1485 return (SATA_FAILURE);
1393 1486 }
1394 1487 } else if (sd->satadev_addr.qual & SATA_ADDR_PMULT) {
1395 1488 /* Check pmports hotplug events */
1396 1489 (void) ahci_probe_pmult(ahci_ctlp, ahci_portp, &addr);
1397 1490 } else if (sd->satadev_addr.qual & (SATA_ADDR_PMPORT |
1398 1491 SATA_ADDR_DPMPORT)) {
1399 1492 if (ahci_probe_pmport(ahci_ctlp, ahci_portp,
1400 1493 &addr, sd) != AHCI_SUCCESS) {
1401 1494 rval = SATA_FAILURE;
1402 1495 goto out;
1403 1496 }
1404 1497 }
1405 1498
1406 1499 /* Update port state and device type */
1407 1500 port_state = AHCIPORT_GET_STATE(ahci_portp, &addr);
1408 1501
1409 1502 switch (port_state) {
1410 1503
1411 1504 case SATA_PSTATE_FAILED:
1412 1505 sd->satadev_state = SATA_PSTATE_FAILED;
1413 1506 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1414 1507 "ahci_tran_probe_port: port %s PORT FAILED", portstr);
1415 1508 goto out;
1416 1509
1417 1510 case SATA_PSTATE_SHUTDOWN:
1418 1511 sd->satadev_state = SATA_PSTATE_SHUTDOWN;
1419 1512 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1420 1513 "ahci_tran_probe_port: port %s PORT SHUTDOWN", portstr);
1421 1514 goto out;
1422 1515
1423 1516 case SATA_PSTATE_PWROFF:
1424 1517 sd->satadev_state = SATA_PSTATE_PWROFF;
1425 1518 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1426 1519 "ahci_tran_probe_port: port %s PORT PWROFF", portstr);
1427 1520 goto out;
1428 1521
1429 1522 case SATA_PSTATE_PWRON:
1430 1523 sd->satadev_state = SATA_PSTATE_PWRON;
1431 1524 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1432 1525 "ahci_tran_probe_port: port %s PORT PWRON", portstr);
1433 1526 break;
1434 1527
1435 1528 default:
1436 1529 sd->satadev_state = port_state;
1437 1530 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1438 1531 "ahci_tran_probe_port: port %s PORT NORMAL %x",
1439 1532 portstr, port_state);
1440 1533 break;
1441 1534 }
1442 1535
1443 1536 device_type = AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr);
1444 1537
1445 1538 switch (device_type) {
1446 1539
1447 1540 case SATA_DTYPE_ATADISK:
1448 1541 sd->satadev_type = SATA_DTYPE_ATADISK;
1449 1542 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1450 1543 "ahci_tran_probe_port: port %s DISK found", portstr);
1451 1544 break;
1452 1545
1453 1546 case SATA_DTYPE_ATAPI:
1454 1547 /*
1455 1548 * HBA driver only knows it's an ATAPI device, and don't know
1456 1549 * it's CD/DVD, tape or ATAPI disk because the ATAPI device
1457 1550 * type need to be determined by checking IDENTIFY PACKET
1458 1551 * DEVICE data
1459 1552 */
1460 1553 sd->satadev_type = SATA_DTYPE_ATAPI;
1461 1554 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1462 1555 "ahci_tran_probe_port: port %s ATAPI found", portstr);
1463 1556 break;
1464 1557
1465 1558 case SATA_DTYPE_PMULT:
1466 1559 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMULT(&addr));
1467 1560 sd->satadev_type = SATA_DTYPE_PMULT;
1468 1561
1469 1562 /* Update the number of pmports. */
1470 1563 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
1471 1564 sd->satadev_add_info = ahci_portp->
1472 1565 ahciport_pmult_info->ahcipmi_num_dev_ports;
1473 1566
1474 1567 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1475 1568 "ahci_tran_probe_port: port %s Port Multiplier found",
1476 1569 portstr);
1477 1570 break;
1478 1571
1479 1572 case SATA_DTYPE_UNKNOWN:
1480 1573 sd->satadev_type = SATA_DTYPE_UNKNOWN;
1481 1574 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1482 1575 "ahci_tran_probe_port: port %s Unknown device found",
1483 1576 portstr);
1484 1577 break;
1485 1578
1486 1579 default:
1487 1580 /* we don't support any other device types */
1488 1581 sd->satadev_type = SATA_DTYPE_NONE;
1489 1582 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1490 1583 "ahci_tran_probe_port: port %s No device found", portstr);
1491 1584 break;
1492 1585 }
1493 1586
1494 1587 out:
1495 1588 /* Register update only fails while probing a pmult/pmport */
1496 1589 if (AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMULT(&addr)) {
1497 1590 ahci_update_sata_registers(ahci_ctlp, port, sd);
1498 1591 } else if (AHCI_ADDR_IS_PMPORT(&addr)) {
1499 1592 if (port_state & SATA_STATE_READY)
1500 1593 if (ahci_update_pmult_pscr(ahci_ctlp,
1501 1594 &addr, sd) != AHCI_SUCCESS)
1502 1595 rval = SATA_FAILURE;
1503 1596 }
1504 1597
1505 1598 /* Check handles for the sata registers access */
1506 1599 if ((ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) ||
1507 1600 (ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS)) {
1508 1601 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
1509 1602 DDI_SERVICE_UNAFFECTED);
1510 1603 rval = SATA_FAILURE;
1511 1604 }
1512 1605
1513 1606 mutex_exit(&ahci_portp->ahciport_mutex);
1514 1607 return (rval);
1515 1608 }
1516 1609
1517 1610 /*
1518 1611 * There are four operation modes in sata framework:
1519 1612 * SATA_OPMODE_INTERRUPTS
1520 1613 * SATA_OPMODE_POLLING
1521 1614 * SATA_OPMODE_ASYNCH
1522 1615 * SATA_OPMODE_SYNCH
1523 1616 *
1524 1617 * Their combined meanings as following:
1525 1618 *
1526 1619 * SATA_OPMODE_SYNCH
1527 1620 * The command has to be completed before sata_tran_start functions returns.
1528 1621 * Either interrupts or polling could be used - it's up to the driver.
1529 1622 * Mode used currently for internal, sata-module initiated operations.
1530 1623 *
1531 1624 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS
1532 1625 * It is the same as the one above.
1533 1626 *
1534 1627 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING
1535 1628 * The command has to be completed before sata_tran_start function returns.
1536 1629 * No interrupt used, polling only. This should be the mode used for scsi
1537 1630 * packets with FLAG_NOINTR.
1538 1631 *
1539 1632 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS
1540 1633 * The command may be queued (callback function specified). Interrupts could
1541 1634 * be used. It's normal operation mode.
1542 1635 */
1543 1636 /*
1544 1637 * Called by sata framework to transport a sata packet down stream.
1545 1638 */
1546 1639 static int
1547 1640 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt)
1548 1641 {
1549 1642 ahci_ctl_t *ahci_ctlp;
1550 1643 ahci_port_t *ahci_portp;
1551 1644 ahci_addr_t addr;
1552 1645 uint8_t cport = spkt->satapkt_device.satadev_addr.cport;
1553 1646 uint8_t port;
1554 1647 char portstr[10];
1555 1648
1556 1649 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip));
1557 1650 port = ahci_ctlp->ahcictl_cport_to_port[cport];
1558 1651
1559 1652 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
1560 1653 "ahci_tran_start enter: cport %d satapkt 0x%p",
1561 1654 cport, (void *)spkt);
1562 1655
1563 1656 ahci_portp = ahci_ctlp->ahcictl_ports[port];
1564 1657
1565 1658 mutex_enter(&ahci_portp->ahciport_mutex);
1566 1659 ahci_get_ahci_addr(ahci_ctlp, &spkt->satapkt_device, &addr);
1567 1660 SET_PORTSTR(portstr, &addr);
1568 1661
1569 1662 /* Sanity check */
1570 1663 if (AHCI_ADDR_IS_PMPORT(&addr)) {
1571 1664 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT ||
1572 1665 ahci_portp->ahciport_pmult_info == NULL) {
1573 1666
1574 1667 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1575 1668 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE;
1576 1669 spkt->satapkt_device.satadev_state = SATA_STATE_UNKNOWN;
1577 1670 ahci_update_sata_registers(ahci_ctlp, port,
1578 1671 &spkt->satapkt_device);
1579 1672 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1580 1673 "ahci_tran_start returning PORT_ERROR while "
1581 1674 "pmult removed: port: %s", portstr);
1582 1675 mutex_exit(&ahci_portp->ahciport_mutex);
1583 1676 return (SATA_TRAN_PORT_ERROR);
1584 1677 }
1585 1678
1586 1679 if (!(AHCIPORT_GET_STATE(ahci_portp, &addr) &
1587 1680 SATA_STATE_READY)) {
1588 1681 if (!ddi_in_panic() ||
1589 1682 ahci_initialize_pmport(ahci_ctlp,
1590 1683 ahci_portp, &addr) != AHCI_SUCCESS) {
1591 1684 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1592 1685 spkt->satapkt_device.satadev_type =
1593 1686 AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr);
1594 1687 spkt->satapkt_device.satadev_state =
1595 1688 AHCIPORT_GET_STATE(ahci_portp, &addr);
1596 1689 ahci_update_sata_registers(ahci_ctlp, port,
1597 1690 &spkt->satapkt_device);
1598 1691 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1599 1692 "ahci_tran_start returning PORT_ERROR "
1600 1693 "while sub-link is not initialized "
1601 1694 "at port: %s", portstr);
1602 1695 mutex_exit(&ahci_portp->ahciport_mutex);
1603 1696 return (SATA_TRAN_PORT_ERROR);
1604 1697 }
1605 1698 }
1606 1699 }
1607 1700
1608 1701 if (AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_FAILED ||
1609 1702 AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_SHUTDOWN||
1610 1703 AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_PWROFF) {
1611 1704 /*
1612 1705 * In case the target driver would send the packet before
1613 1706 * sata framework can have the opportunity to process those
1614 1707 * event reports.
1615 1708 */
1616 1709 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1617 1710 spkt->satapkt_device.satadev_state =
1618 1711 ahci_portp->ahciport_port_state;
1619 1712 ahci_update_sata_registers(ahci_ctlp, port,
1620 1713 &spkt->satapkt_device);
1621 1714 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1622 1715 "ahci_tran_start returning PORT_ERROR while "
1623 1716 "port in FAILED/SHUTDOWN/PWROFF state: "
1624 1717 "port: %s", portstr);
1625 1718 mutex_exit(&ahci_portp->ahciport_mutex);
1626 1719 return (SATA_TRAN_PORT_ERROR);
1627 1720 }
1628 1721
1629 1722 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr) == SATA_DTYPE_NONE) {
1630 1723 /*
1631 1724 * ahci_intr_phyrdy_change() may have rendered it to
1632 1725 * SATA_DTYPE_NONE.
1633 1726 */
1634 1727 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1635 1728 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE;
1636 1729 spkt->satapkt_device.satadev_state =
1637 1730 ahci_portp->ahciport_port_state;
1638 1731 ahci_update_sata_registers(ahci_ctlp, port,
1639 1732 &spkt->satapkt_device);
1640 1733 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1641 1734 "ahci_tran_start returning PORT_ERROR while "
1642 1735 "no device attached: port: %s", portstr);
1643 1736 mutex_exit(&ahci_portp->ahciport_mutex);
1644 1737 return (SATA_TRAN_PORT_ERROR);
1645 1738 }
1646 1739
1647 1740 /* R/W PMULT command will occupy the whole HBA port */
1648 1741 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
1649 1742 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1650 1743 "ahci_tran_start returning BUSY while "
1651 1744 "executing READ/WRITE PORT-MULT command: "
1652 1745 "port: %s", portstr);
1653 1746 spkt->satapkt_reason = SATA_PKT_BUSY;
1654 1747 mutex_exit(&ahci_portp->ahciport_mutex);
1655 1748 return (SATA_TRAN_BUSY);
1656 1749 }
1657 1750
1658 1751 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) {
1659 1752 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1660 1753 "ahci_tran_start returning BUSY while "
1661 1754 "hot-plug in progress: port: %s", portstr);
1662 1755 spkt->satapkt_reason = SATA_PKT_BUSY;
1663 1756 mutex_exit(&ahci_portp->ahciport_mutex);
1664 1757 return (SATA_TRAN_BUSY);
1665 1758 }
1666 1759
1667 1760 /*
1668 1761 * SATA HBA driver should remember that a device was reset and it
1669 1762 * is supposed to reject any packets which do not specify either
1670 1763 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE.
1671 1764 *
1672 1765 * This is to prevent a race condition when a device was arbitrarily
1673 1766 * reset by the HBA driver (and lost it's setting) and a target
1674 1767 * driver sending some commands to a device before the sata framework
1675 1768 * has a chance to restore the device setting (such as cache enable/
1676 1769 * disable or other resettable stuff).
1677 1770 */
1678 1771 /*
1679 1772 * It is unnecessary to use specific flags to indicate
1680 1773 * reset_in_progress for a pmport. While mopping, all command will be
1681 1774 * mopped so that the entire HBA port is being dealt as a single
1682 1775 * object.
1683 1776 */
1684 1777 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) {
1685 1778 ahci_portp->ahciport_reset_in_progress = 0;
1686 1779 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1687 1780 "ahci_tran_start [CLEAR] the "
1688 1781 "reset_in_progress for port: %d", port);
1689 1782 }
1690 1783
1691 1784 if (ahci_portp->ahciport_reset_in_progress &&
1692 1785 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset &&
1693 1786 ! ddi_in_panic()) {
1694 1787 spkt->satapkt_reason = SATA_PKT_BUSY;
1695 1788 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1696 1789 "ahci_tran_start returning BUSY while "
1697 1790 "reset in progress: port: %d", port);
1698 1791 mutex_exit(&ahci_portp->ahciport_mutex);
1699 1792 return (SATA_TRAN_BUSY);
1700 1793 }
1701 1794
1702 1795 #ifdef AHCI_DEBUG
1703 1796 if (spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset) {
1704 1797 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1705 1798 "ahci_tran_start: packet 0x%p [PASSTHRU] at port %d",
1706 1799 spkt, port);
1707 1800 }
1708 1801 #endif
1709 1802
1710 1803 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
1711 1804 spkt->satapkt_reason = SATA_PKT_BUSY;
1712 1805 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1713 1806 "ahci_tran_start returning BUSY while "
1714 1807 "mopping in progress: port: %d", port);
1715 1808 mutex_exit(&ahci_portp->ahciport_mutex);
1716 1809 return (SATA_TRAN_BUSY);
1717 1810 }
1718 1811
1719 1812 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) {
1720 1813 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
1721 1814 DDI_SERVICE_UNAFFECTED);
1722 1815 mutex_exit(&ahci_portp->ahciport_mutex);
1723 1816 return (SATA_TRAN_BUSY);
1724 1817 }
1725 1818
1726 1819 if (spkt->satapkt_op_mode &
1727 1820 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) {
1728 1821 /*
1729 1822 * If a SYNC command to be executed in interrupt context,
1730 1823 * bounce it back to sata module.
1731 1824 */
1732 1825 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) &&
1733 1826 servicing_interrupt()) {
1734 1827 spkt->satapkt_reason = SATA_PKT_BUSY;
1735 1828 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1736 1829 "ahci_tran_start returning BUSY while "
1737 1830 "sending SYNC mode under interrupt context: "
1738 1831 "port : %d", port);
1739 1832 mutex_exit(&ahci_portp->ahciport_mutex);
1740 1833 return (SATA_TRAN_BUSY);
1741 1834 }
1742 1835
1743 1836 /* We need to do the sync start now */
1744 1837 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, &addr,
1745 1838 spkt) == AHCI_FAILURE) {
1746 1839 goto fail_out;
1747 1840 }
1748 1841 } else {
1749 1842 /* Async start, using interrupt */
1750 1843 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, &addr, spkt)
1751 1844 == AHCI_FAILURE) {
1752 1845 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL;
1753 1846 goto fail_out;
1754 1847 }
1755 1848 }
1756 1849
1757 1850 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start "
1758 1851 "sata tran accepted: port %s", portstr);
1759 1852
1760 1853 mutex_exit(&ahci_portp->ahciport_mutex);
1761 1854 return (SATA_TRAN_ACCEPTED);
1762 1855
1763 1856 fail_out:
1764 1857 /*
1765 1858 * Failed to deliver packet to the controller.
1766 1859 * Check if it's caused by invalid handles.
1767 1860 */
1768 1861 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS ||
1769 1862 ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS) {
1770 1863 spkt->satapkt_device.satadev_type =
1771 1864 AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr);
1772 1865 spkt->satapkt_device.satadev_state =
1773 1866 AHCIPORT_GET_STATE(ahci_portp, &addr);
1774 1867 spkt->satapkt_reason = SATA_PKT_DEV_ERROR;
1775 1868 mutex_exit(&ahci_portp->ahciport_mutex);
1776 1869 return (SATA_TRAN_PORT_ERROR);
1777 1870 }
1778 1871
1779 1872 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start "
1780 1873 "return QUEUE_FULL: port %d", port);
1781 1874 mutex_exit(&ahci_portp->ahciport_mutex);
1782 1875 return (SATA_TRAN_QUEUE_FULL);
1783 1876 }
1784 1877
1785 1878 /*
1786 1879 * SATA_OPMODE_SYNCH flag is set
1787 1880 *
1788 1881 * If SATA_OPMODE_POLLING flag is set, then we must poll the command
1789 1882 * without interrupt, otherwise we can still use the interrupt.
1790 1883 */
1791 1884 static int
1792 1885 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
1793 1886 ahci_addr_t *addrp, sata_pkt_t *spkt)
1794 1887 {
1795 1888 int pkt_timeout_ticks;
1796 1889 uint32_t timeout_tags;
1797 1890 int rval;
1798 1891 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
1799 1892 uint8_t port = addrp->aa_port;
1800 1893
1801 1894 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
1802 1895
1803 1896 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: "
1804 1897 "port %d:%d spkt 0x%p", port, addrp->aa_pmport, spkt);
1805 1898
1806 1899 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) {
1807 1900 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING;
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1808 1901 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp,
1809 1902 addrp, spkt)) == AHCI_FAILURE) {
1810 1903 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING;
1811 1904 return (rval);
1812 1905 }
1813 1906
1814 1907 pkt_timeout_ticks =
1815 1908 drv_usectohz((clock_t)spkt->satapkt_time * 1000000);
1816 1909
1817 1910 while (spkt->satapkt_reason == SATA_PKT_BUSY) {
1818 - mutex_exit(&ahci_portp->ahciport_mutex);
1819 -
1820 1911 /* Simulate the interrupt */
1912 + mutex_exit(&ahci_portp->ahciport_mutex);
1821 1913 ahci_port_intr(ahci_ctlp, ahci_portp, port);
1914 + mutex_enter(&ahci_portp->ahciport_mutex);
1822 1915
1823 - drv_usecwait(AHCI_10MS_USECS);
1916 + if (spkt->satapkt_reason != SATA_PKT_BUSY)
1917 + break;
1824 1918
1919 + mutex_exit(&ahci_portp->ahciport_mutex);
1920 + drv_usecwait(AHCI_1MS_USECS);
1825 1921 mutex_enter(&ahci_portp->ahciport_mutex);
1826 - pkt_timeout_ticks -= AHCI_10MS_TICKS;
1922 +
1923 + pkt_timeout_ticks -= AHCI_1MS_TICKS;
1827 1924 if (pkt_timeout_ticks < 0) {
1828 1925 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start "
1829 1926 "port %d satapkt 0x%p timed out\n",
1830 1927 instance, port, (void *)spkt);
1831 1928 timeout_tags = (0x1 << rval);
1832 1929 mutex_exit(&ahci_portp->ahciport_mutex);
1833 1930 ahci_timeout_pkts(ahci_ctlp, ahci_portp,
1834 1931 port, timeout_tags);
1835 1932 mutex_enter(&ahci_portp->ahciport_mutex);
1836 1933 }
1837 1934 }
1935 +
1838 1936 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING;
1839 1937 return (AHCI_SUCCESS);
1840 1938
1841 1939 } else {
1842 1940 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp,
1843 1941 addrp, spkt)) == AHCI_FAILURE)
1844 1942 return (rval);
1845 1943
1846 1944 #if AHCI_DEBUG
1847 1945 /*
1848 1946 * Note that the driver always uses the slot 0 to deliver
1849 1947 * REQUEST SENSE or READ LOG EXT command
1850 1948 */
1851 1949 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
1852 1950 ASSERT(rval == 0);
1853 1951 #endif
1854 1952
1855 1953 while (spkt->satapkt_reason == SATA_PKT_BUSY)
1856 1954 cv_wait(&ahci_portp->ahciport_cv,
1857 1955 &ahci_portp->ahciport_mutex);
1858 1956
1859 1957 return (AHCI_SUCCESS);
1860 1958 }
1861 1959 }
1862 1960
1863 1961 /*
1864 1962 * Searches for and claims a free command slot.
1865 1963 *
1866 1964 * Returns value:
1867 1965 *
1868 1966 * AHCI_FAILURE returned only if
1869 1967 * 1. No empty slot left
1870 1968 * 2. Non-queued command requested while queued command(s) is outstanding
1871 1969 * 3. Queued command requested while non-queued command(s) is outstanding
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1872 1970 * 4. HBA doesn't support multiple-use of command list while already a
1873 1971 * non-queued command is oustanding
1874 1972 * 5. Queued command requested while some queued command(s) has been
1875 1973 * outstanding on a different port multiplier port. (AHCI spec 1.2,
1876 1974 * 9.1.2)
1877 1975 *
1878 1976 * claimed slot number returned if succeeded
1879 1977 *
1880 1978 * NOTE: it will always return slot 0 for following commands to simplify the
1881 1979 * algorithm.
1882 - * 1. REQUEST SENSE or READ LOG EXT command during error recovery process
1883 - * 2. READ/WRITE PORTMULT command
1980 + * 1. REQUEST SENSE or READ LOG EXT command during error recovery process
1981 + * 2. READ/WRITE PORTMULT command
1884 1982 */
1885 1983 static int
1886 1984 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
1887 1985 ahci_addr_t *addrp, int command_type)
1888 1986 {
1889 1987 uint32_t port_cmd_issue;
1890 1988 uint32_t free_slots;
1891 1989 int slot;
1892 1990
1893 1991 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
1894 1992
1895 1993 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter "
1896 1994 "ahciport_pending_tags = 0x%x "
1897 1995 "ahciport_pending_ncq_tags = 0x%x",
1898 1996 ahci_portp->ahciport_pending_tags,
1899 1997 ahci_portp->ahciport_pending_ncq_tags);
1900 1998
1901 1999 /*
1902 2000 * According to the AHCI spec, system software is responsible to
1903 2001 * ensure that queued and non-queued commands are not mixed in
1904 2002 * the command list.
1905 2003 */
1906 2004 if (command_type == AHCI_NON_NCQ_CMD) {
1907 2005 /* Non-NCQ command request */
1908 2006 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
1909 2007 AHCIDBG(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp,
1910 2008 "ahci_claim_free_slot: there is still pending "
1911 2009 "queued command(s) in the command list, "
1912 2010 "so no available slot for the non-queued "
1913 2011 "command", NULL);
1914 2012 return (AHCI_FAILURE);
1915 2013 }
1916 2014 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
1917 2015 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
1918 2016 "ahci_claim_free_slot: there is still pending "
1919 2017 "read/write port-mult command(s) in command list, "
1920 2018 "so no available slot for the non-queued command",
1921 2019 NULL);
1922 2020 return (AHCI_FAILURE);
1923 2021 }
1924 2022 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) &&
1925 2023 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
1926 2024 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1927 2025 "ahci_claim_free_slot: HBA cannot support multiple-"
1928 2026 "use of the command list for non-queued commands",
1929 2027 NULL);
1930 2028 return (AHCI_FAILURE);
1931 2029 }
1932 2030 free_slots = (~ahci_portp->ahciport_pending_tags) &
1933 2031 AHCI_SLOT_MASK(ahci_ctlp);
1934 2032 } else if (command_type == AHCI_NCQ_CMD) {
1935 2033 /* NCQ command request */
1936 2034 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
1937 2035 AHCIDBG(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp,
1938 2036 "ahci_claim_free_slot: there is still pending "
1939 2037 "non-queued command(s) in the command list, "
1940 2038 "so no available slot for the queued command",
1941 2039 NULL);
1942 2040 return (AHCI_FAILURE);
1943 2041 }
1944 2042
1945 2043 /*
1946 2044 * NCQ commands cannot be sent to different port multiplier
1947 2045 * ports in Command-Based Switching mode
1948 2046 */
1949 2047 /*
1950 2048 * NOTE: In Command-Based Switching mode, AHCI controller
1951 2049 * usually reports a 'Handshake Error' when multiple NCQ
1952 2050 * commands are outstanding simultaneously.
1953 2051 */
1954 2052 if (AHCIPORT_DEV_TYPE(ahci_portp, addrp) == SATA_DTYPE_PMULT) {
1955 2053 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
1956 2054 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_FBSS) &&
1957 2055 NCQ_CMD_IN_PROGRESS(ahci_portp) &&
1958 2056 AHCIPORT_NCQ_PMPORT(ahci_portp) !=
1959 2057 addrp->aa_pmport) {
1960 2058 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1961 2059 "ahci_claim_free_slot: there is still "
1962 2060 "pending queued command(s) in the "
1963 2061 "command list for another Port Multiplier "
1964 2062 "port, so no available slot.", NULL);
1965 2063 return (AHCI_FAILURE);
1966 2064 }
1967 2065 }
1968 2066
1969 2067 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) &
1970 2068 AHCI_NCQ_SLOT_MASK(ahci_portp);
1971 2069 } else if (command_type == AHCI_ERR_RETRI_CMD) {
1972 2070 /* Error retrieval command request */
1973 2071 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1974 2072 "ahci_claim_free_slot: slot 0 is allocated for REQUEST "
1975 2073 "SENSE or READ LOG EXT command", NULL);
1976 2074 slot = 0;
1977 2075 goto out;
1978 2076 } else if (command_type == AHCI_RDWR_PMULT_CMD) {
1979 2077 /*
1980 2078 * An extra check on PxCI. Sometimes PxCI bits may not be
1981 2079 * cleared during hot-plug or error recovery process.
1982 2080 */
1983 2081 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
1984 2082 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, addrp->aa_port));
1985 2083
1986 2084 if (port_cmd_issue != 0) {
1987 2085 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
1988 2086 "ahci_claim_free_slot: there is still pending "
1989 2087 "command(s) in command list (0x%x/0x%x, PxCI %x),"
1990 2088 "so no available slot for R/W PMULT command.",
1991 2089 NON_NCQ_CMD_IN_PROGRESS(ahci_portp),
1992 2090 NCQ_CMD_IN_PROGRESS(ahci_portp),
1993 2091 port_cmd_issue);
1994 2092 return (AHCI_FAILURE);
1995 2093 }
1996 2094
1997 2095 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1998 2096 "ahci_claim_free_slot: slot 0 is allocated for "
1999 2097 "READ/WRITE PORTMULT command", NULL);
2000 2098 slot = 0;
2001 2099 goto out;
2002 2100 }
2003 2101
2004 2102 slot = ddi_ffs(free_slots) - 1;
2005 2103 if (slot == -1) {
2006 2104 AHCIDBG(AHCIDBG_VERBOSE, ahci_ctlp,
2007 2105 "ahci_claim_free_slot: no empty slots", NULL);
2008 2106 return (AHCI_FAILURE);
2009 2107 }
2010 2108
2011 2109 /*
2012 2110 * According to the AHCI spec, to allow a simple mechanism for the
2013 2111 * HBA to map command list slots to queue entries, software must
2014 2112 * match the tag number it uses to the slot it is placing the command
2015 2113 * in. For example, if a queued command is placed in slot 5, the tag
2016 2114 * for that command must be 5.
2017 2115 */
2018 2116 if (command_type == AHCI_NCQ_CMD) {
2019 2117 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot);
2020 2118 if (AHCI_ADDR_IS_PMPORT(addrp)) {
2021 2119 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
2022 2120 AHCIPORT_NCQ_PMPORT(ahci_portp) = addrp->aa_pmport;
2023 2121 }
2024 2122 }
2025 2123
2026 2124 ahci_portp->ahciport_pending_tags |= (0x1 << slot);
2027 2125
2028 2126 out:
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2029 2127 AHCIDBG(AHCIDBG_VERBOSE, ahci_ctlp,
2030 2128 "ahci_claim_free_slot: found slot: 0x%x", slot);
2031 2129
2032 2130 return (slot);
2033 2131 }
2034 2132
2035 2133 /*
2036 2134 * Builds the Command Table for the sata packet and delivers it to controller.
2037 2135 *
2038 2136 * Returns:
2039 - * slot number if we can obtain a slot successfully
2137 + * slot number if we can obtain a slot successfully
2040 2138 * otherwise, return AHCI_FAILURE
2041 2139 */
2042 2140 static int
2043 2141 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
2044 2142 ahci_addr_t *addrp, sata_pkt_t *spkt)
2045 2143 {
2046 2144 int cmd_slot;
2047 2145 sata_cmd_t *scmd;
2048 2146 ahci_fis_h2d_register_t *h2d_register_fisp;
2049 2147 ahci_cmd_table_t *cmd_table;
2050 2148 ahci_cmd_header_t *cmd_header;
2051 2149 int ncookies;
2052 2150 int i;
2053 2151 int command_type = AHCI_NON_NCQ_CMD;
2054 2152 int ncq_qdepth;
2055 2153 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
2056 2154 uint8_t port, pmport;
2057 2155 #if AHCI_DEBUG
2058 2156 uint32_t *ptr;
2059 2157 uint8_t *ptr2;
2060 2158 #endif
2061 2159
2062 2160 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2063 2161
2064 2162 port = addrp->aa_port;
2065 2163 pmport = addrp->aa_pmport;
2066 2164
2067 2165 spkt->satapkt_reason = SATA_PKT_BUSY;
2068 2166
2069 2167 scmd = &spkt->satapkt_cmd;
2070 2168
2071 2169 /* Check if the command is a NCQ command */
2072 2170 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED ||
2073 2171 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) {
2074 2172 command_type = AHCI_NCQ_CMD;
2075 2173
2076 2174 /*
2077 2175 * When NCQ is support, system software must determine the
2078 2176 * maximum tag allowed by the device and the HBA, and it
2079 2177 * must use a value not beyond of the lower bound of the two.
2080 2178 *
2081 2179 * Sata module is going to calculate the qdepth and send
2082 2180 * down to HBA driver via sata_cmd.
2083 2181 */
2084 2182 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1;
2085 2183
2086 2184 /*
2087 2185 * At the moment, the driver doesn't support the dynamic
2088 2186 * setting of the maximum ncq depth, and the value can be
2089 2187 * set either during the attach or after hot-plug insertion.
2090 2188 */
2091 2189 if (ahci_portp->ahciport_max_ncq_tags == 0) {
2092 2190 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth;
2093 2191 AHCIDBG(AHCIDBG_NCQ, ahci_ctlp,
2094 2192 "ahci_deliver_satapkt: port %d the max tags for "
2095 2193 "NCQ command is %d", port, ncq_qdepth);
2096 2194 } else {
2097 2195 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) {
2098 2196 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt"
2099 2197 " port %d the max tag for NCQ command is "
2100 2198 "requested to change from %d to %d, at the"
2101 2199 " moment the driver doesn't support the "
2102 2200 "dynamic change so it's going to "
2103 2201 "still use the previous tag value",
2104 2202 instance, port,
2105 2203 ahci_portp->ahciport_max_ncq_tags,
2106 2204 ncq_qdepth);
2107 2205 }
2108 2206 }
2109 2207 }
2110 2208
2111 2209 /* Check if the command is an error retrieval command */
2112 2210 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
2113 2211 command_type = AHCI_ERR_RETRI_CMD;
2114 2212
2115 2213 /* Check if the command is an read/write pmult command */
2116 2214 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp))
2117 2215 command_type = AHCI_RDWR_PMULT_CMD;
2118 2216
2119 2217 /* Check if there is an empty command slot */
2120 2218 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp,
2121 2219 addrp, command_type);
2122 2220 if (cmd_slot == AHCI_FAILURE) {
2123 2221 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "no free command slot", NULL);
2124 2222 return (AHCI_FAILURE);
2125 2223 }
2126 2224
2127 2225 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp,
2128 2226 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, "
2129 2227 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg,
2130 2228 cmd_slot, port, (void *)spkt);
2131 2229
2132 2230 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot];
2133 2231 bzero((void *)cmd_table, ahci_cmd_table_size);
2134 2232
2135 2233 /* For data transfer operations, it is the H2D Register FIS */
2136 2234 h2d_register_fisp =
2137 2235 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register);
2138 2236
2139 2237 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE);
2140 2238
2141 2239 /*
2142 2240 * PMP field only make sense when target is a port multiplier or a
2143 2241 * device behind a port multiplier. Otherwise should set it to 0.
2144 2242 */
2145 2243 if (AHCI_ADDR_IS_PMULT(addrp) || AHCI_ADDR_IS_PMPORT(addrp))
2146 2244 SET_FIS_PMP(h2d_register_fisp, pmport);
2147 2245
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2148 2246 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1);
2149 2247 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg);
2150 2248 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg);
2151 2249 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb);
2152 2250
2153 2251 switch (scmd->satacmd_addr_type) {
2154 2252
2155 2253 case 0:
2156 2254 /*
2157 2255 * satacmd_addr_type will be 0 for the commands below:
2158 - * ATAPI command
2159 - * SATAC_IDLE_IM
2160 - * SATAC_STANDBY_IM
2161 - * SATAC_DOWNLOAD_MICROCODE
2162 - * SATAC_FLUSH_CACHE
2163 - * SATAC_SET_FEATURES
2164 - * SATAC_SMART
2165 - * SATAC_ID_PACKET_DEVICE
2166 - * SATAC_ID_DEVICE
2167 - * SATAC_READ_PORTMULT
2168 - * SATAC_WRITE_PORTMULT
2256 + * ATAPI command
2257 + * SATAC_IDLE_IM
2258 + * SATAC_STANDBY_IM
2259 + * SATAC_DOWNLOAD_MICROCODE
2260 + * SATAC_FLUSH_CACHE
2261 + * SATAC_SET_FEATURES
2262 + * SATAC_SMART
2263 + * SATAC_ID_PACKET_DEVICE
2264 + * SATAC_ID_DEVICE
2265 + * SATAC_READ_PORTMULT
2266 + * SATAC_WRITE_PORTMULT
2169 2267 */
2170 2268 /* FALLTHRU */
2171 2269
2172 2270 case ATA_ADDR_LBA:
2173 2271 /* FALLTHRU */
2174 2272
2175 2273 case ATA_ADDR_LBA28:
2176 2274 /* LBA[7:0] */
2177 2275 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb);
2178 2276
2179 2277 /* LBA[15:8] */
2180 2278 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb);
2181 2279
2182 2280 /* LBA[23:16] */
2183 2281 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb);
2184 2282
2185 2283 /* LBA [27:24] (also called dev_head) */
2186 2284 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg);
2187 2285
2188 2286 break;
2189 2287
2190 2288 case ATA_ADDR_LBA48:
2191 2289 /* LBA[7:0] */
2192 2290 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb);
2193 2291
2194 2292 /* LBA[15:8] */
2195 2293 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb);
2196 2294
2197 2295 /* LBA[23:16] */
2198 2296 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb);
2199 2297
2200 2298 /* LBA [31:24] */
2201 2299 SET_FIS_SECTOR_EXP(h2d_register_fisp,
2202 2300 scmd->satacmd_lba_low_msb);
2203 2301
2204 2302 /* LBA [39:32] */
2205 2303 SET_FIS_CYL_LOW_EXP(h2d_register_fisp,
2206 2304 scmd->satacmd_lba_mid_msb);
2207 2305
2208 2306 /* LBA [47:40] */
2209 2307 SET_FIS_CYL_HI_EXP(h2d_register_fisp,
2210 2308 scmd->satacmd_lba_high_msb);
2211 2309
2212 2310 /* Set dev_head */
2213 2311 SET_FIS_DEV_HEAD(h2d_register_fisp,
2214 2312 scmd->satacmd_device_reg);
2215 2313
2216 2314 /* Set the extended sector count and features */
2217 2315 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp,
2218 2316 scmd->satacmd_sec_count_msb);
2219 2317 SET_FIS_FEATURES_EXP(h2d_register_fisp,
2220 2318 scmd->satacmd_features_reg_ext);
2221 2319 break;
2222 2320 }
2223 2321
2224 2322 /*
2225 2323 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is
2226 2324 * filled into features field, and sector count 8:15 is filled into
2227 2325 * features (exp) field. The hba driver doesn't need to anything
2228 2326 * special with regard to this, since sata framework has already
2229 2327 * done so.
2230 2328 *
2231 2329 * However the driver needs to make sure TAG is filled into sector
2232 2330 * field.
2233 2331 */
2234 2332 if (command_type == AHCI_NCQ_CMD) {
2235 2333 SET_FIS_SECTOR_COUNT(h2d_register_fisp,
2236 2334 (cmd_slot << SATA_TAG_QUEUING_SHIFT));
2237 2335 }
2238 2336
2239 2337 ncookies = scmd->satacmd_num_dma_cookies;
2240 2338 AHCIDBG(AHCIDBG_PRDT, ahci_ctlp,
2241 2339 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x",
2242 2340 ncookies, ahci_dma_prdt_number);
2243 2341
2244 2342 ASSERT(ncookies <= ahci_dma_prdt_number);
2245 2343 ahci_portp->ahciport_prd_bytecounts[cmd_slot] = 0;
2246 2344
2247 2345 /* *** now fill the scatter gather list ******* */
2248 2346 for (i = 0; i < ncookies; i++) {
2249 2347 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr =
2250 2348 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0];
2251 2349 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper =
2252 2350 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1];
2253 2351 cmd_table->ahcict_prdt[i].ahcipi_descr_info =
2254 2352 scmd->satacmd_dma_cookie_list[i].dmac_size - 1;
2255 2353 ahci_portp->ahciport_prd_bytecounts[cmd_slot] +=
2256 2354 scmd->satacmd_dma_cookie_list[i].dmac_size;
2257 2355 }
2258 2356
2259 2357 AHCIDBG(AHCIDBG_PRDT, ahci_ctlp,
2260 2358 "ahciport_prd_bytecounts 0x%x for cmd_slot 0x%x",
2261 2359 ahci_portp->ahciport_prd_bytecounts[cmd_slot], cmd_slot);
2262 2360
2263 2361 /* The ACMD field is filled in for ATAPI command */
2264 2362 if (scmd->satacmd_cmd_reg == SATAC_PACKET) {
2265 2363 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd,
2266 2364 SATA_ATAPI_MAX_CDB_LEN);
2267 2365 }
2268 2366
2269 2367 /* Set Command Header in Command List */
2270 2368 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot];
2271 2369 BZERO_DESCR_INFO(cmd_header);
2272 2370 BZERO_PRD_BYTE_COUNT(cmd_header);
2273 2371
2274 2372 /* Set the number of entries in the PRD table */
2275 2373 SET_PRD_TABLE_LENGTH(cmd_header, ncookies);
2276 2374
2277 2375 /* Set the length of the command in the CFIS area */
2278 2376 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH);
2279 2377
2280 2378 /*
2281 2379 * PMP field only make sense when target is a port multiplier or a
2282 2380 * device behind a port multiplier. Otherwise should set it to 0.
2283 2381 */
2284 2382 if (AHCI_ADDR_IS_PMULT(addrp) || AHCI_ADDR_IS_PMPORT(addrp))
2285 2383 SET_PORT_MULTI_PORT(cmd_header, pmport);
2286 2384
2287 2385 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "command data direction is "
2288 2386 "sata_data_direction = 0x%x",
2289 2387 scmd->satacmd_flags.sata_data_direction);
2290 2388
2291 2389 /* Set A bit if it is an ATAPI command */
2292 2390 if (scmd->satacmd_cmd_reg == SATAC_PACKET)
2293 2391 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI);
2294 2392
2295 2393 /* Set W bit if data is going to the device */
2296 2394 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE)
2297 2395 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE);
2298 2396
2299 2397 /*
2300 2398 * Set the prefetchable bit - this bit is only valid if the PRDTL
2301 2399 * field is non-zero or the ATAPI 'A' bit is set in the command
2302 2400 * header. This bit cannot be set when using native command
2303 2401 * queuing commands or when using FIS-based switching with a Port
2304 2402 * multiplier.
2305 2403 */
2306 2404 if (command_type != AHCI_NCQ_CMD)
2307 2405 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE);
2308 2406
2309 2407 /*
2310 2408 * Now remember the sata packet in ahciport_slot_pkts[].
2311 2409 * Error retrieval command and r/w port multiplier command will
2312 2410 * be stored specifically for each port.
2313 2411 */
2314 2412 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&
2315 2413 !RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp))
2316 2414 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt;
2317 2415
2318 2416 /*
2319 2417 * Keep the timeout value
2320 2418 */
2321 2419 ahci_portp->ahciport_slot_timeout[cmd_slot] = spkt->satapkt_time;
2322 2420
2323 2421 /*
2324 2422 * If the intial timout is less than 1 tick, then make it longer by
2325 2423 * 1 tick to avoid immediate timeout
2326 2424 */
2327 2425 if (ahci_portp->ahciport_slot_timeout[cmd_slot] <=
2328 2426 ahci_watchdog_timeout)
2329 2427 ahci_portp->ahciport_slot_timeout[cmd_slot] +=
2330 2428 ahci_watchdog_timeout;
2331 2429
2332 2430 #if AHCI_DEBUG
2333 2431 if (ahci_debug_flags & AHCIDBG_ATACMD &&
2334 2432 scmd->satacmd_cmd_reg != SATAC_PACKET ||
2335 2433 ahci_debug_flags & AHCIDBG_ATAPICMD &&
2336 2434 scmd->satacmd_cmd_reg == SATAC_PACKET) {
2337 2435
2338 2436 /* Dump the command header and table */
2339 2437 ahci_log(ahci_ctlp, CE_WARN, "\n");
2340 2438 ahci_log(ahci_ctlp, CE_WARN, "Command header&table for spkt "
2341 2439 "0x%p cmd_reg 0x%x port %d", spkt,
2342 2440 scmd->satacmd_cmd_reg, port);
2343 2441 ptr = (uint32_t *)cmd_header;
2344 2442 ahci_log(ahci_ctlp, CE_WARN,
2345 2443 " Command Header:%8x %8x %8x %8x",
2346 2444 ptr[0], ptr[1], ptr[2], ptr[3]);
2347 2445
2348 2446 /* Dump the H2D register FIS */
2349 2447 ptr = (uint32_t *)h2d_register_fisp;
2350 2448 ahci_log(ahci_ctlp, CE_WARN,
2351 2449 " Command FIS: %8x %8x %8x %8x",
2352 2450 ptr[0], ptr[1], ptr[2], ptr[3]);
2353 2451
2354 2452 /* Dump the ACMD register FIS */
2355 2453 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd);
2356 2454 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++)
2357 2455 if (ahci_debug_flags & AHCIDBG_ATAPICMD)
2358 2456 ahci_log(ahci_ctlp, CE_WARN,
2359 2457 " ATAPI command: %2x %2x %2x %2x "
2360 2458 "%2x %2x %2x %2x",
2361 2459 ptr2[8 * i], ptr2[8 * i + 1],
2362 2460 ptr2[8 * i + 2], ptr2[8 * i + 3],
2363 2461 ptr2[8 * i + 4], ptr2[8 * i + 5],
2364 2462 ptr2[8 * i + 6], ptr2[8 * i + 7]);
2365 2463
2366 2464 /* Dump the PRDT */
2367 2465 for (i = 0; i < ncookies; i++) {
2368 2466 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]);
2369 2467 ahci_log(ahci_ctlp, CE_WARN,
2370 2468 " Cookie %d: %8x %8x %8x %8x",
2371 2469 i, ptr[0], ptr[1], ptr[2], ptr[3]);
2372 2470 }
2373 2471 }
2374 2472 #endif
2375 2473
2376 2474 (void) ddi_dma_sync(
2377 2475 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot],
2378 2476 0,
2379 2477 ahci_cmd_table_size,
2380 2478 DDI_DMA_SYNC_FORDEV);
2381 2479
2382 2480 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle,
2383 2481 cmd_slot * sizeof (ahci_cmd_header_t),
2384 2482 sizeof (ahci_cmd_header_t),
2385 2483 DDI_DMA_SYNC_FORDEV);
2386 2484
2387 2485 if ((ahci_check_dma_handle(ahci_portp->
2388 2486 ahciport_cmd_tables_dma_handle[cmd_slot]) != DDI_FM_OK) ||
2389 2487 ahci_check_dma_handle(ahci_portp->
2390 2488 ahciport_cmd_list_dma_handle) != DDI_FM_OK) {
2391 2489 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
2392 2490 DDI_SERVICE_UNAFFECTED);
2393 2491 return (AHCI_FAILURE);
2394 2492 }
2395 2493
2396 2494 /* Set the corresponding bit in the PxSACT.DS for queued command */
2397 2495 if (command_type == AHCI_NCQ_CMD) {
2398 2496 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
2399 2497 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port),
2400 2498 (0x1 << cmd_slot));
2401 2499 }
2402 2500
2403 2501 /* Indicate to the HBA that a command is active. */
2404 2502 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
2405 2503 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port),
2406 2504 (0x1 << cmd_slot));
2407 2505
2408 2506 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt "
2409 2507 "exit: port %d", port);
2410 2508
2411 2509 /* Make sure the command is started by the PxSACT/PxCI */
2412 2510 if (ahci_check_acc_handle(ahci_ctlp->
2413 2511 ahcictl_ahci_acc_handle) != DDI_FM_OK) {
2414 2512 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
2415 2513 DDI_SERVICE_UNAFFECTED);
2416 2514 return (AHCI_FAILURE);
2417 2515 }
2418 2516
2419 2517 return (cmd_slot);
2420 2518 }
2421 2519
2422 2520 /*
2423 2521 * Called by the sata framework to abort the previously sent packet(s).
2424 2522 *
2425 2523 * Reset device to abort commands.
2426 2524 */
2427 2525 static int
2428 2526 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag)
2429 2527 {
2430 2528 ahci_ctl_t *ahci_ctlp;
2431 2529 ahci_port_t *ahci_portp;
2432 2530 uint32_t slot_status = 0;
2433 2531 uint32_t aborted_tags = 0;
2434 2532 uint32_t finished_tags = 0;
2435 2533 uint8_t cport = spkt->satapkt_device.satadev_addr.cport;
2436 2534 uint8_t port;
2437 2535 int tmp_slot;
2438 2536 int instance = ddi_get_instance(dip);
2439 2537
2440 2538 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
2441 2539 port = ahci_ctlp->ahcictl_cport_to_port[cport];
2442 2540
2443 2541 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2444 2542 "ahci_tran_abort enter: port %d", port);
2445 2543
2446 2544 ahci_portp = ahci_ctlp->ahcictl_ports[port];
2447 2545 mutex_enter(&ahci_portp->ahciport_mutex);
2448 2546
2449 2547 /*
2450 2548 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending
2451 2549 * commands are being mopped, therefore there is nothing else to do
2452 2550 */
2453 2551 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2454 2552 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
2455 2553 "ahci_tran_abort: port %d is in "
2456 2554 "mopping process, so just return directly ", port);
2457 2555 mutex_exit(&ahci_portp->ahciport_mutex);
2458 2556 return (SATA_SUCCESS);
2459 2557 }
2460 2558
2461 2559 /*
2462 2560 * If AHCI_PORT_FLAG_RDWR_PMULT flag is set, it means a R/W PMULT
2463 2561 * command is being executed so no other commands is outstanding,
2464 2562 * nothing to do.
2465 2563 */
2466 2564 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RDWR_PMULT) {
2467 2565 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
2468 2566 "ahci_tran_abort: port %d is reading/writing "
2469 2567 "port multiplier, so just return directly ", port);
2470 2568 mutex_exit(&ahci_portp->ahciport_mutex);
2471 2569 return (SATA_SUCCESS);
2472 2570 }
2473 2571
2474 2572 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED |
2475 2573 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN |
2476 2574 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) {
2477 2575 /*
2478 2576 * In case the targer driver would send the request before
2479 2577 * sata framework can have the opportunity to process those
2480 2578 * event reports.
2481 2579 */
2482 2580 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
2483 2581 spkt->satapkt_device.satadev_state =
2484 2582 ahci_portp->ahciport_port_state;
2485 2583 ahci_update_sata_registers(ahci_ctlp, port,
2486 2584 &spkt->satapkt_device);
2487 2585 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2488 2586 "ahci_tran_abort returning SATA_FAILURE while "
2489 2587 "port in FAILED/SHUTDOWN/PWROFF state: "
2490 2588 "port: %d", port);
2491 2589 mutex_exit(&ahci_portp->ahciport_mutex);
2492 2590 return (SATA_FAILURE);
2493 2591 }
2494 2592
2495 2593 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
2496 2594 /*
2497 2595 * ahci_intr_phyrdy_change() may have rendered it to
2498 2596 * AHCI_PORT_TYPE_NODEV.
2499 2597 */
2500 2598 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
2501 2599 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE;
2502 2600 spkt->satapkt_device.satadev_state =
2503 2601 ahci_portp->ahciport_port_state;
2504 2602 ahci_update_sata_registers(ahci_ctlp, port,
2505 2603 &spkt->satapkt_device);
2506 2604 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2507 2605 "ahci_tran_abort returning SATA_FAILURE while "
2508 2606 "no device attached: port: %d", port);
2509 2607 mutex_exit(&ahci_portp->ahciport_mutex);
2510 2608 return (SATA_FAILURE);
2511 2609 }
2512 2610
2513 2611 if (flag == SATA_ABORT_ALL_PACKETS) {
2514 2612 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2515 2613 aborted_tags = ahci_portp->ahciport_pending_tags;
2516 2614 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2517 2615 aborted_tags = ahci_portp->ahciport_pending_ncq_tags;
2518 2616
2519 2617 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets",
2520 2618 instance, port);
2521 2619 } else {
2522 2620 aborted_tags = 0xffffffff;
2523 2621 /*
2524 2622 * Aborting one specific packet, first search the
2525 2623 * ahciport_slot_pkts[] list for matching spkt.
2526 2624 */
2527 2625 for (tmp_slot = 0;
2528 2626 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) {
2529 2627 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) {
2530 2628 aborted_tags = (0x1 << tmp_slot);
2531 2629 break;
2532 2630 }
2533 2631 }
2534 2632
2535 2633 if (aborted_tags == 0xffffffff) {
2536 2634 /* request packet is not on the pending list */
2537 2635 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
2538 2636 "Cannot find the aborting pkt 0x%p on the "
2539 2637 "pending list", (void *)spkt);
2540 2638 ahci_update_sata_registers(ahci_ctlp, port,
2541 2639 &spkt->satapkt_device);
2542 2640 mutex_exit(&ahci_portp->ahciport_mutex);
2543 2641 return (SATA_FAILURE);
2544 2642 }
2545 2643 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p",
2546 2644 instance, port, (void *)spkt);
2547 2645 }
2548 2646
2549 2647 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2550 2648 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2551 2649 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2552 2650 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2553 2651 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2554 2652 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2555 2653
2556 2654 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2557 2655 ahci_portp->ahciport_mop_in_progress++;
2558 2656
2559 2657 /*
2560 2658 * To abort the packet(s), first we are trying to clear PxCMD.ST
2561 2659 * to stop the port, and if the port can be stopped
2562 2660 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0',
2563 2661 * then we just send back the aborted packet(s) with ABORTED flag
2564 2662 * and then restart the port by setting PxCMD.ST and PxCMD.FRE.
2565 2663 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we
2566 2664 * perform a COMRESET.
2567 2665 */
2568 2666 (void) ahci_restart_port_wait_till_ready(ahci_ctlp,
2569 2667 ahci_portp, port, NULL, NULL);
2570 2668
2571 2669 /*
2572 2670 * Compute which have finished and which need to be retried.
2573 2671 *
2574 2672 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags
2575 2673 * minus the slot_status. The aborted_tags has to be deducted by
2576 2674 * finished_tags since we can't possibly abort a tag which had finished
2577 2675 * already.
2578 2676 */
2579 2677 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2580 2678 finished_tags = ahci_portp->ahciport_pending_tags &
2581 2679 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2582 2680 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2583 2681 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2584 2682 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2585 2683
2586 2684 aborted_tags &= ~finished_tags;
2587 2685
2588 2686 ahci_mop_commands(ahci_ctlp,
2589 2687 ahci_portp,
2590 2688 slot_status,
2591 2689 0, /* failed tags */
2592 2690 0, /* timeout tags */
2593 2691 aborted_tags,
2594 2692 0); /* reset tags */
2595 2693
2596 2694 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device);
2597 2695 mutex_exit(&ahci_portp->ahciport_mutex);
2598 2696
2599 2697 return (SATA_SUCCESS);
2600 2698 }
2601 2699
2602 2700 /*
2603 2701 * Used to do device reset and reject all the pending packets on a device
2604 2702 * during the reset operation.
2605 2703 *
2606 2704 * NOTE: ONLY called by ahci_tran_reset_dport
2607 2705 */
2608 2706 static int
2609 2707 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp,
2610 2708 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
2611 2709 {
2612 2710 uint32_t slot_status = 0;
2613 2711 uint32_t reset_tags = 0;
2614 2712 uint32_t finished_tags = 0;
2615 2713 uint8_t port = addrp->aa_port;
2616 2714 sata_device_t sdevice;
2617 2715 int ret;
2618 2716
2619 2717 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2620 2718
2621 2719 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2622 2720 "ahci_reset_device_reject_pkts on port: %d", port);
2623 2721
2624 2722 /*
2625 2723 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending
2626 2724 * commands are being mopped, therefore there is nothing else to do
2627 2725 */
2628 2726 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2629 2727 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2630 2728 "ahci_reset_device_reject_pkts: port %d is in "
2631 2729 "mopping process, so return directly ", port);
2632 2730 return (SATA_SUCCESS);
2633 2731 }
2634 2732
2635 2733 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2636 2734 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2637 2735 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2638 2736 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2639 2737 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2640 2738 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2641 2739 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2642 2740 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2643 2741 }
2644 2742
2645 2743 if (ahci_software_reset(ahci_ctlp, ahci_portp, addrp)
2646 2744 != AHCI_SUCCESS) {
2647 2745 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2648 2746 "Try to do a port reset after software "
2649 2747 "reset failed", port);
2650 2748 ret = ahci_port_reset(ahci_ctlp, ahci_portp, addrp);
2651 2749 if (ret != AHCI_SUCCESS) {
2652 2750 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2653 2751 "ahci_reset_device_reject_pkts: port %d "
2654 2752 "failed", port);
2655 2753 return (SATA_FAILURE);
2656 2754 }
2657 2755 }
2658 2756 /* Set the reset in progress flag */
2659 2757 ahci_portp->ahciport_reset_in_progress = 1;
2660 2758
2661 2759 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2662 2760 ahci_portp->ahciport_mop_in_progress++;
2663 2761
2664 2762 /* Indicate to the framework that a reset has happened */
2665 2763 bzero((void *)&sdevice, sizeof (sata_device_t));
2666 2764 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
2667 2765 sdevice.satadev_addr.pmport = 0;
2668 2766 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
2669 2767 sdevice.satadev_state = SATA_DSTATE_RESET |
2670 2768 SATA_DSTATE_PWR_ACTIVE;
2671 2769 mutex_exit(&ahci_portp->ahciport_mutex);
2672 2770 sata_hba_event_notify(
2673 2771 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
2674 2772 &sdevice,
2675 2773 SATA_EVNT_DEVICE_RESET);
2676 2774 mutex_enter(&ahci_portp->ahciport_mutex);
2677 2775
2678 2776 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
2679 2777 "port %d sending event up: SATA_EVNT_DEVICE_RESET", port);
2680 2778
2681 2779 /* Next try to mop the pending commands */
2682 2780 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2683 2781 finished_tags = ahci_portp->ahciport_pending_tags &
2684 2782 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2685 2783 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2686 2784 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2687 2785 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2688 2786
2689 2787 reset_tags &= ~finished_tags;
2690 2788
2691 2789 ahci_mop_commands(ahci_ctlp,
2692 2790 ahci_portp,
2693 2791 slot_status,
2694 2792 0, /* failed tags */
2695 2793 0, /* timeout tags */
2696 2794 0, /* aborted tags */
2697 2795 reset_tags); /* reset tags */
2698 2796
2699 2797 return (SATA_SUCCESS);
2700 2798 }
2701 2799
2702 2800 /*
2703 2801 * Used to do device reset and reject all the pending packets on a device
2704 2802 * during the reset operation.
2705 2803 *
2706 2804 * NOTE: ONLY called by ahci_tran_reset_dport
2707 2805 */
2708 2806 static int
2709 2807 ahci_reset_pmdevice_reject_pkts(ahci_ctl_t *ahci_ctlp,
2710 2808 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
2711 2809 {
2712 2810 uint32_t finished_tags = 0, reset_tags = 0, slot_status = 0;
2713 2811 uint8_t port = addrp->aa_port;
2714 2812 uint8_t pmport = addrp->aa_pmport;
2715 2813 sata_device_t sdevice;
2716 2814
2717 2815 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2718 2816
2719 2817 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_PMULT, ahci_ctlp,
2720 2818 "ahci_reset_pmdevice_reject_pkts at port %d:%d", port, pmport);
2721 2819
2722 2820 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2723 2821 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2724 2822 "ahci_reset_pmdevice_reject_pkts: port %d is in "
2725 2823 "mopping process, so return directly ", port);
2726 2824 return (SATA_SUCCESS);
2727 2825 }
2728 2826
2729 2827 /* Checking for outstanding commands */
2730 2828 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2731 2829 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2732 2830 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2733 2831 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2734 2832 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2735 2833 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2736 2834 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2737 2835 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2738 2836 }
2739 2837
2740 2838 /* Issue SOFTWARE reset command. */
2741 2839 if (ahci_software_reset(ahci_ctlp, ahci_portp, addrp)
2742 2840 != AHCI_SUCCESS) {
2743 2841 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2744 2842 "Try to do a port reset after software "
2745 2843 "reset failed", port);
2746 2844 return (SATA_FAILURE);
2747 2845 }
2748 2846
2749 2847 /* Set the reset in progress flag */
2750 2848 ahci_portp->ahciport_reset_in_progress = 1;
2751 2849
2752 2850 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2753 2851 ahci_portp->ahciport_mop_in_progress++;
2754 2852
2755 2853 /* Indicate to the framework that a reset has happened */
2756 2854 bzero((void *)&sdevice, sizeof (sata_device_t));
2757 2855 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
2758 2856 sdevice.satadev_addr.pmport = pmport;
2759 2857 if (AHCI_ADDR_IS_PMULT(addrp))
2760 2858 sdevice.satadev_addr.qual = SATA_ADDR_PMULT;
2761 2859 else
2762 2860 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT;
2763 2861 sdevice.satadev_state = SATA_DSTATE_RESET |
2764 2862 SATA_DSTATE_PWR_ACTIVE;
2765 2863 mutex_exit(&ahci_portp->ahciport_mutex);
2766 2864 sata_hba_event_notify(
2767 2865 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
2768 2866 &sdevice,
2769 2867 SATA_EVNT_DEVICE_RESET);
2770 2868 mutex_enter(&ahci_portp->ahciport_mutex);
2771 2869
2772 2870 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
2773 2871 "port %d:%d sending event up: SATA_EVNT_DEVICE_RESET",
2774 2872 port, pmport);
2775 2873
2776 2874 /* Next try to mop the pending commands */
2777 2875 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2778 2876 finished_tags = ahci_portp->ahciport_pending_tags &
2779 2877 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2780 2878 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2781 2879 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2782 2880 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2783 2881 reset_tags &= ~finished_tags;
2784 2882
2785 2883 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
2786 2884 "reset_tags = %x, finished_tags = %x, slot_status = %x",
2787 2885 reset_tags, finished_tags, slot_status);
2788 2886
2789 2887 /*
2790 2888 * NOTE: Because PxCI be only erased by unset PxCMD.ST bit, so even we
2791 2889 * try to reset a single device behind a port multiplier will
2792 2890 * terminate all the commands on that HBA port. We need mop these
2793 2891 * commands as well.
2794 2892 */
2795 2893 ahci_mop_commands(ahci_ctlp,
2796 2894 ahci_portp,
2797 2895 slot_status,
2798 2896 0, /* failed tags */
2799 2897 0, /* timeout tags */
2800 2898 0, /* aborted tags */
2801 2899 reset_tags); /* reset tags */
2802 2900
2803 2901 return (SATA_SUCCESS);
2804 2902 }
2805 2903
2806 2904 /*
2807 2905 * Used to do port reset and reject all the pending packets on a port during
2808 2906 * the reset operation.
2809 2907 */
2810 2908 static int
2811 2909 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp,
2812 2910 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
2813 2911 {
2814 2912 uint32_t slot_status = 0;
2815 2913 uint32_t reset_tags = 0;
2816 2914 uint32_t finished_tags = 0;
2817 2915 uint8_t port = addrp->aa_port;
2818 2916
2819 2917 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2820 2918
2821 2919 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2822 2920 "ahci_reset_port_reject_pkts at port: %d", port);
2823 2921
2824 2922 /*
2825 2923 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending
2826 2924 * commands are being mopped, therefore there is nothing else to do
2827 2925 */
2828 2926 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2829 2927 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2830 2928 "ahci_reset_port_reject_pkts: port %d is in "
2831 2929 "mopping process, so return directly ", port);
2832 2930 return (SATA_SUCCESS);
2833 2931 }
2834 2932
2835 2933 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2836 2934 ahci_portp->ahciport_mop_in_progress++;
2837 2935
2838 2936 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2839 2937 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2840 2938 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2841 2939 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2842 2940 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2843 2941 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2844 2942 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2845 2943 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2846 2944 }
2847 2945
2848 2946 if (ahci_restart_port_wait_till_ready(ahci_ctlp,
2849 2947 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP,
2850 2948 NULL) != AHCI_SUCCESS) {
2851 2949
2852 2950 /* Clear mop flag */
2853 2951 ahci_portp->ahciport_mop_in_progress--;
2854 2952 if (ahci_portp->ahciport_mop_in_progress == 0)
2855 2953 ahci_portp->ahciport_flags &=
2856 2954 ~AHCI_PORT_FLAG_MOPPING;
2857 2955 return (SATA_FAILURE);
2858 2956 }
2859 2957
2860 2958 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2861 2959 finished_tags = ahci_portp->ahciport_pending_tags &
2862 2960 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2863 2961 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2864 2962 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2865 2963 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2866 2964
2867 2965 reset_tags &= ~finished_tags;
2868 2966
2869 2967 ahci_mop_commands(ahci_ctlp,
2870 2968 ahci_portp,
2871 2969 slot_status,
2872 2970 0, /* failed tags */
2873 2971 0, /* timeout tags */
2874 2972 0, /* aborted tags */
2875 2973 reset_tags); /* reset tags */
2876 2974
2877 2975 return (SATA_SUCCESS);
2878 2976 }
2879 2977
2880 2978 /*
2881 2979 * Used to do hba reset and reject all the pending packets on all ports
2882 2980 * during the reset operation.
2883 2981 */
2884 2982 static int
2885 2983 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp)
2886 2984 {
2887 2985 ahci_port_t *ahci_portp;
2888 2986 uint32_t slot_status[AHCI_MAX_PORTS];
2889 2987 uint32_t reset_tags[AHCI_MAX_PORTS];
2890 2988 uint32_t finished_tags[AHCI_MAX_PORTS];
2891 2989 int port;
2892 2990 int ret = SATA_SUCCESS;
2893 2991
2894 2992 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2895 2993 "ahci_reset_hba_reject_pkts enter", NULL);
2896 2994
2897 2995 bzero(slot_status, sizeof (slot_status));
2898 2996 bzero(reset_tags, sizeof (reset_tags));
2899 2997 bzero(finished_tags, sizeof (finished_tags));
2900 2998
2901 2999 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
2902 3000 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
2903 3001 continue;
2904 3002 }
2905 3003
2906 3004 ahci_portp = ahci_ctlp->ahcictl_ports[port];
2907 3005
2908 3006 mutex_enter(&ahci_portp->ahciport_mutex);
2909 3007 ahci_portp->ahciport_reset_in_progress = 1;
2910 3008 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2911 3009 slot_status[port] = ddi_get32(
2912 3010 ahci_ctlp->ahcictl_ahci_acc_handle,
2913 3011 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2914 3012 reset_tags[port] = slot_status[port] &
2915 3013 AHCI_SLOT_MASK(ahci_ctlp);
2916 3014 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
2917 3015 "port %d: reset_tags = 0x%x pending_tags = 0x%x",
2918 3016 port, reset_tags[port],
2919 3017 ahci_portp->ahciport_pending_tags);
2920 3018 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2921 3019 slot_status[port] = ddi_get32(
2922 3020 ahci_ctlp->ahcictl_ahci_acc_handle,
2923 3021 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2924 3022 reset_tags[port] = slot_status[port] &
2925 3023 AHCI_NCQ_SLOT_MASK(ahci_portp);
2926 3024 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
2927 3025 "port %d: reset_tags = 0x%x pending_tags = 0x%x",
2928 3026 port, reset_tags[port],
2929 3027 ahci_portp->ahciport_pending_tags);
2930 3028 }
2931 3029 mutex_exit(&ahci_portp->ahciport_mutex);
2932 3030 }
2933 3031
2934 3032 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) {
2935 3033 ret = SATA_FAILURE;
2936 3034 }
2937 3035
2938 3036 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
2939 3037 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
2940 3038 continue;
2941 3039 }
2942 3040
2943 3041 ahci_portp = ahci_ctlp->ahcictl_ports[port];
2944 3042
2945 3043 mutex_enter(&ahci_portp->ahciport_mutex);
2946 3044 /*
2947 3045 * To prevent recursive enter to ahci_mop_commands, we need
2948 3046 * check AHCI_PORT_FLAG_MOPPING flag.
2949 3047 */
2950 3048 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2951 3049 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2952 3050 "ahci_reset_hba_reject_pkts: port %d is in "
2953 3051 "mopping process, so return directly ", port);
2954 3052 mutex_exit(&ahci_portp->ahciport_mutex);
2955 3053 continue;
2956 3054 }
2957 3055
2958 3056 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2959 3057 ahci_portp->ahciport_mop_in_progress++;
2960 3058
2961 3059 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2962 3060 finished_tags[port] =
2963 3061 ahci_portp->ahciport_pending_tags &
2964 3062 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp);
2965 3063 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2966 3064 finished_tags[port] =
2967 3065 ahci_portp->ahciport_pending_ncq_tags &
2968 3066 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp);
2969 3067
2970 3068 reset_tags[port] &= ~finished_tags[port];
2971 3069
2972 3070 ahci_mop_commands(ahci_ctlp,
2973 3071 ahci_portp,
2974 3072 slot_status[port],
2975 3073 0, /* failed tags */
2976 3074 0, /* timeout tags */
2977 3075 0, /* aborted tags */
2978 3076 reset_tags[port]); /* reset tags */
2979 3077 mutex_exit(&ahci_portp->ahciport_mutex);
2980 3078 }
2981 3079 out:
2982 3080 return (ret);
2983 3081 }
2984 3082
2985 3083 /*
2986 3084 * Called by sata framework to reset a port(s) or device.
2987 3085 */
2988 3086 static int
2989 3087 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd)
2990 3088 {
2991 3089 ahci_ctl_t *ahci_ctlp;
2992 3090 ahci_port_t *ahci_portp;
2993 3091 ahci_addr_t addr;
2994 3092 uint8_t cport = sd->satadev_addr.cport;
2995 3093 uint8_t pmport = sd->satadev_addr.pmport;
2996 3094 uint8_t port;
2997 3095 int ret = SATA_SUCCESS;
2998 3096 int instance = ddi_get_instance(dip);
2999 3097
3000 3098 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
3001 3099 port = ahci_ctlp->ahcictl_cport_to_port[cport];
3002 3100 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3003 3101
3004 3102 ahci_get_ahci_addr(ahci_ctlp, sd, &addr);
3005 3103
3006 3104 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
3007 3105 "ahci_tran_reset_dport enter: cport %d", cport);
3008 3106
3009 3107 switch (sd->satadev_addr.qual) {
3010 3108 case SATA_ADDR_PMPORT:
3011 3109 /*
3012 3110 * If we want to issue a COMRESET on a pmport, we need to
3013 3111 * reject the outstanding commands on that pmport. According
3014 3112 * to AHCI spec, PxCI register could only be cleared by
3015 3113 * clearing PxCMD.ST, which will halt the controller port - as
3016 3114 * well as other pmports.
3017 3115 *
3018 3116 * Therefore we directly reset the controller port for
3019 3117 * simplicity. ahci_tran_probe_port() will handle reset stuff
3020 3118 * like initializing the given pmport.
3021 3119 */
3022 3120 /* FALLTHRU */
3023 3121 case SATA_ADDR_CPORT:
3024 3122 /* Port reset */
3025 3123 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3026 3124 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3027 3125 "port %d reset port", instance, port);
3028 3126
3029 3127 mutex_enter(&ahci_portp->ahciport_mutex);
3030 3128 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, &addr);
3031 3129 mutex_exit(&ahci_portp->ahciport_mutex);
3032 3130
3033 3131 break;
3034 3132
3035 3133 case SATA_ADDR_DPMPORT:
3036 3134 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3037 3135 "port %d:%d reset device", instance, port, pmport);
3038 3136 /* FALLTHRU */
3039 3137 case SATA_ADDR_DCPORT:
3040 3138 /* Device reset */
3041 3139 if (sd->satadev_addr.qual == SATA_ADDR_DCPORT)
3042 3140 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3043 3141 "port %d reset device", instance, port);
3044 3142
3045 3143 mutex_enter(&ahci_portp->ahciport_mutex);
3046 3144 /*
3047 3145 * software reset request must be sent to SATA_PMULT_HOSTPORT
3048 3146 * if target is a port multiplier:
3049 3147 */
3050 3148 if (sd->satadev_addr.qual == SATA_ADDR_DCPORT &&
3051 3149 ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT)
3052 3150 AHCI_ADDR_SET_PMULT(&addr, port);
3053 3151
3054 3152 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED |
3055 3153 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN |
3056 3154 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) {
3057 3155 /*
3058 3156 * In case the targer driver would send the request
3059 3157 * before sata framework can have the opportunity to
3060 3158 * process those event reports.
3061 3159 */
3062 3160 sd->satadev_state = ahci_portp->ahciport_port_state;
3063 3161 ahci_update_sata_registers(ahci_ctlp, port, sd);
3064 3162 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3065 3163 "ahci_tran_reset_dport returning SATA_FAILURE "
3066 3164 "while port in FAILED/SHUTDOWN/PWROFF state: "
3067 3165 "port: %d", port);
3068 3166 mutex_exit(&ahci_portp->ahciport_mutex);
3069 3167 ret = SATA_FAILURE;
3070 3168 break;
3071 3169 }
3072 3170
3073 3171 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr) ==
3074 3172 SATA_DTYPE_NONE) {
3075 3173 /*
3076 3174 * ahci_intr_phyrdy_change() may have rendered it to
3077 3175 * AHCI_PORT_TYPE_NODEV.
3078 3176 */
3079 3177 sd->satadev_type = SATA_DTYPE_NONE;
3080 3178 sd->satadev_state = AHCIPORT_GET_STATE(ahci_portp,
3081 3179 &addr);
3082 3180 ahci_update_sata_registers(ahci_ctlp, port, sd);
3083 3181 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3084 3182 "ahci_tran_reset_dport returning SATA_FAILURE "
3085 3183 "while no device attached: port: %d", port);
3086 3184 mutex_exit(&ahci_portp->ahciport_mutex);
3087 3185 ret = SATA_FAILURE;
3088 3186 break;
3089 3187 }
3090 3188
3091 3189 if (AHCI_ADDR_IS_PORT(&addr)) {
3092 3190 ret = ahci_reset_device_reject_pkts(ahci_ctlp,
3093 3191 ahci_portp, &addr);
3094 3192 } else {
3095 3193 ret = ahci_reset_pmdevice_reject_pkts(ahci_ctlp,
3096 3194 ahci_portp, &addr);
3097 3195 }
3098 3196
3099 3197 mutex_exit(&ahci_portp->ahciport_mutex);
3100 3198 break;
3101 3199
3102 3200 case SATA_ADDR_CNTRL:
3103 3201 /* Reset the whole controller */
3104 3202 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3105 3203 "reset the whole hba", instance);
3106 3204 ret = ahci_reset_hba_reject_pkts(ahci_ctlp);
3107 3205 break;
3108 3206
3109 3207 default:
3110 3208 ret = SATA_FAILURE;
3111 3209 }
3112 3210
3113 3211 return (ret);
3114 3212 }
3115 3213
3116 3214 /*
3117 3215 * Called by sata framework to activate a port as part of hotplug.
3118 3216 * (cfgadm -c connect satax/y)
3119 3217 * Support port multiplier.
3120 3218 */
3121 3219 static int
3122 3220 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev)
3123 3221 {
3124 3222 ahci_ctl_t *ahci_ctlp;
3125 3223 ahci_port_t *ahci_portp;
3126 3224 ahci_addr_t addr;
3127 3225 uint8_t cport = satadev->satadev_addr.cport;
3128 3226 uint8_t pmport = satadev->satadev_addr.pmport;
3129 3227 uint8_t port;
3130 3228 int instance = ddi_get_instance(dip);
3131 3229
3132 3230 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
3133 3231 port = ahci_ctlp->ahcictl_cport_to_port[cport];
3134 3232
3135 3233 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
3136 3234 "ahci_tran_hotplug_port_activate enter: cport %d", cport);
3137 3235
3138 3236 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3139 3237
3140 3238 mutex_enter(&ahci_portp->ahciport_mutex);
3141 3239 ahci_get_ahci_addr(ahci_ctlp, satadev, &addr);
3142 3240 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMPORT(&addr));
3143 3241
3144 3242 if (AHCI_ADDR_IS_PORT(&addr)) {
3145 3243 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated",
3146 3244 instance, port);
3147 3245
3148 3246 /* Enable the interrupts on the port */
3149 3247 ahci_enable_port_intrs(ahci_ctlp, port);
3150 3248
3151 3249 /*
3152 3250 * Reset the port so that the PHY communication would be
3153 3251 * re-established. But this reset is an internal operation
3154 3252 * and the sata module doesn't need to know about it.
3155 3253 * Moreover, the port with a device attached will be started
3156 3254 * too.
3157 3255 */
3158 3256 (void) ahci_restart_port_wait_till_ready(ahci_ctlp,
3159 3257 ahci_portp, port,
3160 3258 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP,
3161 3259 NULL);
3162 3260
3163 3261 /*
3164 3262 * Need to check the link status and device status of the port
3165 3263 * and consider raising power if the port was in D3 state
3166 3264 */
3167 3265 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON;
3168 3266 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF;
3169 3267 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN;
3170 3268 } else if (AHCI_ADDR_IS_PMPORT(&addr)) {
3171 3269 cmn_err(CE_NOTE, "!ahci%d: ahci port %d:%d is activated",
3172 3270 instance, port, pmport);
3173 3271 /* AHCI_ADDR_PMPORT */
3174 3272 AHCIPORT_PMSTATE(ahci_portp, &addr) |= SATA_PSTATE_PWRON;
3175 3273 AHCIPORT_PMSTATE(ahci_portp, &addr) &=
3176 3274 ~(SATA_PSTATE_PWROFF|SATA_PSTATE_SHUTDOWN);
3177 3275 }
3178 3276
3179 3277 satadev->satadev_state = ahci_portp->ahciport_port_state;
3180 3278
3181 3279 ahci_update_sata_registers(ahci_ctlp, port, satadev);
3182 3280
3183 3281 mutex_exit(&ahci_portp->ahciport_mutex);
3184 3282 return (SATA_SUCCESS);
3185 3283 }
3186 3284
3187 3285 /*
3188 3286 * Called by sata framework to deactivate a port as part of hotplug.
3189 3287 * (cfgadm -c disconnect satax/y)
3190 3288 * Support port multiplier.
3191 3289 */
3192 3290 static int
3193 3291 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev)
3194 3292 {
3195 3293 ahci_ctl_t *ahci_ctlp;
3196 3294 ahci_port_t *ahci_portp;
3197 3295 ahci_addr_t addr;
3198 3296 uint8_t cport = satadev->satadev_addr.cport;
3199 3297 uint8_t pmport = satadev->satadev_addr.pmport;
3200 3298 uint8_t port;
3201 3299 uint32_t port_scontrol;
3202 3300 int instance = ddi_get_instance(dip);
3203 3301
3204 3302 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
3205 3303 port = ahci_ctlp->ahcictl_cport_to_port[cport];
3206 3304
3207 3305 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
3208 3306 "ahci_tran_hotplug_port_deactivate enter: cport %d", cport);
3209 3307
3210 3308 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3211 3309 mutex_enter(&ahci_portp->ahciport_mutex);
3212 3310 ahci_get_ahci_addr(ahci_ctlp, satadev, &addr);
3213 3311 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMPORT(&addr));
3214 3312
3215 3313 if (AHCI_ADDR_IS_PORT(&addr)) {
3216 3314 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated",
3217 3315 instance, port);
3218 3316
3219 3317 /* Disable the interrupts on the port */
3220 3318 ahci_disable_port_intrs(ahci_ctlp, port);
3221 3319
3222 3320 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) {
3223 3321
3224 3322 /* First to abort all the pending commands */
3225 3323 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
3226 3324
3227 3325 /* Then stop the port */
3228 3326 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
3229 3327 ahci_portp, port);
3230 3328 }
3231 3329
3232 3330 /* Next put the PHY offline */
3233 3331 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3234 3332 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
3235 3333 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE);
3236 3334 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, (uint32_t *)
3237 3335 AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol);
3238 3336 } else if (AHCI_ADDR_IS_PMPORT(&addr)) {
3239 3337 cmn_err(CE_NOTE, "!ahci%d: ahci port %d:%d is deactivated",
3240 3338 instance, port, pmport);
3241 3339
3242 3340 ahci_disable_port_intrs(ahci_ctlp, port);
3243 3341 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr)
3244 3342 != SATA_DTYPE_NONE)
3245 3343 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
3246 3344
3247 3345 /* Re-enable the interrupts for the other pmports */
3248 3346 ahci_enable_port_intrs(ahci_ctlp, port);
3249 3347 }
3250 3348
3251 3349 /* Update port state */
3252 3350 AHCIPORT_SET_STATE(ahci_portp, &addr, SATA_PSTATE_SHUTDOWN);
3253 3351 satadev->satadev_state = SATA_PSTATE_SHUTDOWN;
3254 3352
3255 3353 ahci_update_sata_registers(ahci_ctlp, port, satadev);
3256 3354
3257 3355 mutex_exit(&ahci_portp->ahciport_mutex);
3258 3356 return (SATA_SUCCESS);
3259 3357 }
3260 3358
3261 3359 /*
3262 3360 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED
3263 3361 * when a device is unplugged or a port is deactivated.
3264 3362 */
3265 3363 static void
3266 3364 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp,
3267 3365 ahci_port_t *ahci_portp, uint8_t port)
3268 3366 {
3269 3367 uint32_t slot_status = 0;
3270 3368 uint32_t abort_tags = 0;
3271 3369
3272 3370 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3273 3371
3274 3372 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
3275 3373 "ahci_reject_all_abort_pkts at port: %d", port);
3276 3374
3277 3375 /* Read/write port multiplier command takes highest priority */
3278 3376 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
3279 3377 slot_status = 0x1;
3280 3378 abort_tags = 0x1;
3281 3379 goto out;
3282 3380 }
3283 3381
3284 3382 /*
3285 3383 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a
3286 3384 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA
3287 3385 * to get the error data, if yes when the device is removed, the
3288 3386 * command needs to be aborted too.
3289 3387 */
3290 3388 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
3291 3389 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
3292 3390 slot_status = 0x1;
3293 3391 abort_tags = 0x1;
3294 3392 goto out;
3295 3393 } else {
3296 3394 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3297 3395 "ahci_reject_all_abort_pkts return directly "
3298 3396 "port %d no needs to reject any outstanding "
3299 3397 "commands", port);
3300 3398 return;
3301 3399 }
3302 3400 }
3303 3401
3304 3402 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
3305 3403 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3306 3404 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
3307 3405 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
3308 3406 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
3309 3407 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3310 3408 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
3311 3409 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
3312 3410 }
3313 3411
3314 3412 out:
3315 3413 /* No need to do mop when there is no outstanding commands */
3316 3414 if (slot_status != 0) {
3317 3415 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
3318 3416 ahci_portp->ahciport_mop_in_progress++;
3319 3417
3320 3418 ahci_mop_commands(ahci_ctlp,
3321 3419 ahci_portp,
3322 3420 slot_status,
3323 3421 0, /* failed tags */
3324 3422 0, /* timeout tags */
3325 3423 abort_tags, /* aborting tags */
3326 3424 0); /* reset tags */
3327 3425 }
3328 3426 }
3329 3427
3330 3428 #if defined(__lock_lint)
3331 3429 static int
3332 3430 ahci_selftest(dev_info_t *dip, sata_device_t *device)
3333 3431 {
3334 3432 return (SATA_SUCCESS);
3335 3433 }
3336 3434 #endif
3337 3435
3338 3436 /*
3339 3437 * Initialize fma capabilities and register with IO fault services.
3340 3438 */
3341 3439 static void
3342 3440 ahci_fm_init(ahci_ctl_t *ahci_ctlp)
3343 3441 {
3344 3442 /*
3345 3443 * Need to change iblock to priority for new MSI intr
3346 3444 */
3347 3445 ddi_iblock_cookie_t fm_ibc;
3348 3446
3349 3447 ahci_ctlp->ahcictl_fm_cap = ddi_getprop(DDI_DEV_T_ANY,
3350 3448 ahci_ctlp->ahcictl_dip,
3351 3449 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
3352 3450 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
3353 3451 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
3354 3452
3355 3453 /* Only register with IO Fault Services if we have some capability */
3356 3454 if (ahci_ctlp->ahcictl_fm_cap) {
3357 3455 /* Adjust access and dma attributes for FMA */
3358 3456 accattr.devacc_attr_access = DDI_FLAGERR_ACC;
3359 3457 buffer_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3360 3458 rcvd_fis_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3361 3459 cmd_list_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3362 3460 cmd_table_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3363 3461
3364 3462 /*
3365 3463 * Register capabilities with IO Fault Services.
3366 3464 * ahcictl_fm_cap will be updated to indicate
3367 3465 * capabilities actually supported (not requested.)
3368 3466 */
3369 3467 ddi_fm_init(ahci_ctlp->ahcictl_dip,
3370 3468 &ahci_ctlp->ahcictl_fm_cap, &fm_ibc);
3371 3469
3372 3470 if (ahci_ctlp->ahcictl_fm_cap == DDI_FM_NOT_CAPABLE) {
3373 3471 cmn_err(CE_WARN, "!ahci%d: fma init failed.",
3374 3472 ddi_get_instance(ahci_ctlp->ahcictl_dip));
3375 3473 return;
3376 3474 }
3377 3475 /*
3378 3476 * Initialize pci ereport capabilities if ereport
3379 3477 * capable (should always be.)
3380 3478 */
3381 3479 if (DDI_FM_EREPORT_CAP(ahci_ctlp->ahcictl_fm_cap) ||
3382 3480 DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3383 3481 pci_ereport_setup(ahci_ctlp->ahcictl_dip);
3384 3482 }
3385 3483
3386 3484 /*
3387 3485 * Register error callback if error callback capable.
3388 3486 */
3389 3487 if (DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3390 3488 ddi_fm_handler_register(ahci_ctlp->ahcictl_dip,
3391 3489 ahci_fm_error_cb, (void *) ahci_ctlp);
3392 3490 }
3393 3491
3394 3492 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3395 3493 "ahci_fm_fini: fma enabled.", NULL);
3396 3494 }
3397 3495 }
3398 3496
3399 3497 /*
3400 3498 * Releases fma capabilities and un-registers with IO fault services.
3401 3499 */
3402 3500 static void
3403 3501 ahci_fm_fini(ahci_ctl_t *ahci_ctlp)
3404 3502 {
3405 3503 /* Only unregister FMA capabilities if registered */
3406 3504 if (ahci_ctlp->ahcictl_fm_cap) {
3407 3505 /*
3408 3506 * Un-register error callback if error callback capable.
3409 3507 */
3410 3508 if (DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3411 3509 ddi_fm_handler_unregister(ahci_ctlp->ahcictl_dip);
3412 3510 }
3413 3511
3414 3512 /*
3415 3513 * Release any resources allocated by pci_ereport_setup()
3416 3514 */
3417 3515 if (DDI_FM_EREPORT_CAP(ahci_ctlp->ahcictl_fm_cap) ||
3418 3516 DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3419 3517 pci_ereport_teardown(ahci_ctlp->ahcictl_dip);
3420 3518 }
3421 3519
3422 3520 /* Unregister from IO Fault Services */
3423 3521 ddi_fm_fini(ahci_ctlp->ahcictl_dip);
3424 3522
3425 3523 /* Adjust access and dma attributes for FMA */
3426 3524 accattr.devacc_attr_access = DDI_DEFAULT_ACC;
3427 3525 buffer_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3428 3526 rcvd_fis_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3429 3527 cmd_list_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3430 3528 cmd_table_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3431 3529
3432 3530 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3433 3531 "ahci_fm_fini: fma disabled.", NULL);
3434 3532 }
3435 3533 }
3436 3534
3437 3535 /*ARGSUSED*/
3438 3536 static int
3439 3537 ahci_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
3440 3538 {
3441 3539 /*
3442 3540 * as the driver can always deal with an error in any dma or
3443 3541 * access handle, we can just return the fme_status value.
3444 3542 */
3445 3543 pci_ereport_post(dip, err, NULL);
3446 3544 return (err->fme_status);
3447 3545 }
3448 3546
3449 3547 int
3450 3548 ahci_check_acc_handle(ddi_acc_handle_t handle)
3451 3549 {
3452 3550 ddi_fm_error_t de;
3453 3551
3454 3552 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
3455 3553 return (de.fme_status);
3456 3554 }
3457 3555
3458 3556 int
3459 3557 ahci_check_dma_handle(ddi_dma_handle_t handle)
3460 3558 {
3461 3559 ddi_fm_error_t de;
3462 3560
3463 3561 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
3464 3562 return (de.fme_status);
3465 3563 }
3466 3564
3467 3565 /*
3468 3566 * Generate an ereport
3469 3567 */
3470 3568 void
3471 3569 ahci_fm_ereport(ahci_ctl_t *ahci_ctlp, char *detail)
3472 3570 {
3473 3571 uint64_t ena;
3474 3572 char buf[FM_MAX_CLASS];
3475 3573
3476 3574 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
3477 3575 ena = fm_ena_generate(0, FM_ENA_FMT1);
3478 3576 if (DDI_FM_EREPORT_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3479 3577 ddi_fm_ereport_post(ahci_ctlp->ahcictl_dip, buf, ena,
3480 3578 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8,
3481 3579 FM_EREPORT_VERSION, NULL);
3482 3580 }
3483 3581 }
3484 3582
3485 3583 /*
3486 3584 * Check if all handles are correctly allocated.
3487 3585 */
3488 3586 static int
3489 3587 ahci_check_all_handle(ahci_ctl_t *ahci_ctlp)
3490 3588 {
3491 3589 int port;
3492 3590
3493 3591 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) {
3494 3592 return (DDI_FAILURE);
3495 3593 }
3496 3594
3497 3595 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3498 3596 ahci_port_t *ahci_portp;
3499 3597
3500 3598 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port))
3501 3599 continue;
3502 3600
3503 3601 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3504 3602
3505 3603 mutex_enter(&ahci_portp->ahciport_mutex);
3506 3604 if (ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS) {
3507 3605 mutex_exit(&ahci_portp->ahciport_mutex);
3508 3606 return (DDI_FAILURE);
3509 3607 }
3510 3608 mutex_exit(&ahci_portp->ahciport_mutex);
3511 3609 }
3512 3610
3513 3611 return (DDI_SUCCESS);
3514 3612 }
3515 3613
3516 3614 /*
3517 3615 * Check the access handles for the controller. Note that
3518 3616 * ahcictl_pci_conf_handle is only used in attach process.
3519 3617 */
3520 3618 static int
3521 3619 ahci_check_ctl_handle(ahci_ctl_t *ahci_ctlp)
3522 3620 {
3523 3621 if ((ahci_check_acc_handle(ahci_ctlp->
3524 3622 ahcictl_pci_conf_handle) != DDI_FM_OK) ||
3525 3623 (ahci_check_acc_handle(ahci_ctlp->
3526 3624 ahcictl_ahci_acc_handle) != DDI_FM_OK)) {
3527 3625 return (DDI_FAILURE);
3528 3626 }
3529 3627 return (DDI_SUCCESS);
3530 3628 }
3531 3629
3532 3630 /*
3533 3631 * Check the DMA handles and the access handles of a controller port.
3534 3632 */
3535 3633 static int
3536 3634 ahci_check_port_handle(ahci_ctl_t *ahci_ctlp, int port)
3537 3635 {
3538 3636 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port];
3539 3637 int slot;
3540 3638
3541 3639 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3542 3640
3543 3641 if ((ahci_check_dma_handle(ahci_portp->
3544 3642 ahciport_rcvd_fis_dma_handle) != DDI_FM_OK) ||
3545 3643 (ahci_check_dma_handle(ahci_portp->
3546 3644 ahciport_cmd_list_dma_handle) != DDI_FM_OK) ||
3547 3645 (ahci_check_acc_handle(ahci_portp->
3548 3646 ahciport_rcvd_fis_acc_handle) != DDI_FM_OK) ||
3549 3647 (ahci_check_acc_handle(ahci_portp->
3550 3648 ahciport_cmd_list_acc_handle) != DDI_FM_OK)) {
3551 3649 return (DDI_FAILURE);
3552 3650 }
3553 3651 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) {
3554 3652 if (ahci_check_slot_handle(ahci_portp, slot)
3555 3653 != DDI_SUCCESS) {
3556 3654 return (DDI_FAILURE);
3557 3655 }
3558 3656 }
3559 3657 return (DDI_SUCCESS);
3560 3658 }
3561 3659
3562 3660 /*
3563 3661 * Check the DMA handles and the access handles of a cmd table slot.
3564 3662 */
3565 3663 static int
3566 3664 ahci_check_slot_handle(ahci_port_t *ahci_portp, int slot)
3567 3665 {
3568 3666 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3569 3667
3570 3668 if ((ahci_check_acc_handle(ahci_portp->
3571 3669 ahciport_cmd_tables_acc_handle[slot]) != DDI_FM_OK) ||
3572 3670 (ahci_check_dma_handle(ahci_portp->
3573 3671 ahciport_cmd_tables_dma_handle[slot]) != DDI_FM_OK)) {
3574 3672 return (DDI_FAILURE);
3575 3673 }
3576 3674 return (DDI_SUCCESS);
3577 3675 }
3578 3676
3579 3677 /*
3580 3678 * Allocate the ports structure, only called by ahci_attach
3581 3679 */
3582 3680 static int
3583 3681 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp)
3584 3682 {
3585 3683 int port, cport = 0;
3586 3684
3587 3685 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
3588 3686 "ahci_alloc_ports_state enter", NULL);
3589 3687
3590 3688 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3591 3689
3592 3690 /* Allocate structures only for the implemented ports */
3593 3691 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3594 3692 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3595 3693 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3596 3694 "hba port %d not implemented", port);
3597 3695 continue;
3598 3696 }
3599 3697
3600 3698 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port;
3601 3699 ahci_ctlp->ahcictl_port_to_cport[port] =
3602 3700 (uint8_t)cport++;
3603 3701
3604 3702 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) {
3605 3703 goto err_out;
3606 3704 }
3607 3705 }
3608 3706
3609 3707 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3610 3708 return (AHCI_SUCCESS);
3611 3709
3612 3710 err_out:
3613 3711 for (port--; port >= 0; port--) {
3614 3712 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3615 3713 ahci_dealloc_port_state(ahci_ctlp, port);
3616 3714 }
3617 3715 }
3618 3716
3619 3717 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3620 3718 return (AHCI_FAILURE);
3621 3719 }
3622 3720
3623 3721 /*
3624 3722 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach
3625 3723 */
3626 3724 static void
3627 3725 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp)
3628 3726 {
3629 3727 int port;
3630 3728
3631 3729 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3632 3730 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3633 3731 /* if this port is implemented by the HBA */
3634 3732 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port))
3635 3733 ahci_dealloc_port_state(ahci_ctlp, port);
3636 3734 }
3637 3735 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3638 3736 }
3639 3737
3640 3738 /*
3641 3739 * Drain the taskq.
3642 3740 */
3643 3741 static void
3644 3742 ahci_drain_ports_taskq(ahci_ctl_t *ahci_ctlp)
3645 3743 {
3646 3744 ahci_port_t *ahci_portp;
3647 3745 int port;
3648 3746
3649 3747 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3650 3748 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3651 3749 continue;
3652 3750 }
3653 3751
3654 3752 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3655 3753
3656 3754 mutex_enter(&ahci_portp->ahciport_mutex);
3657 3755 ddi_taskq_wait(ahci_portp->ahciport_event_taskq);
3658 3756 mutex_exit(&ahci_portp->ahciport_mutex);
3659 3757 }
3660 3758 }
3661 3759
3662 3760 /*
3663 3761 * Initialize the controller and all ports. And then try to start the ports
3664 3762 * if there are devices attached.
3665 3763 *
3666 3764 * This routine can be called from three seperate cases: DDI_ATTACH,
3667 3765 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from
3668 3766 * other two cases; device signature probing are attempted only during
3669 3767 * DDI_ATTACH case.
3670 3768 */
3671 3769 static int
3672 3770 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp)
3673 3771 {
3674 3772 ahci_port_t *ahci_portp;
3675 3773 ahci_addr_t addr;
3676 3774 int port;
3677 3775
3678 3776 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
3679 3777 "ahci_initialize_controller enter", NULL);
3680 3778
3681 3779 /* Disable the whole controller interrupts */
3682 3780 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3683 3781 ahci_disable_all_intrs(ahci_ctlp);
3684 3782 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3685 3783
3686 3784 /* Initialize the implemented ports and structures */
3687 3785 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3688 3786 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3689 3787 continue;
3690 3788 }
3691 3789
3692 3790 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3693 3791 mutex_enter(&ahci_portp->ahciport_mutex);
3694 3792
3695 3793 /*
3696 3794 * Ensure that the controller is not in the running state
3697 3795 * by checking every implemented port's PxCMD register
3698 3796 */
3699 3797 AHCI_ADDR_SET_PORT(&addr, (uint8_t)port);
3700 3798
3701 3799 if (ahci_initialize_port(ahci_ctlp, ahci_portp, &addr)
3702 3800 != AHCI_SUCCESS) {
3703 3801 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3704 3802 "ahci_initialize_controller: failed to "
3705 3803 "initialize port %d", port);
3706 3804 /*
3707 3805 * Set the port state to SATA_PSTATE_FAILED if
3708 3806 * failed to initialize it.
3709 3807 */
3710 3808 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED;
3711 3809 }
3712 3810
3713 3811 mutex_exit(&ahci_portp->ahciport_mutex);
3714 3812 }
3715 3813
3716 3814 /* Enable the whole controller interrupts */
3717 3815 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3718 3816 ahci_enable_all_intrs(ahci_ctlp);
3719 3817 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3720 3818
3721 3819 return (AHCI_SUCCESS);
3722 3820 }
3723 3821
3724 3822 /*
3725 3823 * Reverse of ahci_initialize_controller()
3726 3824 *
3727 3825 * We only need to stop the ports and disable the interrupt.
3728 3826 */
3729 3827 static void
3730 3828 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp)
3731 3829 {
3732 3830 ahci_port_t *ahci_portp;
3733 3831 int port;
3734 3832
3735 3833 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3736 3834 "ahci_uninitialize_controller enter", NULL);
3737 3835
3738 3836 /* disable all the interrupts. */
3739 3837 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3740 3838 ahci_disable_all_intrs(ahci_ctlp);
3741 3839 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3742 3840
3743 3841 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3744 3842 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3745 3843 continue;
3746 3844 }
3747 3845
3748 3846 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3749 3847
3750 3848 /* Stop the port by clearing PxCMD.ST */
3751 3849 mutex_enter(&ahci_portp->ahciport_mutex);
3752 3850
3753 3851 /*
3754 3852 * Here we must disable the port interrupt because
3755 3853 * ahci_disable_all_intrs only clear GHC.IE, and IS
3756 3854 * register will be still set if PxIE is enabled.
3757 3855 * When ahci shares one IRQ with other drivers, the
3758 3856 * intr handler may claim the intr mistakenly.
3759 3857 */
3760 3858 ahci_disable_port_intrs(ahci_ctlp, port);
3761 3859 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
3762 3860 ahci_portp, port);
3763 3861 mutex_exit(&ahci_portp->ahciport_mutex);
3764 3862 }
3765 3863 }
3766 3864
3767 3865 /*
3768 3866 * ahci_alloc_pmult()
3769 3867 * 1. Setting HBA port registers which are necessary for a port multiplier.
3770 3868 * (Set PxCMD.PMA while PxCMD.ST is '0')
3771 3869 * 2. Allocate ahci_pmult_info structure.
3772 3870 *
3773 3871 * NOTE: Must stop port before the function is called.
3774 3872 */
3775 3873 static void
3776 3874 ahci_alloc_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
3777 3875 {
3778 3876 uint32_t port_cmd_status;
3779 3877 uint8_t port = ahci_portp->ahciport_port_num;
3780 3878
3781 3879 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3782 3880
3783 3881 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3784 3882 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3785 3883
3786 3884 /* The port must have been stopped before. */
3787 3885 ASSERT(!(port_cmd_status & AHCI_CMD_STATUS_ST));
3788 3886
3789 3887 if (!(port_cmd_status & AHCI_CMD_STATUS_PMA)) {
3790 3888 /* set PMA bit */
3791 3889 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
3792 3890 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
3793 3891 port_cmd_status|AHCI_CMD_STATUS_PMA);
3794 3892
3795 3893 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
3796 3894 "ahci_alloc_pmult: "
3797 3895 "PxCMD.PMA bit set at port %d.", port);
3798 3896 }
3799 3897
3800 3898 /* Allocate port multiplier information structure */
3801 3899 if (ahci_portp->ahciport_pmult_info == NULL) {
3802 3900 ahci_portp->ahciport_pmult_info = (ahci_pmult_info_t *)
3803 3901 kmem_zalloc(sizeof (ahci_pmult_info_t), KM_SLEEP);
3804 3902 }
3805 3903
3806 3904 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
3807 3905 }
3808 3906
3809 3907 /*
3810 3908 * ahci_dealloc_pmult()
3811 3909 * 1. Clearing related registers when a port multiplier is detached.
3812 3910 * (Clear PxCMD.PMA while PxCMD.ST is '0')
3813 3911 * 2. Deallocate ahci_pmult_info structure.
3814 3912 *
3815 3913 * NOTE: Must stop port before the function is called.
3816 3914 */
3817 3915 static void
3818 3916 ahci_dealloc_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
3819 3917 {
3820 3918 uint32_t port_cmd_status;
3821 3919 uint8_t port = ahci_portp->ahciport_port_num;
3822 3920
3823 3921 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3824 3922
3825 3923 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3826 3924 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3827 3925
3828 3926 if (port_cmd_status & AHCI_CMD_STATUS_PMA) {
3829 3927 /* Clear PMA bit */
3830 3928 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
3831 3929 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
3832 3930 (port_cmd_status & (~AHCI_CMD_STATUS_PMA)));
3833 3931
3834 3932 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
3835 3933 "ahci_dealloc_pmult: "
3836 3934 "PxCMD.PMA bit cleared at port %d.", port);
3837 3935 }
3838 3936
3839 3937 /* Release port multiplier information structure */
3840 3938 if (ahci_portp->ahciport_pmult_info != NULL) {
3841 3939 kmem_free(ahci_portp->ahciport_pmult_info,
3842 3940 sizeof (ahci_pmult_info_t));
3843 3941 ahci_portp->ahciport_pmult_info = NULL;
3844 3942 }
3845 3943 }
3846 3944
3847 3945 /*
3848 3946 * Staggered Spin-up.
3849 3947 */
3850 3948 static void
3851 3949 ahci_staggered_spin_up(ahci_ctl_t *ahci_ctlp, uint8_t port)
3852 3950 {
3853 3951 uint32_t cap_status;
3854 3952 uint32_t port_cmd_status;
3855 3953
3856 3954 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
3857 3955
3858 3956 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3859 3957 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp));
3860 3958
3861 3959 /* Check for staggered spin-up support */
3862 3960 if (!(cap_status & AHCI_HBA_CAP_SSS))
3863 3961 return;
3864 3962
3865 3963 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3866 3964 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3867 3965
3868 3966 /* If PxCMD.SUD == 1, no staggered spin-up is needed */
3869 3967 if (port_cmd_status & AHCI_CMD_STATUS_SUD)
3870 3968 return;
3871 3969
3872 3970 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "Spin-up at port %d", port);
3873 3971
3874 3972 /* Set PxCMD.SUD */
3875 3973 port_cmd_status |= AHCI_CMD_STATUS_SUD;
3876 3974 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
3877 3975 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
3878 3976 port_cmd_status);
3879 3977 }
3880 3978
3881 3979 /*
3882 3980 * The routine is to initialize a port. First put the port in NotRunning
3883 3981 * state, then enable port interrupt and clear Serror register. And under
3884 3982 * AHCI_ATTACH case, find device signature and then try to start the port.
3885 3983 *
3886 3984 * Called by
3887 3985 * 1. ahci_initialize_controller
3888 3986 * 2. ahci_intr_phyrdy_change (hotplug)
3889 3987 */
3890 3988 static int
3891 3989 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
3892 3990 ahci_addr_t *addrp)
3893 3991 {
3894 3992 uint32_t port_sstatus, port_task_file, port_cmd_status;
3895 3993 uint8_t port = addrp->aa_port;
3896 3994 boolean_t resuming = B_TRUE; /* processing DDI_RESUME */
3897 3995 int ret;
3898 3996
3899 3997 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3900 3998
3901 3999 /* AHCI_ADDR_PORT: We've no idea of the attached device here. */
3902 4000 ASSERT(AHCI_ADDR_IS_PORT(addrp));
3903 4001
3904 4002 /*
3905 4003 * At the time being, only probe ports/devices and get the types of
3906 4004 * attached devices during DDI_ATTACH. In fact, the device can be
3907 4005 * changed during power state changes, but at the time being, we
3908 4006 * don't support the situation.
3909 4007 */
3910 4008 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) {
3911 4009 resuming = B_FALSE;
3912 4010 } else {
3913 4011 /* check for DDI_RESUME case */
3914 4012 mutex_exit(&ahci_portp->ahciport_mutex);
3915 4013 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3916 4014 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH)
3917 4015 resuming = B_FALSE;
3918 4016 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3919 4017 mutex_enter(&ahci_portp->ahciport_mutex);
3920 4018 }
3921 4019
3922 4020 if (resuming) {
3923 4021 /*
3924 4022 * During the resume, we need to set the PxCLB, PxCLBU, PxFB
3925 4023 * and PxFBU registers in case these registers were cleared
3926 4024 * during the suspend.
3927 4025 */
3928 4026 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
3929 4027 "ahci_initialize_port: port %d "
3930 4028 "set PxCLB, PxCLBU, PxFB and PxFBU "
3931 4029 "during resume", port);
3932 4030
3933 4031 if (ahci_setup_port_base_addresses(ahci_ctlp, ahci_portp) !=
3934 4032 AHCI_SUCCESS)
3935 4033 return (AHCI_FAILURE);
3936 4034 }
3937 4035
3938 4036 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3939 4037 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3940 4038
3941 4039 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
3942 4040 "ahci_initialize_port: port %d ", port);
3943 4041
3944 4042 /*
3945 4043 * Check whether the port is in NotRunning state, if not,
3946 4044 * put the port in NotRunning state
3947 4045 */
3948 4046 if (port_cmd_status &
3949 4047 (AHCI_CMD_STATUS_ST |
3950 4048 AHCI_CMD_STATUS_CR |
3951 4049 AHCI_CMD_STATUS_FRE |
3952 4050 AHCI_CMD_STATUS_FR)) {
3953 4051 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
3954 4052 ahci_portp, port);
3955 4053 }
3956 4054
3957 4055 /* Make sure the drive is spun-up */
3958 4056 ahci_staggered_spin_up(ahci_ctlp, port);
3959 4057
3960 4058 /* Disable interrupt */
3961 4059 ahci_disable_port_intrs(ahci_ctlp, port);
3962 4060
3963 4061 /* Device is unknown at first */
3964 4062 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
3965 4063
3966 4064 /* Disable the interface power management */
3967 4065 ahci_disable_interface_pm(ahci_ctlp, port);
3968 4066
3969 4067 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3970 4068 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
3971 4069 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3972 4070 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
3973 4071
3974 4072 /* Check physcial link status */
3975 4073 if (SSTATUS_GET_IPM(port_sstatus) == SSTATUS_IPM_NODEV_NOPHYCOM ||
3976 4074 SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_NOPHYCOM ||
3977 4075
3978 4076 /* Check interface status */
3979 4077 port_task_file & AHCI_TFD_STS_BSY ||
3980 4078 port_task_file & AHCI_TFD_STS_DRQ ||
3981 4079
3982 4080 /* Check whether port reset must be executed */
3983 4081 ahci_ctlp->ahcictl_cap & AHCI_CAP_INIT_PORT_RESET ||
3984 4082
3985 4083 /* Always reset port on RESUME */
3986 4084 resuming != B_FALSE) {
3987 4085
3988 4086 /* Something went wrong, we need do some reset things */
3989 4087 ret = ahci_port_reset(ahci_ctlp, ahci_portp, addrp);
3990 4088
3991 4089 /* Does port reset succeed on HBA port? */
3992 4090 if (ret != AHCI_SUCCESS) {
3993 4091 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
3994 4092 "ahci_initialize_port:"
3995 4093 "port reset failed at port %d", port);
3996 4094 return (AHCI_FAILURE);
3997 4095 }
3998 4096
3999 4097 /* Is port failed? */
4000 4098 if (AHCIPORT_GET_STATE(ahci_portp, addrp) &
4001 4099 SATA_PSTATE_FAILED) {
4002 4100 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
4003 4101 "ahci_initialize_port: port %d state 0x%x",
4004 4102 port, ahci_portp->ahciport_port_state);
4005 4103 return (AHCI_FAILURE);
4006 4104 }
4007 4105 }
4008 4106
4009 4107 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_READY);
4010 4108 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "port %d is ready now.", port);
4011 4109
4012 4110 /*
4013 4111 * Try to get the device signature if the port is not empty.
4014 4112 */
4015 4113 if (!resuming && AHCIPORT_DEV_TYPE(ahci_portp, addrp) !=
4016 4114 SATA_DTYPE_NONE)
4017 4115 ahci_find_dev_signature(ahci_ctlp, ahci_portp, addrp);
4018 4116
4019 4117 /* Return directly if no device connected */
4020 4118 if (AHCIPORT_DEV_TYPE(ahci_portp, addrp) == SATA_DTYPE_NONE) {
4021 4119 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4022 4120 "No device connected to port %d", port);
4023 4121 goto out;
4024 4122 }
4025 4123
4026 4124 /* If this is a port multiplier, we need do some initialization */
4027 4125 if (AHCIPORT_DEV_TYPE(ahci_portp, addrp) == SATA_DTYPE_PMULT) {
4028 4126 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4029 4127 "Port multiplier found at port %d", port);
4030 4128 ahci_alloc_pmult(ahci_ctlp, ahci_portp);
4031 4129 }
4032 4130
4033 4131 /* Try to start the port */
4034 4132 if (ahci_start_port(ahci_ctlp, ahci_portp, port)
4035 4133 != AHCI_SUCCESS) {
4036 4134 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4037 4135 "failed to start port %d", port);
4038 4136 return (AHCI_FAILURE);
4039 4137 }
4040 4138 out:
4041 4139 /* Enable port interrupts */
4042 4140 ahci_enable_port_intrs(ahci_ctlp, port);
4043 4141
4044 4142 return (AHCI_SUCCESS);
4045 4143 }
4046 4144
4047 4145 /*
4048 4146 * Handle hardware defect, and check the capabilities. For example,
4049 4147 * power management capabilty and MSI capability.
4050 4148 */
4051 4149 static int
4052 4150 ahci_config_space_init(ahci_ctl_t *ahci_ctlp)
4053 4151 {
4054 4152 ushort_t caps_ptr, cap_count, cap;
4055 4153 #if AHCI_DEBUG
4056 4154 ushort_t pmcap, pmcsr;
4057 4155 ushort_t msimc;
4058 4156 #endif
4059 4157 uint8_t revision;
4060 4158
4061 4159 ahci_ctlp->ahcictl_venid =
4062 4160 pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle,
4063 4161 PCI_CONF_VENID);
4064 4162
4065 4163 ahci_ctlp->ahcictl_devid =
4066 4164 pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle,
4067 4165 PCI_CONF_DEVID);
4068 4166
4069 4167 /*
4070 4168 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those
4071 4169 * controllers with 0x00 revision id work on 4-byte aligned buffer,
4072 4170 * which is a bug and was fixed after 0x00 revision id controllers.
4073 4171 *
4074 4172 * Moreover, VT8251 cannot use multiple command slots in the command
4075 4173 * list for non-queued commands because the previous register content
4076 4174 * of PxCI can be re-written in the register write, so a flag will be
4077 4175 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE.
4078 4176 *
4079 4177 * For VT8251, software reset also has the same defect as the below
4080 4178 * AMD/ATI chipset. That is, software reset will get failed if 0xf
4081 4179 * is filled in pmport field. Therefore, another software reset need
4082 4180 * to be done with 0 filled in pmport field.
4083 4181 */
4084 4182 if (ahci_ctlp->ahcictl_venid == VIA_VENID) {
4085 4183 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle,
4086 4184 PCI_CONF_REVID);
4087 4185 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4088 4186 "revision id = 0x%x", revision);
4089 4187 if (revision == 0x00) {
4090 4188 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4;
4091 4189 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4092 4190 "change ddi_attr_align to 0x4", NULL);
4093 4191 }
4094 4192
4095 4193 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NO_MCMDLIST_NONQUEUE;
4096 4194 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4097 4195 "VT8251 cannot use multiple command lists for "
4098 4196 "non-queued commands", NULL);
4099 4197
4100 4198 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT;
4101 4199 }
4102 4200
4103 4201 /*
4104 4202 * AMD/ATI SB600 (0x1002,0x4380) AHCI chipset doesn't support 64-bit
4105 4203 * DMA addressing for communication memory descriptors though S64A bit
4106 4204 * of CAP register declares it supports. Even though 64-bit DMA for
4107 4205 * data buffer works on ASUS M2A-VM with newer BIOS, three other
4108 4206 * motherboards are known not, so both AHCI_CAP_BUF_32BIT_DMA and
4109 4207 * AHCI_CAP_COMMU_32BIT_DMA are set for this controller.
4110 4208 *
4111 4209 * Due to certain hardware issue, the chipset must do port reset during
4112 4210 * initialization, otherwise, when retrieving device signature,
4113 4211 * software reset will get time out. So AHCI_CAP_INIT_PORT_RESET flag
4114 4212 * need to set.
4115 4213 *
4116 4214 * For this chipset software reset will get failure if the pmport of
4117 4215 * Register FIS was set with SATA_PMULT_HOSTPORT (0xf) and no port
4118 4216 * multiplier is connected to the port. In order to fix the issue,
4119 4217 * AHCI_CAP_SRST_NO_HOSTPORT flag need to be set, and once software
4120 4218 * reset got failure, the driver will try to do another software reset
4121 4219 * with pmport 0.
4122 4220 */
4123 4221 if (ahci_ctlp->ahcictl_venid == 0x1002 &&
4124 4222 ahci_ctlp->ahcictl_devid == 0x4380) {
4125 4223 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA;
4126 4224 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA;
4127 4225 ahci_ctlp->ahcictl_cap |= AHCI_CAP_INIT_PORT_RESET;
4128 4226 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT;
4129 4227
4130 4228 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4131 4229 "ATI SB600 cannot do 64-bit DMA for both data buffer and "
4132 4230 "communication memory descriptors though CAP indicates "
4133 4231 "support, so force it to use 32-bit DMA", NULL);
4134 4232 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4135 4233 "ATI SB600 need to do a port reset during initialization",
4136 4234 NULL);
4137 4235 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4138 4236 "ATI SB600 will get software reset failure if pmport "
4139 4237 "is set 0xf and no port multiplier is attached", NULL);
4140 4238 }
4141 4239
4142 4240 /*
4143 4241 * AMD/ATI SB700/710/750/800 and SP5100 AHCI chipset share the same
4144 4242 * vendor ID and device ID (0x1002,0x4391).
4145 4243 *
4146 4244 * SB700/750 AHCI chipset on some boards doesn't support 64-bit
4147 4245 * DMA addressing for communication memory descriptors though S64A bit
4148 4246 * of CAP register declares the support. However, it does support
4149 4247 * 64-bit DMA for data buffer. So only AHCI_CAP_COMMU_32BIT_DMA is
4150 4248 * set for this controller.
4151 4249 *
4152 4250 * SB710 has the same initialization issue as SB600, so it also need
4153 4251 * a port reset. That is AHCI_CAP_INIT_PORT_RESET need to set for it.
4154 4252 *
4155 4253 * SB700 also has the same issue about software reset, and thus
4156 4254 * AHCI_CAP_SRST_NO_HOSTPORT flag also is needed.
4157 4255 */
4158 4256 if (ahci_ctlp->ahcictl_venid == 0x1002 &&
4159 4257 ahci_ctlp->ahcictl_devid == 0x4391) {
4160 4258 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA;
4161 4259 ahci_ctlp->ahcictl_cap |= AHCI_CAP_INIT_PORT_RESET;
4162 4260 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT;
4163 4261
4164 4262 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4165 4263 "ATI SB700/750 cannot do 64-bit DMA for communication "
4166 4264 "memory descriptors though CAP indicates support, "
4167 4265 "so force it to use 32-bit DMA", NULL);
4168 4266 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4169 4267 "ATI SB710 need to do a port reset during initialization",
4170 4268 NULL);
4171 4269 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4172 4270 "ATI SB700 will get software reset failure if pmport "
4173 4271 "is set 0xf and no port multiplier is attached", NULL);
4174 4272 }
4175 4273
4176 4274 /*
4177 4275 * Check if capabilities list is supported and if so,
4178 4276 * get initial capabilities pointer and clear bits 0,1.
4179 4277 */
4180 4278 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle,
4181 4279 PCI_CONF_STAT) & PCI_STAT_CAP) {
4182 4280 caps_ptr = P2ALIGN(pci_config_get8(
4183 4281 ahci_ctlp->ahcictl_pci_conf_handle,
4184 4282 PCI_CONF_CAP_PTR), 4);
4185 4283 } else {
4186 4284 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
4187 4285 }
4188 4286
4189 4287 /*
4190 4288 * Walk capabilities if supported.
4191 4289 */
4192 4290 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
4193 4291
4194 4292 /*
4195 4293 * Check that we haven't exceeded the maximum number of
4196 4294 * capabilities and that the pointer is in a valid range.
4197 4295 */
4198 4296 if (++cap_count > PCI_CAP_MAX_PTR) {
4199 4297 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4200 4298 "too many device capabilities", NULL);
4201 4299 return (AHCI_FAILURE);
4202 4300 }
4203 4301 if (caps_ptr < PCI_CAP_PTR_OFF) {
4204 4302 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4205 4303 "capabilities pointer 0x%x out of range",
4206 4304 caps_ptr);
4207 4305 return (AHCI_FAILURE);
4208 4306 }
4209 4307
4210 4308 /*
4211 4309 * Get next capability and check that it is valid.
4212 4310 * For now, we only support power management.
4213 4311 */
4214 4312 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle,
4215 4313 caps_ptr);
4216 4314 switch (cap) {
4217 4315 case PCI_CAP_ID_PM:
4218 4316
4219 4317 /* power management supported */
4220 4318 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM;
4221 4319
4222 4320 /* Save PMCSR offset */
4223 4321 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR;
4224 4322
4225 4323 #if AHCI_DEBUG
4226 4324 pmcap = pci_config_get16(
4227 4325 ahci_ctlp->ahcictl_pci_conf_handle,
4228 4326 caps_ptr + PCI_PMCAP);
4229 4327 pmcsr = pci_config_get16(
4230 4328 ahci_ctlp->ahcictl_pci_conf_handle,
4231 4329 ahci_ctlp->ahcictl_pmcsr_offset);
4232 4330 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4233 4331 "Power Management capability found PCI_PMCAP "
4234 4332 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr);
4235 4333 if ((pmcap & 0x3) == 0x3)
4236 4334 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4237 4335 "PCI Power Management Interface "
4238 4336 "spec 1.2 compliant", NULL);
4239 4337 #endif
4240 4338 break;
4241 4339
4242 4340 case PCI_CAP_ID_MSI:
4243 4341 #if AHCI_DEBUG
4244 4342 msimc = pci_config_get16(
4245 4343 ahci_ctlp->ahcictl_pci_conf_handle,
4246 4344 caps_ptr + PCI_MSI_CTRL);
4247 4345 AHCIDBG(AHCIDBG_MSI, ahci_ctlp,
4248 4346 "Message Signaled Interrupt capability found "
4249 4347 "MSICAP_MC.MMC = 0x%x", (msimc & 0xe) >> 1);
4250 4348 #endif
4251 4349 AHCIDBG(AHCIDBG_MSI, ahci_ctlp,
4252 4350 "MSI capability found", NULL);
4253 4351 break;
4254 4352
4255 4353 case PCI_CAP_ID_PCIX:
4256 4354 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4257 4355 "PCI-X capability found", NULL);
4258 4356 break;
4259 4357
4260 4358 case PCI_CAP_ID_PCI_E:
4261 4359 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4262 4360 "PCI Express capability found", NULL);
4263 4361 break;
4264 4362
4265 4363 case PCI_CAP_ID_MSI_X:
4266 4364 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4267 4365 "MSI-X capability found", NULL);
4268 4366 break;
4269 4367
4270 4368 case PCI_CAP_ID_SATA:
4271 4369 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4272 4370 "SATA capability found", NULL);
4273 4371 break;
4274 4372
4275 4373 case PCI_CAP_ID_VS:
4276 4374 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4277 4375 "Vendor Specific capability found", NULL);
4278 4376 break;
4279 4377
4280 4378 default:
4281 4379 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4282 4380 "unrecognized capability 0x%x", cap);
4283 4381 break;
4284 4382 }
4285 4383
4286 4384 /*
4287 4385 * Get next capabilities pointer and clear bits 0,1.
4288 4386 */
4289 4387 caps_ptr = P2ALIGN(pci_config_get8(
4290 4388 ahci_ctlp->ahcictl_pci_conf_handle,
4291 4389 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
4292 4390 }
4293 4391
4294 4392 return (AHCI_SUCCESS);
4295 4393 }
4296 4394
4297 4395 /*
4298 4396 * Read/Write a register at port multiplier by SATA READ PORTMULT / SATA WRITE
4299 4397 * PORTMULT command. SYNC & POLLING mode is used.
4300 4398 */
4301 4399 static int
4302 4400 ahci_rdwr_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4303 4401 uint8_t regn, uint32_t *pregv, uint8_t type)
4304 4402 {
4305 4403 ahci_port_t *ahci_portp;
4306 4404 ahci_addr_t pmult_addr;
4307 4405 sata_pkt_t *spkt;
4308 4406 sata_cmd_t *scmd;
4309 4407 sata_device_t sata_device;
4310 4408 uint8_t port = addrp->aa_port;
4311 4409 uint8_t pmport = addrp->aa_pmport;
4312 4410 uint8_t cport;
4313 4411 uint32_t intr_mask;
4314 4412 int rval;
4315 4413 char portstr[10];
4316 4414
4317 4415 SET_PORTSTR(portstr, addrp);
4318 4416 cport = ahci_ctlp->ahcictl_port_to_cport[port];
4319 4417 ahci_portp = ahci_ctlp->ahcictl_ports[port];
4320 4418
4321 4419 ASSERT(AHCI_ADDR_IS_PMPORT(addrp) || AHCI_ADDR_IS_PMULT(addrp));
4322 4420 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4323 4421
4324 4422 /* Check the existence of the port multiplier */
4325 4423 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT)
4326 4424 return (AHCI_FAILURE);
4327 4425
4328 4426 /* Request a READ/WRITE PORTMULT sata packet. */
4329 4427 bzero(&sata_device, sizeof (sata_device_t));
4330 4428 sata_device.satadev_addr.cport = cport;
4331 4429 sata_device.satadev_addr.pmport = pmport;
4332 4430 sata_device.satadev_addr.qual = SATA_ADDR_PMULT;
4333 4431 sata_device.satadev_rev = SATA_DEVICE_REV;
4334 4432
4335 4433 /*
4336 4434 * Make sure no command is outstanding here. All R/W PMULT requests
4337 4435 * come from
4338 4436 *
4339 4437 * 1. ahci_attach()
4340 4438 * The port should be empty.
4341 4439 *
4342 4440 * 2. ahci_tran_probe_port()
4343 4441 * Any request from SATA framework (via ahci_tran_start) should be
4344 4442 * rejected if R/W PMULT command is outstanding.
4345 4443 *
4346 4444 * If we are doing mopping, do not check those flags because no
4347 4445 * command will be actually outstanding.
4348 4446 *
4349 4447 * If the port has been occupied by any other commands, the probe
4350 4448 * function will return a SATA_RETRY. SATA framework will retry
4351 4449 * later.
4352 4450 */
4353 4451 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
4354 4452 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4355 4453 "R/W PMULT failed: R/W PMULT in progress at port %d.",
4356 4454 port, ahci_portp->ahciport_flags);
4357 4455 return (AHCI_FAILURE);
4358 4456 }
4359 4457
4360 4458 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && (
4361 4459 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) ||
4362 4460 NCQ_CMD_IN_PROGRESS(ahci_portp) ||
4363 4461 NON_NCQ_CMD_IN_PROGRESS(ahci_portp))) {
4364 4462 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4365 4463 "R/W PMULT failed: port %d is occupied (flags 0x%x).",
4366 4464 port, ahci_portp->ahciport_flags);
4367 4465 return (AHCI_FAILURE);
4368 4466 }
4369 4467
4370 4468 /*
4371 4469 * The port multiplier is gone. This may happen when
4372 4470 * 1. Cutting off the power of an enclosure. The device lose the power
4373 4471 * before port multiplier.
4374 4472 * 2. Disconnecting the port multiplier during hot-plugging a sub-drive.
4375 4473 *
4376 4474 * The issued command should be aborted and the following command
4377 4475 * should not be continued.
4378 4476 */
4379 4477 if (!(ahci_portp->ahciport_port_state & SATA_STATE_READY)) {
4380 4478 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4381 4479 "READ/WRITE PMULT failed: "
4382 4480 "port-mult is removed from port %d", port);
4383 4481 return (AHCI_FAILURE);
4384 4482 }
4385 4483
4386 4484 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDWR_PMULT;
4387 4485
4388 4486 spkt = sata_get_rdwr_pmult_pkt(ahci_ctlp->ahcictl_dip,
4389 4487 &sata_device, regn, *pregv, type);
4390 4488
4391 4489 /*
4392 4490 * READ/WRITE PORTMULT command is intended to sent to the control port
4393 4491 * of the port multiplier.
4394 4492 */
4395 4493 AHCI_ADDR_SET_PMULT(&pmult_addr, addrp->aa_port);
4396 4494
4397 4495 ahci_portp->ahciport_rdwr_pmult_pkt = spkt;
4398 4496
4399 4497 /* No interrupt here. Store the interrupt enable mask. */
4400 4498 intr_mask = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4401 4499 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port));
4402 4500 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4403 4501 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0);
4404 4502
4405 4503 rval = ahci_do_sync_start(ahci_ctlp, ahci_portp, &pmult_addr, spkt);
4406 4504
4407 4505 if (rval == AHCI_SUCCESS &&
4408 4506 spkt->satapkt_reason == SATA_PKT_COMPLETED) {
4409 4507 if (type == SATA_RDWR_PMULT_PKT_TYPE_READ) {
4410 4508 scmd = &spkt->satapkt_cmd;
4411 4509 *pregv = scmd->satacmd_lba_high_lsb << 24 |
4412 4510 scmd->satacmd_lba_mid_lsb << 16 |
4413 4511 scmd->satacmd_lba_low_lsb << 8 |
4414 4512 scmd->satacmd_sec_count_lsb;
4415 4513 }
4416 4514 } else {
4417 4515 /* Failed or not completed. */
4418 4516 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4419 4517 "ahci_rdwr_pmult: cannot [%s] %s[%d] at port %s",
4420 4518 type == SATA_RDWR_PMULT_PKT_TYPE_READ?"Read":"Write",
4421 4519 AHCI_ADDR_IS_PMULT(addrp)?"gscr":"pscr", regn, portstr);
4422 4520 rval = AHCI_FAILURE;
4423 4521 }
4424 4522 out:
4425 4523 /* Restore the interrupt mask */
4426 4524 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4427 4525 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), intr_mask);
4428 4526
4429 4527 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_RDWR_PMULT;
4430 4528 ahci_portp->ahciport_rdwr_pmult_pkt = NULL;
4431 4529 sata_free_rdwr_pmult_pkt(spkt);
4432 4530 return (rval);
4433 4531 }
4434 4532
4435 4533 static int
4436 4534 ahci_read_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4437 4535 uint8_t regn, uint32_t *pregv)
4438 4536 {
4439 4537 return ahci_rdwr_pmult(ahci_ctlp, addrp, regn, pregv,
4440 4538 SATA_RDWR_PMULT_PKT_TYPE_READ);
4441 4539 }
4442 4540
4443 4541 static int
4444 4542 ahci_write_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4445 4543 uint8_t regn, uint32_t regv)
4446 4544 {
4447 4545 return ahci_rdwr_pmult(ahci_ctlp, addrp, regn, ®v,
4448 4546 SATA_RDWR_PMULT_PKT_TYPE_WRITE);
4449 4547 }
4450 4548
4451 4549 #define READ_PMULT(addrp, r, pv, out) \
4452 4550 if (ahci_read_pmult(ahci_ctlp, addrp, r, pv) != AHCI_SUCCESS) \
4453 4551 goto out;
4454 4552
4455 4553 #define WRITE_PMULT(addrp, r, v, out) \
4456 4554 if (ahci_write_pmult(ahci_ctlp, addrp, r, v) != AHCI_SUCCESS) \
4457 4555 goto out;
4458 4556
4459 4557 /*
4460 4558 * Update sata registers on port multiplier, including GSCR/PSCR registers.
4461 4559 * ahci_update_pmult_gscr()
4462 4560 * ahci_update_pmult_pscr()
4463 4561 */
4464 4562 static int
4465 4563 ahci_update_pmult_gscr(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4466 4564 sata_pmult_gscr_t *sg)
4467 4565 {
4468 4566 ASSERT(MUTEX_HELD(
4469 4567 &ahci_ctlp->ahcictl_ports[addrp->aa_port]->ahciport_mutex));
4470 4568
4471 4569 READ_PMULT(addrp, SATA_PMULT_GSCR0, &sg->gscr0, err);
4472 4570 READ_PMULT(addrp, SATA_PMULT_GSCR1, &sg->gscr1, err);
4473 4571 READ_PMULT(addrp, SATA_PMULT_GSCR2, &sg->gscr2, err);
4474 4572 READ_PMULT(addrp, SATA_PMULT_GSCR64, &sg->gscr64, err);
4475 4573
4476 4574 return (AHCI_SUCCESS);
4477 4575
4478 4576 err: /* R/W PMULT error */
4479 4577 return (AHCI_FAILURE);
4480 4578 }
4481 4579
4482 4580 static int
4483 4581 ahci_update_pmult_pscr(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4484 4582 sata_device_t *sd)
4485 4583 {
4486 4584 ASSERT(AHCI_ADDR_IS_PMPORT(addrp));
4487 4585 ASSERT(MUTEX_HELD(
4488 4586 &ahci_ctlp->ahcictl_ports[addrp->aa_port]->ahciport_mutex));
4489 4587
4490 4588 READ_PMULT(addrp, SATA_PMULT_REG_SSTS, &sd->satadev_scr.sstatus, err);
4491 4589 READ_PMULT(addrp, SATA_PMULT_REG_SERR, &sd->satadev_scr.serror, err);
4492 4590 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &sd->satadev_scr.scontrol, err);
4493 4591 READ_PMULT(addrp, SATA_PMULT_REG_SACT, &sd->satadev_scr.sactive, err);
4494 4592
4495 4593 return (AHCI_SUCCESS);
4496 4594
4497 4595 err: /* R/W PMULT error */
4498 4596 return (AHCI_FAILURE);
4499 4597 }
4500 4598
4501 4599 /*
4502 4600 * ahci_initialize_pmult()
4503 4601 *
4504 4602 * Initialize a port multiplier, including
4505 4603 * 1. Enable FEATURES register at port multiplier. (SATA Chp.16)
4506 4604 * 2. Redefine MASK register. (SATA Chap 16.?)
4507 4605 */
4508 4606 static int
4509 4607 ahci_initialize_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4510 4608 ahci_addr_t *addrp, sata_device_t *sd)
4511 4609 {
4512 4610 sata_pmult_gscr_t sg;
4513 4611 uint32_t gscr64;
4514 4612 uint8_t port = addrp->aa_port;
4515 4613
4516 4614 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4517 4615
4518 4616 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4519 4617 "[Initialize] Port-multiplier at port %d.", port);
4520 4618
4521 4619 /*
4522 4620 * Enable features of port multiplier. Currently only
4523 4621 * Asynchronous Notification is enabled.
4524 4622 */
4525 4623 /* Check gscr64 for supported features. */
4526 4624 READ_PMULT(addrp, SATA_PMULT_GSCR64, &gscr64, err);
4527 4625
4528 4626 if (gscr64 & SATA_PMULT_CAP_SNOTIF) {
4529 4627 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4530 4628 "port %d: Port Multiplier supports "
4531 4629 "Asynchronous Notification.", port);
4532 4630
4533 4631 /* Write to gscr96 to enabled features */
4534 4632 WRITE_PMULT(addrp, SATA_PMULT_GSCR96,
4535 4633 SATA_PMULT_CAP_SNOTIF, err);
4536 4634
4537 4635 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4538 4636 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port),
4539 4637 AHCI_SNOTIF_CLEAR_ALL);
4540 4638 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4541 4639 "port %d: PMult PxSNTF cleared.", port);
4542 4640
4543 4641 }
4544 4642
4545 4643 /*
4546 4644 * Now we need to update gscr33 register to enable hot-plug interrupt
4547 4645 * for sub devices behind port multiplier.
4548 4646 */
4549 4647 WRITE_PMULT(addrp, SATA_PMULT_GSCR33, (0x1ffff), err);
4550 4648 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4551 4649 "port %d: gscr33 mask set to %x.", port, (0x1ffff));
4552 4650
4553 4651 /*
4554 4652 * Fetch the number of device ports of the port multiplier
4555 4653 */
4556 4654 if (ahci_update_pmult_gscr(ahci_ctlp, addrp, &sg) != AHCI_SUCCESS)
4557 4655 return (AHCI_FAILURE);
4558 4656
4559 4657 /* Register the port multiplier to SATA Framework. */
4560 4658 mutex_exit(&ahci_portp->ahciport_mutex);
4561 4659 sata_register_pmult(ahci_ctlp->ahcictl_dip, sd, &sg);
4562 4660 mutex_enter(&ahci_portp->ahciport_mutex);
4563 4661
4564 4662 ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports =
4565 4663 sd->satadev_add_info & SATA_PMULT_PORTNUM_MASK;
4566 4664
4567 4665 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4568 4666 "port %d: pmult sub-port number updated to %x.", port,
4569 4667 ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports);
4570 4668
4571 4669 /* Till now port-mult is successfully initialized */
4572 4670 ahci_portp->ahciport_port_state |= SATA_DSTATE_PMULT_INIT;
4573 4671 return (AHCI_SUCCESS);
4574 4672
4575 4673 err: /* R/W PMULT error */
4576 4674 return (AHCI_FAILURE);
4577 4675 }
4578 4676
4579 4677 /*
4580 4678 * Initialize a port multiplier port. According to spec, firstly we need
4581 4679 * issue a COMRESET, then a software reset to get its signature.
4582 4680 *
4583 4681 * NOTE: This function should only be called in ahci_probe_pmport()
4584 4682 */
4585 4683 static int
4586 4684 ahci_initialize_pmport(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4587 4685 ahci_addr_t *addrp)
4588 4686 {
4589 4687 uint32_t finished_tags = 0, reset_tags = 0, slot_status = 0;
4590 4688 uint8_t port = addrp->aa_port;
4591 4689 uint8_t pmport = addrp->aa_pmport;
4592 4690 int ret = AHCI_FAILURE;
4593 4691
4594 4692 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4595 4693 ASSERT(AHCI_ADDR_IS_PMPORT(addrp));
4596 4694
4597 4695 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
4598 4696 "ahci_initialize_pmport: port %d:%d", port, pmport);
4599 4697
4600 4698 /* Check HBA port state */
4601 4699 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) {
4602 4700 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
4603 4701 "ahci_initialize_pmport:"
4604 4702 "port %d:%d Port Multiplier is failed.",
4605 4703 port, pmport);
4606 4704 return (AHCI_FAILURE);
4607 4705 }
4608 4706
4609 4707 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) {
4610 4708 return (AHCI_FAILURE);
4611 4709 }
4612 4710 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_HOTPLUG;
4613 4711
4614 4712 /* Checking for outstanding commands */
4615 4713 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
4616 4714 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4617 4715 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
4618 4716 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
4619 4717 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
4620 4718 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4621 4719 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
4622 4720 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
4623 4721 }
4624 4722
4625 4723 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
4626 4724 ahci_portp->ahciport_mop_in_progress++;
4627 4725
4628 4726 /* Clear status */
4629 4727 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_UNKNOWN);
4630 4728
4631 4729 /* Firstly assume an unknown device */
4632 4730 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
4633 4731
4634 4732 ahci_disable_port_intrs(ahci_ctlp, port);
4635 4733
4636 4734 /* port reset is necessary for port multiplier port */
4637 4735 if (ahci_pmport_reset(ahci_ctlp, ahci_portp, addrp) != AHCI_SUCCESS) {
4638 4736 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
4639 4737 "ahci_initialize_pmport:"
4640 4738 "port reset failed at port %d:%d",
4641 4739 port, pmport);
4642 4740 goto out;
4643 4741 }
4644 4742
4645 4743 /* Is port failed? */
4646 4744 if (AHCIPORT_GET_STATE(ahci_portp, addrp) &
4647 4745 SATA_PSTATE_FAILED) {
4648 4746 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4649 4747 "ahci_initialize_pmport: port %d:%d failed. "
4650 4748 "state = 0x%x", port, pmport,
4651 4749 ahci_portp->ahciport_port_state);
4652 4750 goto out;
4653 4751 }
4654 4752
4655 4753 /* Is there any device attached? */
4656 4754 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, addrp)
4657 4755 == SATA_DTYPE_NONE) {
4658 4756 /* Do not waste time on an empty port */
4659 4757 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
4660 4758 "ahci_initialize_pmport: No device is found "
4661 4759 "at port %d:%d", port, pmport);
4662 4760 ret = AHCI_SUCCESS;
4663 4761 goto out;
4664 4762 }
4665 4763
4666 4764 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_READY);
4667 4765 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4668 4766 "port %d:%d is ready now.", port, pmport);
4669 4767
4670 4768 /*
4671 4769 * Till now we can assure a device attached to that HBA port and work
4672 4770 * correctly. Now try to get the device signature. This is an optional
4673 4771 * step. If failed, unknown device is assumed, then SATA module will
4674 4772 * continue to use IDENTIFY DEVICE to get the information of the
4675 4773 * device.
4676 4774 */
4677 4775 ahci_find_dev_signature(ahci_ctlp, ahci_portp, addrp);
4678 4776
4679 4777 ret = AHCI_SUCCESS;
4680 4778
4681 4779 out:
4682 4780 /* Next try to mop the pending commands */
4683 4781 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
4684 4782 finished_tags = ahci_portp->ahciport_pending_tags &
4685 4783 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
4686 4784 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
4687 4785 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
4688 4786 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
4689 4787 reset_tags &= ~finished_tags;
4690 4788
4691 4789 ahci_mop_commands(ahci_ctlp,
4692 4790 ahci_portp,
4693 4791 slot_status,
4694 4792 0, /* failed tags */
4695 4793 0, /* timeout tags */
4696 4794 0, /* aborted tags */
4697 4795 reset_tags); /* reset tags */
4698 4796
4699 4797 /* Clear PxSNTF register if supported. */
4700 4798 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_SNTF) {
4701 4799 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4702 4800 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port),
4703 4801 AHCI_SNOTIF_CLEAR_ALL);
4704 4802 }
4705 4803
4706 4804 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_HOTPLUG;
4707 4805 ahci_enable_port_intrs(ahci_ctlp, port);
4708 4806 return (ret);
4709 4807 }
4710 4808
4711 4809 /*
4712 4810 * ahci_probe_pmult()
4713 4811 *
4714 4812 * This function will be called to probe a port multiplier, which will
4715 4813 * handle hotplug events on port multiplier ports.
4716 4814 *
4717 4815 * NOTE: Only called from ahci_tran_probe_port()
4718 4816 */
4719 4817 static int
4720 4818 ahci_probe_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4721 4819 ahci_addr_t *addrp)
4722 4820 {
4723 4821 sata_device_t sdevice;
4724 4822 ahci_addr_t pmport_addr;
4725 4823 uint32_t gscr32, port_hotplug_tags;
4726 4824 uint32_t pmport_sstatus;
4727 4825 int dev_exists_now = 0, dev_existed_previously = 0;
4728 4826 uint8_t port = addrp->aa_port;
4729 4827 int npmport;
4730 4828
4731 4829 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4732 4830
4733 4831 /* The bits in GSCR32 refers to the pmport that has a hot-plug event. */
4734 4832 READ_PMULT(addrp, SATA_PMULT_GSCR32, &gscr32, err);
4735 4833 port_hotplug_tags = gscr32 & AHCI_PMPORT_MASK(ahci_portp);
4736 4834
4737 4835 do {
4738 4836 npmport = ddi_ffs(port_hotplug_tags) - 1;
4739 4837 if (npmport == -1)
4740 4838 /* no pending hot plug events. */
4741 4839 return (AHCI_SUCCESS);
4742 4840
4743 4841 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4744 4842 "hot-plug event at port %d:%d", port, npmport);
4745 4843
4746 4844 AHCI_ADDR_SET_PMPORT(&pmport_addr, port, (uint8_t)npmport);
4747 4845
4748 4846 /* Check previous device at that port */
4749 4847 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &pmport_addr)
4750 4848 != SATA_DTYPE_NONE)
4751 4849 dev_existed_previously = 1;
4752 4850
4753 4851 /* PxSStatus tells the presence of device. */
4754 4852 READ_PMULT(&pmport_addr, SATA_PMULT_REG_SSTS,
4755 4853 &pmport_sstatus, err);
4756 4854
4757 4855 if (SSTATUS_GET_DET(pmport_sstatus) ==
4758 4856 SSTATUS_DET_DEVPRE_PHYCOM)
4759 4857 dev_exists_now = 1;
4760 4858
4761 4859 /*
4762 4860 * Clear PxSERR is critical. The transition from 0 to 1 will
4763 4861 * emit a FIS which generates an asynchronous notification
4764 4862 * event at controller. If we fail to clear the PxSERR, the
4765 4863 * Async Notif events will no longer be activated on this
4766 4864 * pmport.
4767 4865 */
4768 4866 WRITE_PMULT(&pmport_addr, SATA_PMULT_REG_SERR,
4769 4867 AHCI_SERROR_CLEAR_ALL, err);
4770 4868
4771 4869 bzero((void *)&sdevice, sizeof (sata_device_t));
4772 4870 sdevice.satadev_addr.cport = ahci_ctlp->
4773 4871 ahcictl_port_to_cport[port];
4774 4872 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT;
4775 4873 sdevice.satadev_addr.pmport = (uint8_t)npmport;
4776 4874 sdevice.satadev_state = SATA_PSTATE_PWRON;
4777 4875
4778 4876 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4779 4877 "[Existence] %d -> %d", dev_existed_previously,
4780 4878 dev_exists_now);
4781 4879
4782 4880 if (dev_exists_now) {
4783 4881 if (dev_existed_previously) {
4784 4882 /* Link (may) not change: Exist -> Exist * */
4785 4883 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
4786 4884 "ahci_probe_pmult: port %d:%d "
4787 4885 "device link lost/established",
4788 4886 port, npmport);
4789 4887
4790 4888 mutex_exit(&ahci_portp->ahciport_mutex);
4791 4889 sata_hba_event_notify(
4792 4890 ahci_ctlp->ahcictl_sata_hba_tran->
4793 4891 sata_tran_hba_dip,
4794 4892 &sdevice,
4795 4893 SATA_EVNT_LINK_LOST|
4796 4894 SATA_EVNT_LINK_ESTABLISHED);
4797 4895 mutex_enter(&ahci_portp->ahciport_mutex);
4798 4896 } else {
4799 4897 /* Link change: None -> Exist */
4800 4898 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4801 4899 "ahci_probe_pmult: port %d:%d "
4802 4900 "device link established", port, npmport);
4803 4901
4804 4902 /* Clear port state */
4805 4903 AHCIPORT_SET_STATE(ahci_portp, &pmport_addr,
4806 4904 SATA_STATE_UNKNOWN);
4807 4905 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4808 4906 "ahci_probe_pmult: port %d "
4809 4907 "ahciport_port_state [Cleared].", port);
4810 4908
4811 4909 mutex_exit(&ahci_portp->ahciport_mutex);
4812 4910 sata_hba_event_notify(
4813 4911 ahci_ctlp->ahcictl_sata_hba_tran->
4814 4912 sata_tran_hba_dip,
4815 4913 &sdevice,
4816 4914 SATA_EVNT_LINK_ESTABLISHED);
4817 4915 mutex_enter(&ahci_portp->ahciport_mutex);
4818 4916 }
4819 4917 } else { /* No device exists now */
4820 4918 if (dev_existed_previously) {
4821 4919
4822 4920 /* Link change: Exist -> None */
4823 4921 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4824 4922 "ahci_probe_pmult: port %d:%d "
4825 4923 "device link lost", port, npmport);
4826 4924
4827 4925 /* An existing device is lost. */
4828 4926 AHCIPORT_SET_STATE(ahci_portp, &pmport_addr,
4829 4927 SATA_STATE_UNKNOWN);
4830 4928 AHCIPORT_SET_DEV_TYPE(ahci_portp, &pmport_addr,
4831 4929 SATA_DTYPE_NONE);
4832 4930
4833 4931 mutex_exit(&ahci_portp->ahciport_mutex);
4834 4932 sata_hba_event_notify(
4835 4933 ahci_ctlp->ahcictl_sata_hba_tran->
4836 4934 sata_tran_hba_dip,
4837 4935 &sdevice,
4838 4936 SATA_EVNT_LINK_LOST);
4839 4937 mutex_enter(&ahci_portp->ahciport_mutex);
4840 4938 }
4841 4939 }
4842 4940
4843 4941 CLEAR_BIT(port_hotplug_tags, npmport);
4844 4942 } while (port_hotplug_tags != 0);
4845 4943
4846 4944 return (AHCI_SUCCESS);
4847 4945
4848 4946 err: /* R/W PMULT error */
4849 4947 return (AHCI_FAILURE);
4850 4948 }
4851 4949
4852 4950 /*
4853 4951 * Probe and initialize a port multiplier port.
4854 4952 * A port multiplier port could only be initilaizer here.
4855 4953 */
4856 4954 static int
4857 4955 ahci_probe_pmport(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4858 4956 ahci_addr_t *addrp, sata_device_t *sd)
4859 4957 {
4860 4958 uint32_t port_state;
4861 4959 uint8_t port = addrp->aa_port;
4862 4960 ahci_addr_t addr_pmult;
4863 4961
4864 4962 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4865 4963
4866 4964 /*
4867 4965 * Check the parent - port multiplier first.
4868 4966 */
4869 4967
4870 4968 /*
4871 4969 * Parent port multiplier might have been removed. This event will be
4872 4970 * ignored and failure.
4873 4971 */
4874 4972 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE ||
4875 4973 ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
4876 4974 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4877 4975 "ahci_tran_probe_port: "
4878 4976 "parent device removed, ignore event.", NULL);
4879 4977
4880 4978 return (AHCI_FAILURE);
4881 4979 }
4882 4980
4883 4981 /* The port is ready? */
4884 4982 port_state = ahci_portp->ahciport_port_state;
4885 4983 if (!(port_state & SATA_STATE_READY)) {
4886 4984 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4887 4985 "ahci_tran_probe_port: "
4888 4986 "parent port-mult is NOT ready.", NULL);
4889 4987
4890 4988 if (ahci_restart_port_wait_till_ready(ahci_ctlp,
4891 4989 ahci_portp, port, AHCI_PORT_RESET, NULL) !=
4892 4990 AHCI_SUCCESS) {
4893 4991 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4894 4992 "ahci_tran_probe_port: "
4895 4993 "restart port-mult failed.", NULL);
4896 4994 return (AHCI_FAILURE);
4897 4995 }
4898 4996 }
4899 4997
4900 4998 /*
4901 4999 * If port-mult is restarted due to some reason, we need
4902 5000 * re-initialized the PMult.
4903 5001 */
4904 5002 if (!(port_state & SATA_DSTATE_PMULT_INIT)) {
4905 5003 /* Initialize registers on a port multiplier */
4906 5004 AHCI_ADDR_SET_PMULT(&addr_pmult, addrp->aa_port);
4907 5005 if (ahci_initialize_pmult(ahci_ctlp, ahci_portp,
4908 5006 &addr_pmult, sd) != AHCI_SUCCESS)
4909 5007 return (AHCI_FAILURE);
4910 5008 }
4911 5009
4912 5010 /*
4913 5011 * Then we check the port-mult port
4914 5012 */
4915 5013 /* Is this pmport initialized? */
4916 5014 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp);
4917 5015 if (!(port_state & SATA_STATE_READY)) {
4918 5016
4919 5017 /* ahci_initialize_pmport() will set READY state */
4920 5018 if (ahci_initialize_pmport(ahci_ctlp,
4921 5019 ahci_portp, addrp) != AHCI_SUCCESS)
4922 5020 return (AHCI_FAILURE);
4923 5021 }
4924 5022
4925 5023 return (AHCI_SUCCESS);
4926 5024 }
4927 5025
4928 5026 /*
4929 5027 * AHCI device reset ...; a single device on one of the ports is reset,
4930 5028 * but the HBA and physical communication remain intact. This is the
4931 5029 * least intrusive.
4932 5030 *
4933 5031 * When issuing a software reset sequence, there should not be other
4934 5032 * commands in the command list, so we will first clear and then re-set
4935 5033 * PxCMD.ST to clear PxCI. And before issuing the software reset,
4936 5034 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be
4937 5035 * cleared unless command list override (PxCMD.CLO) is supported.
4938 5036 */
4939 5037 static int
4940 5038 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4941 5039 ahci_addr_t *addrp)
4942 5040 {
4943 5041 ahci_fis_h2d_register_t *h2d_register_fisp;
4944 5042 ahci_cmd_table_t *cmd_table;
4945 5043 ahci_cmd_header_t *cmd_header;
4946 5044 uint32_t port_cmd_status, port_cmd_issue, port_task_file;
4947 5045 int slot, loop_count;
4948 5046 uint8_t port = addrp->aa_port;
4949 5047 uint8_t pmport = addrp->aa_pmport;
4950 5048 int rval = AHCI_FAILURE;
4951 5049
4952 5050 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4953 5051
4954 5052 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
4955 5053 "port %d:%d device software resetting (FIS)", port, pmport);
4956 5054
4957 5055 /* First clear PxCMD.ST (AHCI v1.2 10.4.1) */
4958 5056 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp,
4959 5057 port) != AHCI_SUCCESS) {
4960 5058 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4961 5059 "ahci_software_reset: cannot stop HBA port %d.", port);
4962 5060 goto out;
4963 5061 }
4964 5062
4965 5063 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */
4966 5064 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4967 5065 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
4968 5066
4969 5067 if (port_task_file & AHCI_TFD_STS_BSY ||
4970 5068 port_task_file & AHCI_TFD_STS_DRQ) {
4971 5069 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_SCLO)) {
4972 5070 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4973 5071 "PxTFD.STS.BSY/DRQ is set (PxTFD=0x%x), "
4974 5072 "cannot issue a software reset.", port_task_file);
4975 5073 goto out;
4976 5074 }
4977 5075
4978 5076 /*
4979 5077 * If HBA Support CLO, as Command List Override (CAP.SCLO is
4980 5078 * set), PxCMD.CLO bit should be set before set PxCMD.ST, in
4981 5079 * order to clear PxTFD.STS.BSY and PxTFD.STS.DRQ.
4982 5080 */
4983 5081 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4984 5082 "PxTFD.STS.BSY/DRQ is set, try SCLO.", NULL)
4985 5083
4986 5084 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4987 5085 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
4988 5086 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4989 5087 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
4990 5088 port_cmd_status|AHCI_CMD_STATUS_CLO);
4991 5089
4992 5090 /* Waiting till PxCMD.SCLO bit is cleared */
4993 5091 loop_count = 0;
4994 5092 do {
4995 5093 /* Wait for 10 millisec */
4996 5094 drv_usecwait(AHCI_10MS_USECS);
4997 5095
4998 5096 /* We are effectively timing out after 1 sec. */
4999 5097 if (loop_count++ > 100) {
5000 5098 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5001 5099 "SCLO time out. port %d is busy.", port);
5002 5100 goto out;
5003 5101 }
5004 5102
5005 5103 port_cmd_status =
5006 5104 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5007 5105 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5008 5106 } while (port_cmd_status & AHCI_CMD_STATUS_CLO);
5009 5107
5010 5108 /* Re-check */
5011 5109 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5012 5110 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
5013 5111 if (port_task_file & AHCI_TFD_STS_BSY ||
5014 5112 port_task_file & AHCI_TFD_STS_DRQ) {
5015 5113 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5016 5114 "SCLO cannot clear PxTFD.STS.BSY/DRQ (PxTFD=0x%x)",
5017 5115 port_task_file);
5018 5116 goto out;
5019 5117 }
5020 5118 }
5021 5119
5022 5120 /* Then start port */
5023 5121 if (ahci_start_port(ahci_ctlp, ahci_portp, port)
5024 5122 != AHCI_SUCCESS) {
5025 5123 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5026 5124 "ahci_software_reset: cannot start AHCI port %d.", port);
5027 5125 goto out;
5028 5126 }
5029 5127
5030 5128 /*
5031 5129 * When ahci_port.ahciport_mop_in_progress is set, A non-zero
5032 5130 * ahci_port.ahciport_pending_ncq_tags may fail
5033 5131 * ahci_claim_free_slot(). Actually according to spec, by clearing
5034 5132 * PxCMD.ST there is no command outstanding while executing software
5035 5133 * reseting. Hence we directly use slot 0 instead of
5036 5134 * ahci_claim_free_slot().
5037 5135 */
5038 5136 slot = 0;
5039 5137
5040 5138 /* Now send the first H2D Register FIS with SRST set to 1 */
5041 5139 cmd_table = ahci_portp->ahciport_cmd_tables[slot];
5042 5140 bzero((void *)cmd_table, ahci_cmd_table_size);
5043 5141
5044 5142 h2d_register_fisp =
5045 5143 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register);
5046 5144
5047 5145 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE);
5048 5146 SET_FIS_PMP(h2d_register_fisp, pmport);
5049 5147 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST);
5050 5148
5051 5149 /* Set Command Header in Command List */
5052 5150 cmd_header = &ahci_portp->ahciport_cmd_list[slot];
5053 5151 BZERO_DESCR_INFO(cmd_header);
5054 5152 BZERO_PRD_BYTE_COUNT(cmd_header);
5055 5153 SET_COMMAND_FIS_LENGTH(cmd_header, 5);
5056 5154 SET_PORT_MULTI_PORT(cmd_header, pmport);
5057 5155
5058 5156 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1);
5059 5157 SET_RESET(cmd_header, 1);
5060 5158 SET_WRITE(cmd_header, 1);
5061 5159
5062 5160 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot],
5063 5161 0,
5064 5162 ahci_cmd_table_size,
5065 5163 DDI_DMA_SYNC_FORDEV);
5066 5164
5067 5165 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle,
5068 5166 slot * sizeof (ahci_cmd_header_t),
5069 5167 sizeof (ahci_cmd_header_t),
5070 5168 DDI_DMA_SYNC_FORDEV);
5071 5169
5072 5170 /* Indicate to the HBA that a command is active. */
5073 5171 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5074 5172 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port),
5075 5173 (0x1 << slot));
5076 5174
5077 5175 loop_count = 0;
5078 5176
5079 5177 /* Loop till the first command is finished */
5080 5178 do {
5081 5179 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5082 5180 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
5083 5181
5084 5182 /* We are effectively timing out after 1 sec. */
5085 5183 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) {
5086 5184 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5087 5185 "the first SRST FIS is timed out, "
5088 5186 "loop_count = %d", loop_count);
5089 5187 goto out;
5090 5188 }
5091 5189 /* Wait for 10 millisec */
5092 5190 drv_usecwait(AHCI_10MS_USECS);
5093 5191 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot));
5094 5192
5095 5193 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5096 5194 "ahci_software_reset: 1st loop count: %d, "
5097 5195 "port_cmd_issue = 0x%x, slot = 0x%x",
5098 5196 loop_count, port_cmd_issue, slot);
5099 5197
5100 5198 /* According to ATA spec, we need wait at least 5 microsecs here. */
5101 5199 drv_usecwait(AHCI_1MS_USECS);
5102 5200
5103 5201 /* Now send the second H2D Register FIS with SRST cleard to zero */
5104 5202 cmd_table = ahci_portp->ahciport_cmd_tables[slot];
5105 5203 bzero((void *)cmd_table, ahci_cmd_table_size);
5106 5204
5107 5205 h2d_register_fisp =
5108 5206 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register);
5109 5207
5110 5208 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE);
5111 5209 SET_FIS_PMP(h2d_register_fisp, pmport);
5112 5210
5113 5211 /* Set Command Header in Command List */
5114 5212 cmd_header = &ahci_portp->ahciport_cmd_list[slot];
5115 5213 BZERO_DESCR_INFO(cmd_header);
5116 5214 BZERO_PRD_BYTE_COUNT(cmd_header);
5117 5215 SET_COMMAND_FIS_LENGTH(cmd_header, 5);
5118 5216 SET_PORT_MULTI_PORT(cmd_header, pmport);
5119 5217
5120 5218 SET_WRITE(cmd_header, 1);
5121 5219
5122 5220 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot],
5123 5221 0,
5124 5222 ahci_cmd_table_size,
5125 5223 DDI_DMA_SYNC_FORDEV);
5126 5224
5127 5225 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle,
5128 5226 slot * sizeof (ahci_cmd_header_t),
5129 5227 sizeof (ahci_cmd_header_t),
5130 5228 DDI_DMA_SYNC_FORDEV);
5131 5229
5132 5230 /* Indicate to the HBA that a command is active. */
5133 5231 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5134 5232 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port),
5135 5233 (0x1 << slot));
5136 5234
5137 5235 loop_count = 0;
5138 5236
5139 5237 /* Loop till the second command is finished */
5140 5238 do {
5141 5239 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5142 5240 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
5143 5241
5144 5242 /* We are effectively timing out after 1 sec. */
5145 5243 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) {
5146 5244 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5147 5245 "the second SRST FIS is timed out, "
5148 5246 "loop_count = %d", loop_count);
5149 5247 goto out;
5150 5248 }
5151 5249
5152 5250 /* Wait for 10 millisec */
5153 5251 drv_usecwait(AHCI_10MS_USECS);
5154 5252 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot));
5155 5253
5156 5254 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5157 5255 "ahci_software_reset: 2nd loop count: %d, "
5158 5256 "port_cmd_issue = 0x%x, slot = 0x%x",
5159 5257 loop_count, port_cmd_issue, slot);
5160 5258
5161 5259 if ((ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) ||
5162 5260 (ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS)) {
5163 5261 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
5164 5262 DDI_SERVICE_UNAFFECTED);
5165 5263 goto out;
5166 5264 }
5167 5265
5168 5266 rval = AHCI_SUCCESS;
5169 5267 out:
5170 5268 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5171 5269 "ahci_software_reset: %s at port %d:%d",
5172 5270 rval == AHCI_SUCCESS ? "succeed" : "failed",
5173 5271 port, pmport);
5174 5272
5175 5273 return (rval);
5176 5274 }
5177 5275
5178 5276 /*
5179 5277 * AHCI port reset ...; the physical communication between the HBA and device
5180 5278 * on a port are disabled. This is more intrusive.
5181 5279 *
5182 5280 * When an HBA or port reset occurs, Phy communication is going to
5183 5281 * be re-established with the device through a COMRESET followed by the
5184 5282 * normal out-of-band communication sequence defined in Serial ATA. At
5185 5283 * the end of reset, the device, if working properly, will send a D2H
5186 5284 * Register FIS, which contains the device signature. When the HBA receives
5187 5285 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates
5188 5286 * the PxSIG register with the signature.
5189 5287 *
5190 5288 * NOTE: It is expected both PxCMD.ST and PxCMD.CR are cleared before the
5191 5289 * function is called. If not, it is assumed the interface is in hung
5192 5290 * condition.
5193 5291 */
5194 5292 static int
5195 5293 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
5196 5294 ahci_addr_t *addrp)
5197 5295 {
5198 5296 ahci_addr_t pmult_addr;
5199 5297 uint32_t port_cmd_status;
5200 5298 uint32_t port_scontrol, port_sstatus;
5201 5299 uint32_t port_task_file;
5202 5300 uint32_t port_state;
5203 5301 uint8_t port = addrp->aa_port;
5204 5302
5205 5303 int loop_count;
5206 5304 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
5207 5305
5208 5306 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5209 5307
5210 5308 /* Target is a port multiplier port? */
5211 5309 if (AHCI_ADDR_IS_PMPORT(addrp))
5212 5310 return (ahci_pmport_reset(ahci_ctlp, ahci_portp, addrp));
5213 5311
5214 5312 /* Otherwise it must be an HBA port. */
5215 5313 ASSERT(AHCI_ADDR_IS_PORT(addrp));
5216 5314
5217 5315 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
5218 5316 "Port %d port resetting...", port);
5219 5317 ahci_portp->ahciport_port_state = 0;
5220 5318
5221 5319 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5222 5320 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5223 5321
5224 5322 /*
5225 5323 * According to the spec, SUD bit should be set here,
5226 5324 * but JMicron JMB363 doesn't follow it, so print
5227 5325 * a debug message.
5228 5326 */
5229 5327 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD))
5230 5328 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5231 5329 "ahci_port_reset: port %d SUD bit not set", port);
5232 5330
5233 5331 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5234 5332 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
5235 5333 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET);
5236 5334
5237 5335 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5238 5336 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port),
5239 5337 port_scontrol);
5240 5338
5241 5339 /* Enable PxCMD.FRE to read device */
5242 5340 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5243 5341 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5244 5342 port_cmd_status|AHCI_CMD_STATUS_FRE);
5245 5343
5246 5344 /*
5247 5345 * The port enters P:StartComm state, and the HBA tells the link layer
5248 5346 * to start communication, which involves sending COMRESET to the
5249 5347 * device. And the HBA resets PxTFD.STS to 7Fh.
5250 5348 *
5251 5349 * Give time for COMRESET to percolate, according to the AHCI
5252 5350 * spec, software shall wait at least 1 millisecond before
5253 5351 * clearing PxSCTL.DET
5254 5352 */
5255 5353 drv_usecwait(AHCI_1MS_USECS * 2);
5256 5354
5257 5355 /* Fetch the SCONTROL again and rewrite the DET part with 0 */
5258 5356 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5259 5357 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
5260 5358 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION);
5261 5359 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5262 5360 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port),
5263 5361 port_scontrol);
5264 5362
5265 5363 /*
5266 5364 * When a COMINIT is received from the device, then the port enters
5267 5365 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets
5268 5366 * PxSSTS.DET to 1h to indicate a device is detected but communication
5269 5367 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate
5270 5368 * a COMINIT has been received.
5271 5369 */
5272 5370 /*
5273 5371 * The DET field is valid only if IPM field indicates
5274 5372 * that the interface is in active state.
5275 5373 */
5276 5374 loop_count = 0;
5277 5375 for (;;) {
5278 5376 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5279 5377 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
5280 5378
5281 5379 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) {
5282 5380 /*
5283 5381 * If the interface is not active, the DET field
5284 5382 * is considered not accurate. So we want to
5285 5383 * continue looping.
5286 5384 */
5287 5385 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV);
5288 5386 }
5289 5387
5290 5388 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM)
5291 5389 break;
5292 5390
5293 5391 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) {
5294 5392 /*
5295 5393 * We are effectively timing out after 0.1 sec.
5296 5394 */
5297 5395 break;
5298 5396 }
5299 5397
5300 5398 /* Wait for 10 millisec */
5301 5399 drv_usecwait(AHCI_10MS_USECS);
5302 5400 }
5303 5401
5304 5402 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
5305 5403 "ahci_port_reset: 1st loop count: %d, "
5306 5404 "port_sstatus = 0x%x port %d",
5307 5405 loop_count, port_sstatus, port);
5308 5406
5309 5407 if (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM) {
5310 5408 /*
5311 5409 * Either the port is not active or there
5312 5410 * is no device present.
5313 5411 */
5314 5412 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_NONE);
5315 5413 return (AHCI_SUCCESS);
5316 5414 }
5317 5415
5318 5416 /* Clear port serror register for the port */
5319 5417 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5320 5418 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
5321 5419 AHCI_SERROR_CLEAR_ALL);
5322 5420
5323 5421 /*
5324 5422 * Devices should return a FIS contains its signature to HBA after
5325 5423 * COMINIT signal. Check whether a D2H Register FIS is received by
5326 5424 * polling PxTFD.STS.
5327 5425 */
5328 5426 loop_count = 0;
5329 5427 for (;;) {
5330 5428 port_task_file =
5331 5429 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5332 5430 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
5333 5431
5334 5432 if ((port_task_file & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ |
5335 5433 AHCI_TFD_STS_ERR)) == 0)
5336 5434 break;
5337 5435
5338 5436 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) {
5339 5437 /*
5340 5438 * We are effectively timing out after 11 sec.
5341 5439 */
5342 5440 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d "
5343 5441 "the device hardware has been initialized and "
5344 5442 "the power-up diagnostics failed",
5345 5443 instance, port);
5346 5444
5347 5445 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: "
5348 5446 "port %d: some or all of BSY, DRQ and ERR in "
5349 5447 "PxTFD.STS are not clear. We need another "
5350 5448 "software reset.", port);
5351 5449
5352 5450 /* Clear port serror register for the port */
5353 5451 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5354 5452 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
5355 5453 AHCI_SERROR_CLEAR_ALL);
5356 5454
5357 5455 AHCI_ADDR_SET_PMULT(&pmult_addr, port);
5358 5456
5359 5457 /* Try another software reset. */
5360 5458 if (ahci_software_reset(ahci_ctlp, ahci_portp,
5361 5459 &pmult_addr) != AHCI_SUCCESS) {
5362 5460 AHCIPORT_SET_STATE(ahci_portp, addrp,
5363 5461 SATA_PSTATE_FAILED);
5364 5462 return (AHCI_FAILURE);
5365 5463 }
5366 5464 break;
5367 5465 }
5368 5466
5369 5467 /* Wait for 10 millisec */
5370 5468 drv_usecwait(AHCI_10MS_USECS);
5371 5469 }
5372 5470
5373 5471 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
5374 5472 "ahci_port_reset: 2nd loop count: %d, "
5375 5473 "port_task_file = 0x%x port %d",
5376 5474 loop_count, port_task_file, port);
5377 5475
5378 5476 /* Clear port serror register for the port */
5379 5477 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5380 5478 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
5381 5479 AHCI_SERROR_CLEAR_ALL);
5382 5480
5383 5481 /* Set port as ready */
5384 5482 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp);
5385 5483 AHCIPORT_SET_STATE(ahci_portp, addrp, port_state|SATA_STATE_READY);
5386 5484
5387 5485 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp,
5388 5486 "ahci_port_reset: succeed at port %d.", port);
5389 5487 return (AHCI_SUCCESS);
5390 5488 }
5391 5489
5392 5490 /*
5393 5491 * COMRESET on a port multiplier port.
5394 5492 *
5395 5493 * NOTE: Only called in ahci_port_reset()
5396 5494 */
5397 5495 static int
5398 5496 ahci_pmport_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
5399 5497 ahci_addr_t *addrp)
5400 5498 {
5401 5499 uint32_t port_scontrol, port_sstatus, port_serror;
5402 5500 uint32_t port_cmd_status, port_intr_status;
5403 5501 uint32_t port_state;
5404 5502 uint8_t port = addrp->aa_port;
5405 5503 uint8_t pmport = addrp->aa_pmport;
5406 5504 int loop_count;
5407 5505 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
5408 5506
5409 5507 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
5410 5508 "port %d:%d: pmport resetting", port, pmport);
5411 5509
5412 5510 /* Initialize pmport state */
5413 5511 AHCIPORT_SET_STATE(ahci_portp, addrp, 0);
5414 5512
5415 5513 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &port_scontrol, err);
5416 5514 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET);
5417 5515 WRITE_PMULT(addrp, SATA_PMULT_REG_SCTL, port_scontrol, err);
5418 5516
5419 5517 /* PxCMD.FRE should be set before. */
5420 5518 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5421 5519 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5422 5520 ASSERT(port_cmd_status & AHCI_CMD_STATUS_FRE);
5423 5521 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE))
5424 5522 return (AHCI_FAILURE);
5425 5523
5426 5524 /*
5427 5525 * Give time for COMRESET to percolate, according to the AHCI
5428 5526 * spec, software shall wait at least 1 millisecond before
5429 5527 * clearing PxSCTL.DET
5430 5528 */
5431 5529 drv_usecwait(AHCI_1MS_USECS*2);
5432 5530
5433 5531 /*
5434 5532 * Fetch the SCONTROL again and rewrite the DET part with 0
5435 5533 * This will generate an Asychronous Notification events.
5436 5534 */
5437 5535 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &port_scontrol, err);
5438 5536 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION);
5439 5537 WRITE_PMULT(addrp, SATA_PMULT_REG_SCTL, port_scontrol, err);
5440 5538
5441 5539 /*
5442 5540 * The port enters P:StartComm state, and HBA tells link layer to
5443 5541 * start communication, which involves sending COMRESET to device.
5444 5542 * And the HBA resets PxTFD.STS to 7Fh.
5445 5543 *
5446 5544 * When a COMINIT is received from the device, then the port enters
5447 5545 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets
5448 5546 * PxSSTS.DET to 1h to indicate a device is detected but communication
5449 5547 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate
5450 5548 * a COMINIT has been received.
5451 5549 */
5452 5550 /*
5453 5551 * The DET field is valid only if IPM field indicates
5454 5552 * that the interface is in active state.
5455 5553 */
5456 5554 loop_count = 0;
5457 5555 do {
5458 5556 READ_PMULT(addrp, SATA_PMULT_REG_SSTS, &port_sstatus, err);
5459 5557
5460 5558 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) {
5461 5559 /*
5462 5560 * If the interface is not active, the DET field
5463 5561 * is considered not accurate. So we want to
5464 5562 * continue looping.
5465 5563 */
5466 5564 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV);
5467 5565 }
5468 5566
5469 5567 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) {
5470 5568 /*
5471 5569 * We are effectively timing out after 0.1 sec.
5472 5570 */
5473 5571 break;
5474 5572 }
5475 5573
5476 5574 /* Wait for 10 millisec */
5477 5575 drv_usecwait(AHCI_10MS_USECS);
5478 5576
5479 5577 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM);
5480 5578
5481 5579 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5482 5580 "ahci_pmport_reset: 1st loop count: %d, "
5483 5581 "port_sstatus = 0x%x port %d:%d",
5484 5582 loop_count, port_sstatus, port, pmport);
5485 5583
5486 5584 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) ||
5487 5585 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) {
5488 5586 /*
5489 5587 * Either the port is not active or there
5490 5588 * is no device present.
5491 5589 */
5492 5590 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp,
5493 5591 "ahci_pmport_reset: "
5494 5592 "no device attached to port %d:%d",
5495 5593 port, pmport);
5496 5594 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_NONE);
5497 5595 return (AHCI_SUCCESS);
5498 5596 }
5499 5597
5500 5598 /* Now we can make sure there is a device connected to the port */
5501 5599 /* COMINIT signal is supposed to be received (PxSERR.DIAG.X = '1') */
5502 5600 READ_PMULT(addrp, SATA_PMULT_REG_SERR, &port_serror, err);
5503 5601
5504 5602 if (!(port_serror & (1 << 26))) {
5505 5603 cmn_err(CE_WARN, "!ahci%d: ahci_pmport_reset: "
5506 5604 "COMINIT signal from the device not received port %d:%d",
5507 5605 instance, port, pmport);
5508 5606
5509 5607 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_PSTATE_FAILED);
5510 5608 return (AHCI_FAILURE);
5511 5609 }
5512 5610
5513 5611 /*
5514 5612 * After clear PxSERR register, we will receive a D2H FIS.
5515 5613 * Normally this FIS will cause a IPMS error according to AHCI spec
5516 5614 * v1.2 because there is no command outstanding for it. So we need
5517 5615 * to ignore this error.
5518 5616 */
5519 5617 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_IGNORE_IPMS;
5520 5618 WRITE_PMULT(addrp, SATA_PMULT_REG_SERR, AHCI_SERROR_CLEAR_ALL, err);
5521 5619
5522 5620 /* Now we need to check the D2H FIS by checking IPMS error. */
5523 5621 loop_count = 0;
5524 5622 do {
5525 5623 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5526 5624 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port));
5527 5625
5528 5626 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) {
5529 5627 /*
5530 5628 * No D2H FIS received. This is possible according
5531 5629 * to SATA 2.6 spec.
5532 5630 */
5533 5631 cmn_err(CE_WARN, "ahci_port_reset: port %d:%d "
5534 5632 "PxIS.IPMS is not set, we need another "
5535 5633 "software reset.", port, pmport);
5536 5634
5537 5635 break;
5538 5636 }
5539 5637
5540 5638 /* Wait for 10 millisec */
5541 5639 mutex_exit(&ahci_portp->ahciport_mutex);
5542 5640 delay(AHCI_10MS_TICKS);
5543 5641 mutex_enter(&ahci_portp->ahciport_mutex);
5544 5642
5545 5643 } while (!(port_intr_status & AHCI_INTR_STATUS_IPMS));
5546 5644
5547 5645 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5548 5646 "ahci_pmport_reset: 2st loop count: %d, "
5549 5647 "port_sstatus = 0x%x port %d:%d",
5550 5648 loop_count, port_sstatus, port, pmport);
5551 5649
5552 5650 /* Clear IPMS */
5553 5651 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5554 5652 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port),
5555 5653 AHCI_INTR_STATUS_IPMS);
5556 5654 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_IGNORE_IPMS;
5557 5655
5558 5656 /* This pmport is now ready for ahci_tran_start() */
5559 5657 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp);
5560 5658 AHCIPORT_SET_STATE(ahci_portp, addrp, port_state|SATA_STATE_READY);
5561 5659
5562 5660 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp,
5563 5661 "ahci_pmport_reset: succeed at port %d:%d", port, pmport);
5564 5662 return (AHCI_SUCCESS);
5565 5663
5566 5664 err: /* R/W PMULT error */
5567 5665 /* IPMS flags might be set before. */
5568 5666 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_IGNORE_IPMS;
5569 5667 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp,
5570 5668 "ahci_pmport_reset: failed at port %d:%d", port, pmport);
5571 5669
5572 5670 return (AHCI_FAILURE);
5573 5671 }
5574 5672
5575 5673 /*
5576 5674 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled.
5577 5675 * This is the most intrusive.
5578 5676 *
5579 5677 * When an HBA reset occurs, Phy communication will be re-established with
5580 5678 * the device through a COMRESET followed by the normal out-of-band
5581 5679 * communication sequence defined in Serial ATA. At the end of reset, the
5582 5680 * device, if working properly, will send a D2H Register FIS, which contains
5583 5681 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS
5584 5682 * and PxTFD.ERR register fields, and updates the PxSIG register with the
5585 5683 * signature.
5586 5684 *
5587 5685 * Remember to set GHC.AE to 1 before calling ahci_hba_reset.
5588 5686 */
5589 5687 static int
5590 5688 ahci_hba_reset(ahci_ctl_t *ahci_ctlp)
5591 5689 {
5592 5690 ahci_port_t *ahci_portp;
5593 5691 uint32_t ghc_control;
5594 5692 uint8_t port;
5595 5693 int loop_count;
5596 5694 int rval = AHCI_SUCCESS;
5597 5695
5598 5696 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting",
5599 5697 NULL);
5600 5698
5601 5699 mutex_enter(&ahci_ctlp->ahcictl_mutex);
5602 5700
5603 5701 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5604 5702 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
5605 5703
5606 5704 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */
5607 5705 ghc_control |= AHCI_HBA_GHC_HR;
5608 5706 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5609 5707 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
5610 5708
5611 5709 /*
5612 5710 * Wait until HBA Reset complete or timeout
5613 5711 */
5614 5712 loop_count = 0;
5615 5713 do {
5616 5714 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5617 5715 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
5618 5716
5619 5717 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) {
5620 5718 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
5621 5719 "ahci hba reset is timing out, "
5622 5720 "ghc_control = 0x%x", ghc_control);
5623 5721 /* We are effectively timing out after 1 sec. */
5624 5722 break;
5625 5723 }
5626 5724
5627 5725 /* Wait for 10 millisec */
5628 5726 drv_usecwait(AHCI_10MS_USECS);
5629 5727 } while (ghc_control & AHCI_HBA_GHC_HR);
5630 5728
5631 5729 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5632 5730 "ahci_hba_reset: 1st loop count: %d, "
5633 5731 "ghc_control = 0x%x", loop_count, ghc_control);
5634 5732
5635 5733 if (ghc_control & AHCI_HBA_GHC_HR) {
5636 5734 /* The hba is not reset for some reasons */
5637 5735 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
5638 5736 "hba reset failed: HBA in a hung or locked state", NULL);
5639 5737 mutex_exit(&ahci_ctlp->ahcictl_mutex);
5640 5738 return (AHCI_FAILURE);
5641 5739 }
5642 5740
5643 5741 /*
5644 5742 * HBA reset will clear (AHCI Spec v1.2 10.4.3) GHC.IE / GHC.AE
5645 5743 */
5646 5744 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5647 5745 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
5648 5746 ghc_control |= (AHCI_HBA_GHC_AE | AHCI_HBA_GHC_IE);
5649 5747 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5650 5748 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
5651 5749
5652 5750 mutex_exit(&ahci_ctlp->ahcictl_mutex);
5653 5751
5654 5752 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
5655 5753 /* Only check implemented ports */
5656 5754 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
5657 5755 continue;
5658 5756 }
5659 5757
5660 5758 ahci_portp = ahci_ctlp->ahcictl_ports[port];
5661 5759 mutex_enter(&ahci_portp->ahciport_mutex);
5662 5760
5663 5761 /* Make sure the drive is spun-up */
5664 5762 ahci_staggered_spin_up(ahci_ctlp, port);
5665 5763
5666 5764 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp,
5667 5765 port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, NULL) !=
5668 5766 AHCI_SUCCESS) {
5669 5767 rval = AHCI_FAILURE;
5670 5768 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5671 5769 "ahci_hba_reset: port %d failed", port);
5672 5770 /*
5673 5771 * Set the port state to SATA_PSTATE_FAILED if
5674 5772 * failed to initialize it.
5675 5773 */
5676 5774 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED;
5677 5775 }
5678 5776
5679 5777 mutex_exit(&ahci_portp->ahciport_mutex);
5680 5778 }
5681 5779
5682 5780 return (rval);
5683 5781 }
5684 5782
5685 5783 /*
5686 5784 * This routine is only called from AHCI_ATTACH or phyrdy change
5687 5785 * case. It first calls software reset, then stop the port and try to
5688 5786 * read PxSIG register to find the type of device attached to the port.
5689 5787 *
5690 5788 * The caller should make sure a valid device exists on specified port and
5691 5789 * physical communication has been established so that the signature could
5692 5790 * be retrieved by software reset.
5693 5791 *
5694 5792 * NOTE: The port interrupts should be disabled before the function is called.
5695 5793 */
5696 5794 static void
5697 5795 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
5698 5796 ahci_addr_t *addrp)
5699 5797 {
5700 5798 ahci_addr_t dev_addr;
5701 5799 uint32_t signature;
5702 5800 uint8_t port = addrp->aa_port;
5703 5801 uint8_t pmport = addrp->aa_pmport;
5704 5802 int rval;
5705 5803
5706 5804 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5707 5805 ASSERT(AHCI_ADDR_IS_VALID(addrp));
5708 5806
5709 5807 /*
5710 5808 * If the HBA doesn't support port multiplier, then the driver
5711 5809 * doesn't need to bother to check port multiplier device.
5712 5810 *
5713 5811 * The second port of ICH7 on ASUS P5W DH deluxe motherboard is
5714 5812 * connected to Silicon Image 4723, to which the two sata drives
5715 5813 * attached can be set with RAID1, RAID0 or Spanning mode.
5716 5814 *
5717 5815 * We found software reset will get failure if port multiplier address
5718 5816 * 0xf is used by software reset, so just ignore the check since
5719 5817 * ICH7 doesn't support port multiplier device at all.
5720 5818 */
5721 5819 if (AHCI_ADDR_IS_PORT(addrp) &&
5722 5820 (ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_CBSS)) {
5723 5821 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
5724 5822 "ahci_find_dev_signature enter: port %d", port);
5725 5823
5726 5824 /*
5727 5825 * NOTE: when the ahci address is a HBA port, we do not know
5728 5826 * it is a device or a port multiplier that attached. we need
5729 5827 * try a software reset at port multiplier address (0xf
5730 5828 * pmport)
5731 5829 */
5732 5830 AHCI_ADDR_SET_PMULT(&dev_addr, addrp->aa_port);
5733 5831 } else {
5734 5832 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
5735 5833 "ahci_find_dev_signature enter: port %d:%d",
5736 5834 port, pmport);
5737 5835 dev_addr = *addrp;
5738 5836 }
5739 5837
5740 5838 /* Assume it is unknown. */
5741 5839 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
5742 5840
5743 5841 /* Issue a software reset to get the signature */
5744 5842 rval = ahci_software_reset(ahci_ctlp, ahci_portp, &dev_addr);
5745 5843 if (rval != AHCI_SUCCESS) {
5746 5844
5747 5845 /*
5748 5846 * Try to do software reset again with pmport set with 0 if
5749 5847 * the controller is set with AHCI_CAP_SRST_NO_HOSTPORT and
5750 5848 * the original pmport is set with SATA_PMULT_HOSTPORT (0xf)
5751 5849 */
5752 5850 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_SRST_NO_HOSTPORT) &&
5753 5851 (dev_addr.aa_pmport == SATA_PMULT_HOSTPORT)) {
5754 5852 dev_addr.aa_pmport = 0;
5755 5853 rval = ahci_software_reset(ahci_ctlp, ahci_portp,
5756 5854 &dev_addr);
5757 5855 }
5758 5856
5759 5857 if (rval != AHCI_SUCCESS) {
5760 5858 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5761 5859 "ahci_find_dev_signature: software reset failed "
5762 5860 "at port %d:%d, cannot get signature.",
5763 5861 port, pmport);
5764 5862
5765 5863 AHCIPORT_SET_STATE(ahci_portp, addrp,
5766 5864 SATA_PSTATE_FAILED);
5767 5865 return;
5768 5866 }
5769 5867 }
5770 5868
5771 5869 /*
5772 5870 * ahci_software_reset has started the port, so we need manually stop
5773 5871 * the port again.
5774 5872 */
5775 5873 if (AHCI_ADDR_IS_PORT(addrp)) {
5776 5874 if (ahci_put_port_into_notrunning_state(ahci_ctlp,
5777 5875 ahci_portp, port) != AHCI_SUCCESS) {
5778 5876 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5779 5877 "ahci_find_dev_signature: cannot stop port %d.",
5780 5878 port);
5781 5879 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED;
5782 5880 return;
5783 5881 }
5784 5882 }
5785 5883
5786 5884 /* Now we can make sure that a valid signature is received. */
5787 5885 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5788 5886 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port));
5789 5887
5790 5888 if (AHCI_ADDR_IS_PMPORT(addrp)) {
5791 5889 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
5792 5890 "ahci_find_dev_signature: signature = 0x%x at port %d:%d",
5793 5891 signature, port, pmport);
5794 5892 } else {
5795 5893 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp,
5796 5894 "ahci_find_dev_signature: signature = 0x%x at port %d",
5797 5895 signature, port);
5798 5896 }
5799 5897
5800 5898 /* NOTE: Only support ATAPI device at controller port. */
5801 5899 if (signature == AHCI_SIGNATURE_ATAPI && !AHCI_ADDR_IS_PORT(addrp))
5802 5900 signature = SATA_DTYPE_UNKNOWN;
5803 5901
5804 5902 switch (signature) {
5805 5903
5806 5904 case AHCI_SIGNATURE_DISK:
5807 5905 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_ATADISK);
5808 5906 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5809 5907 "Disk is found at port: %d", port);
5810 5908 break;
5811 5909
5812 5910 case AHCI_SIGNATURE_ATAPI:
5813 5911 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_ATAPI);
5814 5912 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5815 5913 "ATAPI device is found at port: %d", port);
5816 5914 break;
5817 5915
5818 5916 case AHCI_SIGNATURE_PORT_MULTIPLIER:
5819 5917 /* Port Multiplier cannot recursively attached. */
5820 5918 ASSERT(AHCI_ADDR_IS_PORT(addrp));
5821 5919 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_PMULT);
5822 5920 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5823 5921 "Port Multiplier is found at port: %d", port);
5824 5922 break;
5825 5923
5826 5924 default:
5827 5925 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
5828 5926 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5829 5927 "Unknown device is found at port: %d", port);
5830 5928 }
5831 5929 }
5832 5930
5833 5931 /*
5834 5932 * According to the spec, to reliably detect hot plug removals, software
5835 5933 * must disable interface power management. Software should perform the
5836 5934 * following initialization on a port after a device is attached:
5837 5935 * Set PxSCTL.IPM to 3h to disable interface state transitions
5838 5936 * Set PxCMD.ALPE to '0' to disable aggressive power management
5839 5937 * Disable device initiated interface power management by SET FEATURE
5840 5938 *
5841 5939 * We can ignore the last item because by default the feature is disabled
5842 5940 */
5843 5941 static void
5844 5942 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port)
5845 5943 {
5846 5944 uint32_t port_scontrol, port_cmd_status;
5847 5945
5848 5946 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5849 5947 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
5850 5948 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH);
5851 5949 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5852 5950 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol);
5853 5951
5854 5952 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5855 5953 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5856 5954 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE;
5857 5955 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5858 5956 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status);
5859 5957 }
5860 5958
5861 5959 /*
5862 5960 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set
5863 5961 * to 1, then set it firstly.
5864 5962 *
5865 5963 * Each port contains two major DMA engines. One DMA engine walks through
5866 5964 * the command list, and is controlled by PxCMD.ST. The second DMA engine
5867 5965 * copies received FISes into system memory, and is controlled by PxCMD.FRE.
5868 5966 *
5869 5967 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR
5870 5968 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear
5871 5969 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'.
5872 5970 *
5873 5971 * Software shall not set PxCMD.ST to '1' unless a functional device is
5874 5972 * present on the port(as determined by PxTFD.STS.BSY = '0',
5875 5973 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h).
5876 5974 */
5877 5975 static int
5878 5976 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port)
5879 5977 {
5880 5978 uint32_t port_cmd_status;
5881 5979
5882 5980 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5883 5981
5884 5982 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port);
5885 5983
5886 5984 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) {
5887 5985 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed "
5888 5986 "the state for port %d is 0x%x",
5889 5987 port, ahci_portp->ahciport_port_state);
5890 5988 return (AHCI_FAILURE);
5891 5989 }
5892 5990
5893 5991 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
5894 5992 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed "
5895 5993 "no device is attached at port %d", port);
5896 5994 return (AHCI_FAILURE);
5897 5995 }
5898 5996
5899 5997 /* First to set PxCMD.FRE before setting PxCMD.ST. */
5900 5998 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5901 5999 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5902 6000
5903 6001 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) {
5904 6002 port_cmd_status |= AHCI_CMD_STATUS_FRE;
5905 6003 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5906 6004 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5907 6005 port_cmd_status);
5908 6006 }
5909 6007
5910 6008 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5911 6009 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5912 6010
5913 6011 port_cmd_status |= AHCI_CMD_STATUS_ST;
5914 6012
5915 6013 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5916 6014 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5917 6015 port_cmd_status);
5918 6016
5919 6017 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED;
5920 6018
5921 6019 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port: "
5922 6020 "PxCMD.ST set to '1' at port %d", port);
5923 6021
5924 6022 return (AHCI_SUCCESS);
5925 6023 }
5926 6024
5927 6025 /*
5928 6026 * Setup PxCLB, PxCLBU, PxFB, and PxFBU for particular port. First, we need
5929 6027 * to make sure PxCMD.ST, PxCMD.CR, PxCMD.FRE, and PxCMD.FR are all cleared.
5930 6028 * Then set PxCLB, PxCLBU, PxFB, and PxFBU.
5931 6029 */
5932 6030 static int
5933 6031 ahci_setup_port_base_addresses(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
5934 6032 {
5935 6033 uint8_t port = ahci_portp->ahciport_port_num;
5936 6034 uint32_t port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5937 6035 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5938 6036
5939 6037 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5940 6038
5941 6039 /* Step 1: Make sure both PxCMD.ST and PxCMD.CR are cleared. */
5942 6040 if (port_cmd_status & (AHCI_CMD_STATUS_ST | AHCI_CMD_STATUS_CR)) {
5943 6041 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp,
5944 6042 port) != AHCI_SUCCESS)
5945 6043 return (AHCI_FAILURE);
5946 6044
5947 6045 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5948 6046 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5949 6047 }
5950 6048
5951 6049 /* Step 2: Make sure both PxCMD.FRE and PxCMD.FR are cleared. */
5952 6050 if (port_cmd_status & (AHCI_CMD_STATUS_FRE | AHCI_CMD_STATUS_FR)) {
5953 6051 int loop_count = 0;
5954 6052
5955 6053 /* Clear PxCMD.FRE */
5956 6054 port_cmd_status &= ~AHCI_CMD_STATUS_FRE;
5957 6055 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5958 6056 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5959 6057 port_cmd_status);
5960 6058
5961 6059 /* Wait until PxCMD.FR is cleared */
5962 6060 for (;;) {
5963 6061 port_cmd_status =
5964 6062 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5965 6063 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5966 6064
5967 6065 if (!(port_cmd_status & AHCI_CMD_STATUS_FR))
5968 6066 break;
5969 6067
5970 6068 if (loop_count++ >= AHCI_POLLRATE_PORT_IDLE_FR) {
5971 6069 AHCIDBG(AHCIDBG_INIT | AHCIDBG_ERRS, ahci_ctlp,
5972 6070 "ahci_setup_port_base_addresses: cannot "
5973 6071 "clear PxCMD.FR for port %d.", port);
5974 6072
5975 6073 /*
5976 6074 * We are effectively timing out after 0.5 sec.
5977 6075 * This value is specified in AHCI spec.
5978 6076 */
5979 6077 return (AHCI_FAILURE);
5980 6078 }
5981 6079
5982 6080 /* Wait for 1 millisec */
5983 6081 drv_usecwait(AHCI_1MS_USECS);
5984 6082 }
5985 6083 }
5986 6084
5987 6085 /* Step 3: Config Port Command List Base Address */
5988 6086 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5989 6087 (uint32_t *)AHCI_PORT_PxCLB(ahci_ctlp, port),
5990 6088 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address);
5991 6089
5992 6090 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5993 6091 (uint32_t *)AHCI_PORT_PxCLBU(ahci_ctlp, port),
5994 6092 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_notused);
5995 6093
5996 6094 /* Step 4: Config Port Received FIS Base Address */
5997 6095 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5998 6096 (uint32_t *)AHCI_PORT_PxFB(ahci_ctlp, port),
5999 6097 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address);
6000 6098
6001 6099 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
6002 6100 (uint32_t *)AHCI_PORT_PxFBU(ahci_ctlp, port),
6003 6101 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_notused);
6004 6102
6005 6103 return (AHCI_SUCCESS);
6006 6104 }
6007 6105
6008 6106 /*
6009 6107 * Allocate the ahci_port_t including Received FIS and Command List.
6010 6108 * The argument - port is the physical port number, and not logical
6011 6109 * port number seen by the SATA framework.
6012 6110 */
6013 6111 static int
6014 6112 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port)
6015 6113 {
6016 6114 dev_info_t *dip = ahci_ctlp->ahcictl_dip;
6017 6115 ahci_port_t *ahci_portp;
6018 6116 char taskq_name[64] = "event_handle_taskq";
6019 6117
6020 6118 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
6021 6119
6022 6120 ahci_portp =
6023 6121 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP);
6024 6122
6025 6123 ahci_ctlp->ahcictl_ports[port] = ahci_portp;
6026 6124 ahci_portp->ahciport_port_num = port;
6027 6125
6028 6126 /* Initialize the port condition variable */
6029 6127 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL);
6030 6128
6031 6129 /* Initialize the port mutex */
6032 6130 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER,
6033 6131 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri);
6034 6132
6035 6133 mutex_enter(&ahci_portp->ahciport_mutex);
6036 6134
6037 6135 /*
6038 6136 * Allocate memory for received FIS structure and
6039 6137 * command list for this port
6040 6138 */
6041 6139 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) {
6042 6140 goto err_case1;
6043 6141 }
6044 6142
6045 6143 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) {
6046 6144 goto err_case2;
6047 6145 }
6048 6146
6049 6147 /* Setup PxCMD.CLB, PxCMD.CLBU, PxCMD.FB, and PxCMD.FBU */
6050 6148 if (ahci_setup_port_base_addresses(ahci_ctlp, ahci_portp) !=
6051 6149 AHCI_SUCCESS) {
6052 6150 goto err_case3;
6053 6151 }
6054 6152
6055 6153 (void) snprintf(taskq_name + strlen(taskq_name),
6056 6154 sizeof (taskq_name) - strlen(taskq_name),
6057 6155 "_port%d", port);
6058 6156
6059 6157 /* Create the taskq for the port */
6060 6158 if ((ahci_portp->ahciport_event_taskq = ddi_taskq_create(dip,
6061 6159 taskq_name, 2, TASKQ_DEFAULTPRI, 0)) == NULL) {
6062 6160 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event "
6063 6161 "handle", ddi_get_instance(ahci_ctlp->ahcictl_dip));
6064 6162 goto err_case3;
6065 6163 }
6066 6164
6067 6165 /* Allocate the argument for the taskq */
6068 6166 ahci_portp->ahciport_event_args =
6069 6167 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP);
6070 6168
6071 6169 ahci_portp->ahciport_event_args->ahciea_addrp =
6072 6170 kmem_zalloc(sizeof (ahci_addr_t), KM_SLEEP);
6073 6171
6074 6172 if (ahci_portp->ahciport_event_args == NULL)
6075 6173 goto err_case4;
6076 6174
6077 6175 /* Initialize the done queue */
6078 6176 ahci_portp->ahciport_doneq = NULL;
6079 6177 ahci_portp->ahciport_doneqtail = &ahci_portp->ahciport_doneq;
6080 6178 ahci_portp->ahciport_doneq_len = 0;
6081 6179
6082 6180 mutex_exit(&ahci_portp->ahciport_mutex);
6083 6181
6084 6182 return (AHCI_SUCCESS);
6085 6183
6086 6184 err_case4:
6087 6185 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq);
6088 6186
6089 6187 err_case3:
6090 6188 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp);
6091 6189
6092 6190 err_case2:
6093 6191 ahci_dealloc_rcvd_fis(ahci_portp);
6094 6192
6095 6193 err_case1:
6096 6194 mutex_exit(&ahci_portp->ahciport_mutex);
6097 6195 mutex_destroy(&ahci_portp->ahciport_mutex);
6098 6196 cv_destroy(&ahci_portp->ahciport_cv);
6099 6197
6100 6198 kmem_free(ahci_portp, sizeof (ahci_port_t));
6101 6199
6102 6200 return (AHCI_FAILURE);
6103 6201 }
6104 6202
6105 6203 /*
6106 6204 * Reverse of ahci_alloc_port_state().
6107 6205 */
6108 6206 static void
6109 6207 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port)
6110 6208 {
6111 6209 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port];
6112 6210
6113 6211 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
6114 6212 ASSERT(ahci_portp != NULL);
6115 6213
6116 6214 mutex_enter(&ahci_portp->ahciport_mutex);
6117 6215 kmem_free(ahci_portp->ahciport_event_args->ahciea_addrp,
6118 6216 sizeof (ahci_addr_t));
6119 6217 ahci_portp->ahciport_event_args->ahciea_addrp = NULL;
6120 6218 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t));
6121 6219 ahci_portp->ahciport_event_args = NULL;
6122 6220 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq);
6123 6221 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp);
6124 6222 ahci_dealloc_rcvd_fis(ahci_portp);
6125 6223 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
6126 6224 mutex_exit(&ahci_portp->ahciport_mutex);
6127 6225
6128 6226 mutex_destroy(&ahci_portp->ahciport_mutex);
6129 6227 cv_destroy(&ahci_portp->ahciport_cv);
6130 6228
6131 6229 kmem_free(ahci_portp, sizeof (ahci_port_t));
6132 6230
6133 6231 ahci_ctlp->ahcictl_ports[port] = NULL;
6134 6232 }
6135 6233
6136 6234 /*
6137 6235 * Allocates memory for the Received FIS Structure
6138 6236 */
6139 6237 static int
6140 6238 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6141 6239 {
6142 6240 size_t rcvd_fis_size;
6143 6241 size_t ret_len;
6144 6242 uint_t cookie_count;
6145 6243
6146 6244 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6147 6245
6148 6246 rcvd_fis_size = sizeof (ahci_rcvd_fis_t);
6149 6247
6150 6248 /* allocate rcvd FIS dma handle. */
6151 6249 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip,
6152 6250 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr,
6153 6251 DDI_DMA_SLEEP,
6154 6252 NULL,
6155 6253 &ahci_portp->ahciport_rcvd_fis_dma_handle) !=
6156 6254 DDI_SUCCESS) {
6157 6255 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6158 6256 "rcvd FIS dma handle alloc failed", NULL);
6159 6257
6160 6258 return (AHCI_FAILURE);
6161 6259 }
6162 6260
6163 6261 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle,
6164 6262 rcvd_fis_size,
6165 6263 &accattr,
6166 6264 DDI_DMA_CONSISTENT,
6167 6265 DDI_DMA_SLEEP,
6168 6266 NULL,
6169 6267 (caddr_t *)&ahci_portp->ahciport_rcvd_fis,
6170 6268 &ret_len,
6171 6269 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) {
6172 6270
6173 6271 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6174 6272 "rcvd FIS dma mem alloc fail", NULL);
6175 6273 /* error.. free the dma handle. */
6176 6274 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle);
6177 6275 return (AHCI_FAILURE);
6178 6276 }
6179 6277
6180 6278 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle,
6181 6279 NULL,
6182 6280 (caddr_t)ahci_portp->ahciport_rcvd_fis,
6183 6281 rcvd_fis_size,
6184 6282 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
6185 6283 DDI_DMA_SLEEP,
6186 6284 NULL,
6187 6285 &ahci_portp->ahciport_rcvd_fis_dma_cookie,
6188 6286 &cookie_count) != DDI_DMA_MAPPED) {
6189 6287
6190 6288 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6191 6289 "rcvd FIS dma handle bind fail", NULL);
6192 6290 /* error.. free the dma handle & free the memory. */
6193 6291 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle);
6194 6292 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle);
6195 6293 return (AHCI_FAILURE);
6196 6294 }
6197 6295
6198 6296 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size);
6199 6297
6200 6298 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx",
6201 6299 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress);
6202 6300 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x",
6203 6301 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address);
6204 6302
6205 6303 return (AHCI_SUCCESS);
6206 6304 }
6207 6305
6208 6306 /*
6209 6307 * Deallocates the Received FIS Structure
6210 6308 */
6211 6309 static void
6212 6310 ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp)
6213 6311 {
6214 6312 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6215 6313
6216 6314 /* Unbind the cmd list dma handle first. */
6217 6315 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle);
6218 6316
6219 6317 /* Then free the underlying memory. */
6220 6318 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle);
6221 6319
6222 6320 /* Now free the handle itself. */
6223 6321 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle);
6224 6322 }
6225 6323
6226 6324 /*
6227 6325 * Allocates memory for the Command List, which contains up to 32 entries.
6228 6326 * Each entry contains a command header, which is a 32-byte structure that
6229 6327 * includes the pointer to the command table.
6230 6328 */
6231 6329 static int
6232 6330 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6233 6331 {
6234 6332 size_t cmd_list_size;
6235 6333 size_t ret_len;
6236 6334 uint_t cookie_count;
6237 6335
6238 6336 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6239 6337
6240 6338 cmd_list_size =
6241 6339 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t);
6242 6340
6243 6341 /* allocate cmd list dma handle. */
6244 6342 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip,
6245 6343 &ahci_ctlp->ahcictl_cmd_list_dma_attr,
6246 6344 DDI_DMA_SLEEP,
6247 6345 NULL,
6248 6346 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) {
6249 6347
6250 6348 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6251 6349 "cmd list dma handle alloc failed", NULL);
6252 6350 return (AHCI_FAILURE);
6253 6351 }
6254 6352
6255 6353 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle,
6256 6354 cmd_list_size,
6257 6355 &accattr,
6258 6356 DDI_DMA_CONSISTENT,
6259 6357 DDI_DMA_SLEEP,
6260 6358 NULL,
6261 6359 (caddr_t *)&ahci_portp->ahciport_cmd_list,
6262 6360 &ret_len,
6263 6361 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) {
6264 6362
6265 6363 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6266 6364 "cmd list dma mem alloc fail", NULL);
6267 6365 /* error.. free the dma handle. */
6268 6366 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6269 6367 return (AHCI_FAILURE);
6270 6368 }
6271 6369
6272 6370 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle,
6273 6371 NULL,
6274 6372 (caddr_t)ahci_portp->ahciport_cmd_list,
6275 6373 cmd_list_size,
6276 6374 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
6277 6375 DDI_DMA_SLEEP,
6278 6376 NULL,
6279 6377 &ahci_portp->ahciport_cmd_list_dma_cookie,
6280 6378 &cookie_count) != DDI_DMA_MAPPED) {
6281 6379
6282 6380 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6283 6381 "cmd list dma handle bind fail", NULL);
6284 6382 /* error.. free the dma handle & free the memory. */
6285 6383 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle);
6286 6384 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6287 6385 return (AHCI_FAILURE);
6288 6386 }
6289 6387
6290 6388 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size);
6291 6389
6292 6390 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx",
6293 6391 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress);
6294 6392
6295 6393 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x",
6296 6394 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address);
6297 6395
6298 6396 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) {
6299 6397 goto err_out;
6300 6398 }
6301 6399
6302 6400 return (AHCI_SUCCESS);
6303 6401
6304 6402 err_out:
6305 6403 /* Unbind the cmd list dma handle first. */
6306 6404 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle);
6307 6405
6308 6406 /* Then free the underlying memory. */
6309 6407 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle);
6310 6408
6311 6409 /* Now free the handle itself. */
6312 6410 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6313 6411
6314 6412 return (AHCI_FAILURE);
6315 6413 }
6316 6414
6317 6415 /*
6318 6416 * Deallocates the Command List
6319 6417 */
6320 6418 static void
6321 6419 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6322 6420 {
6323 6421 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6324 6422
6325 6423 /* First dealloc command table */
6326 6424 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp);
6327 6425
6328 6426 /* Unbind the cmd list dma handle first. */
6329 6427 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle);
6330 6428
6331 6429 /* Then free the underlying memory. */
6332 6430 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle);
6333 6431
6334 6432 /* Now free the handle itself. */
6335 6433 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6336 6434 }
6337 6435
6338 6436 /*
6339 6437 * Allocates memory for all Command Tables, which contains Command FIS,
6340 6438 * ATAPI Command and Physical Region Descriptor Table.
6341 6439 */
6342 6440 static int
6343 6441 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6344 6442 {
6345 6443 size_t ret_len;
6346 6444 ddi_dma_cookie_t cmd_table_dma_cookie;
6347 6445 uint_t cookie_count;
6348 6446 int slot;
6349 6447
6350 6448 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6351 6449
6352 6450 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
6353 6451 "ahci_alloc_cmd_tables: port %d enter",
6354 6452 ahci_portp->ahciport_port_num);
6355 6453
6356 6454 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) {
6357 6455 /* Allocate cmd table dma handle. */
6358 6456 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip,
6359 6457 &ahci_ctlp->ahcictl_cmd_table_dma_attr,
6360 6458 DDI_DMA_SLEEP,
6361 6459 NULL,
6362 6460 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) !=
6363 6461 DDI_SUCCESS) {
6364 6462
6365 6463 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6366 6464 "cmd table dma handle alloc failed", NULL);
6367 6465
6368 6466 goto err_out;
6369 6467 }
6370 6468
6371 6469 if (ddi_dma_mem_alloc(
6372 6470 ahci_portp->ahciport_cmd_tables_dma_handle[slot],
6373 6471 ahci_cmd_table_size,
6374 6472 &accattr,
6375 6473 DDI_DMA_CONSISTENT,
6376 6474 DDI_DMA_SLEEP,
6377 6475 NULL,
6378 6476 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot],
6379 6477 &ret_len,
6380 6478 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) !=
6381 6479 NULL) {
6382 6480
6383 6481 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6384 6482 "cmd table dma mem alloc fail", NULL);
6385 6483
6386 6484 /* error.. free the dma handle. */
6387 6485 ddi_dma_free_handle(
6388 6486 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6389 6487 goto err_out;
6390 6488 }
6391 6489
6392 6490 if (ddi_dma_addr_bind_handle(
6393 6491 ahci_portp->ahciport_cmd_tables_dma_handle[slot],
6394 6492 NULL,
6395 6493 (caddr_t)ahci_portp->ahciport_cmd_tables[slot],
6396 6494 ahci_cmd_table_size,
6397 6495 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
6398 6496 DDI_DMA_SLEEP,
6399 6497 NULL,
6400 6498 &cmd_table_dma_cookie,
6401 6499 &cookie_count) != DDI_DMA_MAPPED) {
6402 6500
6403 6501 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6404 6502 "cmd table dma handle bind fail", NULL);
6405 6503 /* error.. free the dma handle & free the memory. */
6406 6504 ddi_dma_mem_free(
6407 6505 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]);
6408 6506 ddi_dma_free_handle(
6409 6507 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6410 6508 goto err_out;
6411 6509 }
6412 6510
6413 6511 bzero((void *)ahci_portp->ahciport_cmd_tables[slot],
6414 6512 ahci_cmd_table_size);
6415 6513
6416 6514 /* Config Port Command Table Base Address */
6417 6515 SET_COMMAND_TABLE_BASE_ADDR(
6418 6516 (&ahci_portp->ahciport_cmd_list[slot]),
6419 6517 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull);
6420 6518
6421 6519 #ifndef __lock_lint
6422 6520 SET_COMMAND_TABLE_BASE_ADDR_UPPER(
6423 6521 (&ahci_portp->ahciport_cmd_list[slot]),
6424 6522 cmd_table_dma_cookie.dmac_laddress >> 32);
6425 6523 #endif
6426 6524 }
6427 6525
6428 6526 return (AHCI_SUCCESS);
6429 6527 err_out:
6430 6528
6431 6529 for (slot--; slot >= 0; slot--) {
6432 6530 /* Unbind the cmd table dma handle first */
6433 6531 (void) ddi_dma_unbind_handle(
6434 6532 ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6435 6533
6436 6534 /* Then free the underlying memory */
6437 6535 ddi_dma_mem_free(
6438 6536 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]);
6439 6537
6440 6538 /* Now free the handle itself */
6441 6539 ddi_dma_free_handle(
6442 6540 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6443 6541 }
6444 6542
6445 6543 return (AHCI_FAILURE);
6446 6544 }
6447 6545
6448 6546 /*
6449 6547 * Deallocates memory for all Command Tables.
6450 6548 */
6451 6549 static void
6452 6550 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6453 6551 {
6454 6552 int slot;
6455 6553
6456 6554 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6457 6555
6458 6556 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
6459 6557 "ahci_dealloc_cmd_tables: %d enter",
6460 6558 ahci_portp->ahciport_port_num);
6461 6559
6462 6560 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) {
6463 6561 /* Unbind the cmd table dma handle first. */
6464 6562 (void) ddi_dma_unbind_handle(
6465 6563 ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6466 6564
6467 6565 /* Then free the underlying memory. */
6468 6566 ddi_dma_mem_free(
6469 6567 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]);
6470 6568
6471 6569 /* Now free the handle itself. */
6472 6570 ddi_dma_free_handle(
6473 6571 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6474 6572 }
6475 6573 }
6476 6574
6477 6575 /*
6478 6576 * Update SATA registers at controller ports
6479 6577 */
6480 6578 static void
6481 6579 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port,
6482 6580 sata_device_t *sd)
6483 6581 {
6484 6582 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
6485 6583
6486 6584 sd->satadev_scr.sstatus =
6487 6585 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6488 6586 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port)));
6489 6587 sd->satadev_scr.serror =
6490 6588 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6491 6589 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port)));
6492 6590 sd->satadev_scr.scontrol =
6493 6591 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6494 6592 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port)));
6495 6593 sd->satadev_scr.sactive =
6496 6594 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6497 6595 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port)));
6498 6596 }
6499 6597
6500 6598 /*
6501 6599 * For poll mode, ahci_port_intr will be called to emulate the interrupt
6502 6600 */
6503 6601 static void
6504 6602 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port)
6505 6603 {
6506 6604 uint32_t port_intr_status;
6507 6605 uint32_t port_intr_enable;
6508 6606
6509 6607 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
6510 6608 "ahci_port_intr enter: port %d", port);
6511 6609
6512 6610 mutex_enter(&ahci_portp->ahciport_mutex);
6513 6611 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) {
6514 6612 /* For SATA_OPMODE_POLLING commands */
6515 6613 port_intr_enable =
6516 6614 (AHCI_INTR_STATUS_DHRS |
6517 6615 AHCI_INTR_STATUS_PSS |
6518 6616 AHCI_INTR_STATUS_SDBS |
6519 6617 AHCI_INTR_STATUS_UFS |
6520 6618 AHCI_INTR_STATUS_PCS |
6521 6619 AHCI_INTR_STATUS_PRCS |
6522 6620 AHCI_INTR_STATUS_OFS |
6523 6621 AHCI_INTR_STATUS_INFS |
6524 6622 AHCI_INTR_STATUS_IFS |
6525 6623 AHCI_INTR_STATUS_HBDS |
6526 6624 AHCI_INTR_STATUS_HBFS |
6527 6625 AHCI_INTR_STATUS_TFES);
6528 6626 } else {
6529 6627 /*
6530 6628 * port_intr_enable indicates that the corresponding interrrupt
6531 6629 * reporting is enabled.
6532 6630 */
6533 6631 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6534 6632 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port));
6535 6633 }
6536 6634
6537 6635 /* IPMS error in port reset should be ignored according AHCI spec. */
6538 6636 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_IGNORE_IPMS))
6539 6637 port_intr_enable |= AHCI_INTR_STATUS_IPMS;
6540 6638 mutex_exit(&ahci_portp->ahciport_mutex);
6541 6639
6542 6640 /*
6543 6641 * port_intr_stats indicates that the corresponding interrupt
6544 6642 * condition is active.
6545 6643 */
6546 6644 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6547 6645 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port));
6548 6646
6549 6647 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6550 6648 "ahci_port_intr: port %d, port_intr_status = 0x%x, "
6551 6649 "port_intr_enable = 0x%x",
6552 6650 port, port_intr_status, port_intr_enable);
6553 6651
6554 6652 port_intr_status &= port_intr_enable;
6555 6653
6556 6654 /*
6557 6655 * Pending interrupt events are indicated by the PxIS register.
6558 6656 * Make sure we don't miss any event.
6559 6657 */
6560 6658 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) {
6561 6659 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
6562 6660 DDI_SERVICE_UNAFFECTED);
6563 6661 ddi_fm_acc_err_clear(ahci_ctlp->ahcictl_ahci_acc_handle,
6564 6662 DDI_FME_VERSION);
6565 6663 return;
6566 6664 }
6567 6665
6568 6666 /* First clear the port interrupts status */
6569 6667 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
6570 6668 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port),
6571 6669 port_intr_status);
6572 6670
6573 6671 /* Check the completed non-queued commands */
6574 6672 if (port_intr_status & (AHCI_INTR_STATUS_DHRS |
6575 6673 AHCI_INTR_STATUS_PSS)) {
6576 6674 (void) ahci_intr_cmd_cmplt(ahci_ctlp,
6577 6675 ahci_portp, port);
6578 6676 }
6579 6677
6580 6678 /* Check the completed queued commands */
6581 6679 if (port_intr_status & AHCI_INTR_STATUS_SDBS) {
6582 6680 (void) ahci_intr_set_device_bits(ahci_ctlp,
6583 6681 ahci_portp, port);
6584 6682 }
6585 6683
6586 6684 /* Check the port connect change status interrupt bit */
6587 6685 if (port_intr_status & AHCI_INTR_STATUS_PCS) {
6588 6686 (void) ahci_intr_port_connect_change(ahci_ctlp,
6589 6687 ahci_portp, port);
6590 6688 }
6591 6689
6592 6690 /* Check the device mechanical presence status interrupt bit */
6593 6691 if (port_intr_status & AHCI_INTR_STATUS_DMPS) {
6594 6692 (void) ahci_intr_device_mechanical_presence_status(
6595 6693 ahci_ctlp, ahci_portp, port);
6596 6694 }
6597 6695
6598 6696 /* Check the PhyRdy change status interrupt bit */
6599 6697 if (port_intr_status & AHCI_INTR_STATUS_PRCS) {
6600 6698 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp,
6601 6699 port);
6602 6700 }
6603 6701
6604 6702 /*
6605 6703 * Check the non-fatal error interrupt bits, there are four
6606 6704 * kinds of non-fatal errors at the time being:
6607 6705 *
6608 6706 * PxIS.UFS - Unknown FIS Error
6609 6707 * PxIS.OFS - Overflow Error
6610 6708 * PxIS.INFS - Interface Non-Fatal Error
6611 6709 * PxIS.IPMS - Incorrect Port Multiplier Status Error
6612 6710 *
6613 6711 * For these non-fatal errors, the HBA can continue to operate,
6614 6712 * so the driver just log the error messages.
6615 6713 */
6616 6714 if (port_intr_status & (AHCI_INTR_STATUS_UFS |
6617 6715 AHCI_INTR_STATUS_OFS |
6618 6716 AHCI_INTR_STATUS_IPMS |
6619 6717 AHCI_INTR_STATUS_INFS)) {
6620 6718 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp,
6621 6719 port, port_intr_status);
6622 6720 }
6623 6721
6624 6722 /*
6625 6723 * Check the fatal error interrupt bits, there are four kinds
6626 6724 * of fatal errors for AHCI controllers:
6627 6725 *
6628 6726 * PxIS.HBFS - Host Bus Fatal Error
6629 6727 * PxIS.HBDS - Host Bus Data Error
6630 6728 * PxIS.IFS - Interface Fatal Error
6631 6729 * PxIS.TFES - Task File Error
6632 6730 *
6633 6731 * The fatal error means the HBA can not recover from it by
6634 6732 * itself, and it will try to abort the transfer, and the software
6635 6733 * must intervene to restart the port.
6636 6734 */
6637 6735 if (port_intr_status & (AHCI_INTR_STATUS_IFS |
6638 6736 AHCI_INTR_STATUS_HBDS |
6639 6737 AHCI_INTR_STATUS_HBFS |
6640 6738 AHCI_INTR_STATUS_TFES))
6641 6739 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp,
6642 6740 port, port_intr_status);
6643 6741
6644 6742 /* Check the cold port detect interrupt bit */
6645 6743 if (port_intr_status & AHCI_INTR_STATUS_CPDS) {
6646 6744 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port);
6647 6745 }
6648 6746
6649 6747 /* Second clear the corresponding bit in IS.IPS */
6650 6748 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
6651 6749 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port));
6652 6750
6653 6751 /* Try to recover at the end of the interrupt handler. */
6654 6752 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle) !=
6655 6753 DDI_FM_OK) {
6656 6754 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
6657 6755 DDI_SERVICE_UNAFFECTED);
6658 6756 ddi_fm_acc_err_clear(ahci_ctlp->ahcictl_ahci_acc_handle,
6659 6757 DDI_FME_VERSION);
6660 6758 }
6661 6759 }
6662 6760
6663 6761 /*
6664 6762 * Interrupt service handler
6665 6763 */
6666 6764 static uint_t
6667 6765 ahci_intr(caddr_t arg1, caddr_t arg2)
6668 6766 {
6669 6767 #ifndef __lock_lint
6670 6768 _NOTE(ARGUNUSED(arg2))
6671 6769 #endif
6672 6770 /* LINTED */
6673 6771 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1;
6674 6772 ahci_port_t *ahci_portp;
6675 6773 int32_t global_intr_status;
6676 6774 uint8_t port;
6677 6775
6678 6776 /*
6679 6777 * global_intr_status indicates that the corresponding port has
6680 6778 * an interrupt pending.
6681 6779 */
6682 6780 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6683 6781 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp));
6684 6782
6685 6783 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) {
6686 6784 /* The interrupt is not ours */
6687 6785 return (DDI_INTR_UNCLAIMED);
6688 6786 }
6689 6787
6690 6788 /*
6691 6789 * Check the handle after reading global_intr_status - we don't want
6692 6790 * to miss any port with pending interrupts.
6693 6791 */
6694 6792 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle) !=
6695 6793 DDI_FM_OK) {
6696 6794 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
6697 6795 DDI_SERVICE_UNAFFECTED);
6698 6796 ddi_fm_acc_err_clear(ahci_ctlp->ahcictl_ahci_acc_handle,
6699 6797 DDI_FME_VERSION);
6700 6798 return (DDI_INTR_UNCLAIMED);
6701 6799 }
6702 6800
6703 6801 /* Loop for all the ports */
6704 6802 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
6705 6803 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
6706 6804 continue;
6707 6805 }
6708 6806 if (!((0x1 << port) & global_intr_status)) {
6709 6807 continue;
6710 6808 }
6711 6809
6712 6810 ahci_portp = ahci_ctlp->ahcictl_ports[port];
6713 6811
6714 6812 /* Call ahci_port_intr */
6715 6813 ahci_port_intr(ahci_ctlp, ahci_portp, port);
6716 6814 }
6717 6815
6718 6816 return (DDI_INTR_CLAIMED);
6719 6817 }
6720 6818
6721 6819 /*
6722 6820 * For non-queued commands, when the corresponding bit in the PxCI register
6723 6821 * is cleared, it means the command is completed successfully. And according
6724 6822 * to the HBA state machine, there are three conditions which possibly will
6725 6823 * try to clear the PxCI register bit.
|
↓ open down ↓ |
4547 lines elided |
↑ open up ↑ |
6726 6824 * 1. Receive one D2H Register FIS which is with 'I' bit set
6727 6825 * 2. Update PIO Setup FIS
6728 6826 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset)
6729 6827 *
6730 6828 * Process completed non-queued commands when the interrupt status bit -
6731 6829 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set.
6732 6830 *
6733 6831 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received
6734 6832 * with the 'I' bit set. And the following commands will send thus
6735 6833 * FIS with 'I' bit set upon the successful completion:
6736 - * 1. Non-data commands
6737 - * 2. DMA data-in command
6738 - * 3. DMA data-out command
6739 - * 4. PIO data-out command
6834 + * 1. Non-data commands
6835 + * 2. DMA data-in command
6836 + * 3. DMA data-out command
6837 + * 4. PIO data-out command
6740 6838 * 5. PACKET non-data commands
6741 6839 * 6. PACKET PIO data-in command
6742 6840 * 7. PACKET PIO data-out command
6743 6841 * 8. PACKET DMA data-in command
6744 6842 * 9. PACKET DMA data-out command
6745 6843 *
6746 6844 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received
6747 6845 * with the 'I' bit set. And the following commands will send this
6748 6846 * FIS upon the successful completion:
6749 - * 1. PIO data-in command
6847 + * 1. PIO data-in command
6750 6848 */
6751 6849 static int
6752 6850 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp,
6753 6851 ahci_port_t *ahci_portp, uint8_t port)
6754 6852 {
6755 6853 uint32_t port_cmd_issue = 0;
6756 6854 uint32_t finished_tags;
6757 6855 int finished_slot;
6758 6856 sata_pkt_t *satapkt;
6759 6857 ahci_fis_d2h_register_t *rcvd_fisp;
6760 6858 #if AHCI_DEBUG
6761 6859 ahci_cmd_header_t *cmd_header;
6762 6860 uint32_t cmd_dmacount;
6763 6861 #endif
6764 6862
6765 6863 mutex_enter(&ahci_portp->ahciport_mutex);
6766 6864
6767 6865 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&
6768 6866 !RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) &&
6769 6867 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
6770 6868 /*
6771 6869 * Spurious interrupt. Nothing to be done.
6772 6870 */
6773 6871 mutex_exit(&ahci_portp->ahciport_mutex);
6774 6872 return (AHCI_SUCCESS);
6775 6873 }
6776 6874
6777 6875 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6778 6876 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
6779 6877
6780 6878 /* If the PxCI corrupts, don't complete the commmands. */
6781 6879 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle)
6782 6880 != DDI_FM_OK) {
6783 6881 mutex_exit(&ahci_portp->ahciport_mutex);
6784 6882 return (AHCI_FAILURE);
6785 6883 }
6786 6884
6787 6885 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
6788 6886 /* Slot 0 is always used during error recovery */
6789 6887 finished_tags = 0x1 & ~port_cmd_issue;
6790 6888 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
6791 6889 "ahci_intr_cmd_cmplt: port %d the sata pkt for error "
6792 6890 "retrieval is finished, and finished_tags = 0x%x",
6793 6891 port, finished_tags);
6794 6892 } else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
6795 6893 finished_tags = 0x1 & ~port_cmd_issue;
6796 6894 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
6797 6895 "ahci_intr_cmd_cmplt: port %d the sata pkt for r/w "
6798 6896 "port multiplier is finished, and finished_tags = 0x%x",
6799 6897 port, finished_tags);
6800 6898
6801 6899 } else {
6802 6900
6803 6901 finished_tags = ahci_portp->ahciport_pending_tags &
6804 6902 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp);
6805 6903 }
6806 6904
6807 6905 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6808 6906 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, "
6809 6907 "port_cmd_issue = 0x%x finished_tags = 0x%x",
6810 6908 ahci_portp->ahciport_pending_tags, port_cmd_issue,
6811 6909 finished_tags);
6812 6910
6813 6911 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&
6814 6912 (finished_tags == 0x1)) {
6815 6913 satapkt = ahci_portp->ahciport_err_retri_pkt;
6816 6914 ASSERT(satapkt != NULL);
6817 6915
6818 6916 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6819 6917 "ahci_intr_cmd_cmplt: sending up pkt 0x%p "
6820 6918 "with SATA_PKT_COMPLETED", (void *)satapkt);
6821 6919
6822 6920 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
6823 6921 goto out;
6824 6922 }
6825 6923
6826 6924 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) &&
6827 6925 (finished_tags == 0x1)) {
6828 6926 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
6829 6927 ASSERT(satapkt != NULL);
6830 6928
6831 6929 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6832 6930 "ahci_intr_cmd_cmplt: sending up pkt 0x%p "
6833 6931 "with SATA_PKT_COMPLETED", (void *)satapkt);
6834 6932
6835 6933 /* READ PORTMULT need copy out FIS content. */
6836 6934 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
6837 6935 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->
6838 6936 ahcirf_d2h_register_fis);
6839 6937 satapkt->satapkt_cmd.satacmd_status_reg =
6840 6938 GET_RFIS_STATUS(rcvd_fisp);
6841 6939 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp);
6842 6940 }
6843 6941
6844 6942 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
6845 6943 goto out;
6846 6944 }
6847 6945
6848 6946 while (finished_tags) {
6849 6947 finished_slot = ddi_ffs(finished_tags) - 1;
6850 6948 if (finished_slot == -1) {
6851 6949 goto out;
6852 6950 }
6853 6951
6854 6952 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot];
6855 6953 ASSERT(satapkt != NULL);
6856 6954 #if AHCI_DEBUG
6857 6955 /*
6858 6956 * For non-native queued commands, the PRD byte count field
6859 6957 * shall contain an accurate count of the number of bytes
6860 6958 * transferred for the command before the PxCI bit is cleared
6861 6959 * to '0' for the command.
6862 6960 *
6863 6961 * The purpose of this field is to let software know how many
6864 6962 * bytes transferred for a given operation in order to
6865 6963 * determine if underflow occurred. When issuing native command
6866 6964 * queuing commands, this field should not be used and is not
6867 6965 * required to be valid since in this case underflow is always
6868 6966 * illegal.
6869 6967 *
6870 6968 * For data reads, the HBA will update its PRD byte count with
6871 6969 * the total number of bytes received from the last FIS, and
6872 6970 * may be able to continue normally. For data writes, the
6873 6971 * device will detect an error, and HBA most likely will get
6874 6972 * a fatal error.
6875 6973 *
6876 6974 * Therefore, here just put code to debug part. And please
6877 6975 * refer to the comment above ahci_intr_fatal_error for the
6878 6976 * definition of underflow error.
6879 6977 */
6880 6978 cmd_dmacount =
6881 6979 ahci_portp->ahciport_prd_bytecounts[finished_slot];
6882 6980 if (cmd_dmacount) {
6883 6981 cmd_header =
6884 6982 &ahci_portp->ahciport_cmd_list[finished_slot];
6885 6983 AHCIDBG(AHCIDBG_INTR|AHCIDBG_PRDT, ahci_ctlp,
6886 6984 "ahci_intr_cmd_cmplt: port %d, "
6887 6985 "PRD Byte Count = 0x%x, "
6888 6986 "ahciport_prd_bytecounts = 0x%x", port,
6889 6987 cmd_header->ahcich_prd_byte_count,
6890 6988 cmd_dmacount);
6891 6989
6892 6990 if (cmd_header->ahcich_prd_byte_count != cmd_dmacount) {
6893 6991 AHCIDBG(AHCIDBG_UNDERFLOW, ahci_ctlp,
6894 6992 "ahci_intr_cmd_cmplt: port %d, "
6895 6993 "an underflow occurred", port);
6896 6994 }
6897 6995 }
6898 6996 #endif
6899 6997
6900 6998 /*
6901 6999 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS
6902 7000 * feature, sata_special_regs flag will be set, and the
6903 7001 * driver should copy the status and the other corresponding
6904 7002 * register values in the D2H Register FIS received (It's
6905 7003 * working on Non-data protocol) from the device back to
6906 7004 * the sata_cmd.
6907 7005 *
6908 7006 * For every AHCI port, there is only one Received FIS
6909 7007 * structure, which contains the FISes received from the
6910 7008 * device, So we're trying to copy the content of D2H
6911 7009 * Register FIS in the Received FIS structure back to
6912 7010 * the sata_cmd.
6913 7011 */
6914 7012 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
6915 7013 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->
6916 7014 ahcirf_d2h_register_fis);
6917 7015 satapkt->satapkt_cmd.satacmd_status_reg =
6918 7016 GET_RFIS_STATUS(rcvd_fisp);
6919 7017 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp);
6920 7018 }
6921 7019
6922 7020 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6923 7021 "ahci_intr_cmd_cmplt: sending up pkt 0x%p "
6924 7022 "with SATA_PKT_COMPLETED", (void *)satapkt);
6925 7023
6926 7024 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot);
6927 7025 CLEAR_BIT(finished_tags, finished_slot);
6928 7026 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL;
6929 7027
6930 7028 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
6931 7029 }
6932 7030 out:
6933 7031 AHCIDBG(AHCIDBG_PKTCOMP, ahci_ctlp,
6934 7032 "ahci_intr_cmd_cmplt: pending_tags = 0x%x",
6935 7033 ahci_portp->ahciport_pending_tags);
6936 7034
6937 7035 ahci_flush_doneq(ahci_portp);
6938 7036
6939 7037 mutex_exit(&ahci_portp->ahciport_mutex);
6940 7038
6941 7039 return (AHCI_SUCCESS);
6942 7040 }
6943 7041
6944 7042 /*
6945 7043 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received
6946 7044 * with the 'I' bit set and has been copied into system memory. It will
6947 7045 * be sent under the following situations:
6948 7046 *
6949 7047 * 1. NCQ command is completed
6950 7048 *
6951 7049 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed
6952 7050 * via the Set Device Bits FIS. When such event is generated, the software
6953 7051 * needs to read PxSACT register and compares the current value to the
6954 7052 * list of commands previously issue by software. ahciport_pending_ncq_tags
6955 7053 * keeps the tags of previously issued commands.
6956 7054 *
6957 7055 * 2. Asynchronous Notification
6958 7056 *
6959 7057 * Asynchronous Notification is a feature in SATA spec 2.6.
6960 7058 *
6961 7059 * 1) ATAPI device will send a signal to the host when media is inserted or
6962 7060 * removed and avoids polling the device for media changes. The signal
6963 7061 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits
6964 7062 * set to '1'. At the moment, it's not supported yet.
6965 7063 *
6966 7064 * 2) Port multiplier will send a signal to the host when a hot plug event
6967 7065 * has occured on a port multiplier port. It is used when command based
6968 7066 * switching is employed. This is handled by ahci_intr_pmult_sntf_events()
6969 7067 */
6970 7068 static int
6971 7069 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp,
6972 7070 ahci_port_t *ahci_portp, uint8_t port)
6973 7071 {
6974 7072 ahci_addr_t addr;
6975 7073
6976 7074 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
6977 7075 "ahci_intr_set_device_bits enter: port %d", port);
6978 7076
6979 7077 /* Initialize HBA port address */
6980 7078 AHCI_ADDR_SET_PORT(&addr, port);
6981 7079
6982 7080 /* NCQ plug handler */
6983 7081 (void) ahci_intr_ncq_events(ahci_ctlp, ahci_portp, &addr);
6984 7082
6985 7083 /* Check port multiplier's asynchronous notification events */
6986 7084 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_SNTF) {
6987 7085 (void) ahci_intr_pmult_sntf_events(ahci_ctlp,
6988 7086 ahci_portp, port);
6989 7087 }
6990 7088
6991 7089 /* ATAPI events is not supported yet */
6992 7090
6993 7091 return (AHCI_SUCCESS);
6994 7092 }
6995 7093 /*
6996 7094 * NCQ interrupt handler. Called upon a NCQ command is completed.
6997 7095 * Only be called from ahci_intr_set_device_bits().
6998 7096 */
6999 7097 static int
7000 7098 ahci_intr_ncq_events(ahci_ctl_t *ahci_ctlp,
7001 7099 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
7002 7100 {
7003 7101 uint32_t port_sactive;
7004 7102 uint32_t port_cmd_issue;
7005 7103 uint32_t issued_tags;
7006 7104 int issued_slot;
7007 7105 uint32_t finished_tags;
7008 7106 int finished_slot;
7009 7107 uint8_t port = addrp->aa_port;
7010 7108 sata_pkt_t *satapkt;
7011 7109
7012 7110 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7013 7111 "ahci_intr_set_device_bits enter: port %d", port);
7014 7112
7015 7113 mutex_enter(&ahci_portp->ahciport_mutex);
7016 7114 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7017 7115 mutex_exit(&ahci_portp->ahciport_mutex);
7018 7116 return (AHCI_SUCCESS);
7019 7117 }
7020 7118
7021 7119 /*
7022 7120 * First the handler got which commands are finished by checking
7023 7121 * PxSACT register
7024 7122 */
7025 7123 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7026 7124 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
7027 7125
7028 7126 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
7029 7127 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp);
7030 7128
7031 7129 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7032 7130 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x "
7033 7131 "port_sactive = 0x%x", port,
7034 7132 ahci_portp->ahciport_pending_ncq_tags, port_sactive);
7035 7133
7036 7134 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7037 7135 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags);
7038 7136
7039 7137 /*
7040 7138 * For NCQ commands, the software can determine which command has
7041 7139 * already been transmitted to the device by checking PxCI register.
7042 7140 */
7043 7141 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7044 7142 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
7045 7143
7046 7144 issued_tags = ahci_portp->ahciport_pending_tags &
7047 7145 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp);
7048 7146
7049 7147 /* If the PxSACT/PxCI corrupts, don't complete the NCQ commmands. */
7050 7148 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle)
7051 7149 != DDI_FM_OK) {
7052 7150 mutex_exit(&ahci_portp->ahciport_mutex);
7053 7151 return (AHCI_FAILURE);
7054 7152 }
7055 7153
7056 7154 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7057 7155 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x "
7058 7156 "port_cmd_issue = 0x%x", port,
7059 7157 ahci_portp->ahciport_pending_tags, port_cmd_issue);
7060 7158
7061 7159 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7062 7160 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags);
7063 7161
7064 7162 /*
7065 7163 * Clear ahciport_pending_tags bit when the corresponding command
7066 7164 * is already sent down to the device.
7067 7165 */
7068 7166 while (issued_tags) {
7069 7167 issued_slot = ddi_ffs(issued_tags) - 1;
7070 7168 if (issued_slot == -1) {
7071 7169 goto next;
7072 7170 }
7073 7171 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot);
7074 7172 CLEAR_BIT(issued_tags, issued_slot);
7075 7173 }
7076 7174
7077 7175 next:
7078 7176 while (finished_tags) {
7079 7177 finished_slot = ddi_ffs(finished_tags) - 1;
7080 7178 if (finished_slot == -1) {
7081 7179 goto out;
7082 7180 }
7083 7181
7084 7182 /* The command is certainly transmitted to the device */
7085 7183 ASSERT(!(ahci_portp->ahciport_pending_tags &
7086 7184 (0x1 << finished_slot)));
7087 7185
7088 7186 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot];
7089 7187 ASSERT(satapkt != NULL);
7090 7188
7091 7189 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7092 7190 "ahci_intr_set_device_bits: sending up pkt 0x%p "
7093 7191 "with SATA_PKT_COMPLETED", (void *)satapkt);
7094 7192
7095 7193 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot);
7096 7194 CLEAR_BIT(finished_tags, finished_slot);
7097 7195 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL;
7098 7196
7099 7197 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
7100 7198 }
7101 7199 out:
7102 7200 AHCIDBG(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp,
7103 7201 "ahci_intr_set_device_bits: port %d "
7104 7202 "pending_ncq_tags = 0x%x pending_tags = 0x%x",
7105 7203 port, ahci_portp->ahciport_pending_ncq_tags,
7106 7204 ahci_portp->ahciport_pending_tags);
7107 7205
7108 7206 ahci_flush_doneq(ahci_portp);
7109 7207
7110 7208 mutex_exit(&ahci_portp->ahciport_mutex);
7111 7209
7112 7210 return (AHCI_SUCCESS);
7113 7211 }
7114 7212
7115 7213 /*
7116 7214 * Port multiplier asynchronous notification event handler. Called upon a
7117 7215 * device is hot plugged/pulled.
7118 7216 *
7119 7217 * The async-notification event will only be recorded by ahcipmi_snotif_tags
7120 7218 * here and will be handled by ahci_probe_pmult().
7121 7219 *
7122 7220 * NOTE: called only from ahci_port_intr().
7123 7221 */
7124 7222 static int
7125 7223 ahci_intr_pmult_sntf_events(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
7126 7224 uint8_t port)
7127 7225 {
7128 7226 sata_device_t sdevice;
7129 7227
7130 7228 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
7131 7229 "ahci_intr_pmult_sntf_events enter: port %d ", port);
7132 7230
7133 7231 /* no hot-plug while attaching process */
7134 7232 mutex_enter(&ahci_ctlp->ahcictl_mutex);
7135 7233 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) {
7136 7234 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7137 7235 return (AHCI_SUCCESS);
7138 7236 }
7139 7237 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7140 7238
7141 7239 mutex_enter(&ahci_portp->ahciport_mutex);
7142 7240 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
7143 7241 mutex_exit(&ahci_portp->ahciport_mutex);
7144 7242 return (AHCI_SUCCESS);
7145 7243 }
7146 7244
7147 7245 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
7148 7246
7149 7247 ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags =
7150 7248 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7151 7249 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port));
7152 7250 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7153 7251 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port),
7154 7252 AHCI_SNOTIF_CLEAR_ALL);
7155 7253
7156 7254 if (ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags == 0) {
7157 7255 mutex_exit(&ahci_portp->ahciport_mutex);
7158 7256 return (AHCI_SUCCESS);
7159 7257 }
7160 7258
7161 7259 /* Port Multiplier sub-device hot-plug handler */
7162 7260 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
7163 7261 mutex_exit(&ahci_portp->ahciport_mutex);
7164 7262 return (AHCI_SUCCESS);
7165 7263 }
7166 7264
7167 7265 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_PMULT_SNTF) {
7168 7266 /* Not allowed to re-enter. */
7169 7267 mutex_exit(&ahci_portp->ahciport_mutex);
7170 7268 return (AHCI_SUCCESS);
7171 7269 }
7172 7270
7173 7271 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_PMULT_SNTF;
7174 7272
7175 7273 /*
7176 7274 * NOTE:
7177 7275 * Even if Asynchronous Notification is supported (and enabled) by
7178 7276 * both controller and the port multiplier, the content of PxSNTF
7179 7277 * register is always set to 0x8000 by async notification event. We
7180 7278 * need to check GSCR[32] on the port multiplier to find out the
7181 7279 * owner of this event.
7182 7280 * This is not accord with SATA spec 2.6 and needs further
7183 7281 * clarification.
7184 7282 */
7185 7283 /* hot-plug will not reported while reseting. */
7186 7284 if (ahci_portp->ahciport_reset_in_progress == 1) {
7187 7285 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
7188 7286 "port %d snotif event ignored", port);
7189 7287 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_PMULT_SNTF;
7190 7288 mutex_exit(&ahci_portp->ahciport_mutex);
7191 7289 return (AHCI_SUCCESS);
7192 7290 }
7193 7291
7194 7292 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
7195 7293 "PxSNTF is set to 0x%x by port multiplier",
7196 7294 ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags);
7197 7295
7198 7296 /*
7199 7297 * Now we need do some necessary operation and inform SATA framework
7200 7298 * that link/device events has happened.
7201 7299 */
7202 7300 bzero((void *)&sdevice, sizeof (sata_device_t));
7203 7301 sdevice.satadev_addr.cport = ahci_ctlp->
7204 7302 ahcictl_port_to_cport[port];
7205 7303 sdevice.satadev_addr.pmport = SATA_PMULT_HOSTPORT;
7206 7304 sdevice.satadev_addr.qual = SATA_ADDR_PMULT;
7207 7305 sdevice.satadev_state = SATA_PSTATE_PWRON;
7208 7306
7209 7307 /* Just reject packets, do not stop that port. */
7210 7308 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
7211 7309
7212 7310 mutex_exit(&ahci_portp->ahciport_mutex);
7213 7311 sata_hba_event_notify(
7214 7312 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7215 7313 &sdevice,
7216 7314 SATA_EVNT_PMULT_LINK_CHANGED);
7217 7315 mutex_enter(&ahci_portp->ahciport_mutex);
7218 7316
7219 7317 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_PMULT_SNTF;
7220 7318 mutex_exit(&ahci_portp->ahciport_mutex);
7221 7319
7222 7320 return (AHCI_SUCCESS);
7223 7321 }
7224 7322
7225 7323 /*
7226 7324 * 1=Change in Current Connect Status. 0=No change in Current Connect Status.
7227 7325 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared
7228 7326 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it
7229 7327 * indicates a COMINIT signal was received.
7230 7328 *
7231 7329 * Hot plug insertion is detected by reception of a COMINIT signal from the
7232 7330 * device. On reception of unsolicited COMINIT, the HBA shall generate a
7233 7331 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall
7234 7332 * begin the normal communication negotiation sequence as outlined in the
7235 7333 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the
7236 7334 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the
7237 7335 * PxSSTS.DET field shall be set to 1h. When the communication negotiation
7238 7336 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set
7239 7337 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy
7240 7338 * to handle hot plug insertion. In this interrupt handler, just do nothing
7241 7339 * but print some log message and clear the bit.
7242 7340 */
7243 7341 static int
7244 7342 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp,
7245 7343 ahci_port_t *ahci_portp, uint8_t port)
7246 7344 {
7247 7345 #if AHCI_DEBUG
7248 7346 uint32_t port_serror;
7249 7347 #endif
7250 7348
7251 7349 mutex_enter(&ahci_portp->ahciport_mutex);
7252 7350
7253 7351 #if AHCI_DEBUG
7254 7352 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7255 7353 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port));
7256 7354
7257 7355 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
7258 7356 "ahci_intr_port_connect_change: port %d, "
7259 7357 "port_serror = 0x%x", port, port_serror);
7260 7358 #endif
7261 7359
7262 7360 /* Clear PxSERR.DIAG.X to clear the interrupt bit */
7263 7361 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7264 7362 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
7265 7363 SERROR_EXCHANGED_ERR);
7266 7364
7267 7365 mutex_exit(&ahci_portp->ahciport_mutex);
7268 7366
7269 7367 return (AHCI_SUCCESS);
7270 7368 }
7271 7369
7272 7370 /*
7273 7371 * Hot Plug Operation for platforms that support Mechanical Presence
7274 7372 * Switches.
7275 7373 *
7276 7374 * When set, it indicates that a mechanical presence switch attached to this
7277 7375 * port has been opened or closed, which may lead to a change in the connection
7278 7376 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP
7279 7377 * are set to '1'.
7280 7378 *
7281 7379 * At the moment, this interrupt is not needed and disabled and we just log
7282 7380 * the debug message.
7283 7381 */
7284 7382 static int
7285 7383 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp,
7286 7384 ahci_port_t *ahci_portp, uint8_t port)
7287 7385 {
7288 7386 uint32_t cap_status, port_cmd_status;
7289 7387
7290 7388 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
7291 7389 "ahci_intr_device_mechanical_presence_status enter, "
7292 7390 "port %d", port);
7293 7391
7294 7392 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7295 7393 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp));
7296 7394
7297 7395 mutex_enter(&ahci_portp->ahciport_mutex);
7298 7396 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7299 7397 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7300 7398
7301 7399 if (!(cap_status & AHCI_HBA_CAP_SMPS) ||
7302 7400 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) {
7303 7401 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7304 7402 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore "
7305 7403 "the interrupt: cap_status = 0x%x, "
7306 7404 "port_cmd_status = 0x%x", cap_status, port_cmd_status);
7307 7405 mutex_exit(&ahci_portp->ahciport_mutex);
7308 7406
7309 7407 return (AHCI_SUCCESS);
7310 7408 }
7311 7409
7312 7410 #if AHCI_DEBUG
7313 7411 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) {
7314 7412 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7315 7413 "The mechanical presence switch is open: "
7316 7414 "port %d, port_cmd_status = 0x%x",
7317 7415 port, port_cmd_status);
7318 7416 } else {
7319 7417 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7320 7418 "The mechanical presence switch is close: "
7321 7419 "port %d, port_cmd_status = 0x%x",
7322 7420 port, port_cmd_status);
7323 7421 }
7324 7422 #endif
7325 7423
7326 7424 mutex_exit(&ahci_portp->ahciport_mutex);
7327 7425
7328 7426 return (AHCI_SUCCESS);
7329 7427 }
7330 7428
7331 7429 /*
7332 7430 * Native Hot Plug Support.
7333 7431 *
7334 7432 * When set, it indicates that the internal PHYRDY signal changed state.
7335 7433 * This bit reflects the state of PxSERR.DIAG.N.
7336 7434 *
7337 7435 * There are three kinds of conditions to generate this interrupt event:
7338 7436 * 1. a device is inserted
7339 7437 * 2. a device is disconnected
7340 7438 * 3. when the link enters/exits a Partial or Slumber interface power
7341 7439 * management state
7342 7440 *
7343 7441 * If inteface power management is enabled for a port, the PxSERR.DIAG.N
7344 7442 * bit may be set due to the link entering the Partial or Slumber power
7345 7443 * management state, rather than due to a hot plug insertion or removal
7346 7444 * event. So far, the interface power management is disabled, so the
7347 7445 * driver can reliably get removal detection notification via the
7348 7446 * PxSERR.DIAG.N bit.
7349 7447 */
7350 7448 static int
7351 7449 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp,
7352 7450 ahci_port_t *ahci_portp, uint8_t port)
7353 7451 {
7354 7452 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */
7355 7453 sata_device_t sdevice;
7356 7454 int dev_exists_now = 0;
7357 7455 int dev_existed_previously = 0;
7358 7456 ahci_addr_t port_addr;
7359 7457
7360 7458 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
7361 7459 "ahci_intr_phyrdy_change enter, port %d", port);
7362 7460
7363 7461 /* Clear PxSERR.DIAG.N to clear the interrupt bit */
7364 7462 mutex_enter(&ahci_portp->ahciport_mutex);
7365 7463 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7366 7464 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
7367 7465 SERROR_PHY_RDY_CHG);
7368 7466 mutex_exit(&ahci_portp->ahciport_mutex);
7369 7467
7370 7468 mutex_enter(&ahci_ctlp->ahcictl_mutex);
7371 7469 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) ||
7372 7470 (ahci_portp == NULL)) {
7373 7471 /* The whole controller setup is not yet done. */
7374 7472 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7375 7473 return (AHCI_SUCCESS);
7376 7474 }
7377 7475 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7378 7476
7379 7477 mutex_enter(&ahci_portp->ahciport_mutex);
7380 7478
7381 7479 /* SStatus tells the presence of device. */
7382 7480 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7383 7481 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
7384 7482
7385 7483 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) {
7386 7484 dev_exists_now = 1;
7387 7485 }
7388 7486
7389 7487 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) {
7390 7488 dev_existed_previously = 1;
7391 7489 }
7392 7490
7393 7491 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) {
7394 7492 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV;
7395 7493 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
7396 7494 "ahci_intr_phyrdy_change: port %d "
7397 7495 "AHCI_PORT_FLAG_NODEV is cleared", port);
7398 7496 if (dev_exists_now == 0)
7399 7497 dev_existed_previously = 1;
7400 7498 }
7401 7499
7402 7500 bzero((void *)&sdevice, sizeof (sata_device_t));
7403 7501 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
7404 7502 sdevice.satadev_addr.qual = SATA_ADDR_CPORT;
7405 7503 sdevice.satadev_addr.pmport = 0;
7406 7504 sdevice.satadev_state = SATA_PSTATE_PWRON;
7407 7505 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON;
7408 7506
7409 7507 AHCI_ADDR_SET_PORT(&port_addr, port);
7410 7508
7411 7509 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_HOTPLUG;
7412 7510 if (dev_exists_now) {
7413 7511 if (dev_existed_previously) { /* 1 -> 1 */
7414 7512 /* Things are fine now. The loss was temporary. */
7415 7513 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
7416 7514 "ahci_intr_phyrdy_change port %d "
7417 7515 "device link lost/established", port);
7418 7516
7419 7517 mutex_exit(&ahci_portp->ahciport_mutex);
7420 7518 sata_hba_event_notify(
7421 7519 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7422 7520 &sdevice,
7423 7521 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED);
7424 7522 mutex_enter(&ahci_portp->ahciport_mutex);
7425 7523
7426 7524 } else { /* 0 -> 1 */
7427 7525 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
7428 7526 "ahci_intr_phyrdy_change: port %d "
7429 7527 "device link established", port);
7430 7528
7431 7529 /*
7432 7530 * A new device has been detected. The new device
7433 7531 * might be a port multiplier instead of a drive, so
7434 7532 * we cannot update the signature directly.
7435 7533 */
7436 7534 (void) ahci_initialize_port(ahci_ctlp,
7437 7535 ahci_portp, &port_addr);
7438 7536
7439 7537 /* Try to start the port */
7440 7538 if (ahci_start_port(ahci_ctlp, ahci_portp, port)
7441 7539 != AHCI_SUCCESS) {
7442 7540 sdevice.satadev_state |= SATA_PSTATE_FAILED;
7443 7541 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
7444 7542 "ahci_intr_phyrdy_change: port %d failed "
7445 7543 "at start port", port);
7446 7544 }
7447 7545
7448 7546 /* Clear the max queue depth for inserted device */
7449 7547 ahci_portp->ahciport_max_ncq_tags = 0;
7450 7548
7451 7549 mutex_exit(&ahci_portp->ahciport_mutex);
7452 7550 sata_hba_event_notify(
7453 7551 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7454 7552 &sdevice,
7455 7553 SATA_EVNT_LINK_ESTABLISHED);
7456 7554 mutex_enter(&ahci_portp->ahciport_mutex);
7457 7555
7458 7556 }
7459 7557 } else { /* No device exists now */
7460 7558
7461 7559 if (dev_existed_previously) { /* 1 -> 0 */
7462 7560 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
7463 7561 "ahci_intr_phyrdy_change: port %d "
7464 7562 "device link lost", port);
7465 7563
7466 7564 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
7467 7565 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
7468 7566 ahci_portp, port);
7469 7567
7470 7568 if (ahci_portp->ahciport_device_type ==
7471 7569 SATA_DTYPE_PMULT) {
7472 7570 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
7473 7571 }
7474 7572
7475 7573 /* An existing device is lost. */
7476 7574 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE;
7477 7575 ahci_portp->ahciport_port_state = SATA_STATE_UNKNOWN;
7478 7576
7479 7577 mutex_exit(&ahci_portp->ahciport_mutex);
7480 7578 sata_hba_event_notify(
7481 7579 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7482 7580 &sdevice,
7483 7581 SATA_EVNT_LINK_LOST);
7484 7582 mutex_enter(&ahci_portp->ahciport_mutex);
7485 7583 }
7486 7584 }
7487 7585 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_HOTPLUG;
7488 7586
7489 7587 mutex_exit(&ahci_portp->ahciport_mutex);
7490 7588
7491 7589 return (AHCI_SUCCESS);
7492 7590 }
7493 7591
7494 7592 /*
7495 7593 * PxIS.UFS - Unknown FIS Error
7496 7594 *
7497 7595 * This interrupt event means an unknown FIS was received and has been
7498 7596 * copied into system memory. An unknown FIS is not considered an illegal
7499 7597 * FIS, unless the length received is more than 64 bytes. If an unknown
7500 7598 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues
7501 7599 * normal operation. If the unknown FIS is more than 64 bytes, then it
7502 7600 * won't be posted to memory and PxSERR.ERR.P will be set, which is then
7503 7601 * a fatal error.
7504 7602 *
7505 7603 * PxIS.IPMS - Incorrect Port Multiplier Status
7506 7604 *
7507 7605 * IPMS Indicates that the HBA received a FIS from a device that did not
7508 7606 * have a command outstanding. The IPMS bit may be set during enumeration
7509 7607 * of devices on a Port Multiplier due to the normal Port Multiplier
7510 7608 * enumeration process. It is recommended that IPMS only be used after
7511 7609 * enumeration is complete on the Port Multiplier (copied from spec).
7512 7610 *
7513 7611 * PxIS.OFS - Overflow Error
7514 7612 *
7515 7613 * Command list overflow is defined as software building a command table
7516 7614 * that has fewer total bytes than the transaction given to the device.
7517 7615 * On device writes, the HBA will run out of data, and on reads, there
7518 7616 * will be no room to put the data.
7519 7617 *
7520 7618 * For an overflow on data read, either PIO or DMA, the HBA will set
7521 7619 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a
7522 7620 * non-fatal error when the HBA can continues. Sometimes, it will cause
7523 7621 * a fatal error and need the software to do something.
7524 7622 *
7525 7623 * For an overflow on data write, setting PxIS.OFS is optional for both
7526 7624 * DMA and PIO, and it's a fatal error, and a COMRESET is required by
7527 7625 * software to clean up from this serious error.
7528 7626 *
7529 7627 * PxIS.INFS - Interface Non-Fatal Error
7530 7628 *
7531 7629 * This interrupt event indicates that the HBA encountered an error on
7532 7630 * the Serial ATA interface but was able to continue operation. The kind
7533 7631 * of error usually occurred during a non-Data FIS, and under this condition
7534 7632 * the FIS will be re-transmitted by HBA automatically.
7535 7633 *
7536 7634 * When the FMA is implemented, there should be a stat structure to
7537 7635 * record how many every kind of error happens.
7538 7636 */
7539 7637 static int
7540 7638 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
7541 7639 uint8_t port, uint32_t intr_status)
7542 7640 {
7543 7641 uint32_t port_serror;
7544 7642 #if AHCI_DEBUG
7545 7643 uint32_t port_cmd_status;
7546 7644 uint32_t port_cmd_issue;
7547 7645 uint32_t port_sactive;
7548 7646 int current_slot;
7549 7647 uint32_t current_tags;
7550 7648 sata_pkt_t *satapkt;
7551 7649 ahci_cmd_header_t *cmd_header;
7552 7650 uint32_t cmd_dmacount;
7553 7651 #endif
7554 7652
7555 7653 mutex_enter(&ahci_portp->ahciport_mutex);
7556 7654
7557 7655 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7558 7656 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port));
7559 7657
7560 7658 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp,
7561 7659 "ahci_intr_non_fatal_error: port %d, "
7562 7660 "PxSERR = 0x%x, PxIS = 0x%x ", port, port_serror, intr_status);
7563 7661
7564 7662 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1);
7565 7663
7566 7664 if (intr_status & AHCI_INTR_STATUS_UFS) {
7567 7665 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
7568 7666 "ahci port %d has unknown FIS error", port);
7569 7667
7570 7668 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */
7571 7669 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7572 7670 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
7573 7671 SERROR_FIS_TYPE);
7574 7672 }
7575 7673
7576 7674 #if AHCI_DEBUG
7577 7675 if (intr_status & AHCI_INTR_STATUS_IPMS) {
7578 7676 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci port %d "
7579 7677 "has Incorrect Port Multiplier Status error", port);
7580 7678 }
7581 7679
7582 7680 if (intr_status & AHCI_INTR_STATUS_OFS) {
7583 7681 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7584 7682 "ahci port %d has overflow error", port);
7585 7683 }
7586 7684
7587 7685 if (intr_status & AHCI_INTR_STATUS_INFS) {
7588 7686 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7589 7687 "ahci port %d has interface non fatal error", port);
7590 7688 }
7591 7689
7592 7690 /*
7593 7691 * Record the error occurred command's slot.
7594 7692 */
7595 7693 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) ||
7596 7694 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
7597 7695 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7598 7696 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7599 7697
7600 7698 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
7601 7699 AHCI_CMD_STATUS_CCS_SHIFT;
7602 7700
7603 7701 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
7604 7702 satapkt = ahci_portp->ahciport_err_retri_pkt;
7605 7703 ASSERT(satapkt != NULL);
7606 7704 ASSERT(current_slot == 0);
7607 7705 } else {
7608 7706 satapkt = ahci_portp->ahciport_slot_pkts[current_slot];
7609 7707 }
7610 7708
7611 7709 if (satapkt != NULL) {
7612 7710 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7613 7711 "ahci_intr_non_fatal_error: pending_tags = 0x%x "
7614 7712 "cmd 0x%x", ahci_portp->ahciport_pending_tags,
7615 7713 satapkt->satapkt_cmd.satacmd_cmd_reg);
7616 7714
7617 7715 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7618 7716 "ahci_intr_non_fatal_error: port %d, "
7619 7717 "satapkt 0x%p is being processed when error occurs",
7620 7718 port, (void *)satapkt);
7621 7719
7622 7720 /*
7623 7721 * PRD Byte Count field of command header is not
7624 7722 * required to reflect the total number of bytes
7625 7723 * transferred when an overflow occurs, so here
7626 7724 * just log the value.
7627 7725 */
7628 7726 cmd_dmacount =
7629 7727 ahci_portp->ahciport_prd_bytecounts[current_slot];
7630 7728 if (cmd_dmacount) {
7631 7729 cmd_header = &ahci_portp->
7632 7730 ahciport_cmd_list[current_slot];
7633 7731 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7634 7732 "ahci_intr_non_fatal_error: port %d, "
7635 7733 "PRD Byte Count = 0x%x, "
7636 7734 "ahciport_prd_bytecounts = 0x%x", port,
7637 7735 cmd_header->ahcich_prd_byte_count,
7638 7736 cmd_dmacount);
7639 7737 }
7640 7738 }
7641 7739 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7642 7740 /*
7643 7741 * For queued command, list those command which have already
7644 7742 * been transmitted to the device and still not completed.
7645 7743 */
7646 7744 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7647 7745 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
7648 7746
7649 7747 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7650 7748 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
7651 7749
7652 7750 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp,
7653 7751 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x "
7654 7752 "port_sactive = 0x%x port_cmd_issue = 0x%x",
7655 7753 ahci_portp->ahciport_pending_ncq_tags,
7656 7754 port_sactive, port_cmd_issue);
7657 7755
7658 7756 current_tags = ahci_portp->ahciport_pending_ncq_tags &
7659 7757 port_sactive & ~port_cmd_issue &
7660 7758 AHCI_NCQ_SLOT_MASK(ahci_portp);
7661 7759
7662 7760 while (current_tags) {
7663 7761 current_slot = ddi_ffs(current_tags) - 1;
7664 7762 if (current_slot == -1) {
7665 7763 goto out;
7666 7764 }
7667 7765
7668 7766 satapkt = ahci_portp->ahciport_slot_pkts[current_slot];
7669 7767 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS,
7670 7768 ahci_ctlp, "ahci_intr_non_fatal_error: "
7671 7769 "port %d, satapkt 0x%p is outstanding when "
7672 7770 "error occurs", port, (void *)satapkt);
7673 7771
7674 7772 CLEAR_BIT(current_tags, current_slot);
7675 7773 }
7676 7774 }
7677 7775 out:
7678 7776 #endif
7679 7777 mutex_exit(&ahci_portp->ahciport_mutex);
7680 7778
7681 7779 return (AHCI_SUCCESS);
7682 7780 }
7683 7781
7684 7782 /*
7685 7783 * According to the AHCI spec, the error types include system memory
7686 7784 * errors, interface errors, port multiplier errors, device errors,
7687 7785 * command list overflow, command list underflow, native command
7688 7786 * queuing tag errors and pio data transfer errors.
7689 7787 *
7690 7788 * System memory errors such as target abort, master abort, and parity
7691 7789 * may cause the host to stop, and they are serious errors and needed
7692 7790 * to be recovered with software intervention. When system software
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7693 7791 * has given a pointer to the HBA that doesn't exist in physical memory,
7694 7792 * a master/target abort error occurs, and PxIS.HBFS will be set. A
7695 7793 * data error such as CRC or parity occurs, the HBA aborts the transfer
7696 7794 * (if necessary) and PxIS.HBDS will be set.
7697 7795 *
7698 7796 * Interface errors are errors that occur due to electrical issues on
7699 7797 * the interface, or protocol miscommunication between the device and
7700 7798 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS
7701 7799 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that
7702 7800 * causes PxIS.IFS/PxIS.INFS to be set are
7703 - * 1. in PxSERR.ERR, P bit is set to '1'
7801 + * 1. in PxSERR.ERR, P bit is set to '1'
7704 7802 * 2. in PxSERR.DIAG, C or H bit is set to '1'
7705 7803 * 3. PhyRdy drop unexpectly, N bit is set to '1'
7706 7804 * If the error occurred during a non-data FIS, the FIS must be
7707 7805 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If
7708 7806 * the error occurred during a data FIS, the transfer will stop, so
7709 7807 * the error is fatal and PxIS.IFS is set.
7710 7808 *
7711 7809 * When a FIS arrives that updates the taskfile, the HBA checks to see
7712 7810 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA
7713 7811 * stops processing any more commands.
7714 7812 *
7715 7813 * Command list overflow is defined as software building a command table
7716 7814 * that has fewer total bytes than the transaction given to the device.
7717 7815 * On device writes, the HBA will run out of data, and on reads, there
7718 7816 * will be no room to put the data. For an overflow on data read, either
7719 7817 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error.
7720 7818 * For an overflow on data write, setting PxIS.OFS is optional for both
7721 7819 * DMA and PIO, and a COMRESET is required by software to clean up from
7722 7820 * this serious error.
7723 7821 *
7724 7822 * Command list underflow is defined as software building a command
7725 7823 * table that has more total bytes than the transaction given to the
7726 7824 * device. For data writes, both PIO and DMA, the device will detect
7727 7825 * an error and end the transfer. And these errors are most likely going
7728 7826 * to be fatal errors that will cause the port to be restarted. For
7729 7827 * data reads, the HBA updates its PRD byte count, and may be
7730 7828 * able to continue normally, but is not required to. And The HBA is
7731 7829 * not required to detect underflow conditions for native command
7732 7830 * queuing command.
7733 7831 *
7734 7832 * The HBA does not actively check incoming DMA Setup FISes to ensure
7735 7833 * that the PxSACT register bit for that slot is set. Existing error
7736 7834 * mechanisms, such as host bus failure, or bad protocol, are used to
7737 7835 * recover from this case.
7738 7836 *
7739 7837 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final
7740 7838 * DATA FIS must be an integral number of Dwords. If the HBA receives
7741 7839 * a request which is not an integral number of Dwords, the HBA
7742 7840 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until
7743 7841 * software restarts the port. And the HBA ensures that the size
7744 7842 * of the DATA FIS received during a PIO command matches the size in
7745 7843 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the
7746 7844 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then
7747 7845 * stop running until software restarts the port.
7748 7846 */
7749 7847 /*
7750 7848 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES.
7751 7849 *
7752 7850 * PxIS.IFS indicates that the hba encountered an error on the serial ata
7753 7851 * interface which caused the transfer to stop.
7754 7852 *
7755 7853 * PxIS.HBDS indicates that the hba encountered a data error
7756 7854 * (uncorrectable ecc/parity) when reading from or writing to system memory.
7757 7855 *
7758 7856 * PxIS.HBFS indicates that the hba encountered a host bus error that it
7759 7857 * cannot recover from, such as a bad software pointer.
7760 7858 *
7761 7859 * PxIS.TFES is set whenever the status register is updated by the device
7762 7860 * and the error bit (bit 0) is set.
7763 7861 */
7764 7862 static int
7765 7863 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp,
7766 7864 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status)
7767 7865 {
7768 7866 uint32_t port_cmd_status;
7769 7867 uint32_t port_serror;
7770 7868 uint32_t task_file_status;
7771 7869 int failed_slot;
7772 7870 sata_pkt_t *spkt = NULL;
7773 7871 uint8_t err_byte;
7774 7872 ahci_event_arg_t *args;
7775 7873 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
7776 7874 uint32_t failed_tags = 0;
7777 7875 int task_fail_flag = 0, task_abort_flag = 0;
7778 7876 uint32_t slot_status;
7779 7877
7780 7878 mutex_enter(&ahci_portp->ahciport_mutex);
7781 7879
7782 7880 /*
7783 7881 * ahci_intr_phyrdy_change() may have rendered it to
7784 7882 * SATA_DTYPE_NONE.
7785 7883 */
7786 7884 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
7787 7885 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
7788 7886 "ahci_intr_fatal_error: port %d no device attached, "
7789 7887 "and just return without doing anything", port);
7790 7888 goto out0;
7791 7889 }
7792 7890
7793 7891 if (intr_status & AHCI_INTR_STATUS_TFES) {
7794 7892 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7795 7893 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
7796 7894 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7797 7895 "ahci_intr_fatal_error: port %d "
7798 7896 "task_file_status = 0x%x", port, task_file_status);
7799 7897 task_fail_flag = 1;
7800 7898
7801 7899 err_byte = (task_file_status & AHCI_TFD_ERR_MASK)
7802 7900 >> AHCI_TFD_ERR_SHIFT;
7803 7901 if (err_byte == SATA_ERROR_ABORT)
7804 7902 task_abort_flag = 1;
7805 7903 }
7806 7904
7807 7905 /*
7808 7906 * Here we just log the fatal error info in interrupt context.
7809 7907 * Misc recovery processing will be handled in task queue.
7810 7908 */
7811 7909 if (task_fail_flag == 1) {
7812 7910 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7813 7911 /*
7814 7912 * Read PxCMD.CCS to determine the slot that the HBA
7815 7913 * was processing when the error occurred.
7816 7914 */
7817 7915 port_cmd_status = ddi_get32(
7818 7916 ahci_ctlp->ahcictl_ahci_acc_handle,
7819 7917 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7820 7918 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
7821 7919 AHCI_CMD_STATUS_CCS_SHIFT;
7822 7920 failed_tags = 0x1 << failed_slot;
7823 7921
7824 7922 spkt = ahci_portp->ahciport_slot_pkts[failed_slot];
7825 7923 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7826 7924 "ahci_intr_fatal_error: spkt 0x%p is being "
7827 7925 "processed when fatal error occurred for port %d",
7828 7926 spkt, port);
7829 7927
7830 7928 /*
7831 7929 * Won't emit the error message if it is an IDENTIFY
7832 7930 * DEVICE command sent to an ATAPI device.
7833 7931 */
7834 7932 if ((spkt != NULL) &&
7835 7933 (spkt->satapkt_cmd.satacmd_cmd_reg ==
7836 7934 SATAC_ID_DEVICE) &&
7837 7935 (task_abort_flag == 1))
7838 7936 goto out1;
7839 7937
7840 7938 /*
7841 7939 * Won't emit the error message if it is an ATAPI PACKET
7842 7940 * command
7843 7941 */
7844 7942 if ((spkt != NULL) &&
7845 7943 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET))
7846 7944 goto out1;
7847 7945
7848 7946 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7849 7947 slot_status = ddi_get32(
7850 7948 ahci_ctlp->ahcictl_ahci_acc_handle,
7851 7949 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
7852 7950 failed_tags = slot_status &
7853 7951 AHCI_NCQ_SLOT_MASK(ahci_portp);
7854 7952 }
7855 7953 }
7856 7954
7857 7955 /* print the fatal error type */
7858 7956 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status);
7859 7957 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_ERRPRINT;
7860 7958
7861 7959 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7862 7960 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port));
7863 7961
7864 7962 /* print PxSERR related error message */
7865 7963 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0);
7866 7964
7867 7965 /* print task file register value */
7868 7966 if (task_fail_flag == 1) {
7869 7967 cmn_err(CE_WARN, "!ahci%d: ahci port %d task_file_status "
7870 7968 "= 0x%x", instance, port, task_file_status);
7871 7969 if (task_abort_flag == 1) {
7872 7970 cmn_err(CE_WARN, "!ahci%d: the below command (s) on "
7873 7971 "port %d are aborted", instance, port);
7874 7972 ahci_dump_commands(ahci_ctlp, port, failed_tags);
7875 7973 }
7876 7974 }
7877 7975
7878 7976 out1:
7879 7977 /* Prepare the argument for the taskq */
7880 7978 args = ahci_portp->ahciport_event_args;
7881 7979 args->ahciea_ctlp = (void *)ahci_ctlp;
7882 7980 args->ahciea_portp = (void *)ahci_portp;
7883 7981 args->ahciea_event = intr_status;
7884 7982 AHCI_ADDR_SET_PORT((ahci_addr_t *)args->ahciea_addrp, port);
7885 7983
7886 7984 /* Start the taskq to handle error recovery */
7887 7985 if ((ddi_taskq_dispatch(ahci_portp->ahciport_event_taskq,
7888 7986 ahci_events_handler,
7889 7987 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
7890 7988 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_ERRPRINT;
7891 7989 cmn_err(CE_WARN, "!ahci%d: start taskq for error recovery "
7892 7990 "port %d failed", instance, port);
7893 7991 }
7894 7992 out0:
7895 7993 mutex_exit(&ahci_portp->ahciport_mutex);
7896 7994
7897 7995 return (AHCI_SUCCESS);
7898 7996 }
7899 7997
7900 7998 /*
7901 7999 * Hot Plug Operation for platforms that support Cold Presence Detect.
7902 8000 *
7903 8001 * When set, a device status has changed as detected by the cold presence
7904 8002 * detect logic. This bit can either be set due to a non-connected port
7905 8003 * receiving a device, or a connected port having its device removed.
7906 8004 * This bit is only valid if the port supports cold presence detect as
7907 8005 * indicated by PxCMD.CPD set to '1'.
7908 8006 *
7909 8007 * At the moment, this interrupt is not needed and disabled and we just
7910 8008 * log the debug message.
7911 8009 */
7912 8010 static int
7913 8011 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp,
7914 8012 ahci_port_t *ahci_portp, uint8_t port)
7915 8013 {
7916 8014 uint32_t port_cmd_status;
7917 8015 sata_device_t sdevice;
7918 8016
7919 8017 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7920 8018 "ahci_intr_cold_port_detect enter, port %d", port);
7921 8019
7922 8020 mutex_enter(&ahci_portp->ahciport_mutex);
7923 8021
7924 8022 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7925 8023 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7926 8024 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) {
7927 8025 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7928 8026 "port %d does not support cold presence detect, so "
7929 8027 "we just ignore this interrupt", port);
7930 8028 mutex_exit(&ahci_portp->ahciport_mutex);
7931 8029 return (AHCI_SUCCESS);
7932 8030 }
7933 8031
7934 8032 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7935 8033 "port %d device status has changed", port);
7936 8034
7937 8035 bzero((void *)&sdevice, sizeof (sata_device_t));
7938 8036 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
7939 8037 sdevice.satadev_addr.qual = SATA_ADDR_CPORT;
7940 8038 sdevice.satadev_addr.pmport = 0;
7941 8039 sdevice.satadev_state = SATA_PSTATE_PWRON;
7942 8040
7943 8041 if (port_cmd_status & AHCI_CMD_STATUS_CPS) {
7944 8042 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7945 8043 "port %d: a device is hot plugged", port);
7946 8044 mutex_exit(&ahci_portp->ahciport_mutex);
7947 8045 sata_hba_event_notify(
7948 8046 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7949 8047 &sdevice,
7950 8048 SATA_EVNT_DEVICE_ATTACHED);
7951 8049 mutex_enter(&ahci_portp->ahciport_mutex);
7952 8050
7953 8051 } else {
7954 8052 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7955 8053 "port %d: a device is hot unplugged", port);
7956 8054 mutex_exit(&ahci_portp->ahciport_mutex);
7957 8055 sata_hba_event_notify(
7958 8056 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7959 8057 &sdevice,
7960 8058 SATA_EVNT_DEVICE_DETACHED);
7961 8059 mutex_enter(&ahci_portp->ahciport_mutex);
7962 8060 }
7963 8061
7964 8062 mutex_exit(&ahci_portp->ahciport_mutex);
7965 8063
7966 8064 return (AHCI_SUCCESS);
7967 8065 }
7968 8066
7969 8067 /*
7970 8068 * Enable the interrupts for a particular port.
7971 8069 */
7972 8070 static void
7973 8071 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port)
7974 8072 {
7975 8073 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
7976 8074
7977 8075 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
7978 8076 "ahci_enable_port_intrs enter, port %d", port);
7979 8077
7980 8078 /*
7981 8079 * Clear port interrupt status before enabling interrupt
7982 8080 */
7983 8081 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7984 8082 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port),
7985 8083 AHCI_PORT_INTR_MASK);
7986 8084
7987 8085 /*
7988 8086 * Clear the pending bit from IS.IPS
7989 8087 */
7990 8088 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7991 8089 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port));
7992 8090
7993 8091 /*
7994 8092 * Enable the following interrupts:
7995 8093 * Device to Host Register FIS Interrupt (DHRS)
7996 8094 * PIO Setup FIS Interrupt (PSS)
7997 8095 * Set Device Bits Interrupt (SDBS)
7998 8096 * Unknown FIS Interrupt (UFS)
7999 8097 * Port Connect Change Status (PCS)
8000 8098 * PhyRdy Change Status (PRCS)
8001 8099 * Overflow Status (OFS)
8002 8100 * Interface Non-fatal Error Status (INFS)
8003 8101 * Interface Fatal Error Status (IFS)
8004 8102 * Host Bus Data Error Status (HBDS)
8005 8103 * Host Bus Fatal Error Status (HBFS)
8006 8104 * Task File Error Status (TFES)
8007 8105 */
8008 8106 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8009 8107 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port),
8010 8108 (AHCI_INTR_STATUS_DHRS |
8011 8109 AHCI_INTR_STATUS_PSS |
8012 8110 AHCI_INTR_STATUS_SDBS |
8013 8111 AHCI_INTR_STATUS_UFS |
8014 8112 AHCI_INTR_STATUS_DPS |
8015 8113 AHCI_INTR_STATUS_PCS |
8016 8114 AHCI_INTR_STATUS_PRCS |
8017 8115 AHCI_INTR_STATUS_OFS |
8018 8116 AHCI_INTR_STATUS_INFS |
8019 8117 AHCI_INTR_STATUS_IFS |
8020 8118 AHCI_INTR_STATUS_HBDS |
8021 8119 AHCI_INTR_STATUS_HBFS |
8022 8120 AHCI_INTR_STATUS_TFES));
8023 8121 }
8024 8122
8025 8123 /*
8026 8124 * Enable interrupts for all the ports.
8027 8125 */
8028 8126 static void
8029 8127 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp)
8030 8128 {
8031 8129 uint32_t ghc_control;
8032 8130
8033 8131 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
8034 8132
8035 8133 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter", NULL);
8036 8134
8037 8135 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8038 8136 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
8039 8137
8040 8138 ghc_control |= AHCI_HBA_GHC_IE;
8041 8139
8042 8140 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8043 8141 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
8044 8142 }
8045 8143
8046 8144 /*
8047 8145 * Disable interrupts for a particular port.
8048 8146 */
8049 8147 static void
8050 8148 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port)
8051 8149 {
8052 8150 ASSERT(ahci_ctlp->ahcictl_flags & AHCI_QUIESCE ||
8053 8151 MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
8054 8152
8055 8153 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
8056 8154 "ahci_disable_port_intrs enter, port %d", port);
8057 8155
8058 8156 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8059 8157 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0);
8060 8158 }
8061 8159
8062 8160 /*
8063 8161 * Disable interrupts for the whole HBA.
8064 8162 *
8065 8163 * The global bit is cleared, then all interrupt sources from all
8066 8164 * ports are disabled.
8067 8165 */
8068 8166 static void
8069 8167 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp)
8070 8168 {
8071 8169 uint32_t ghc_control;
8072 8170
8073 8171 ASSERT(ahci_ctlp->ahcictl_flags & (AHCI_ATTACH | AHCI_QUIESCE) ||
8074 8172 MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
8075 8173
8076 8174 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter",
8077 8175 NULL);
8078 8176
8079 8177 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8080 8178 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
8081 8179
8082 8180 ghc_control &= ~AHCI_HBA_GHC_IE;
8083 8181
8084 8182 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8085 8183 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
8086 8184 }
8087 8185
8088 8186 /*
8089 8187 * Handle FIXED or MSI interrupts.
8090 8188 */
8091 8189 /*
8092 8190 * According to AHCI spec, the HBA may support several interrupt modes:
8093 8191 * * pin based interrupts (FIXED)
8094 8192 * * single MSI message interrupts
8095 8193 * * multiple MSI based message interrupts
8096 8194 *
8097 8195 * For pin based interrupts, the software interrupt handler need to check IS
8098 8196 * register to find out which port has pending interrupts. And then check
8099 8197 * PxIS register to find out which interrupt events happened on that port.
8100 8198 *
8101 8199 * For single MSI message interrupts, MSICAP.MC.MSIE is set with '1', and
8102 8200 * MSICAP.MC.MME is set with '0'. This mode is similar to pin based interrupts
8103 8201 * in that software interrupt handler need to check IS register to determine
8104 8202 * which port triggered the interrupts since it uses a single message for all
8105 8203 * port interrupts.
8106 8204 *
8107 8205 * HBA may optionally support multiple MSI message for better performance. In
8108 8206 * this mode, each port may have its own interrupt message, and thus generation
8109 8207 * of interrupts is no longer controlled through the IS register. MSICAP.MC.MMC
8110 8208 * represents a power-of-2 wrapper on the number of implemented ports, and
8111 8209 * the mapping of ports to interrupts is done in a 1-1 relationship, up to the
8112 8210 * maximum number of assigned interrupts. When the number of MSI messages
8113 8211 * allocated is less than the number requested, then hardware may have two
8114 8212 * implementation behaviors:
8115 8213 * * assign each ports its own interrupt and then force all additional
8116 8214 * ports to share the last interrupt message, and this condition is
8117 8215 * indicated by clearing GHC.MRSM to '0'
8118 8216 * * revert to single MSI mode, indicated by setting GHC.MRSM to '1'
8119 8217 * When multiple-message MSI is enabled, hardware will still set IS register
8120 8218 * as single message case. And this IS register may be used by software when
8121 8219 * fewer than the requested number of messages is granted in order to determine
8122 8220 * which port had the interrupt.
8123 8221 *
8124 8222 * Note: The current ahci driver only supports the first two interrupt modes:
8125 8223 * pin based interrupts and single MSI message interrupts, and the reason
8126 8224 * is indicated in below code.
8127 8225 */
8128 8226 static int
8129 8227 ahci_add_intrs(ahci_ctl_t *ahci_ctlp, int intr_type)
8130 8228 {
8131 8229 dev_info_t *dip = ahci_ctlp->ahcictl_dip;
8132 8230 int count, avail, actual;
8133 8231 int i, rc;
8134 8232
8135 8233 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
8136 8234 "ahci_add_intrs enter interrupt type 0x%x", intr_type);
8137 8235
8138 8236 /* get number of interrupts. */
8139 8237 rc = ddi_intr_get_nintrs(dip, intr_type, &count);
8140 8238 if ((rc != DDI_SUCCESS) || (count == 0)) {
8141 8239 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8142 8240 "ddi_intr_get_nintrs() failed, "
8143 8241 "rc %d count %d\n", rc, count);
8144 8242 return (DDI_FAILURE);
8145 8243 }
8146 8244
8147 8245 /* get number of available interrupts. */
8148 8246 rc = ddi_intr_get_navail(dip, intr_type, &avail);
8149 8247 if ((rc != DDI_SUCCESS) || (avail == 0)) {
8150 8248 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8151 8249 "ddi_intr_get_navail() failed, "
8152 8250 "rc %d avail %d\n", rc, avail);
8153 8251 return (DDI_FAILURE);
8154 8252 }
8155 8253
8156 8254 #if AHCI_DEBUG
8157 8255 if (avail < count) {
8158 8256 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8159 8257 "ddi_intr_get_nintrs returned %d, navail() returned %d",
8160 8258 count, avail);
8161 8259 }
8162 8260 #endif
8163 8261
8164 8262 /*
8165 8263 * Note: So far Solaris restricts the maximum number of messages for
8166 8264 * x86 to 2, that is avail is 2, so here we set the count with 1 to
8167 8265 * force the driver to use single MSI message interrupt. In future if
8168 8266 * Solaris remove the restriction, then we need to delete the below
8169 8267 * code and try to use multiple interrupt routine to gain better
8170 8268 * performance.
8171 8269 */
8172 8270 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
8173 8271 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
8174 8272 "force to use one interrupt routine though the "
8175 8273 "HBA supports %d interrupt", count);
8176 8274 count = 1;
8177 8275 }
8178 8276
8179 8277 /* Allocate an array of interrupt handles. */
8180 8278 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t);
8181 8279 ahci_ctlp->ahcictl_intr_htable =
8182 8280 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP);
8183 8281
8184 8282 /* call ddi_intr_alloc(). */
8185 8283 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable,
8186 8284 intr_type, 0, count, &actual, DDI_INTR_ALLOC_NORMAL);
8187 8285
8188 8286 if ((rc != DDI_SUCCESS) || (actual == 0)) {
8189 8287 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8190 8288 "ddi_intr_alloc() failed, rc %d count %d actual %d "
8191 8289 "avail %d\n", rc, count, actual, avail);
8192 8290 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8193 8291 ahci_ctlp->ahcictl_intr_size);
8194 8292 return (DDI_FAILURE);
8195 8293 }
8196 8294
8197 8295 /* use interrupt count returned */
8198 8296 #if AHCI_DEBUG
8199 8297 if (actual < count) {
8200 8298 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8201 8299 "Requested: %d, Received: %d", count, actual);
8202 8300 }
8203 8301 #endif
8204 8302
8205 8303 ahci_ctlp->ahcictl_intr_cnt = actual;
8206 8304
8207 8305 /*
8208 8306 * Get priority for first, assume remaining are all the same.
8209 8307 */
8210 8308 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0],
8211 8309 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) {
8212 8310 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8213 8311 "ddi_intr_get_pri() failed", NULL);
8214 8312
8215 8313 /* Free already allocated intr. */
8216 8314 for (i = 0; i < actual; i++) {
8217 8315 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]);
8218 8316 }
8219 8317
8220 8318 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8221 8319 ahci_ctlp->ahcictl_intr_size);
8222 8320 return (DDI_FAILURE);
8223 8321 }
8224 8322
8225 8323 /* Test for high level interrupt. */
8226 8324 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) {
8227 8325 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8228 8326 "ahci_add_intrs: Hi level intr not supported", NULL);
8229 8327
8230 8328 /* Free already allocated intr. */
8231 8329 for (i = 0; i < actual; i++) {
8232 8330 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]);
8233 8331 }
8234 8332
8235 8333 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8236 8334 sizeof (ddi_intr_handle_t));
8237 8335
8238 8336 return (DDI_FAILURE);
8239 8337 }
8240 8338
8241 8339 /* Call ddi_intr_add_handler(). */
8242 8340 for (i = 0; i < actual; i++) {
8243 8341 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[i],
8244 8342 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) {
8245 8343 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8246 8344 "ddi_intr_add_handler() failed", NULL);
8247 8345
8248 8346 /* Free already allocated intr. */
8249 8347 for (i = 0; i < actual; i++) {
8250 8348 (void) ddi_intr_free(
8251 8349 ahci_ctlp->ahcictl_intr_htable[i]);
8252 8350 }
8253 8351
8254 8352 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8255 8353 ahci_ctlp->ahcictl_intr_size);
8256 8354 return (DDI_FAILURE);
8257 8355 }
8258 8356 }
8259 8357
8260 8358 if (ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0],
8261 8359 &ahci_ctlp->ahcictl_intr_cap) != DDI_SUCCESS) {
8262 8360 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8263 8361 "ddi_intr_get_cap() failed", NULL);
8264 8362
8265 8363 /* Free already allocated intr. */
8266 8364 for (i = 0; i < actual; i++) {
8267 8365 (void) ddi_intr_free(
8268 8366 ahci_ctlp->ahcictl_intr_htable[i]);
8269 8367 }
8270 8368
8271 8369 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8272 8370 ahci_ctlp->ahcictl_intr_size);
8273 8371 return (DDI_FAILURE);
8274 8372 }
8275 8373
8276 8374 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) {
8277 8375 /* Call ddi_intr_block_enable() for MSI. */
8278 8376 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable,
8279 8377 ahci_ctlp->ahcictl_intr_cnt);
8280 8378 } else {
8281 8379 /* Call ddi_intr_enable() for FIXED or MSI non block enable. */
8282 8380 for (i = 0; i < ahci_ctlp->ahcictl_intr_cnt; i++) {
8283 8381 (void) ddi_intr_enable(
8284 8382 ahci_ctlp->ahcictl_intr_htable[i]);
8285 8383 }
8286 8384 }
8287 8385
8288 8386 return (DDI_SUCCESS);
8289 8387 }
8290 8388
8291 8389 /*
8292 8390 * Removes the registered interrupts irrespective of whether they
8293 8391 * were legacy or MSI.
8294 8392 *
8295 8393 * NOTE: The controller interrupts must be disabled before calling
8296 8394 * this routine.
8297 8395 */
8298 8396 static void
8299 8397 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp)
8300 8398 {
8301 8399 int x;
8302 8400
8303 8401 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered", NULL);
8304 8402
8305 8403 /* Disable all interrupts. */
8306 8404 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) &&
8307 8405 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) {
8308 8406 /* Call ddi_intr_block_disable(). */
8309 8407 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable,
8310 8408 ahci_ctlp->ahcictl_intr_cnt);
8311 8409 } else {
8312 8410 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
8313 8411 (void) ddi_intr_disable(
8314 8412 ahci_ctlp->ahcictl_intr_htable[x]);
8315 8413 }
8316 8414 }
8317 8415
8318 8416 /* Call ddi_intr_remove_handler(). */
8319 8417 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
8320 8418 (void) ddi_intr_remove_handler(
8321 8419 ahci_ctlp->ahcictl_intr_htable[x]);
8322 8420 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]);
8323 8421 }
8324 8422
8325 8423 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size);
8326 8424 }
8327 8425
8328 8426 /*
8329 8427 * This routine tries to put port into P:NotRunning state by clearing
8330 8428 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h
8331 8429 * and PxCMD.CR to '0'.
8332 8430 */
8333 8431 static int
8334 8432 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp,
8335 8433 ahci_port_t *ahci_portp, uint8_t port)
8336 8434 {
8337 8435 uint32_t port_cmd_status;
8338 8436 int loop_count;
8339 8437
8340 8438 ASSERT(ahci_ctlp->ahcictl_flags & AHCI_QUIESCE ||
8341 8439 MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
8342 8440
8343 8441 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
8344 8442 "ahci_put_port_into_notrunning_state enter: port %d", port);
8345 8443
8346 8444 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8347 8445 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
8348 8446
8349 8447 port_cmd_status &= ~AHCI_CMD_STATUS_ST;
8350 8448 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8351 8449 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status);
8352 8450
8353 8451 /* Wait until PxCMD.CR is cleared */
8354 8452 loop_count = 0;
8355 8453 do {
8356 8454 port_cmd_status =
8357 8455 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8358 8456 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
8359 8457
8360 8458 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) {
8361 8459 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
8362 8460 "clearing port %d CMD.CR timeout, "
8363 8461 "port_cmd_status = 0x%x", port,
8364 8462 port_cmd_status);
8365 8463 /*
8366 8464 * We are effectively timing out after 0.5 sec.
8367 8465 * This value is specified in AHCI spec.
8368 8466 */
8369 8467 break;
8370 8468 }
8371 8469
8372 8470 /* Wait for 10 millisec */
8373 8471 drv_usecwait(AHCI_10MS_USECS);
8374 8472 } while (port_cmd_status & AHCI_CMD_STATUS_CR);
8375 8473
8376 8474 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED;
8377 8475
8378 8476 if (port_cmd_status & AHCI_CMD_STATUS_CR) {
8379 8477 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
8380 8478 "ahci_put_port_into_notrunning_state: failed to clear "
8381 8479 "PxCMD.CR to '0' after loop count: %d, and "
8382 8480 "port_cmd_status = 0x%x", loop_count, port_cmd_status);
8383 8481 return (AHCI_FAILURE);
8384 8482 } else {
8385 8483 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
8386 8484 "ahci_put_port_into_notrunning_state: succeeded to clear "
8387 8485 "PxCMD.CR to '0' after loop count: %d, and "
8388 8486 "port_cmd_status = 0x%x", loop_count, port_cmd_status);
8389 8487 return (AHCI_SUCCESS);
8390 8488 }
8391 8489 }
8392 8490
8393 8491 /*
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8394 8492 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY
8395 8493 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a
8396 8494 * stable state, then set PxCMD.ST to '1' to start the port directly.
8397 8495 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a
8398 8496 * COMRESET to the device to put it in an idle state.
8399 8497 *
8400 8498 * The fifth argument returns whether the port reset is involved during
8401 8499 * the process.
8402 8500 *
8403 8501 * The routine will be called under following scenarios:
8404 - * + To reset the HBA
8502 + * + To reset the HBA
8405 8503 * + To abort the packet(s)
8406 8504 * + To reset the port
8407 8505 * + To activate the port
8408 8506 * + Fatal error recovery
8409 8507 * + To abort the timeout packet(s)
8410 8508 *
8411 8509 * NOTES!!! During this procedure, PxSERR register will be cleared, and
8412 8510 * according to the spec, the clearance of three bits will also clear
8413 8511 * three interrupt status bits.
8414 8512 * 1. PxSERR.DIAG.F will clear PxIS.UFS
8415 8513 * 2. PxSERR.DIAG.X will clear PxIS.PCS
8416 8514 * 3. PxSERR.DIAG.N will clear PxIS.PRCS
8417 8515 *
8418 8516 * Among these three interrupt events, the driver needs to take care of
8419 8517 * PxIS.PRCS, which is the hot plug event. When the driver found out
8420 8518 * a device was unplugged, it will call the interrupt handler.
8421 8519 */
8422 8520 static int
8423 8521 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp,
8424 8522 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag)
8425 8523 {
8426 8524 uint32_t port_sstatus;
8427 8525 uint32_t task_file_status;
8428 8526 sata_device_t sdevice;
8429 8527 int rval;
8430 8528 ahci_addr_t addr_port;
8431 8529 ahci_pmult_info_t *pminfo = NULL;
8432 8530 int dev_exists_begin = 0;
8433 8531 int dev_exists_end = 0;
8434 8532 uint32_t previous_dev_type = ahci_portp->ahciport_device_type;
8435 8533 int npmport = 0;
8436 8534 uint8_t cport = ahci_ctlp->ahcictl_port_to_cport[port];
8437 8535
8438 8536 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
8439 8537
8440 8538 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
8441 8539 "ahci_restart_port_wait_till_ready: port %d enter", port);
8442 8540
8443 8541 AHCI_ADDR_SET_PORT(&addr_port, port);
8444 8542
8445 8543 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE)
8446 8544 dev_exists_begin = 1;
8447 8545
8448 8546 /* First clear PxCMD.ST */
8449 8547 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp,
8450 8548 port);
8451 8549 if (rval != AHCI_SUCCESS)
8452 8550 /*
8453 8551 * If PxCMD.CR does not clear within a reasonable time, it
8454 8552 * may assume the interface is in a hung condition and may
8455 8553 * continue with issuing the port reset.
8456 8554 */
8457 8555 goto reset;
8458 8556
8459 8557 /* Then clear PxSERR */
8460 8558 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8461 8559 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
8462 8560 AHCI_SERROR_CLEAR_ALL);
8463 8561
8464 8562 /* Then get PxTFD */
8465 8563 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8466 8564 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
8467 8565
8468 8566 /*
8469 8567 * Check whether the device is in a stable status, if yes,
8470 8568 * then start the port directly. However for ahci_tran_reset_dport,
8471 8569 * we may have to perform a port reset.
8472 8570 */
8473 8571 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) &&
8474 8572 !(flag & AHCI_PORT_RESET))
8475 8573 goto out;
8476 8574
8477 8575 reset:
8478 8576 /*
8479 8577 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue
8480 8578 * a COMRESET to the device
8481 8579 */
8482 8580 ahci_disable_port_intrs(ahci_ctlp, port);
8483 8581 rval = ahci_port_reset(ahci_ctlp, ahci_portp, &addr_port);
8484 8582 ahci_enable_port_intrs(ahci_ctlp, port);
8485 8583
8486 8584 #ifdef AHCI_DEBUG
8487 8585 if (rval != AHCI_SUCCESS)
8488 8586 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8489 8587 "ahci_restart_port_wait_till_ready: port %d failed",
8490 8588 port);
8491 8589 #endif
8492 8590
8493 8591 if (reset_flag != NULL)
8494 8592 *reset_flag = 1;
8495 8593
8496 8594 /* Indicate to the framework that a reset has happened. */
8497 8595 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) &&
8498 8596 (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) &&
8499 8597 !(flag & AHCI_RESET_NO_EVENTS_UP)) {
8500 8598 /* Set the reset in progress flag */
8501 8599 ahci_portp->ahciport_reset_in_progress = 1;
8502 8600
8503 8601 bzero((void *)&sdevice, sizeof (sata_device_t));
8504 8602 sdevice.satadev_addr.cport =
8505 8603 ahci_ctlp->ahcictl_port_to_cport[port];
8506 8604 sdevice.satadev_addr.pmport = 0;
8507 8605 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
8508 8606
8509 8607 sdevice.satadev_state = SATA_DSTATE_RESET |
8510 8608 SATA_DSTATE_PWR_ACTIVE;
8511 8609 if (ahci_ctlp->ahcictl_sata_hba_tran) {
8512 8610 mutex_exit(&ahci_portp->ahciport_mutex);
8513 8611 sata_hba_event_notify(
8514 8612 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
8515 8613 &sdevice,
8516 8614 SATA_EVNT_DEVICE_RESET);
8517 8615 mutex_enter(&ahci_portp->ahciport_mutex);
8518 8616 }
8519 8617
8520 8618 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
8521 8619 "port %d sending event up: SATA_EVNT_DEVICE_RESET", port);
8522 8620 } else {
8523 8621 ahci_portp->ahciport_reset_in_progress = 0;
8524 8622 }
8525 8623
8526 8624 out:
8527 8625 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8528 8626
8529 8627 /* SStatus tells the presence of device. */
8530 8628 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8531 8629 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
8532 8630
8533 8631 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) {
8534 8632 dev_exists_end = 1;
8535 8633 }
8536 8634
8537 8635 if (dev_exists_begin == 0 && dev_exists_end == 0) /* 0 -> 0 */
8538 8636 return (rval);
8539 8637
8540 8638 /* Check whether a hot plug event happened */
8541 8639 if (dev_exists_begin == 1 && dev_exists_end == 0) { /* 1 -> 0 */
8542 8640 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8543 8641 "ahci_restart_port_wait_till_ready: port %d "
8544 8642 "device is removed", port);
8545 8643 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV;
8546 8644 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8547 8645 "ahci_restart_port_wait_till_ready: port %d "
8548 8646 "AHCI_PORT_FLAG_NODEV flag is set", port);
8549 8647 mutex_exit(&ahci_portp->ahciport_mutex);
8550 8648 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port);
8551 8649 mutex_enter(&ahci_portp->ahciport_mutex);
8552 8650
8553 8651 return (rval);
8554 8652 }
8555 8653
8556 8654
8557 8655 /* 0/1 -> 1 : device may change */
8558 8656 /*
8559 8657 * May be called by ahci_fatal_error_recovery_handler, so
8560 8658 * don't issue software if the previous device is ATAPI.
8561 8659 */
8562 8660 if (ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPI)
8563 8661 return (rval);
8564 8662
8565 8663 /*
8566 8664 * The COMRESET will make port multiplier enter legacy mode.
8567 8665 * Issue a software reset to make it work again.
8568 8666 */
8569 8667 ahci_disable_port_intrs(ahci_ctlp, port);
8570 8668 ahci_find_dev_signature(ahci_ctlp, ahci_portp, &addr_port);
8571 8669 ahci_enable_port_intrs(ahci_ctlp, port);
8572 8670
8573 8671 /*
8574 8672 * Following codes are specific for the port multiplier
8575 8673 */
8576 8674 if (previous_dev_type != SATA_DTYPE_PMULT &&
8577 8675 ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
8578 8676 /* in case previous_dev_type is corrupt */
8579 8677 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
8580 8678 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8581 8679 return (rval);
8582 8680 }
8583 8681
8584 8682 /* Device change: PMult -> Non-PMult */
8585 8683 if (previous_dev_type == SATA_DTYPE_PMULT &&
8586 8684 ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
8587 8685 /*
8588 8686 * This might happen because
8589 8687 * 1. Software reset failed. Port multiplier is not correctly
8590 8688 * enumerated.
8591 8689 * 2. Another non-port-multiplier device is attached. Perhaps
8592 8690 * the port multiplier was replaced by another device by
8593 8691 * whatever reason, but AHCI driver missed hot-plug event.
8594 8692 *
8595 8693 * Now that the port has been initialized, we just need to
8596 8694 * update the port structure according new device, then report
8597 8695 * and wait SATA framework to probe new device.
8598 8696 */
8599 8697
8600 8698 /* Force to release pmult resource */
8601 8699 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
8602 8700 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8603 8701
8604 8702 bzero((void *)&sdevice, sizeof (sata_device_t));
8605 8703 sdevice.satadev_addr.cport =
8606 8704 ahci_ctlp->ahcictl_port_to_cport[port];
8607 8705 sdevice.satadev_addr.pmport = 0;
8608 8706 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
8609 8707
8610 8708 sdevice.satadev_state = SATA_DSTATE_RESET |
8611 8709 SATA_DSTATE_PWR_ACTIVE;
8612 8710
8613 8711 mutex_exit(&ahci_portp->ahciport_mutex);
8614 8712 sata_hba_event_notify(
8615 8713 ahci_ctlp->ahcictl_dip,
8616 8714 &sdevice,
8617 8715 SATA_EVNT_DEVICE_RESET);
8618 8716 mutex_enter(&ahci_portp->ahciport_mutex);
8619 8717
8620 8718 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8621 8719 "Port multiplier is [Gone] at port %d ", port);
8622 8720 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
8623 8721 "port %d sending event up: SATA_EVNT_DEVICE_RESET", port);
8624 8722
8625 8723 return (AHCI_SUCCESS);
8626 8724 }
8627 8725
8628 8726 /* Device change: Non-PMult -> PMult */
8629 8727 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) {
8630 8728
8631 8729 /* NOTE: The PxCMD.PMA may be cleared by HBA reset. */
8632 8730 ahci_alloc_pmult(ahci_ctlp, ahci_portp);
8633 8731
8634 8732 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8635 8733 }
8636 8734 pminfo = ahci_portp->ahciport_pmult_info;
8637 8735 ASSERT(pminfo != NULL);
8638 8736
8639 8737 /* Device (may) change: PMult -> PMult */
8640 8738 /*
8641 8739 * First initialize port multiplier. Set state to READY and wait for
8642 8740 * probe entry point to initialize it
8643 8741 */
8644 8742 ahci_portp->ahciport_port_state = SATA_STATE_READY;
8645 8743
8646 8744 /*
8647 8745 * It's a little complicated while target is a port multiplier. we
8648 8746 * need to COMRESET all pmports behind that PMult otherwise those
8649 8747 * sub-links between the PMult and the sub-devices will be in an
8650 8748 * inactive state (indicated by PSCR0/PxSSTS) and the following access
8651 8749 * to those sub-devices will be rejected by Link-Fatal-Error.
8652 8750 */
8653 8751 /*
8654 8752 * The PxSNTF will be set soon after the pmult is plugged. While the
8655 8753 * pmult itself is attaching, sata_hba_event_notfiy will fail. so we
8656 8754 * simply mark every sub-port as 'unknown', then ahci_probe_pmport
8657 8755 * will initialized it.
8658 8756 */
8659 8757 for (npmport = 0; npmport < pminfo->ahcipmi_num_dev_ports; npmport++)
8660 8758 pminfo->ahcipmi_port_state[npmport] = SATA_STATE_UNKNOWN;
8661 8759
8662 8760 /* Report reset event. */
8663 8761 ahci_portp->ahciport_reset_in_progress = 1;
8664 8762
8665 8763 bzero((void *)&sdevice, sizeof (sata_device_t));
8666 8764 sdevice.satadev_addr.cport = cport;
8667 8765 sdevice.satadev_addr.pmport = SATA_PMULT_HOSTPORT;
8668 8766 sdevice.satadev_addr.qual = SATA_ADDR_PMULT;
8669 8767 sdevice.satadev_state = SATA_DSTATE_RESET | SATA_DSTATE_PWR_ACTIVE;
8670 8768 sata_hba_event_notify(ahci_ctlp->ahcictl_dip, &sdevice,
8671 8769 SATA_EVNT_DEVICE_RESET);
8672 8770
8673 8771 return (rval);
8674 8772 }
8675 8773
8676 8774 /*
8677 8775 * This routine may be called under four scenarios:
8678 8776 * a) do the recovery from fatal error
8679 8777 * b) or we need to timeout some commands
8680 8778 * c) or we need to abort some commands
8681 8779 * d) or we need reset device/port/controller
8682 8780 *
8683 8781 * In all these scenarios, we need to send any pending unfinished
8684 8782 * commands up to sata framework.
8685 8783 */
8686 8784 static void
8687 8785 ahci_mop_commands(ahci_ctl_t *ahci_ctlp,
8688 8786 ahci_port_t *ahci_portp,
8689 8787 uint32_t slot_status,
8690 8788 uint32_t failed_tags,
8691 8789 uint32_t timeout_tags,
8692 8790 uint32_t aborted_tags,
8693 8791 uint32_t reset_tags)
8694 8792 {
8695 8793 uint32_t finished_tags = 0;
8696 8794 uint32_t unfinished_tags = 0;
8697 8795 int tmp_slot;
8698 8796 sata_pkt_t *satapkt;
8699 8797 int ncq_cmd_in_progress = 0;
8700 8798 int err_retri_cmd_in_progress = 0;
8701 8799 int rdwr_pmult_cmd_in_progress = 0;
8702 8800
8703 8801 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
8704 8802
8705 8803 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp,
8706 8804 "ahci_mop_commands entered: port: %d slot_status: 0x%x",
8707 8805 ahci_portp->ahciport_port_num, slot_status);
8708 8806
8709 8807 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp,
8710 8808 "ahci_mop_commands: failed_tags: 0x%x, "
8711 8809 "timeout_tags: 0x%x aborted_tags: 0x%x, "
8712 8810 "reset_tags: 0x%x", failed_tags,
8713 8811 timeout_tags, aborted_tags, reset_tags);
8714 8812
8715 8813 #ifdef AHCI_DEBUG
8716 8814 if (ahci_debug_flags & AHCIDBG_ERRS) {
8717 8815 int i;
8718 8816 char msg_buf[200] = {0, };
8719 8817 for (i = 0x1f; i >= 0; i--) {
8720 8818 if (ahci_portp->ahciport_slot_pkts[i] != NULL)
8721 8819 msg_buf[i] = 'X';
8722 8820 else
8723 8821 msg_buf[i] = '.';
8724 8822 }
8725 8823 msg_buf[0x20] = '\0';
8726 8824 cmn_err(CE_NOTE, "port[%d] slots: %s",
8727 8825 ahci_portp->ahciport_port_num, msg_buf);
8728 8826 cmn_err(CE_NOTE, "[ERR-RT] %p [RW-PM] %p ",
8729 8827 (void *)ahci_portp->ahciport_err_retri_pkt,
8730 8828 (void *)ahci_portp->ahciport_rdwr_pmult_pkt);
8731 8829 }
8732 8830 #endif
8733 8831
8734 8832 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
8735 8833 finished_tags = ahci_portp->ahciport_pending_tags &
8736 8834 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
8737 8835
8738 8836 unfinished_tags = slot_status &
8739 8837 AHCI_SLOT_MASK(ahci_ctlp) &
8740 8838 ~failed_tags &
8741 8839 ~aborted_tags &
8742 8840 ~reset_tags &
8743 8841 ~timeout_tags;
8744 8842 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
8745 8843 ncq_cmd_in_progress = 1;
8746 8844 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
8747 8845 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
8748 8846
8749 8847 unfinished_tags = slot_status &
8750 8848 AHCI_NCQ_SLOT_MASK(ahci_portp) &
8751 8849 ~failed_tags &
8752 8850 ~aborted_tags &
8753 8851 ~reset_tags &
8754 8852 ~timeout_tags;
8755 8853 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
8756 8854
8757 8855 /*
8758 8856 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is
8759 8857 * set, it means REQUEST SENSE or READ LOG EXT command doesn't
8760 8858 * complete successfully due to one of the following three
8761 8859 * conditions:
8762 8860 *
8763 8861 * 1. Fatal error - failed_tags includes its slot
8764 8862 * 2. Timed out - timeout_tags includes its slot
8765 8863 * 3. Aborted when hot unplug - aborted_tags includes its
8766 8864 * slot
8767 8865 *
8768 8866 * Please note that the command is always sent down in Slot 0
8769 8867 */
8770 8868 err_retri_cmd_in_progress = 1;
8771 8869 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp,
8772 8870 "ahci_mop_commands is called for port %d while "
8773 8871 "REQUEST SENSE or READ LOG EXT for error retrieval "
8774 8872 "is being executed slot_status = 0x%x",
8775 8873 ahci_portp->ahciport_port_num, slot_status);
8776 8874 ASSERT(ahci_portp->ahciport_mop_in_progress > 1);
8777 8875 ASSERT(slot_status == 0x1);
8778 8876 } else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
8779 8877 rdwr_pmult_cmd_in_progress = 1;
8780 8878 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
8781 8879 "ahci_mop_commands is called for port %d while "
8782 8880 "READ/WRITE PORTMULT command is being executed",
8783 8881 ahci_portp->ahciport_port_num);
8784 8882
8785 8883 ASSERT(slot_status == 0x1);
8786 8884 }
8787 8885
8788 8886 #ifdef AHCI_DEBUG
8789 8887 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp,
8790 8888 "ahci_mop_commands: finished_tags: 0x%x, "
8791 8889 "unfinished_tags 0x%x", finished_tags, unfinished_tags);
8792 8890 #endif
8793 8891
8794 8892 /* Send up finished packets with SATA_PKT_COMPLETED */
8795 8893 while (finished_tags) {
8796 8894 tmp_slot = ddi_ffs(finished_tags) - 1;
8797 8895 if (tmp_slot == -1) {
8798 8896 break;
8799 8897 }
8800 8898
8801 8899 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8802 8900 ASSERT(satapkt != NULL);
8803 8901
8804 8902 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: "
8805 8903 "sending up pkt 0x%p with SATA_PKT_COMPLETED",
8806 8904 (void *)satapkt);
8807 8905
8808 8906 /*
8809 8907 * Cannot fetch the return register content since the port
8810 8908 * was restarted, so the corresponding tag will be set to
8811 8909 * aborted tags.
8812 8910 */
8813 8911 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
8814 8912 CLEAR_BIT(finished_tags, tmp_slot);
8815 8913 aborted_tags |= tmp_slot;
8816 8914 continue;
8817 8915 }
8818 8916
8819 8917 if (ncq_cmd_in_progress)
8820 8918 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8821 8919 tmp_slot);
8822 8920 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8823 8921 CLEAR_BIT(finished_tags, tmp_slot);
8824 8922 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8825 8923
8826 8924 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
8827 8925 }
8828 8926
8829 8927 /* Send up failed packets with SATA_PKT_DEV_ERROR. */
8830 8928 while (failed_tags) {
8831 8929 if (err_retri_cmd_in_progress) {
8832 8930 satapkt = ahci_portp->ahciport_err_retri_pkt;
8833 8931 ASSERT(satapkt != NULL);
8834 8932 ASSERT(failed_tags == 0x1);
8835 8933
8836 8934 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8837 8935 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR",
8838 8936 (void *)satapkt);
8839 8937 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_DEV_ERROR);
8840 8938 break;
8841 8939 }
8842 8940 if (rdwr_pmult_cmd_in_progress) {
8843 8941 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8844 8942 ASSERT(satapkt != NULL);
8845 8943 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8846 8944 "ahci_mop_commands: sending up "
8847 8945 "rdwr pmult pkt 0x%p with SATA_PKT_DEV_ERROR",
8848 8946 (void *)satapkt);
8849 8947 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_DEV_ERROR);
8850 8948 break;
8851 8949 }
8852 8950
8853 8951 tmp_slot = ddi_ffs(failed_tags) - 1;
8854 8952 if (tmp_slot == -1) {
8855 8953 break;
8856 8954 }
8857 8955
8858 8956 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8859 8957 ASSERT(satapkt != NULL);
8860 8958
8861 8959 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8862 8960 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR",
8863 8961 (void *)satapkt);
8864 8962
8865 8963 if (ncq_cmd_in_progress)
8866 8964 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8867 8965 tmp_slot);
8868 8966 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8869 8967 CLEAR_BIT(failed_tags, tmp_slot);
8870 8968 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8871 8969
8872 8970 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_DEV_ERROR);
8873 8971 }
8874 8972
8875 8973 /* Send up timeout packets with SATA_PKT_TIMEOUT. */
8876 8974 while (timeout_tags) {
8877 8975 if (err_retri_cmd_in_progress) {
8878 8976 satapkt = ahci_portp->ahciport_err_retri_pkt;
8879 8977 ASSERT(satapkt != NULL);
8880 8978 ASSERT(timeout_tags == 0x1);
8881 8979
8882 8980 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8883 8981 "sending up pkt 0x%p with SATA_PKT_TIMEOUT",
8884 8982 (void *)satapkt);
8885 8983 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_TIMEOUT);
8886 8984 break;
8887 8985 }
8888 8986 if (rdwr_pmult_cmd_in_progress) {
8889 8987 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8890 8988 ASSERT(satapkt != NULL);
8891 8989 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8892 8990 "ahci_mop_commands: sending up "
8893 8991 "rdwr pmult pkt 0x%p with SATA_PKT_TIMEOUT",
8894 8992 (void *)satapkt);
8895 8993 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_TIMEOUT);
8896 8994 break;
8897 8995 }
8898 8996
8899 8997 tmp_slot = ddi_ffs(timeout_tags) - 1;
8900 8998 if (tmp_slot == -1) {
8901 8999 break;
8902 9000 }
8903 9001
8904 9002 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8905 9003 ASSERT(satapkt != NULL);
8906 9004
8907 9005 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8908 9006 "sending up pkt 0x%p with SATA_PKT_TIMEOUT",
8909 9007 (void *)satapkt);
8910 9008
8911 9009 if (ncq_cmd_in_progress)
8912 9010 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8913 9011 tmp_slot);
8914 9012 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8915 9013 CLEAR_BIT(timeout_tags, tmp_slot);
8916 9014 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8917 9015
8918 9016 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_TIMEOUT);
8919 9017 }
8920 9018
8921 9019 /* Send up aborted packets with SATA_PKT_ABORTED */
8922 9020 while (aborted_tags) {
8923 9021 if (err_retri_cmd_in_progress) {
8924 9022 satapkt = ahci_portp->ahciport_err_retri_pkt;
8925 9023 ASSERT(satapkt != NULL);
8926 9024 ASSERT(aborted_tags == 0x1);
8927 9025
8928 9026 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8929 9027 "sending up pkt 0x%p with SATA_PKT_ABORTED",
8930 9028 (void *)satapkt);
8931 9029 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_ABORTED);
8932 9030 break;
8933 9031 }
8934 9032 if (rdwr_pmult_cmd_in_progress) {
8935 9033 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8936 9034 ASSERT(satapkt != NULL);
8937 9035 ASSERT(aborted_tags == 0x1);
8938 9036 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8939 9037 "ahci_mop_commands: sending up "
8940 9038 "rdwr pmult pkt 0x%p with SATA_PKT_ABORTED",
8941 9039 (void *)satapkt);
8942 9040 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_ABORTED);
8943 9041 break;
8944 9042 }
8945 9043
8946 9044 tmp_slot = ddi_ffs(aborted_tags) - 1;
8947 9045 if (tmp_slot == -1) {
8948 9046 break;
8949 9047 }
8950 9048
8951 9049 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8952 9050 ASSERT(satapkt != NULL);
8953 9051
8954 9052 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8955 9053 "sending up pkt 0x%p with SATA_PKT_ABORTED",
8956 9054 (void *)satapkt);
8957 9055
8958 9056 if (ncq_cmd_in_progress)
8959 9057 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8960 9058 tmp_slot);
8961 9059 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8962 9060 CLEAR_BIT(aborted_tags, tmp_slot);
8963 9061 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8964 9062
8965 9063 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_ABORTED);
8966 9064 }
8967 9065
8968 9066 /* Send up reset packets with SATA_PKT_RESET. */
8969 9067 while (reset_tags) {
8970 9068 if (rdwr_pmult_cmd_in_progress) {
8971 9069 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8972 9070 ASSERT(satapkt != NULL);
8973 9071 ASSERT(aborted_tags == 0x1);
8974 9072 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8975 9073 "ahci_mop_commands: sending up "
8976 9074 "rdwr pmult pkt 0x%p with SATA_PKT_RESET",
8977 9075 (void *)satapkt);
8978 9076 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_RESET);
8979 9077 break;
8980 9078 }
8981 9079
8982 9080 tmp_slot = ddi_ffs(reset_tags) - 1;
8983 9081 if (tmp_slot == -1) {
8984 9082 break;
8985 9083 }
8986 9084
8987 9085 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8988 9086 ASSERT(satapkt != NULL);
8989 9087
8990 9088 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8991 9089 "sending up pkt 0x%p with SATA_PKT_RESET",
8992 9090 (void *)satapkt);
8993 9091
8994 9092 if (ncq_cmd_in_progress)
8995 9093 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8996 9094 tmp_slot);
8997 9095 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8998 9096 CLEAR_BIT(reset_tags, tmp_slot);
8999 9097 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
9000 9098
9001 9099 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_RESET);
9002 9100 }
9003 9101
9004 9102 /* Send up unfinished packets with SATA_PKT_RESET */
9005 9103 while (unfinished_tags) {
9006 9104 tmp_slot = ddi_ffs(unfinished_tags) - 1;
9007 9105 if (tmp_slot == -1) {
9008 9106 break;
9009 9107 }
9010 9108
9011 9109 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
9012 9110 ASSERT(satapkt != NULL);
9013 9111
9014 9112 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
9015 9113 "sending up pkt 0x%p with SATA_PKT_RESET",
9016 9114 (void *)satapkt);
9017 9115
9018 9116 if (ncq_cmd_in_progress)
9019 9117 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
9020 9118 tmp_slot);
9021 9119 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
9022 9120 CLEAR_BIT(unfinished_tags, tmp_slot);
9023 9121 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
9024 9122
9025 9123 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_RESET);
9026 9124 }
9027 9125
9028 9126 ahci_portp->ahciport_mop_in_progress--;
9029 9127 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0);
9030 9128
9031 9129 if (ahci_portp->ahciport_mop_in_progress == 0)
9032 9130 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING;
9033 9131
9034 9132 ahci_flush_doneq(ahci_portp);
9035 9133 }
9036 9134
9037 9135 /*
9038 9136 * This routine is going to first request a READ LOG EXT sata pkt from sata
9039 9137 * module, and then deliver it to the HBA to get the ncq failure context.
9040 9138 * The return value is the exactly failed tags.
9041 9139 */
9042 9140 static uint32_t
9043 9141 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
9044 9142 uint8_t port)
9045 9143 {
9046 9144 sata_device_t sdevice;
9047 9145 sata_pkt_t *rdlog_spkt, *spkt;
9048 9146 ddi_dma_handle_t buf_dma_handle;
9049 9147 ahci_addr_t addr;
9050 9148 int loop_count;
9051 9149 int rval;
9052 9150 int failed_slot;
9053 9151 uint32_t failed_tags = 0;
9054 9152 struct sata_ncq_error_recovery_page *ncq_err_page;
9055 9153
9056 9154 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp,
9057 9155 "ahci_get_rdlogext_data enter: port %d", port);
9058 9156
9059 9157 /* Prepare the sdevice data */
9060 9158 bzero((void *)&sdevice, sizeof (sata_device_t));
9061 9159 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
9062 9160
9063 9161 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
9064 9162 sdevice.satadev_addr.pmport = 0;
9065 9163
9066 9164 /* Translate sata_device.satadev_addr -> ahci_addr */
9067 9165 ahci_get_ahci_addr(ahci_ctlp, &sdevice, &addr);
9068 9166
9069 9167 /*
9070 9168 * Call the sata hba interface to get a rdlog spkt
9071 9169 */
9072 9170 loop_count = 0;
9073 9171 loop:
9074 9172 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip,
9075 9173 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ);
9076 9174 if (rdlog_spkt == NULL) {
9077 9175 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) {
9078 9176 /* Sleep for a while */
9079 9177 drv_usecwait(AHCI_10MS_USECS);
9080 9178 goto loop;
9081 9179 }
9082 9180 /* Timed out after 1s */
9083 9181 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9084 9182 "failed to get rdlog spkt for port %d", port);
9085 9183 return (failed_tags);
9086 9184 }
9087 9185
9088 9186 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH);
9089 9187
9090 9188 /*
9091 9189 * This flag is used to handle the specific error recovery when the
9092 9190 * READ LOG EXT command gets a failure (fatal error or time-out).
9093 9191 */
9094 9192 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT;
9095 9193
9096 9194 /*
9097 9195 * This start is not supposed to fail because after port is restarted,
9098 9196 * the whole command list is empty.
9099 9197 */
9100 9198 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt;
9101 9199 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, &addr, rdlog_spkt);
9102 9200 ahci_portp->ahciport_err_retri_pkt = NULL;
9103 9201
9104 9202 /* Remove the flag after READ LOG EXT command is completed */
9105 9203 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_RDLOGEXT;
9106 9204
9107 9205 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) {
9108 9206 /* Update the request log data */
9109 9207 buf_dma_handle = *(ddi_dma_handle_t *)
9110 9208 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle);
9111 9209 rval = ddi_dma_sync(buf_dma_handle, 0, 0,
9112 9210 DDI_DMA_SYNC_FORKERNEL);
9113 9211 if (rval == DDI_SUCCESS) {
9114 9212 ncq_err_page =
9115 9213 (struct sata_ncq_error_recovery_page *)rdlog_spkt->
9116 9214 satapkt_cmd.satacmd_bp->b_un.b_addr;
9117 9215
9118 9216 /* Get the failed tag */
9119 9217 failed_slot = ncq_err_page->ncq_tag;
9120 9218 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9121 9219 "ahci_get_rdlogext_data: port %d "
9122 9220 "failed slot %d", port, failed_slot);
9123 9221 if (failed_slot & NQ) {
9124 9222 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9125 9223 "the failed slot is not a valid tag", NULL);
9126 9224 goto out;
9127 9225 }
9128 9226
9129 9227 failed_slot &= NCQ_TAG_MASK;
9130 9228 spkt = ahci_portp->ahciport_slot_pkts[failed_slot];
9131 9229 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9132 9230 "ahci_get_rdlogext_data: failed spkt 0x%p",
9133 9231 (void *)spkt);
9134 9232 if (spkt == NULL) {
9135 9233 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9136 9234 "the failed slot spkt is NULL", NULL);
9137 9235 goto out;
9138 9236 }
9139 9237
9140 9238 failed_tags = 0x1 << failed_slot;
9141 9239
9142 9240 /* Fill out the error context */
9143 9241 ahci_copy_ncq_err_page(&spkt->satapkt_cmd,
9144 9242 ncq_err_page);
9145 9243 ahci_update_sata_registers(ahci_ctlp, port,
9146 9244 &spkt->satapkt_device);
9147 9245 }
9148 9246 }
9149 9247 out:
9150 9248 sata_free_error_retrieval_pkt(rdlog_spkt);
9151 9249
9152 9250 return (failed_tags);
9153 9251 }
9154 9252
9155 9253 /*
9156 9254 * This routine is going to first request a REQUEST SENSE sata pkt from sata
9157 9255 * module, and then deliver it to the HBA to get the sense data and copy
9158 9256 * the sense data back to the orignal failed sata pkt, and free the REQUEST
9159 9257 * SENSE sata pkt later.
9160 9258 */
9161 9259 static void
9162 9260 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
9163 9261 uint8_t port, sata_pkt_t *spkt)
9164 9262 {
9165 9263 sata_device_t sdevice;
9166 9264 sata_pkt_t *rs_spkt;
9167 9265 sata_cmd_t *sata_cmd;
9168 9266 ddi_dma_handle_t buf_dma_handle;
9169 9267 ahci_addr_t addr;
9170 9268 int loop_count;
9171 9269 #if AHCI_DEBUG
9172 9270 struct scsi_extended_sense *rqsense;
9173 9271 #endif
9174 9272
9175 9273 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
9176 9274 "ahci_get_rqsense_data enter: port %d", port);
9177 9275
9178 9276 /* Prepare the sdevice data */
9179 9277 bzero((void *)&sdevice, sizeof (sata_device_t));
9180 9278 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
9181 9279
9182 9280 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
9183 9281 sdevice.satadev_addr.pmport = 0;
9184 9282
9185 9283 /* Translate sata_device.satadev_addr -> ahci_addr */
9186 9284 ahci_get_ahci_addr(ahci_ctlp, &sdevice, &addr);
9187 9285
9188 9286 sata_cmd = &spkt->satapkt_cmd;
9189 9287
9190 9288 /*
9191 9289 * Call the sata hba interface to get a rs spkt
9192 9290 */
9193 9291 loop_count = 0;
9194 9292 loop:
9195 9293 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip,
9196 9294 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI);
9197 9295 if (rs_spkt == NULL) {
9198 9296 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) {
9199 9297 /* Sleep for a while */
9200 9298 drv_usecwait(AHCI_10MS_USECS);
9201 9299 goto loop;
9202 9300
9203 9301 }
9204 9302 /* Timed out after 1s */
9205 9303 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9206 9304 "failed to get rs spkt for port %d", port);
9207 9305 return;
9208 9306 }
9209 9307
9210 9308 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH);
9211 9309
9212 9310 /*
9213 9311 * This flag is used to handle the specific error recovery when the
9214 9312 * REQUEST SENSE command gets a faiure (fatal error or time-out).
9215 9313 */
9216 9314 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE;
9217 9315
9218 9316 /*
9219 9317 * This start is not supposed to fail because after port is restarted,
9220 9318 * the whole command list is empty.
9221 9319 */
9222 9320 ahci_portp->ahciport_err_retri_pkt = rs_spkt;
9223 9321 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, &addr, rs_spkt);
9224 9322 ahci_portp->ahciport_err_retri_pkt = NULL;
9225 9323
9226 9324 /* Remove the flag after REQUEST SENSE command is completed */
9227 9325 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_RQSENSE;
9228 9326
9229 9327 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) {
9230 9328 /* Update the request sense data */
9231 9329 buf_dma_handle = *(ddi_dma_handle_t *)
9232 9330 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle);
9233 9331 (void) ddi_dma_sync(buf_dma_handle, 0, 0,
9234 9332 DDI_DMA_SYNC_FORKERNEL);
9235 9333 /* Copy the request sense data */
9236 9334 bcopy(rs_spkt->
9237 9335 satapkt_cmd.satacmd_bp->b_un.b_addr,
9238 9336 &sata_cmd->satacmd_rqsense,
9239 9337 SATA_ATAPI_MIN_RQSENSE_LEN);
9240 9338 #if AHCI_DEBUG
9241 9339 rqsense = (struct scsi_extended_sense *)
9242 9340 sata_cmd->satacmd_rqsense;
9243 9341
9244 9342 /* Dump the sense data */
9245 9343 AHCIDBG(AHCIDBG_SENSEDATA, ahci_ctlp, "\n", NULL);
9246 9344 AHCIDBG(AHCIDBG_SENSEDATA, ahci_ctlp,
9247 9345 "Sense data for satapkt %p ATAPI cmd 0x%x",
9248 9346 spkt, sata_cmd->satacmd_acdb[0]);
9249 9347 AHCIDBG(AHCIDBG_SENSEDATA, ahci_ctlp,
9250 9348 " es_code 0x%x es_class 0x%x "
9251 9349 "es_key 0x%x es_add_code 0x%x "
9252 9350 "es_qual_code 0x%x",
9253 9351 rqsense->es_code, rqsense->es_class,
9254 9352 rqsense->es_key, rqsense->es_add_code,
9255 9353 rqsense->es_qual_code);
9256 9354 #endif
9257 9355 }
9258 9356
9259 9357 sata_free_error_retrieval_pkt(rs_spkt);
9260 9358 }
9261 9359
9262 9360 /*
9263 9361 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover,
9264 9362 * the port must be restarted. When the HBA detects thus error, it may try
9265 9363 * to abort a transfer. And if the transfer was aborted, the device is
9266 9364 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both
9267 9365 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows
9268 9366 * that the device is in a stable status and transfers may be restarted without
9269 9367 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set,
9270 9368 * then the software will send the COMRESET to do the port reset.
9271 9369 *
9272 9370 * Software should perform the appropriate error recovery actions based on
9273 9371 * whether non-queued commands were being issued or natived command queuing
9274 9372 * commands were being issued.
9275 9373 *
9276 9374 * And software will complete the command that had the error with error mark
9277 9375 * to higher level software.
9278 9376 *
9279 9377 * Fatal errors include the following:
9280 9378 * PxIS.IFS - Interface Fatal Error Status
9281 9379 * PxIS.HBDS - Host Bus Data Error Status
9282 9380 * PxIS.HBFS - Host Bus Fatal Error Status
9283 9381 * PxIS.TFES - Task File Error Status
9284 9382 */
9285 9383 static void
9286 9384 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp,
9287 9385 ahci_port_t *ahci_portp, ahci_addr_t *addrp, uint32_t intr_status)
9288 9386 {
9289 9387 uint32_t port_cmd_status;
9290 9388 uint32_t slot_status = 0;
9291 9389 uint32_t failed_tags = 0;
9292 9390 int failed_slot;
9293 9391 int reset_flag = 0, flag = 0;
9294 9392 ahci_fis_d2h_register_t *ahci_rcvd_fisp;
9295 9393 sata_cmd_t *sata_cmd = NULL;
9296 9394 sata_pkt_t *spkt = NULL;
9297 9395 #if AHCI_DEBUG
9298 9396 ahci_cmd_header_t *cmd_header;
9299 9397 #endif
9300 9398 uint8_t port = addrp->aa_port;
9301 9399 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9302 9400 int rval;
9303 9401
9304 9402 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
9305 9403
9306 9404 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
9307 9405 "ahci_fatal_error_recovery_handler enter: port %d", port);
9308 9406
9309 9407 /* Port multiplier error */
9310 9408 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) {
9311 9409 /* FBS code is neither completed nor tested. */
9312 9410 ahci_pmult_error_recovery_handler(ahci_ctlp, ahci_portp,
9313 9411 port, intr_status);
9314 9412
9315 9413 /* Force a port reset */
9316 9414 flag = AHCI_PORT_RESET;
9317 9415 }
9318 9416
9319 9417 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) ||
9320 9418 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9321 9419
9322 9420 /* Read PxCI to see which commands are still outstanding */
9323 9421 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9324 9422 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
9325 9423
9326 9424 /*
9327 9425 * Read PxCMD.CCS to determine the slot that the HBA
9328 9426 * was processing when the error occurred.
9329 9427 */
9330 9428 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9331 9429 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
9332 9430 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
9333 9431 AHCI_CMD_STATUS_CCS_SHIFT;
9334 9432
9335 9433 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9336 9434 spkt = ahci_portp->ahciport_err_retri_pkt;
9337 9435 ASSERT(spkt != NULL);
9338 9436 } else {
9339 9437 spkt = ahci_portp->ahciport_slot_pkts[failed_slot];
9340 9438 if (spkt == NULL) {
9341 9439 /* May happen when interface errors occur? */
9342 9440 goto next;
9343 9441 }
9344 9442 }
9345 9443
9346 9444 #if AHCI_DEBUG
9347 9445 /*
9348 9446 * Debugging purpose...
9349 9447 */
9350 9448 if (ahci_portp->ahciport_prd_bytecounts[failed_slot]) {
9351 9449 cmd_header =
9352 9450 &ahci_portp->ahciport_cmd_list[failed_slot];
9353 9451 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
9354 9452 "ahci_fatal_error_recovery_handler: port %d, "
9355 9453 "PRD Byte Count = 0x%x, "
9356 9454 "ahciport_prd_bytecounts = 0x%x", port,
9357 9455 cmd_header->ahcich_prd_byte_count,
9358 9456 ahci_portp->ahciport_prd_bytecounts[failed_slot]);
9359 9457 }
9360 9458 #endif
9361 9459
9362 9460 sata_cmd = &spkt->satapkt_cmd;
9363 9461
9364 9462 /* Fill out the status and error registers for PxIS.TFES */
9365 9463 if (intr_status & AHCI_INTR_STATUS_TFES) {
9366 9464 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->
9367 9465 ahcirf_d2h_register_fis);
9368 9466
9369 9467 /* Copy the error context back to the sata_cmd */
9370 9468 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp);
9371 9469 }
9372 9470
9373 9471 /* The failed command must be one of the outstanding commands */
9374 9472 failed_tags = 0x1 << failed_slot;
9375 9473 ASSERT(failed_tags & slot_status);
9376 9474
9377 9475 /* Update the sata registers, especially PxSERR register */
9378 9476 ahci_update_sata_registers(ahci_ctlp, port,
9379 9477 &spkt->satapkt_device);
9380 9478
9381 9479 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9382 9480 /* Read PxSACT to see which commands are still outstanding */
9383 9481 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9384 9482 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
9385 9483 }
9386 9484 next:
9387 9485
9388 9486 #if AHCI_DEBUG
9389 9487 /*
9390 9488 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is
9391 9489 * set, it means a fatal error happened after REQUEST SENSE command
9392 9490 * or READ LOG EXT command is delivered to the HBA during the error
9393 9491 * recovery process. At this time, the only outstanding command is
9394 9492 * supposed to be REQUEST SENSE command or READ LOG EXT command.
9395 9493 */
9396 9494 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9397 9495 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9398 9496 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE "
9399 9497 "command or READ LOG EXT command for error data retrieval "
9400 9498 "failed", port);
9401 9499 ASSERT(slot_status == 0x1);
9402 9500 ASSERT(failed_slot == 0);
9403 9501 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] ==
9404 9502 SCMD_REQUEST_SENSE ||
9405 9503 spkt->satapkt_cmd.satacmd_cmd_reg ==
9406 9504 SATAC_READ_LOG_EXT);
9407 9505 }
9408 9506 #endif
9409 9507
9410 9508 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
9411 9509 ahci_portp->ahciport_mop_in_progress++;
9412 9510
9413 9511 rval = ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp,
9414 9512 port, flag, &reset_flag);
9415 9513
9416 9514 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_ERRPRINT) {
9417 9515 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_ERRPRINT;
9418 9516 if (rval == AHCI_SUCCESS)
9419 9517 cmn_err(CE_WARN, "!ahci%d: error recovery for port %d "
9420 9518 "succeed", instance, port);
9421 9519 else
9422 9520 cmn_err(CE_WARN, "!ahci%d: error recovery for port %d "
9423 9521 "failed", instance, port);
9424 9522 }
9425 9523
9426 9524 /*
9427 9525 * Won't retrieve error information:
9428 9526 * 1. Port reset was involved to recover
9429 9527 * 2. Device is gone
9430 9528 * 3. IDENTIFY DEVICE command sent to ATAPI device
9431 9529 * 4. REQUEST SENSE or READ LOG EXT command during error recovery
9432 9530 */
9433 9531 if (reset_flag ||
9434 9532 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE ||
9435 9533 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE ||
9436 9534 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
9437 9535 goto out;
9438 9536
9439 9537 /*
9440 9538 * Deliver READ LOG EXT to gather information about the error when
9441 9539 * a COMRESET has not been performed as part of the error recovery
9442 9540 * during NCQ command processing.
9443 9541 */
9444 9542 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9445 9543 failed_tags = ahci_get_rdlogext_data(ahci_ctlp,
9446 9544 ahci_portp, port);
9447 9545 goto out;
9448 9546 }
9449 9547
9450 9548 /*
9451 9549 * Deliver REQUEST SENSE for ATAPI command to gather information about
9452 9550 * the error when a COMRESET has not been performed as part of the
9453 9551 * error recovery.
9454 9552 */
9455 9553 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPI)
9456 9554 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt);
9457 9555 out:
9458 9556 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9459 9557 "ahci_fatal_error_recovery_handler: port %d fatal error "
9460 9558 "occurred slot_status = 0x%x, pending_tags = 0x%x, "
9461 9559 "pending_ncq_tags = 0x%x failed_tags = 0x%x",
9462 9560 port, slot_status, ahci_portp->ahciport_pending_tags,
9463 9561 ahci_portp->ahciport_pending_ncq_tags, failed_tags);
9464 9562
9465 9563 ahci_mop_commands(ahci_ctlp,
|
↓ open down ↓ |
1051 lines elided |
↑ open up ↑ |
9466 9564 ahci_portp,
9467 9565 slot_status,
9468 9566 failed_tags, /* failed tags */
9469 9567 0, /* timeout tags */
9470 9568 0, /* aborted tags */
9471 9569 0); /* reset tags */
9472 9570 }
9473 9571
9474 9572 /*
9475 9573 * Used to recovery a PMULT pmport fatal error under FIS-based switching.
9476 - * 1. device specific.PxFBS.SDE=1
9477 - * 2. Non-Deivce specific.
9574 + * 1. device specific.PxFBS.SDE=1
9575 + * 2. Non Device specific.
9478 9576 * Nothing will be done when Command-based switching is employed.
9479 9577 *
9480 9578 * Currently code is neither completed nor tested.
9481 9579 */
9482 9580 static void
9483 9581 ahci_pmult_error_recovery_handler(ahci_ctl_t *ahci_ctlp,
9484 9582 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status)
9485 9583 {
9486 9584 #ifndef __lock_lint
9487 9585 _NOTE(ARGUNUSED(intr_status))
9488 9586 #endif
9489 9587 uint32_t port_fbs_ctrl;
9490 9588 int loop_count = 0;
9491 9589 ahci_addr_t addr;
9492 9590
9493 9591 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
9494 9592
9495 9593 /* Nothing will be done under Command-based switching. */
9496 9594 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_FBSS))
9497 9595 return;
9498 9596
9499 9597 port_fbs_ctrl = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9500 9598 (uint32_t *)AHCI_PORT_PxFBS(ahci_ctlp, port));
9501 9599
9502 9600 if (!(port_fbs_ctrl & AHCI_FBS_EN))
9503 9601 /* FBS is not enabled. */
9504 9602 return;
9505 9603
9506 9604 /* Problem's getting complicated now. */
9507 9605 /*
9508 9606 * If FIS-based switching is used, we need to check
9509 9607 * the PxFBS to see the error type.
9510 9608 */
9511 9609 port_fbs_ctrl = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9512 9610 (uint32_t *)AHCI_PORT_PxFBS(ahci_ctlp, port));
9513 9611
9514 9612 /* Refer to spec(v1.2) 9.3.6.1 */
9515 9613 if (port_fbs_ctrl & AHCI_FBS_SDE) {
9516 9614 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9517 9615 "A Device Sepcific Error: port %d", port);
9518 9616 /*
9519 9617 * Controller has paused commands for all other
9520 9618 * sub-devices until PxFBS.DEC is set.
9521 9619 */
9522 9620 ahci_reject_all_abort_pkts(ahci_ctlp,
9523 9621 ahci_portp, 0);
9524 9622
9525 9623 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
9526 9624 (uint32_t *)AHCI_PORT_PxFBS(ahci_ctlp, port),
9527 9625 port_fbs_ctrl | AHCI_FBS_DEC);
9528 9626
9529 9627 /*
9530 9628 * Wait controller clear PxFBS.DEC,
9531 9629 * then we can continue.
9532 9630 */
9533 9631 loop_count = 0;
9534 9632 do {
9535 9633 port_fbs_ctrl = ddi_get32(ahci_ctlp->
9536 9634 ahcictl_ahci_acc_handle, (uint32_t *)
9537 9635 AHCI_PORT_PxFBS(ahci_ctlp, port));
9538 9636
9539 9637 if (loop_count++ > 1000)
9540 9638 /*
9541 9639 * Esclate the error. Follow
9542 9640 * non-device specific error
9543 9641 * procedure.
9544 9642 */
9545 9643 return;
9546 9644
9547 9645 drv_usecwait(AHCI_100US_USECS);
9548 9646 } while (port_fbs_ctrl & AHCI_FBS_DEC);
9549 9647
9550 9648 /*
9551 9649 * Issue a software reset to ensure drive is in
9552 9650 * a known state.
9553 9651 */
9554 9652 (void) ahci_software_reset(ahci_ctlp,
9555 9653 ahci_portp, &addr);
9556 9654
9557 9655 } else {
9558 9656
9559 9657 /* Process Non-Device Specific Error. */
9560 9658 /* This will be handled later on. */
9561 9659 cmn_err(CE_NOTE, "!FBS is not supported now.");
9562 9660 }
9563 9661 }
9564 9662 /*
9565 9663 * Handle events - fatal error recovery
9566 9664 */
9567 9665 static void
9568 9666 ahci_events_handler(void *args)
9569 9667 {
9570 9668 ahci_event_arg_t *ahci_event_arg;
9571 9669 ahci_ctl_t *ahci_ctlp;
9572 9670 ahci_port_t *ahci_portp;
9573 9671 ahci_addr_t *addrp;
9574 9672 uint32_t event;
9575 9673 int instance;
9576 9674
9577 9675 ahci_event_arg = (ahci_event_arg_t *)args;
9578 9676
9579 9677 ahci_ctlp = ahci_event_arg->ahciea_ctlp;
9580 9678 ahci_portp = ahci_event_arg->ahciea_portp;
9581 9679 addrp = ahci_event_arg->ahciea_addrp;
9582 9680 event = ahci_event_arg->ahciea_event;
9583 9681 instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9584 9682
9585 9683 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
9586 9684 "ahci_events_handler enter: port %d intr_status = 0x%x",
9587 9685 ahci_portp->ahciport_port_num, event);
9588 9686
9589 9687 mutex_enter(&ahci_portp->ahciport_mutex);
9590 9688
9591 9689 /*
9592 9690 * ahci_intr_phyrdy_change() may have rendered it to
9593 9691 * SATA_DTYPE_NONE.
9594 9692 */
9595 9693 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
9596 9694 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
9597 9695 "ahci_events_handler: port %d no device attached, "
9598 9696 "and just return without doing anything",
9599 9697 ahci_portp->ahciport_port_num);
9600 9698
9601 9699 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_ERRPRINT) {
9602 9700 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_ERRPRINT;
9603 9701 cmn_err(CE_WARN, "!ahci%d: error recovery for port %d "
9604 9702 "succeed", instance, ahci_portp->ahciport_port_num);
9605 9703 }
9606 9704
9607 9705 goto out;
9608 9706 }
9609 9707
9610 9708 if (event & (AHCI_INTR_STATUS_IFS |
9611 9709 AHCI_INTR_STATUS_HBDS |
9612 9710 AHCI_INTR_STATUS_HBFS |
9613 9711 AHCI_INTR_STATUS_TFES))
9614 9712 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp,
9615 9713 addrp, event);
9616 9714
9617 9715 out:
9618 9716 mutex_exit(&ahci_portp->ahciport_mutex);
9619 9717 }
9620 9718
9621 9719 /*
9622 9720 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they
9623 9721 * detect there are some commands which are timed out.
9624 9722 */
9625 9723 static void
9626 9724 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
9627 9725 uint8_t port, uint32_t tmp_timeout_tags)
9628 9726 {
9629 9727 uint32_t slot_status = 0;
9630 9728 uint32_t finished_tags = 0;
9631 9729 uint32_t timeout_tags = 0;
9632 9730
9633 9731 AHCIDBG(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp,
9634 9732 "ahci_timeout_pkts enter: port %d", port);
9635 9733
9636 9734 mutex_enter(&ahci_portp->ahciport_mutex);
9637 9735
9638 9736 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) ||
9639 9737 RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) ||
9640 9738 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9641 9739 /* Read PxCI to see which commands are still outstanding */
9642 9740 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9643 9741 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
9644 9742 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9645 9743 /* Read PxSACT to see which commands are still outstanding */
9646 9744 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9647 9745 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
9648 9746 }
9649 9747
9650 9748 #if AHCI_DEBUG
9651 9749 /*
9652 9750 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is
9653 9751 * set, it means a fatal error happened after REQUEST SENSE command
9654 9752 * or READ LOG EXT command is delivered to the HBA during the error
9655 9753 * recovery process. At this time, the only outstanding command is
9656 9754 * supposed to be REQUEST SENSE command or READ LOG EXT command.
9657 9755 */
9658 9756 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9659 9757 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp,
9660 9758 "ahci_timeout_pkts called while REQUEST SENSE "
9661 9759 "command or READ LOG EXT command for error recovery "
9662 9760 "timed out timeout_tags = 0x%x, slot_status = 0x%x, "
9663 9761 "pending_tags = 0x%x, pending_ncq_tags = 0x%x",
9664 9762 tmp_timeout_tags, slot_status,
9665 9763 ahci_portp->ahciport_pending_tags,
9666 9764 ahci_portp->ahciport_pending_ncq_tags);
9667 9765 ASSERT(slot_status == 0x1);
9668 9766 } else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
9669 9767 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp,
9670 9768 "ahci_timeout_pkts called while executing R/W PMULT "
9671 9769 "command timeout_tags = 0x%x, slot_status = 0x%x",
9672 9770 tmp_timeout_tags, slot_status);
9673 9771 ASSERT(slot_status == 0x1);
9674 9772 }
9675 9773 #endif
9676 9774
9677 9775 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
9678 9776 ahci_portp->ahciport_mop_in_progress++;
9679 9777
9680 9778 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp,
9681 9779 port, AHCI_PORT_RESET, NULL);
9682 9780
9683 9781 /*
9684 9782 * Re-identify timeout tags because some previously checked commands
9685 9783 * could already complete.
9686 9784 */
9687 9785 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9688 9786 finished_tags = ahci_portp->ahciport_pending_tags &
9689 9787 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
9690 9788 timeout_tags = tmp_timeout_tags & ~finished_tags;
9691 9789
9692 9790 AHCIDBG(AHCIDBG_TIMEOUT, ahci_ctlp,
9693 9791 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, "
9694 9792 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, "
9695 9793 "pending_tags = 0x%x ",
9696 9794 port, finished_tags, timeout_tags,
9697 9795 slot_status, ahci_portp->ahciport_pending_tags);
9698 9796 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9699 9797 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
9700 9798 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
9701 9799 timeout_tags = tmp_timeout_tags & ~finished_tags;
9702 9800
9703 9801 AHCIDBG(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp,
9704 9802 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, "
9705 9803 "timeout_tags = 0x%x, port_sactive = 0x%x, "
9706 9804 "pending_ncq_tags = 0x%x ",
9707 9805 port, finished_tags, timeout_tags,
9708 9806 slot_status, ahci_portp->ahciport_pending_ncq_tags);
9709 9807 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) ||
9710 9808 RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
9711 9809 timeout_tags = tmp_timeout_tags;
9712 9810 }
9713 9811
9714 9812 ahci_mop_commands(ahci_ctlp,
9715 9813 ahci_portp,
9716 9814 slot_status,
9717 9815 0, /* failed tags */
9718 9816 timeout_tags, /* timeout tags */
9719 9817 0, /* aborted tags */
9720 9818 0); /* reset tags */
9721 9819
9722 9820 mutex_exit(&ahci_portp->ahciport_mutex);
9723 9821 }
9724 9822
9725 9823 /*
9726 9824 * Watchdog handler kicks in every 5 seconds to timeout any commands pending
9727 9825 * for long time.
9728 9826 */
9729 9827 static void
9730 9828 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp)
9731 9829 {
9732 9830 ahci_port_t *ahci_portp;
9733 9831 sata_pkt_t *spkt;
9734 9832 uint32_t pending_tags;
9735 9833 uint32_t timeout_tags;
9736 9834 uint32_t port_cmd_status;
9737 9835 uint32_t port_sactive;
9738 9836 uint8_t port;
9739 9837 int tmp_slot;
9740 9838 int current_slot;
9741 9839 uint32_t current_tags;
9742 9840 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9743 9841
9744 9842 mutex_enter(&ahci_ctlp->ahcictl_mutex);
9745 9843
9746 9844 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
9747 9845 "ahci_watchdog_handler entered", NULL);
9748 9846
9749 9847 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
9750 9848 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
9751 9849 continue;
9752 9850 }
9753 9851
9754 9852 ahci_portp = ahci_ctlp->ahcictl_ports[port];
9755 9853
9756 9854 mutex_enter(&ahci_portp->ahciport_mutex);
9757 9855 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
9758 9856 mutex_exit(&ahci_portp->ahciport_mutex);
9759 9857 continue;
9760 9858 }
9761 9859
9762 9860 /* Skip the check for those ports in error recovery */
9763 9861 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) &&
9764 9862 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) {
9765 9863 mutex_exit(&ahci_portp->ahciport_mutex);
9766 9864 continue;
9767 9865 }
9768 9866
9769 9867 pending_tags = 0;
9770 9868 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9771 9869 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
9772 9870
9773 9871 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) ||
9774 9872 RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
9775 9873 current_slot = 0;
9776 9874 pending_tags = 0x1;
9777 9875 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9778 9876 current_slot =
9779 9877 (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
9780 9878 AHCI_CMD_STATUS_CCS_SHIFT;
9781 9879 pending_tags = ahci_portp->ahciport_pending_tags;
9782 9880 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9783 9881 port_sactive = ddi_get32(
9784 9882 ahci_ctlp->ahcictl_ahci_acc_handle,
9785 9883 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
9786 9884 current_tags = port_sactive &
9787 9885 ~port_cmd_status &
9788 9886 AHCI_NCQ_SLOT_MASK(ahci_portp);
9789 9887 pending_tags = ahci_portp->ahciport_pending_ncq_tags;
9790 9888 }
9791 9889
9792 9890 timeout_tags = 0;
9793 9891 while (pending_tags) {
9794 9892 tmp_slot = ddi_ffs(pending_tags) - 1;
9795 9893 if (tmp_slot == -1) {
9796 9894 break;
9797 9895 }
9798 9896
9799 9897 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
9800 9898 spkt = ahci_portp->ahciport_err_retri_pkt;
9801 9899 else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp))
9802 9900 spkt = ahci_portp->ahciport_rdwr_pmult_pkt;
9803 9901 else
9804 9902 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
9805 9903
9806 9904 if ((spkt != NULL) && spkt->satapkt_time &&
9807 9905 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) {
9808 9906 /*
9809 9907 * If a packet has survived for more than it's
9810 9908 * max life cycles, it is a candidate for time
9811 9909 * out.
9812 9910 */
9813 9911 ahci_portp->ahciport_slot_timeout[tmp_slot] -=
9814 9912 ahci_watchdog_timeout;
9815 9913
9816 9914 if (ahci_portp->ahciport_slot_timeout[tmp_slot]
9817 9915 > 0)
9818 9916 goto next;
9819 9917
9820 9918 #if AHCI_DEBUG
9821 9919 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9822 9920 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT,
9823 9921 ahci_ctlp, "watchdog: the current "
9824 9922 "tags is 0x%x", current_tags);
9825 9923 } else {
9826 9924 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT,
9827 9925 ahci_ctlp, "watchdog: the current "
9828 9926 "slot is %d", current_slot);
9829 9927 }
9830 9928 #endif
9831 9929
9832 9930 /*
9833 9931 * We need to check whether the HBA has
9834 9932 * begun to execute the command, if not,
9835 9933 * then re-set the timer of the command.
9836 9934 */
9837 9935 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) &&
9838 9936 (tmp_slot != current_slot) ||
9839 9937 NCQ_CMD_IN_PROGRESS(ahci_portp) &&
9840 9938 ((0x1 << tmp_slot) & current_tags)) {
9841 9939 ahci_portp->ahciport_slot_timeout \
9842 9940 [tmp_slot] = spkt->satapkt_time;
9843 9941 } else {
9844 9942 timeout_tags |= (0x1 << tmp_slot);
9845 9943 cmn_err(CE_WARN, "!ahci%d: watchdog "
9846 9944 "port %d satapkt 0x%p timed out\n",
9847 9945 instance, port, (void *)spkt);
9848 9946 }
9849 9947 }
9850 9948 next:
9851 9949 CLEAR_BIT(pending_tags, tmp_slot);
9852 9950 }
9853 9951
9854 9952 if (timeout_tags) {
9855 9953 mutex_exit(&ahci_portp->ahciport_mutex);
9856 9954 mutex_exit(&ahci_ctlp->ahcictl_mutex);
9857 9955 ahci_timeout_pkts(ahci_ctlp, ahci_portp,
9858 9956 port, timeout_tags);
9859 9957 mutex_enter(&ahci_ctlp->ahcictl_mutex);
9860 9958 mutex_enter(&ahci_portp->ahciport_mutex);
9861 9959 }
9862 9960
9863 9961 mutex_exit(&ahci_portp->ahciport_mutex);
9864 9962 }
9865 9963
9866 9964 /* Re-install the watchdog timeout handler */
9867 9965 if (ahci_ctlp->ahcictl_timeout_id != 0) {
9868 9966 ahci_ctlp->ahcictl_timeout_id =
9869 9967 timeout((void (*)(void *))ahci_watchdog_handler,
9870 9968 (caddr_t)ahci_ctlp, ahci_watchdog_tick);
9871 9969 }
9872 9970
9873 9971 mutex_exit(&ahci_ctlp->ahcictl_mutex);
9874 9972 }
9875 9973
9876 9974 /*
9877 9975 * Fill the error context into sata_cmd for non-queued command error.
9878 9976 */
9879 9977 static void
9880 9978 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp)
9881 9979 {
9882 9980 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp);
9883 9981 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp);
9884 9982 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp);
9885 9983 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp);
9886 9984 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp);
9887 9985 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp);
9888 9986 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp);
9889 9987
9890 9988 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) {
9891 9989 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp);
9892 9990 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp);
9893 9991 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp);
9894 9992 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp);
9895 9993 }
9896 9994 }
9897 9995
9898 9996 /*
9899 9997 * Fill the ncq error page into sata_cmd for queued command error.
9900 9998 */
9901 9999 static void
9902 10000 ahci_copy_ncq_err_page(sata_cmd_t *scmd,
9903 10001 struct sata_ncq_error_recovery_page *ncq_err_page)
9904 10002 {
9905 10003 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext;
9906 10004 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count;
9907 10005 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext;
9908 10006 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number;
9909 10007 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext;
9910 10008 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low;
9911 10009 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext;
9912 10010 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high;
9913 10011 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head;
9914 10012 scmd->satacmd_status_reg = ncq_err_page->ncq_status;
9915 10013 scmd->satacmd_error_reg = ncq_err_page->ncq_error;
9916 10014 }
9917 10015
9918 10016 /*
9919 10017 * Put the respective register value to sata_cmd_t for satacmd_flags.
9920 10018 */
9921 10019 static void
9922 10020 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp)
9923 10021 {
9924 10022 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb)
9925 10023 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp);
9926 10024 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb)
9927 10025 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp);
9928 10026 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb)
9929 10027 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp);
9930 10028 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb)
9931 10029 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp);
9932 10030 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb)
9933 10031 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp);
9934 10032 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb)
9935 10033 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp);
9936 10034 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb)
9937 10035 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp);
9938 10036 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb)
9939 10037 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp);
9940 10038 if (scmd->satacmd_flags.sata_copy_out_device_reg)
9941 10039 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp);
9942 10040 if (scmd->satacmd_flags.sata_copy_out_error_reg)
9943 10041 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp);
9944 10042 }
9945 10043
9946 10044 static void
9947 10045 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port,
9948 10046 uint32_t intr_status)
9949 10047 {
9950 10048 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9951 10049
9952 10050 if (intr_status & AHCI_INTR_STATUS_IFS)
9953 10051 cmn_err(CE_WARN, "!ahci%d: ahci port %d has interface fatal "
9954 10052 "error", instance, port);
9955 10053
9956 10054 if (intr_status & AHCI_INTR_STATUS_HBDS)
9957 10055 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus data error",
9958 10056 instance, port);
9959 10057
9960 10058 if (intr_status & AHCI_INTR_STATUS_HBFS)
9961 10059 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus fatal error",
9962 10060 instance, port);
9963 10061
9964 10062 if (intr_status & AHCI_INTR_STATUS_TFES)
9965 10063 cmn_err(CE_WARN, "!ahci%d: ahci port %d has task file error",
9966 10064 instance, port);
9967 10065
9968 10066 cmn_err(CE_WARN, "!ahci%d: ahci port %d is trying to do error "
9969 10067 "recovery", instance, port);
9970 10068 }
9971 10069
9972 10070 static void
9973 10071 ahci_dump_commands(ahci_ctl_t *ahci_ctlp, uint8_t port,
9974 10072 uint32_t slot_tags)
9975 10073 {
9976 10074 ahci_port_t *ahci_portp;
9977 10075 int tmp_slot;
9978 10076 sata_pkt_t *spkt;
9979 10077 sata_cmd_t cmd;
9980 10078
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9981 10079 ahci_portp = ahci_ctlp->ahcictl_ports[port];
9982 10080 ASSERT(ahci_portp != NULL);
9983 10081
9984 10082 while (slot_tags) {
9985 10083 tmp_slot = ddi_ffs(slot_tags) - 1;
9986 10084 if (tmp_slot == -1) {
9987 10085 break;
9988 10086 }
9989 10087
9990 10088 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
9991 - ASSERT(spkt != NULL);
9992 - cmd = spkt->satapkt_cmd;
10089 + if (spkt != NULL) {
10090 + cmd = spkt->satapkt_cmd;
9993 10091
9994 - cmn_err(CE_WARN, "!satapkt 0x%p: cmd_reg = 0x%x "
9995 - "features_reg = 0x%x sec_count_msb = 0x%x "
9996 - "lba_low_msb = 0x%x lba_mid_msb = 0x%x "
9997 - "lba_high_msb = 0x%x sec_count_lsb = 0x%x "
9998 - "lba_low_lsb = 0x%x lba_mid_lsb = 0x%x "
9999 - "lba_high_lsb = 0x%x device_reg = 0x%x "
10000 - "addr_type = 0x%x cmd_flags = 0x%x", (void *)spkt,
10001 - cmd.satacmd_cmd_reg, cmd.satacmd_features_reg,
10002 - cmd.satacmd_sec_count_msb, cmd.satacmd_lba_low_msb,
10003 - cmd.satacmd_lba_mid_msb, cmd.satacmd_lba_high_msb,
10004 - cmd.satacmd_sec_count_lsb, cmd.satacmd_lba_low_lsb,
10005 - cmd.satacmd_lba_mid_lsb, cmd.satacmd_lba_high_lsb,
10006 - cmd.satacmd_device_reg, cmd.satacmd_addr_type,
10007 - *((uint32_t *)&(cmd.satacmd_flags)));
10092 + cmn_err(CE_WARN, "!satapkt 0x%p: cmd_reg = 0x%x "
10093 + "features_reg = 0x%x sec_count_msb = 0x%x "
10094 + "lba_low_msb = 0x%x lba_mid_msb = 0x%x "
10095 + "lba_high_msb = 0x%x sec_count_lsb = 0x%x "
10096 + "lba_low_lsb = 0x%x lba_mid_lsb = 0x%x "
10097 + "lba_high_lsb = 0x%x device_reg = 0x%x "
10098 + "addr_type = 0x%x cmd_flags = 0x%x", (void *)spkt,
10099 + cmd.satacmd_cmd_reg, cmd.satacmd_features_reg,
10100 + cmd.satacmd_sec_count_msb, cmd.satacmd_lba_low_msb,
10101 + cmd.satacmd_lba_mid_msb, cmd.satacmd_lba_high_msb,
10102 + cmd.satacmd_sec_count_lsb, cmd.satacmd_lba_low_lsb,
10103 + cmd.satacmd_lba_mid_lsb, cmd.satacmd_lba_high_lsb,
10104 + cmd.satacmd_device_reg, cmd.satacmd_addr_type,
10105 + *((uint32_t *)&(cmd.satacmd_flags)));
10106 + }
10008 10107
10009 10108 CLEAR_BIT(slot_tags, tmp_slot);
10010 10109 }
10011 10110 }
10012 10111
10013 10112 /*
10014 10113 * Dump the serror message to the log.
10015 10114 */
10016 10115 static void
10017 10116 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port,
10018 10117 uint32_t port_serror, int debug_only)
10019 10118 {
10020 10119 static char err_buf[512];
10021 10120 static char err_msg_header[16];
10022 10121 char *err_msg = err_buf;
10023 10122
10024 10123 *err_buf = '\0';
10025 10124 *err_msg_header = '\0';
10026 10125
10027 10126 if (port_serror & SERROR_DATA_ERR_FIXED) {
10028 10127 err_msg = strcat(err_msg,
10029 10128 "\tRecovered Data Integrity Error (I)\n");
10030 10129 }
10031 10130
10032 10131 if (port_serror & SERROR_COMM_ERR_FIXED) {
10033 10132 err_msg = strcat(err_msg,
10034 10133 "\tRecovered Communication Error (M)\n");
10035 10134 }
10036 10135
10037 10136 if (port_serror & SERROR_DATA_ERR) {
10038 10137 err_msg = strcat(err_msg,
10039 10138 "\tTransient Data Integrity Error (T)\n");
10040 10139 }
10041 10140
10042 10141 if (port_serror & SERROR_PERSISTENT_ERR) {
10043 10142 err_msg = strcat(err_msg,
10044 10143 "\tPersistent Communication or Data Integrity Error (C)\n");
10045 10144 }
10046 10145
10047 10146 if (port_serror & SERROR_PROTOCOL_ERR) {
10048 10147 err_msg = strcat(err_msg, "\tProtocol Error (P)\n");
10049 10148 }
10050 10149
10051 10150 if (port_serror & SERROR_INT_ERR) {
10052 10151 err_msg = strcat(err_msg, "\tInternal Error (E)\n");
10053 10152 }
10054 10153
10055 10154 if (port_serror & SERROR_PHY_RDY_CHG) {
10056 10155 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n");
10057 10156 }
10058 10157
10059 10158 if (port_serror & SERROR_PHY_INT_ERR) {
10060 10159 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n");
10061 10160 }
10062 10161
10063 10162 if (port_serror & SERROR_COMM_WAKE) {
10064 10163 err_msg = strcat(err_msg, "\tComm Wake (W)\n");
10065 10164 }
10066 10165
10067 10166 if (port_serror & SERROR_10B_TO_8B_ERR) {
10068 10167 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n");
10069 10168 }
10070 10169
10071 10170 if (port_serror & SERROR_DISPARITY_ERR) {
10072 10171 err_msg = strcat(err_msg, "\tDisparity Error (D)\n");
10073 10172 }
10074 10173
10075 10174 if (port_serror & SERROR_CRC_ERR) {
10076 10175 err_msg = strcat(err_msg, "\tCRC Error (C)\n");
10077 10176 }
10078 10177
10079 10178 if (port_serror & SERROR_HANDSHAKE_ERR) {
10080 10179 err_msg = strcat(err_msg, "\tHandshake Error (H)\n");
10081 10180 }
10082 10181
10083 10182 if (port_serror & SERROR_LINK_SEQ_ERR) {
10084 10183 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n");
10085 10184 }
10086 10185
10087 10186 if (port_serror & SERROR_TRANS_ERR) {
10088 10187 err_msg = strcat(err_msg,
10089 10188 "\tTransport state transition error (T)\n");
10090 10189 }
10091 10190
10092 10191 if (port_serror & SERROR_FIS_TYPE) {
10093 10192 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n");
10094 10193 }
10095 10194
10096 10195 if (port_serror & SERROR_EXCHANGED_ERR) {
10097 10196 err_msg = strcat(err_msg, "\tExchanged (X)\n");
10098 10197 }
10099 10198
10100 10199 if (*err_msg == '\0')
10101 10200 return;
10102 10201
10103 10202 if (debug_only) {
10104 10203 (void) sprintf(err_msg_header, "port %d", port);
10105 10204 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, err_msg_header, NULL);
10106 10205 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, err_msg, NULL);
10107 10206 } else if (ahci_ctlp) {
10108 10207 cmn_err(CE_WARN, "!ahci%d: %s %s",
10109 10208 ddi_get_instance(ahci_ctlp->ahcictl_dip),
10110 10209 err_msg_header, err_msg);
10111 10210
10112 10211 /* sata trace debug */
10113 10212 sata_trace_debug(ahci_ctlp->ahcictl_dip,
10114 10213 "ahci%d: %s %s", ddi_get_instance(ahci_ctlp->ahcictl_dip),
10115 10214 err_msg_header, err_msg);
10116 10215 } else {
10117 10216 cmn_err(CE_WARN, "!ahci: %s %s", err_msg_header, err_msg);
10118 10217
10119 10218 /* sata trace debug */
10120 10219 sata_trace_debug(NULL, "ahci: %s %s", err_msg_header, err_msg);
10121 10220 }
10122 10221 }
10123 10222
10124 10223 /*
10125 10224 * Translate the sata_address_t type into the ahci_addr_t type.
10126 10225 * sata_device.satadev_addr structure is used as source.
10127 10226 */
10128 10227 static void
10129 10228 ahci_get_ahci_addr(ahci_ctl_t *ahci_ctlp, sata_device_t *sd,
10130 10229 ahci_addr_t *ahci_addrp)
10131 10230 {
10132 10231 sata_address_t *sata_addrp = &sd->satadev_addr;
10133 10232 ahci_addrp->aa_port =
10134 10233 ahci_ctlp->ahcictl_cport_to_port[sata_addrp->cport];
10135 10234 ahci_addrp->aa_pmport = sata_addrp->pmport;
10136 10235
10137 10236 switch (sata_addrp->qual) {
10138 10237 case SATA_ADDR_DCPORT:
10139 10238 case SATA_ADDR_CPORT:
10140 10239 ahci_addrp->aa_qual = AHCI_ADDR_PORT;
10141 10240 break;
10142 10241 case SATA_ADDR_PMULT:
10143 10242 case SATA_ADDR_PMULT_SPEC:
10144 10243 ahci_addrp->aa_qual = AHCI_ADDR_PMULT;
10145 10244 break;
10146 10245 case SATA_ADDR_DPMPORT:
10147 10246 case SATA_ADDR_PMPORT:
10148 10247 ahci_addrp->aa_qual = AHCI_ADDR_PMPORT;
10149 10248 break;
10150 10249 case SATA_ADDR_NULL:
10151 10250 default:
10152 10251 /* something went wrong */
10153 10252 ahci_addrp->aa_qual = AHCI_ADDR_NULL;
10154 10253 break;
10155 10254 }
10156 10255 }
10157 10256
10158 10257 /*
10159 10258 * This routine is to calculate the total number of ports implemented
10160 10259 * by the HBA.
10161 10260 */
10162 10261 static int
10163 10262 ahci_get_num_implemented_ports(uint32_t ports_implemented)
10164 10263 {
10165 10264 uint8_t i;
10166 10265 int num = 0;
10167 10266
10168 10267 for (i = 0; i < AHCI_MAX_PORTS; i++) {
10169 10268 if (((uint32_t)0x1 << i) & ports_implemented)
10170 10269 num++;
10171 10270 }
10172 10271
10173 10272 return (num);
10174 10273 }
10175 10274
10176 10275 #if AHCI_DEBUG
10177 10276 static void
10178 10277 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...)
10179 10278 {
10180 10279 static char name[16];
10181 10280 va_list ap;
10182 10281
10183 10282 mutex_enter(&ahci_log_mutex);
10184 10283
10185 10284 va_start(ap, fmt);
10186 10285 if (ahci_ctlp) {
10187 10286 (void) sprintf(name, "ahci%d: ",
10188 10287 ddi_get_instance(ahci_ctlp->ahcictl_dip));
10189 10288 } else {
10190 10289 (void) sprintf(name, "ahci: ");
10191 10290 }
10192 10291
10193 10292 (void) vsprintf(ahci_log_buf, fmt, ap);
10194 10293 va_end(ap);
10195 10294
10196 10295 cmn_err(level, "%s%s", name, ahci_log_buf);
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10197 10296
10198 10297 mutex_exit(&ahci_log_mutex);
10199 10298 }
10200 10299 #endif
10201 10300
10202 10301 /*
10203 10302 * quiesce(9E) entry point.
10204 10303 *
10205 10304 * This function is called when the system is single-threaded at high
10206 10305 * PIL with preemption disabled. Therefore, this function must not be
10207 - * blocked.
10306 + * blocked. Because no taskqs are running, there is no need for us to
10307 + * take any action for enclosure services which are running in the
10308 + * taskq context, especially as no interrupts are generated by it nor
10309 + * are any messages expected to come in.
10208 10310 *
10209 10311 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
10210 10312 * DDI_FAILURE indicates an error condition and should almost never happen.
10211 10313 */
10212 10314 static int
10213 10315 ahci_quiesce(dev_info_t *dip)
10214 10316 {
10215 10317 ahci_ctl_t *ahci_ctlp;
10216 10318 ahci_port_t *ahci_portp;
10217 10319 int instance, port;
10218 10320
10219 10321 instance = ddi_get_instance(dip);
10220 10322 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
10221 10323
10222 10324 if (ahci_ctlp == NULL)
10223 10325 return (DDI_FAILURE);
10224 10326
10225 10327 #if AHCI_DEBUG
10226 10328 ahci_debug_flags = 0;
10227 10329 #endif
10228 10330
10229 10331 ahci_ctlp->ahcictl_flags |= AHCI_QUIESCE;
10230 10332
10231 10333 /* disable all the interrupts. */
10232 10334 ahci_disable_all_intrs(ahci_ctlp);
10233 10335
10234 10336 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
10235 10337 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
10236 10338 continue;
10237 10339 }
10238 10340
10239 10341 ahci_portp = ahci_ctlp->ahcictl_ports[port];
10240 10342
10241 10343 /*
10242 10344 * Stop the port by clearing PxCMD.ST
10243 10345 *
10244 10346 * Here we must disable the port interrupt because
10245 10347 * ahci_disable_all_intrs only clear GHC.IE, and IS
10246 10348 * register will be still set if PxIE is enabled.
10247 10349 * When ahci shares one IRQ with other drivers, the
10248 10350 * intr handler may claim the intr mistakenly.
10249 10351 */
10250 10352 ahci_disable_port_intrs(ahci_ctlp, port);
10251 10353 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
10252 10354 ahci_portp, port);
10253 10355 }
10254 10356
10255 10357 ahci_ctlp->ahcictl_flags &= ~AHCI_QUIESCE;
10256 10358
10257 10359 return (DDI_SUCCESS);
10258 10360 }
10259 10361
10260 10362 /*
10261 10363 * The function will add a sata packet to the done queue.
10262 10364 */
10263 10365 static void
10264 10366 ahci_add_doneq(ahci_port_t *ahci_portp, sata_pkt_t *satapkt, int reason)
10265 10367 {
10266 10368 ASSERT(satapkt != NULL);
10267 10369 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
10268 10370
10269 10371 /* set the reason for all packets */
10270 10372 satapkt->satapkt_reason = reason;
10271 10373 satapkt->satapkt_hba_driver_private = NULL;
10272 10374
10273 10375 if (! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) &&
10274 10376 satapkt->satapkt_comp) {
10275 10377 /*
10276 10378 * only add to queue when mode is not synch and there is
10277 10379 * completion callback
10278 10380 */
10279 10381 *ahci_portp->ahciport_doneqtail = satapkt;
10280 10382 ahci_portp->ahciport_doneqtail =
10281 10383 (sata_pkt_t **)&(satapkt->satapkt_hba_driver_private);
10282 10384 ahci_portp->ahciport_doneq_len++;
10283 10385
10284 10386 } else if ((satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) &&
10285 10387 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING))
10286 10388 /*
10287 10389 * for sync/non-poll mode, just call cv_broadcast
10288 10390 */
10289 10391 cv_broadcast(&ahci_portp->ahciport_cv);
10290 10392 }
10291 10393
10292 10394 /*
10293 10395 * The function will call completion callback of sata packet on the
10294 10396 * completed queue
10295 10397 */
10296 10398 static void
10297 10399 ahci_flush_doneq(ahci_port_t *ahci_portp)
10298 10400 {
10299 10401 sata_pkt_t *satapkt, *next;
10300 10402
10301 10403 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
10302 10404
10303 10405 if (ahci_portp->ahciport_doneq) {
10304 10406 satapkt = ahci_portp->ahciport_doneq;
10305 10407
10306 10408 ahci_portp->ahciport_doneq = NULL;
10307 10409 ahci_portp->ahciport_doneqtail = &ahci_portp->ahciport_doneq;
10308 10410 ahci_portp->ahciport_doneq_len = 0;
10309 10411
10310 10412 mutex_exit(&ahci_portp->ahciport_mutex);
10311 10413
10312 10414 while (satapkt != NULL) {
10313 10415 next = satapkt->satapkt_hba_driver_private;
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10314 10416 satapkt->satapkt_hba_driver_private = NULL;
10315 10417
10316 10418 /* Call the callback */
10317 10419 (*satapkt->satapkt_comp)(satapkt);
10318 10420
10319 10421 satapkt = next;
10320 10422 }
10321 10423
10322 10424 mutex_enter(&ahci_portp->ahciport_mutex);
10323 10425 }
10426 +}
10427 +
10428 +/*
10429 + * Sets the state for the specified port on the controller to desired state.
10430 + * This must be run in the context of the enclosure taskq which ensures that
10431 + * only one event is outstanding at any time.
10432 + */
10433 +static boolean_t
10434 +ahci_em_set_led(ahci_ctl_t *ahci_ctlp, uint8_t port, ahci_em_led_state_t desire)
10435 +{
10436 + ahci_em_led_msg_t msg;
10437 + ahci_em_msg_hdr_t hdr;
10438 + uint32_t msgval, hdrval;
10439 + uint_t i, max_delay = ahci_em_tx_delay_count;
10440 +
10441 + msg.alm_hba = port;
10442 + msg.alm_pminfo = 0;
10443 + msg.alm_value = 0;
10444 +
10445 + if (desire & AHCI_EM_LED_IDENT_ENABLE) {
10446 + msg.alm_value |= AHCI_LED_ON << AHCI_LED_IDENT_OFF;
10447 + }
10448 +
10449 + if (desire & AHCI_EM_LED_FAULT_ENABLE) {
10450 + msg.alm_value |= AHCI_LED_ON << AHCI_LED_FAULT_OFF;
10451 + }
10452 +
10453 + if ((ahci_ctlp->ahcictl_em_ctl & AHCI_HBA_EM_CTL_ATTR_ALHD) == 0 &&
10454 + (desire & AHCI_EM_LED_ACTIVITY_DISABLE) == 0) {
10455 + msg.alm_value |= AHCI_LED_ON << AHCI_LED_ACTIVITY_OFF;
10456 + }
10457 +
10458 + hdr.aemh_rsvd = 0;
10459 + hdr.aemh_mlen = sizeof (ahci_em_led_msg_t);
10460 + hdr.aemh_dlen = 0;
10461 + hdr.aemh_mtype = AHCI_EM_MSG_TYPE_LED;
10462 +
10463 + bcopy(&msg, &msgval, sizeof (msgval));
10464 + bcopy(&hdr, &hdrval, sizeof (hdrval));
10465 +
10466 + /*
10467 + * First, make sure we can transmit. We should not have been placed in a
10468 + * situation where an outstanding transmission is going on.
10469 + */
10470 + for (i = 0; i < max_delay; i++) {
10471 + uint32_t val;
10472 +
10473 + val = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
10474 + (uint32_t *)AHCI_GLOBAL_EM_CTL(ahci_ctlp));
10475 + if ((val & AHCI_HBA_EM_CTL_CTL_TM) == 0)
10476 + break;
10477 +
10478 + delay(drv_usectohz(ahci_em_tx_delay_ms * 1000));
10479 + }
10480 +
10481 + if (i == max_delay)
10482 + return (B_FALSE);
10483 +
10484 + ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
10485 + (uint32_t *)ahci_ctlp->ahcictl_em_tx_off, hdrval);
10486 + ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
10487 + (uint32_t *)(ahci_ctlp->ahcictl_em_tx_off + 4), msgval);
10488 + ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
10489 + (uint32_t *)AHCI_GLOBAL_EM_CTL(ahci_ctlp), AHCI_HBA_EM_CTL_CTL_TM);
10490 +
10491 + for (i = 0; i < max_delay; i++) {
10492 + uint32_t val;
10493 +
10494 + val = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
10495 + (uint32_t *)AHCI_GLOBAL_EM_CTL(ahci_ctlp));
10496 + if ((val & AHCI_HBA_EM_CTL_CTL_TM) == 0)
10497 + break;
10498 +
10499 + delay(drv_usectohz(ahci_em_tx_delay_ms * 1000));
10500 + }
10501 +
10502 + if (i == max_delay)
10503 + return (B_FALSE);
10504 +
10505 + return (B_TRUE);
10506 +}
10507 +
10508 +typedef struct ahci_em_led_task_arg {
10509 + ahci_ctl_t *aelta_ctl;
10510 + uint8_t aelta_port;
10511 + uint_t aelta_op;
10512 + ahci_em_led_state_t aelta_state;
10513 + uint_t aelta_ret;
10514 + kcondvar_t aelta_cv;
10515 + uint_t aelta_ref;
10516 +} ahci_em_led_task_arg_t;
10517 +
10518 +static void
10519 +ahci_em_led_task_free(ahci_em_led_task_arg_t *task)
10520 +{
10521 + ASSERT3U(task->aelta_ref, ==, 0);
10522 + cv_destroy(&task->aelta_cv);
10523 + kmem_free(task, sizeof (*task));
10524 +}
10525 +
10526 +static void
10527 +ahci_em_led_task(void *arg)
10528 +{
10529 + boolean_t ret, cleanup = B_FALSE;
10530 + ahci_em_led_task_arg_t *led = arg;
10531 + ahci_em_led_state_t state;
10532 +
10533 + mutex_enter(&led->aelta_ctl->ahcictl_mutex);
10534 + if (led->aelta_ctl->ahcictl_em_flags != AHCI_EM_USABLE) {
10535 + led->aelta_ret = EIO;
10536 + mutex_exit(&led->aelta_ctl->ahcictl_mutex);
10537 + return;
10538 + }
10539 +
10540 + state = led->aelta_ctl->ahcictl_em_state[led->aelta_port];
10541 + mutex_exit(&led->aelta_ctl->ahcictl_mutex);
10542 +
10543 + switch (led->aelta_op) {
10544 + case AHCI_EM_IOC_SET_OP_ADD:
10545 + state |= led->aelta_state;
10546 + break;
10547 + case AHCI_EM_IOC_SET_OP_REM:
10548 + state &= ~led->aelta_state;
10549 + break;
10550 + case AHCI_EM_IOC_SET_OP_SET:
10551 + state = led->aelta_state;
10552 + break;
10553 + default:
10554 + led->aelta_ret = ENOTSUP;
10555 + return;
10556 + }
10557 +
10558 + ret = ahci_em_set_led(led->aelta_ctl, led->aelta_port, state);
10559 +
10560 + mutex_enter(&led->aelta_ctl->ahcictl_mutex);
10561 + if (ret) {
10562 + led->aelta_ctl->ahcictl_em_state[led->aelta_port] =
10563 + led->aelta_state;
10564 + led->aelta_ret = 0;
10565 + } else {
10566 + led->aelta_ret = EIO;
10567 + led->aelta_ctl->ahcictl_em_flags |= AHCI_EM_TIMEOUT;
10568 + }
10569 + led->aelta_ref--;
10570 + if (led->aelta_ref > 0) {
10571 + cv_signal(&led->aelta_cv);
10572 + } else {
10573 + cleanup = B_TRUE;
10574 + }
10575 + mutex_exit(&led->aelta_ctl->ahcictl_mutex);
10576 +
10577 + if (cleanup) {
10578 + ahci_em_led_task_free(led);
10579 + }
10580 +}
10581 +
10582 +static void
10583 +ahci_em_reset(void *arg)
10584 +{
10585 + uint_t i, max_delay = ahci_em_reset_delay_count;
10586 + ahci_ctl_t *ahci_ctlp = arg;
10587 +
10588 + /*
10589 + * We've been asked to reset the device. The caller should have set the
10590 + * resetting flag. Make sure that we don't have a request to quiesce.
10591 + */
10592 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10593 + ASSERT(ahci_ctlp->ahcictl_em_flags & AHCI_EM_RESETTING);
10594 + if (ahci_ctlp->ahcictl_em_flags & AHCI_EM_QUIESCE) {
10595 + ahci_ctlp->ahcictl_em_flags &= ~AHCI_EM_RESETTING;
10596 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10597 + return;
10598 + }
10599 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10600 +
10601 + ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
10602 + (uint32_t *)AHCI_GLOBAL_EM_CTL(ahci_ctlp), AHCI_HBA_EM_CTL_CTL_RST);
10603 + for (i = 0; i < max_delay; i++) {
10604 + uint32_t val;
10605 +
10606 + val = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
10607 + (uint32_t *)AHCI_GLOBAL_EM_CTL(ahci_ctlp));
10608 + if ((val & AHCI_HBA_EM_CTL_CTL_RST) == 0)
10609 + break;
10610 +
10611 + delay(drv_usectohz(ahci_em_reset_delay_ms * 1000));
10612 + }
10613 +
10614 + if (i == max_delay) {
10615 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10616 + ahci_ctlp->ahcictl_em_flags &= ~AHCI_EM_RESETTING;
10617 + ahci_ctlp->ahcictl_em_flags |= AHCI_EM_TIMEOUT;
10618 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10619 + cmn_err(CE_WARN, "!ahci%d: enclosure timed out resetting",
10620 + ddi_get_instance(ahci_ctlp->ahcictl_dip));
10621 + return;
10622 + }
10623 +
10624 + for (i = 0; i < ahci_ctlp->ahcictl_num_ports; i++) {
10625 +
10626 + if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, i))
10627 + continue;
10628 +
10629 + /*
10630 + * Try to flush all the LEDs as part of reset. If it fails,
10631 + * drive on.
10632 + */
10633 + if (!ahci_em_set_led(ahci_ctlp, i,
10634 + ahci_ctlp->ahcictl_em_state[i])) {
10635 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10636 + ahci_ctlp->ahcictl_em_flags &= ~AHCI_EM_RESETTING;
10637 + ahci_ctlp->ahcictl_em_flags |= AHCI_EM_TIMEOUT;
10638 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10639 + cmn_err(CE_WARN, "!ahci%d: enclosure timed out "
10640 + "setting port %u",
10641 + ddi_get_instance(ahci_ctlp->ahcictl_dip), i);
10642 + return;
10643 + }
10644 + }
10645 +
10646 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10647 + ahci_ctlp->ahcictl_em_flags &= ~AHCI_EM_RESETTING;
10648 + ahci_ctlp->ahcictl_em_flags |= AHCI_EM_READY;
10649 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10650 +}
10651 +
10652 +static boolean_t
10653 +ahci_em_init(ahci_ctl_t *ahci_ctlp)
10654 +{
10655 + char name[128];
10656 +
10657 + /*
10658 + * First make sure we actually have enclosure services and if so, that
10659 + * we have the hardware support that we care about for this.
10660 + */
10661 + if (ahci_ctlp->ahcictl_em_loc == 0 ||
10662 + (ahci_ctlp->ahcictl_em_ctl & AHCI_HBA_EM_CTL_SUPP_LED) == 0)
10663 + return (B_TRUE);
10664 +
10665 + /*
10666 + * Next, make sure that the buffer is large enough for us. We need two
10667 + * dwords or 8 bytes. The location register is stored in dwords.
10668 + */
10669 + if ((ahci_ctlp->ahcictl_em_loc & AHCI_HBA_EM_LOC_SZ_MASK) <
10670 + AHCI_EM_BUFFER_MIN) {
10671 + return (B_TRUE);
10672 + }
10673 +
10674 + ahci_ctlp->ahcictl_em_flags |= AHCI_EM_PRESENT;
10675 +
10676 + ahci_ctlp->ahcictl_em_tx_off = ((ahci_ctlp->ahcictl_em_loc &
10677 + AHCI_HBA_EM_LOC_OFST_MASK) >> AHCI_HBA_EM_LOC_OFST_SHIFT) * 4;
10678 + ahci_ctlp->ahcictl_em_tx_off += ahci_ctlp->ahcictl_ahci_addr;
10679 +
10680 + bzero(ahci_ctlp->ahcictl_em_state,
10681 + sizeof (ahci_ctlp->ahcictl_em_state));
10682 +
10683 + (void) snprintf(name, sizeof (name), "ahcti_em_taskq%d",
10684 + ddi_get_instance(ahci_ctlp->ahcictl_dip));
10685 + if ((ahci_ctlp->ahcictl_em_taskq =
10686 + ddi_taskq_create(ahci_ctlp->ahcictl_dip, name, 1,
10687 + TASKQ_DEFAULTPRI, 0)) == NULL) {
10688 + cmn_err(CE_WARN, "!ahci%d: ddi_tasq_create failed for em "
10689 + "services", ddi_get_instance(ahci_ctlp->ahcictl_dip));
10690 + return (B_FALSE);
10691 + }
10692 +
10693 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10694 + ahci_ctlp->ahcictl_em_flags |= AHCI_EM_RESETTING;
10695 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10696 + (void) ddi_taskq_dispatch(ahci_ctlp->ahcictl_em_taskq, ahci_em_reset,
10697 + ahci_ctlp, DDI_SLEEP);
10698 +
10699 + return (B_TRUE);
10700 +}
10701 +
10702 +static int
10703 +ahci_em_ioctl_get(ahci_ctl_t *ahci_ctlp, intptr_t arg)
10704 +{
10705 + int i;
10706 + ahci_ioc_em_get_t get;
10707 +
10708 + bzero(&get, sizeof (get));
10709 + get.aiemg_nports = ahci_ctlp->ahcictl_ports_implemented;
10710 + if ((ahci_ctlp->ahcictl_em_ctl & AHCI_HBA_EM_CTL_ATTR_ALHD) == 0) {
10711 + get.aiemg_flags |= AHCI_EM_FLAG_CONTROL_ACTIVITY;
10712 + }
10713 +
10714 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10715 + for (i = 0; i < ahci_ctlp->ahcictl_num_ports; i++) {
10716 + if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, i)) {
10717 + continue;
10718 + }
10719 + get.aiemg_status[i] = ahci_ctlp->ahcictl_em_state[i];
10720 + }
10721 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10722 +
10723 + if (ddi_copyout(&get, (void *)arg, sizeof (get), 0) != 0)
10724 + return (EFAULT);
10725 +
10726 + return (0);
10727 +}
10728 +
10729 +static int
10730 +ahci_em_ioctl_set(ahci_ctl_t *ahci_ctlp, intptr_t arg)
10731 +{
10732 + int ret;
10733 + ahci_ioc_em_set_t set;
10734 + ahci_em_led_task_arg_t *task;
10735 + boolean_t signal, cleanup;
10736 +
10737 + if (ddi_copyin((void *)arg, &set, sizeof (set), 0) != 0)
10738 + return (EFAULT);
10739 +
10740 + if (set.aiems_port > ahci_ctlp->ahcictl_num_ports)
10741 + return (EINVAL);
10742 +
10743 + if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, set.aiems_port)) {
10744 + return (EINVAL);
10745 + }
10746 +
10747 + if ((set.aiems_leds & ~(AHCI_EM_LED_IDENT_ENABLE |
10748 + AHCI_EM_LED_FAULT_ENABLE |
10749 + AHCI_EM_LED_ACTIVITY_DISABLE)) != 0) {
10750 + return (EINVAL);
10751 + }
10752 +
10753 + switch (set.aiems_op) {
10754 + case AHCI_EM_IOC_SET_OP_ADD:
10755 + case AHCI_EM_IOC_SET_OP_REM:
10756 + case AHCI_EM_IOC_SET_OP_SET:
10757 + break;
10758 + default:
10759 + return (EINVAL);
10760 + }
10761 +
10762 + if ((set.aiems_leds & AHCI_EM_LED_ACTIVITY_DISABLE) != 0 &&
10763 + ((ahci_ctlp->ahcictl_em_ctl & AHCI_HBA_EM_CTL_ATTR_ALHD) != 0)) {
10764 + return (ENOTSUP);
10765 + }
10766 +
10767 + task = kmem_alloc(sizeof (*task), KM_NOSLEEP | KM_NORMALPRI);
10768 + if (task == NULL) {
10769 + return (ENOMEM);
10770 + }
10771 +
10772 + task->aelta_ctl = ahci_ctlp;
10773 + task->aelta_port = (uint8_t)set.aiems_port;
10774 + task->aelta_op = set.aiems_op;
10775 + task->aelta_state = set.aiems_leds;
10776 +
10777 + cv_init(&task->aelta_cv, NULL, CV_DRIVER, NULL);
10778 +
10779 + /*
10780 + * Initialize the reference count to two. One for us and one for the
10781 + * taskq. This will be used in case we get canceled.
10782 + */
10783 + task->aelta_ref = 2;
10784 +
10785 + /*
10786 + * Once dispatched, the task state is protected by our global mutex.
10787 + */
10788 + (void) ddi_taskq_dispatch(ahci_ctlp->ahcictl_em_taskq,
10789 + ahci_em_led_task, task, DDI_SLEEP);
10790 +
10791 + signal = B_FALSE;
10792 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10793 + while (task->aelta_ref > 1) {
10794 + if (cv_wait_sig(&task->aelta_cv, &ahci_ctlp->ahcictl_mutex) ==
10795 + 0) {
10796 + signal = B_TRUE;
10797 + break;
10798 + }
10799 + }
10800 +
10801 + /*
10802 + * Remove our reference count. If we were woken up because of a signal
10803 + * then the taskq may still be dispatched. In which case we shouldn't
10804 + * free this memory until it is done. In that case, the taskq will take
10805 + * care of it.
10806 + */
10807 + task->aelta_ref--;
10808 + cleanup = (task->aelta_ref == 0);
10809 + if (signal) {
10810 + ret = EINTR;
10811 + } else {
10812 + ret = task->aelta_ret;
10813 + }
10814 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10815 +
10816 + if (cleanup) {
10817 + ahci_em_led_task_free(task);
10818 + }
10819 +
10820 + return (ret);
10821 +}
10822 +
10823 +static int
10824 +ahci_em_ioctl(dev_info_t *dip, int cmd, intptr_t arg)
10825 +{
10826 + int inst;
10827 + ahci_ctl_t *ahci_ctlp;
10828 +
10829 + inst = ddi_get_instance(dip);
10830 + if ((ahci_ctlp = ddi_get_soft_state(ahci_statep, inst)) == NULL) {
10831 + return (ENXIO);
10832 + }
10833 +
10834 + switch (cmd) {
10835 + case AHCI_EM_IOC_GET:
10836 + return (ahci_em_ioctl_get(ahci_ctlp, arg));
10837 + case AHCI_EM_IOC_SET:
10838 + return (ahci_em_ioctl_set(ahci_ctlp, arg));
10839 + default:
10840 + return (ENOTTY);
10841 + }
10842 +
10843 +}
10844 +
10845 +static void
10846 +ahci_em_quiesce(ahci_ctl_t *ahci_ctlp)
10847 +{
10848 + ASSERT(ahci_ctlp->ahcictl_em_flags & AHCI_EM_PRESENT);
10849 +
10850 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10851 + ahci_ctlp->ahcictl_em_flags |= AHCI_EM_QUIESCE;
10852 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10853 +
10854 + ddi_taskq_wait(ahci_ctlp->ahcictl_em_taskq);
10855 +}
10856 +
10857 +static void
10858 +ahci_em_suspend(ahci_ctl_t *ahci_ctlp)
10859 +{
10860 + ahci_em_quiesce(ahci_ctlp);
10861 +
10862 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10863 + ahci_ctlp->ahcictl_em_flags &= ~AHCI_EM_READY;
10864 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10865 +}
10866 +
10867 +static void
10868 +ahci_em_resume(ahci_ctl_t *ahci_ctlp)
10869 +{
10870 + mutex_enter(&ahci_ctlp->ahcictl_mutex);
10871 + ahci_ctlp->ahcictl_em_flags |= AHCI_EM_RESETTING;
10872 + mutex_exit(&ahci_ctlp->ahcictl_mutex);
10873 +
10874 + (void) ddi_taskq_dispatch(ahci_ctlp->ahcictl_em_taskq, ahci_em_reset,
10875 + ahci_ctlp, DDI_SLEEP);
10876 +}
10877 +
10878 +static void
10879 +ahci_em_fini(ahci_ctl_t *ahci_ctlp)
10880 +{
10881 + if ((ahci_ctlp->ahcictl_em_flags & AHCI_EM_PRESENT) == 0) {
10882 + return;
10883 + }
10884 +
10885 + ahci_em_quiesce(ahci_ctlp);
10886 + ddi_taskq_destroy(ahci_ctlp->ahcictl_em_taskq);
10887 + ahci_ctlp->ahcictl_em_taskq = NULL;
10324 10888 }
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