1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1, (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
26
27 * You may not use this file except in compliance with the License.
28
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35
36 #ifndef _QEDE_H
37 #define _QEDE_H
38
39 #include <sys/stream.h>
40
41 #include <sys/ddi.h>
42 #include <sys/ddifm.h>
43 #include <sys/dditypes.h>
44 #include <sys/sunddi.h>
45 #include <sys/fm/io/ddi.h>
46 #include <sys/mac_provider.h>
47 #include <sys/mac_ether.h>
48 #include <sys/kobj.h>
49 #include <sys/mac.h>
50 #include <sys/dlpi.h>
51 #include <sys/pattr.h>
52 #include <sys/gld.h>
53 #include <inet/ip.h>
54 #include <inet/tcp.h>
55 #include <netinet/udp.h>
56 #include <sys/ethernet.h>
57 #include <sys/pci.h>
58 #include <sys/netlb.h>
59 #include <sys/strsun.h>
60 #include <sys/strsubr.h>
61 #include <sys/policy.h>
62
63 #include "qede_version.h"
64 #include "bcm_osal.h"
65 #include "qede_fp.h"
66
67 #if 1
68 #include "ecore.h"
69 #include "ecore_status.h"
70 #include "ecore_utils.h"
71 #include "ecore_chain.h"
72 #include "ecore_hsi_common.h"
73 #include "ecore_hsi_eth.h"
74 #include "ecore_proto_if.h"
75 #include "ecore_iov_api.h"
76 #include "ecore_int_api.h"
77 #include "ecore_dev_api.h"
78 #include "ecore_l2_api.h"
79 #include "ecore_hw.h"
80 #include "nvm_cfg.h"
81 #include "ecore_mcp.h"
82 #include "ecore_dbg_fw_funcs.h"
83 #include <sys/pcie.h>
84 #include <sys/time.h>
85 #else
86 #include <ecore.h>
87 #include <ecore_status.h>
88 #include <ecore_utils.h>
89 #include <ecore_hsi_common.h>
90 #include <ecore_hsi_eth.h>
91 #include <ecore_proto_if.h>
92 #include <ecore_chain.h>
93 #include <ecore_iov_api.h>
94 #include <ecore_int_api.h>
95 #include <ecore_dev_api.h>
96 #include <ecore_ll2_api.h>
97 #include <ecore_l2_api.h>
98 #include <ecore_mcp.h>
99 #endif
100
101
102
103 #ifndef STRINGIFY
104 #define XSTRINGIFY(x) #x
105 #define STRINGIFY(x) XSTRINGIFY(x)
106 #endif
107 #define QEDE_STR_SIZE 32
108 /* Product Identification Banner */
109 #define QEDE_PRODUCT_INFO\
110 "QLogic FastLinQ QL45xxx " STRINGIFY(MAJVERSION) \
111 "." STRINGIFY(MINVERSION) "." STRINGIFY(REVVERSION)
112
113 /*
114 * Debug Infrastructure
115 */
116 #define DEBUG_NONE 0x0
117 #define DEBUG_ATTACH 0x1
118
119 #ifndef DEBUG_LEVEL
120 #define DEBUG_LEVEL DEBUG_NONE
121 #endif
122
123 #ifdef DEBUG
124 #define qede_dbg(MASK, ptr, fmt, ...) \
125 do { \
126 if (DEBUG_LEVEL & (MASK)) { \
127 qede_print("!%s(%d) STRINGIFY(MASK):" fmt, __func__, \
128 (ptr)->instance, \
129 ##__VA_ARGS__);\
130 } \
131 } while (0);
132
133 #define qede_info(ptr, fmt, ...) \
134 do { \
135 qede_print("!%s(%d):" fmt, __func__, (ptr)->instance, \
136 ##__VA_ARGS__); \
137 } while (0);
138
139 #define qede_warn(ptr, fmt, ...) \
140 do { \
141 qede_print_err("!%s(%d):" fmt, __func__, (ptr)->instance, \
142 ##__VA_ARGS__); \
143 } while (0);
144 #else
145 #define qede_dbg(MASK, ptr, fmt, ...)
146 #define qede_info(ptr, fmt, ...)
147 #define qede_warn(ptr, fmt, ...)
148 #endif
149
150 #ifdef __sparc
151 #define QEDE_PAGE_ALIGNMENT 0x0000000000002000ull
152 #define QEDE_PAGE_SIZE 0x0000000000002000ull
153 #else
154 #define QEDE_PAGE_ALIGNMENT 0x0000000000001000ull
155 #define QEDE_PAGE_SIZE 0x0000000000001000ull
156 #endif
157
158 #define LE_TO_HOST_64 LE_64
159 #define HOST_TO_LE_64 LE_64
160 #define HOST_TO_LE_32 LE_32
161 #define LE_TO_HOST_32 LE_32
162 #define HOST_TO_LE_16 LE_16
163 #define LE_TO_HOST_16 LE_16
164
165
166
167 #define QEDE_LSO_MAXLEN 65535
168
169 #define BUF_2K_SIZE 2048
170 #define BUF_2K_ALIGNMENT BUF_2K_SIZE
171
172 #define MIN_TX_RING_COUNT 1
173 #define MAX_TX_RING_COUNT 1
174 #define DEFAULT_TX_RING_COUNT 1
175 #define MAX_TC_COUNT 1
176 #define DEFAULT_TRFK_CLASS_COUNT 1
177
178 #define MIN_TX_RING_SIZE 1024
179 #define DEFAULT_TX_RING_SIZE 8192
180
181 #define DEFAULT_TX_COPY_THRESHOLD 256
182 #define DEFAULT_TX_RECYCLE_THRESHOLD 128
183
184 #define TX_RING_MASK (tx_ring->tx_ring_size - 1)
185
186 #define IP_ALIGNMENT_BYTES 2
187 #define QEDE_MAX_ETHER_HDR 18
188
189 #define MIN_FASTPATH_COUNT 1
190 #define MAX_FASTPATH_COUNT 6
191 #define DEFAULT_FASTPATH_COUNT 4
192
193 #define MIN_RX_RING_SIZE 1024
194 #define DEFAULT_RX_RING_SIZE 8192
195 #define MAX_RX_RING_SIZE DEFAULT_RX_RING_SIZE
196
197 #define MIN_RX_BUF_SIZE 2048
198 #define MAX_RX_BUF_SIZE 2048
199 #define DEFAULT_RX_BUF_SIZE 2048
200
201 #define DEFAULT_RX_COPY_THRESHOLD 128
202 #define RX_RING_MASK (rx_ring->rx_buf_count - 1)
203 #define MIN_RX_BUF_COUNT MIN_RX_RING_SIZE
204 #define MAX_RX_BUF_COUNT MAX_RX_RING_SIZE
205 #define DEFAULT_RX_BUF_COUNT DEFAULT_RX_RING_SIZE
206 #define RX_LOW_BUFFER_THRESHOLD 128
207
208 #define USER_OPTION_CKSUM_NONE 0x0
209 #define USER_OPTION_CKSUM_L3 0x1
210 #define USER_OPTION_CKSUM_L3_L4 0x2
211 #define DEFAULT_CKSUM_OFFLOAD USER_OPTION_CKSUM_L3_L4
212
213 #define QEDE_OFFLOAD_NONE 0x00000000
214 #define QEDE_OFFLOAD_TX_IP_CKSUM 0x00000001
215 #define QEDE_OFFLOAD_RX_IP_CKSUM 0x00000002
216 #define QEDE_OFFLOAD_TX_TCP_CKSUM 0x00000004
217 #define QEDE_OFFLOAD_RX_TCP_CKSUM 0x00000008
218 #define QEDE_OFFLOAD_TX_UDP_CKSUM 0x00000010
219 #define QEDE_OFFLOAD_RX_UDP_CKSUM 0x00000020
220
221 #define DEFAULT_JUMBO_MTU 9000
222 #define MIN_MTU ETHERMTU
223 #define MAX_MTU DEFAULT_JUMBO_MTU
224 #define DEFAULT_MTU ETHERMTU
225
226 #define DEFAULT_ECORE_DEBUG_LEVEL ECORE_LEVEL_ERR
227
228
229 #define DEFAULT_ECORE_DEBUG_MODULE ECORE_MSG_DRV
230
231 #define VLAN_TAGSZ 0x4
232
233 #define MAX_TC 1
234
235 #define DUPLEX_HALF 0
236 #define DUPLEX_FULL 1
237
238 #define ETH_ALLEN 6
239
240 #define MAC_STRING "%2x:%2x:%2x:%2x:%2x:%2x"
241 #define MACTOSTR(a) a[0], a[1], a[2], a[3], a[4], a[5]
242
243 #define MAX_MC_SOFT_LIMIT 1024
244
245 #define qede_delay(_msecs_) delay(drv_usectohz(_msecs_ * 1000))
246
247 #define QEDE_CMD 73
248
249
250 typedef struct _KstatRingMap
251 {
252 uint32_t idx; /* ring index */
253 void * qede; /* reference back to qede_t */
254 } KstatRingMap;
255
256 #define IS_ETH_MULTICAST(eth_addr) \
257 (((unsigned char *) (eth_addr))[0] & ((unsigned char) 0x01))
258
259 #define IS_ETH_ADDRESS_EQUAL(eth_addr1, eth_addr2) \
260 ((((unsigned char *) (eth_addr1))[0] == \
261 ((unsigned char *) (eth_addr2))[0]) && \
262 (((unsigned char *) (eth_addr1))[1] == \
263 ((unsigned char *) (eth_addr2))[1]) && \
264 (((unsigned char *) (eth_addr1))[2] == \
265 ((unsigned char *) (eth_addr2))[2]) && \
266 (((unsigned char *) (eth_addr1))[3] == \
267 ((unsigned char *) (eth_addr2))[3]) && \
268 (((unsigned char *) (eth_addr1))[4] == \
269 ((unsigned char *) (eth_addr2))[4]) && \
270 (((unsigned char *) (eth_addr1))[5] == \
271 ((unsigned char *) (eth_addr2))[5]))
272
273 #define COPY_ETH_ADDRESS(src, dst) \
274 ((unsigned char *) (dst))[0] = ((unsigned char *) (src))[0]; \
275 ((unsigned char *) (dst))[1] = ((unsigned char *) (src))[1]; \
276 ((unsigned char *) (dst))[2] = ((unsigned char *) (src))[2]; \
277 ((unsigned char *) (dst))[3] = ((unsigned char *) (src))[3]; \
278 ((unsigned char *) (dst))[4] = ((unsigned char *) (src))[4]; \
279 ((unsigned char *) (dst))[5] = ((unsigned char *) (src))[5];
280
281
282 union db_prod {
283 struct eth_db_data data;
284 uint32_t raw;
285 };
286
287 struct qede;
288 struct qede_fastpath;
289 struct qede_rx_ring;
290 struct qede_tx_pktinfo_s;
291
292 typedef struct qede_tx_ring {
293 struct qede_fastpath *fp;
294 struct qede *qede;
295 uint32_t tx_queue_index;
296 uint16_t *hw_cons_ptr;
297
298 /* pointer to driver ring control */
299 struct ecore_chain tx_bd_ring;
300 u16 sw_tx_cons;
301 u16 sw_tx_prod;
302 u16 bd_ring_size;
303
304 /* From ecore_sp_tx_queue_start() */
305 void __iomem *doorbell_addr;
306 ddi_acc_handle_t doorbell_handle;
307
308 /* Saved copy of doorbell data for this tx queue */
309 union db_prod tx_db;
310
311 uint32_t fp_idx;
312 kmutex_t tx_lock;
313 int tx_buf_size;
314 uint32_t tx_ring_size;
315 bool queue_started;
316 mac_ring_handle_t mac_ring_handle;
317
318 /* pre-allocated bcopy packets */
319 qede_tx_bcopy_list_t bcopy_list;
320 /* pre-allocated dma handles */
321 qede_dma_handles_list_t dmah_list;
322 /* List of recycle entires for tx packets */
323 qede_tx_recycle_list_t *tx_recycle_list;
324
325 #ifdef DBLK_DMA_PREMAP
326 pm_handle_t pm_handle;
327 #endif
328 /* dma_handle for tx bd ring */
329 ddi_dma_handle_t tx_bd_dmah;
330 ddi_dma_handle_t tx_pbl_dmah;
331
332 bool tx_q_sleeping;
333
334 uint64_t tx_pkt_count;
335 uint64_t tx_byte_count;
336 uint64_t tx_pkt_dropped;
337 uint64_t tx_copy_count;
338 uint64_t tx_bind_count;
339 uint64_t tx_bind_fail;
340 uint64_t tx_premap_count;
341 uint64_t tx_premap_fail;
342 uint64_t tx_pullup_count;
343 uint64_t tx_too_many_cookies;
344 uint64_t tx_lso_pkt_count;
345 uint64_t tx_ring_pause;
346 uint64_t tx_too_many_mblks;
347 uint64_t tx_mapped_pkts;
348 uint64_t tx_jumbo_pkt_count;
349 struct ecore_queue_cid *p_cid;
350 } qede_tx_ring_t;
351
352
353 typedef struct qede_vector_info {
354 /*
355 * Pointer to a fastpath structure,
356 * or to a hwfnc.
357 */
358 void *fp;
359 struct qede *qede;
360 uint32_t vect_index;
361 bool handler_added;
362 /* set and cleared by ISR, checked by stop path
363 * when waiting for quiesce
364 */
365 bool in_isr;
366 } qede_vector_info_t;
367
368
369 typedef struct qede_fastpath {
370 qede_vector_info_t *vect_info;
371
372 /* Status block associated with this fp */
373 ddi_dma_handle_t sb_dma_handle;
374 ddi_acc_handle_t sb_acc_handle;
375 struct status_block *sb_virt;
376 uint64_t sb_phys;
377
378 struct ecore_sb_info *sb_info;
379 struct qede_rx_ring *rx_ring;
380 qede_tx_ring_t *tx_ring[MAX_TC];
381 struct qede *qede;
382
383 uint32_t fp_index;
384 uint32_t fp_hw_eng_index;
385 uint32_t vport_id; /* */
386 uint32_t stats_id; /* vport id to hold stats */
387 uint32_t rx_queue_index;
388 uint32_t rss_id;
389 kmutex_t fp_lock;
390 uint32_t disabled_by_poll;
391 } qede_fastpath_t;
392
393 enum qede_agg_state {
394 QEDE_AGG_STATE_NONE = 0,
395 QEDE_AGG_STATE_START = 1,
396 QEDE_AGG_STATE_ERROR = 2
397 };
398
399 #define QEDE_MAX_BD_PER_AGG 16
400 struct qede_rx_buffer_s;
401 typedef struct qede_lro_info {
402 uint16_t pars_flags;
403 uint16_t pad;
404 uint16_t vlan_tag;
405 uint16_t bd_count;
406 uint32_t rss_hash;
407 uint32_t header_len;
408 uint32_t free_buffer_count;
409 struct qede_rx_buffer_s *rx_buffer[QEDE_MAX_BD_PER_AGG];
410 enum qede_agg_state agg_state;
411 } qede_lro_info_t;
412
413 typedef struct qede_dma_info_s {
414 ddi_acc_handle_t acc_handle;
415 ddi_dma_handle_t dma_handle;
416 u32 ncookies;
417 u32 offset;
418 u64 phys_addr;
419 void *virt_addr;
420 u32 pad;
421 } qede_dma_info_t;
422
423 enum rx_buf_state {
424 RX_BUF_STATE_FREE,
425 RX_BUF_STATE_WITH_FW,
426 RX_BUF_STATE_WITH_OS,
427 RX_BUF_STATE_WITH_DRV,
428 };
429
430 struct qede_rx_buf_area;
431
432 typedef struct qede_rx_buffer_s {
433 qede_dma_info_t dma_info;
434 mblk_t *mp;
435 u32 index;
436 struct qede_rx_ring *rx_ring;
437
438 /* Recycle function */
439 frtn_t recycle;
440 u32 ref_cnt;
441 enum rx_buf_state buf_state;
442 struct qede_rx_buf_area *rx_buf_area;
443 } qede_rx_buffer_t;
444
445 typedef struct qede_rx_buf_list_s {
446 kmutex_t lock;
447 u16 head, tail;
448 u32 num_entries;
449 qede_rx_buffer_t *buf_list[DEFAULT_RX_RING_SIZE];
450 } qede_rx_buf_list_t;
451
452 typedef struct qede_rx_buf_area {
453 //kmutex_t rx_buf_area_lock;
454 qede_rx_buffer_t rx_buf_pool[DEFAULT_RX_RING_SIZE];
455
456 qede_rx_buf_list_t active_buf_list;
457 qede_rx_buf_list_t passive_buf_list;
458
459 u32 bufs_per_page;
460 struct qede_rx_ring *rx_ring;
461 u32 inactive;
462 u32 buf_upstream;
463 } qede_rx_buf_area_t;
464
465 typedef struct qede_rx_ring {
466 uint32_t rx_buf_count;
467 uint32_t rx_buf_size;
468 /*
469 * Pointer to an array of producer indicies.
470 * Returned in call to ecore_sp_eth_rx_queue_start()
471 * during qede_start(). Driver uses address
472 * to update producer indicies for
473 * CQE and RX buffer chains.
474 */
475 void __iomem *hw_rxq_prod_addr;
476
477 /* Pointer to hw cqe consumer index.
478 * Taken from sb_virt->pi_array after
479 * rx_ring has been started by calling
480 * ecore_sp_eth_rx_queue_start().
481 * This value is little endian and requires
482 * swapping on big endian platforms.
483 * It is updated by ecore and read by
484 * the driver while processing rings.
485 */
486 uint16_t *hw_cons_ptr;
487
488 u16 sw_rx_cons;
489 u16 sw_rx_prod;
490 u16 last_cqe_consumer;
491
492 /*
493 * Driver buffer descriptor ring defining
494 * buffers on a one-to-one releationship
495 * to ecore_chain rx_bd_ring.
496 */
497 qede_rx_buffer_t *rx_buffers;
498 qede_rx_buf_area_t *rx_buf_area;
499 /*
500 * Descriptor rings returned from
501 * ecore_chain_alloc()
502 */
503 struct ecore_chain rx_bd_ring;
504 struct ecore_chain rx_cqe_ring;
505
506 uint32_t rss_id;
507 bool queue_started;
508 bool mac_ring_started;
509 kmutex_t rx_lock;
510 kmutex_t rx_replen_lock;
511 mac_ring_handle_t mac_ring_handle;
512 u64 mr_gen_num; /* Mac rings generation number */
513 uint32_t group_index;
514 qede_fastpath_t *fp;
515 struct qede *qede;
516
517 /* dma_handles for rx dma mem */
518 ddi_dma_handle_t rx_bd_dmah;
519 ddi_dma_handle_t rx_cqe_dmah;
520 ddi_dma_handle_t rx_cqe_pbl_dmah;
521 uint32_t rx_copy_threshold;
522 uint32_t rx_low_buffer_threshold;
523 struct qede_lro_info lro_info[ETH_TPA_MAX_AGGS_NUM];
524 uint32_t lro_active_count;
525
526 uint64_t rx_copy_cnt;
527 uint64_t rx_drop_cnt;
528 uint64_t rx_low_water_cnt;
529 uint64_t rx_poll_cnt;
530 uint64_t rx_reg_pkt_cnt;
531 uint64_t rx_jumbo_pkt_cnt;
532 uint64_t rx_lro_pkt_cnt;
533 uint64_t rx_byte_cnt;
534 uint64_t rx_pkt_cnt;
535 uint8_t intrEnableCnt;
536 uint8_t intrDisableCnt;
537 struct ecore_queue_cid *p_cid;
538 } qede_rx_ring_t;
539
540 typedef uint32_t qede_offload_t;
541 typedef struct qede_params {
542 qede_offload_t enabled_offloads;
543 boolean_t multi_promisc_fl;
544 boolean_t promisc_fl;
545 uint32_t link_state;
546 u32 loopback_mode;
547 } qede_params_t;
548
549 typedef struct qede_intr_context {
550 /* bit field indicating enable/disable state of vector */
551 volatile uint32_t intr_state;
552 qede_vector_info_t *intr_vect_info;
553 int intr_vect_info_array_size; /* based on hw max vectors */
554 ddi_intr_handle_t *intr_hdl_array; /* handle array from ddi_intr_alloc() */
555 int intr_hdl_array_size; /* based on hw max vectors */
556 int intr_types_available; /* from ddi_intr_get_supported_types */
557 int intr_type_forced; /* from qede.conf */
558 int intr_type_in_use; /* interrupt type currently used */
559 int intr_vect_supported; /* from ddi_intr_get_nintrs */
560 int intr_vect_available; /* from ddi_intr_get_navail */
561 int intr_vect_to_request; /* intr count requested */
562 int intr_vect_allocated; /* intr count taken */
563 uint32_t intr_pri;
564 int intr_cap;
565 uint32_t intr_fp_vector_count;
566 enum ecore_int_mode intr_mode;
567 } qede_intr_context_t;
568
569 #define QEDE_LINK_PAUSE_AUTONEG_ENABLE (1 << 0)
570 #define QEDE_LINK_PAUSE_RX_ENABLE (1 << 1)
571 #define QEDE_LINK_PAUSE_TX_ENABLE (1 << 2)
572
573 typedef struct qede_props {
574 uint32_t link_speed;
575 boolean_t link_duplex;
576 boolean_t tx_pause;
577 boolean_t rx_pause;
578 time_t uptime;
579 } qede_props_t;
580
581 typedef struct qede_link_props {
582 uint8_t port_type;
583 boolean_t autoneg;
584 boolean_t asym_pause;
585 boolean_t pause;
586 boolean_t param_100000fdx;
587 boolean_t param_50000fdx;
588 boolean_t param_40000fdx;
589 boolean_t param_25000fdx;
590 boolean_t param_10000fdx;
591 boolean_t param_1000fdx;
592 boolean_t param_1000hdx;
593 } qede_link_props_t;
594
595 typedef struct qede_link_cfg {
596 boolean_t link_up;
597 uint32_t speed;
598 uint8_t duplex;
599 uint8_t port;
600 boolean_t autoneg;
601 uint32_t pause_cfg;
602 qede_link_props_t supp_capab;
603 qede_link_props_t adv_capab;
604 qede_link_props_t rem_capab;
605 } qede_link_cfg_t;
606
607 enum qede_filter_type {
608 QEDE_FILTER_UCAST,
609 QEDE_FILTER_MCAST,
610 QEDE_FILTER_RX_MODE,
611 QEDE_MAX_FILTER_TYPES,
612
613 };
614
615 enum qede_filter_rx_mode_type {
616 QEDE_FILTER_RX_MODE_REGULAR,
617 QEDE_FILTER_RX_MODE_MULTI_PROMISC,
618 QEDE_FILTER_RX_MODE_PROMISC,
619 };
620
621
622
623 struct qede_mcast_filter_params {
624 enum qede_filter_rx_mode_type acc_flg;
625 struct ecore_filter_mcast mcast;
626 };
627
628 #define QEDE_MAX_UCST_CNT 8
629 typedef struct qede_mac_addr {
630 struct ether_addr mac_addr;
631 boolean_t set;
632 } qede_mac_addr_t;
633
634
635
636 enum qede_state {
637 QEDE_STATE_UNKNOWN,
638 QEDE_STATE_ATTACHED,
639 QEDE_STATE_STARTING, /* Transitioning State */
640 QEDE_STATE_STARTED,
641 QEDE_STATE_STOPPING, /* Transitioning State */
642 QEDE_STATE_STOPPED,
643 QEDE_STATE_SUSPENDING, /* Transitioning State */
644 QEDE_STATE_SUSPENDED,
645 QEDE_STATE_RESUMING, /* Transitioning State */
646 QEDE_STATE_FAILED,
647 };
648
649 enum qede_attach_resources {
650 QEDE_STRUCT_ALLOC = (1 << 0),
651 QEDE_FM = (1 << 1),
652 QEDE_PCI = (1 << 2),
653 QEDE_ECORE_HW_PREP = (1 << 3),
654 QEDE_SET_PARAMS = (1 << 4),
655 QEDE_CALLBACK = (1 << 5),
656 QEDE_IO_STRUCT_ALLOC = (1 << 6),
657 QEDE_INIT_LOCKS = (1 << 7),
658 QEDE_INTR_ALLOC = (1 << 8),
659 QEDE_INTR_CONFIG = (1 << 9),
660 QEDE_EDEV_CONFIG = (1 << 10),
661 QEDE_KSTAT_INIT = (1 << 11),
662 QEDE_GLD_INIT = (1 << 12),
663 QEDE_SP_INTR_ENBL = (1 << 13),
664 QEDE_ECORE_HW_INIT = (1 << 14),
665 /*
666 = (1 << 15),
667 = (1 << 16),
668 = (1 << 17),
669 = (1 << 18),
670 = (1 << 19),
671 = (1 << 20),
672 */
673 };
674
675 enum qede_vport_state {
676 QEDE_VPORT_UNKNOWN,
677 QEDE_VPORT_STARTED,
678 QEDE_VPORT_ON,
679 QEDE_VPORT_OFF,
680 QEDE_VPORT_STOPPED
681 };
682
683 #define QEDE_MAX_GROUPS 1
684 typedef struct qede_mac_group {
685 int group_index;
686 mac_group_handle_t group_handle;
687 struct qede *qede;
688 } qede_mac_group_t;
689
690 typedef struct qede_link_input_params {
691 struct ecore_mcp_link_params default_link_params;
692 u32 loopback_mode;
693 }qede_link_input_params_t;
694
695 typedef struct qede {
696 struct ecore_dev edev; /* keep this at the beginning of the structure */
697 dev_info_t *dip;
698 int instance;
699 enum qede_state qede_state;
700 #define MAX_QEDE_NAME_LEN 8
701 char name[MAX_QEDE_NAME_LEN];
702
703 /* PCI access handle */
704 ddi_acc_handle_t pci_cfg_handle;
705
706 /* BAR 0 - registers */
707 ddi_acc_handle_t regs_handle;
708 off_t regview_size;
709 caddr_t regview;
710 uint64_t pci_bar0_base;
711
712 /* BAR 2 - doorbell */
713 ddi_acc_handle_t doorbell_handle;
714 off_t doorbell_size;
715 caddr_t doorbell;
716 uint64_t pci_bar2_base;
717
718 /* Vport params */
719 struct ecore_sp_vport_update_params vport_params[MAX_HWFNS_PER_DEVICE];
720 struct ecore_rss_params rss_params[MAX_HWFNS_PER_DEVICE];
721 enum qede_vport_state vport_state[MAX_HWFNS_PER_DEVICE];
722
723 /* mac Layer related vars */
724 mac_handle_t mac_handle;
725 qede_mac_group_t rx_groups[QEDE_MAX_GROUPS];
726 qede_mac_group_t tx_groups[QEDE_MAX_GROUPS];
727
728 u8 *sp_dpc;
729 /*
730 * pre-mapped buffer cache handle for TX
731 * used for getting sglist for mbkls
732 * that were already mapped in mac layer
733 */
734 #ifdef DBLK_DMA_PREMAP
735 pm_handle_t pm_handle;
736 #endif
737
738 /* current operating paramters */
739 uint32_t mtu;
740 uint32_t num_fp;
741 uint32_t mc_cnt;
742
743 uint32_t tx_ring_size;
744 uint32_t tx_buf_size;
745 uint16_t tx_recycle_threshold;
746 u16 pad; // remove later
747
748 int checksum;
749 qede_offload_t enabled_offloads;
750 uint32_t rx_ring_size;
751 uint32_t rx_buf_count;
752 uint32_t rx_buf_size;
753 uint32_t rx_copy_threshold;
754 uint32_t rx_low_buffer_threshold;
755 boolean_t lso_enable;
756 boolean_t lro_enable;
757 boolean_t jumbo_enable;
758 boolean_t log_enable;
759 uint32_t ecore_debug_level;
760 uint32_t ecore_debug_module;
761 boolean_t intr_coalesce;
762 uint32_t intr_rx_coal_usec;
763 uint32_t intr_tx_coal_usec;
764
765 /* From ecore_hw_init */
766 uint32_t num_hwfns;
767 unsigned char ether_addr[ETHERADDRL];
768 uint32_t num_tc;
769
770 qede_mac_addr_t ucst_mac[QEDE_MAX_UCST_CNT];
771 uint32_t ucst_total;
772 uint32_t ucst_avail;
773 qede_mac_addr_t suspnd_mac_list[QEDE_MAX_UCST_CNT];
774
775
776 /* software data structures for tx/rx */
777 qede_intr_context_t intr_ctx;
778 qede_fastpath_t fp_array[MAX_FASTPATH_COUNT];
779 struct ecore_sb_info sb_array[MAX_FASTPATH_COUNT];
780 qede_rx_ring_t rx_array[MAX_FASTPATH_COUNT];
781 qede_tx_ring_t tx_array[MAX_TC_COUNT][MAX_FASTPATH_COUNT];
782
783 uint16_t tx_bcopy_threshold;
784 uint16_t pad1; /* remove later */
785
786 /* status_block phys mem */
787 bool sb_phy_mem_alloc;
788
789 kmutex_t drv_lock;
790 kmutex_t watch_lock;
791 uint32_t callback_flags;
792 enum qede_attach_resources attach_resources;
793
794 /*
795 * qede osal mem management queues
796 */
797 qede_phys_mem_list_t phys_mem_list;
798 qede_mem_list_t mem_list;
799
800 qede_props_t props;
801 qede_link_cfg_t hwinit;
802 qede_link_cfg_t curcfg;
803 qede_params_t params;
804 volatile uint32_t plumbed;
805 qede_mcast_list_t mclist;
806
807 uint32_t mfw_ver;
808
809 char devName[QEDE_STR_SIZE];
810 char version[QEDE_STR_SIZE];
811 char versionFW[QEDE_STR_SIZE];
812 char versionMFW[QEDE_STR_SIZE];
813 char chip_name[QEDE_STR_SIZE];
814 char chipID[QEDE_STR_SIZE];
815 char intrAlloc[QEDE_STR_SIZE];
816 char bus_dev_func[QEDE_STR_SIZE];
817 char vendor_device[QEDE_STR_SIZE];
818
819 uint64_t txTotalPkts;
820 uint64_t txTotalBytes;
821 uint64_t txTotalDiscards;
822 uint64_t rxTotalPkts;
823 uint64_t rxTotalBytes;
824 uint64_t rxTotalDiscards;
825
826 uint64_t intrFired;
827 kmutex_t kstat_lock;
828 kmutex_t gld_lock;
829 uint64_t intrSbCnt[MAX_FASTPATH_COUNT + 1];
830 uint64_t intrSbNoChangeCnt[MAX_FASTPATH_COUNT + 1];
831 uint64_t intrSbPollCnt[MAX_FASTPATH_COUNT + 1];
832 uint64_t intrSbPollNoChangeCnt[MAX_FASTPATH_COUNT + 1];
833
834 kstat_t *kstats;
835 kstat_t *kstats_link;
836 kstat_t *kstats_intr;
837 kstat_t *kstats_vport;
838 kstat_t *kstats_rxq[MAX_FASTPATH_COUNT];
839 KstatRingMap kstats_rxq_map[MAX_FASTPATH_COUNT];
840 kstat_t *kstats_txq[MAX_FASTPATH_COUNT];
841 KstatRingMap kstats_txq_map[MAX_FASTPATH_COUNT];
842 struct ecore_eth_stats save_stats;
843
844 mblk_t *stored_mp;
845 int mp_index;
846 qede_link_input_params_t link_input_params; /*(test) */
847 uint32_t loop_back_mode; /*(test) */
848 bool lb_linkup; /*(test) */
849 uint32_t forced_speed_10G;
850 uint8_t pci_func;
851 void *nvm_buf;
852 void *nvm_buf_start;
853 uint32_t nvm_buf_size;
854 uint32_t copy_len;
855 uint8_t *reserved_buf;
856 int fm_cap;
857 uint64_t allocbFailures;
858 volatile uint32_t detach_unsafe;
859
860 } qede_t;
861
862 /*
863 * ioctl commands
864 */
865
866 typedef enum {
867 QEDE_DRV_INFO = 2,
868 QEDE_RD_PCICFG,
869 QEDE_WR_PCICFG,
870 QEDE_RW_REG,
871 QEDE_RW_NVRAM,
872 QEDE_FUNC_INFO,
873 QEDE_MAC_ADDR
874 } qede_ioctl_cmd_t;
875
876
877
878 /*
879 * ioctl message structure for FW update utility
880 */
881
882 /* regiser read/write commands */
883 #define QEDE_REG_READ 0
884 #define QEDE_REG_WRITE 1
885
886 /* nvram read/write commands */
887 #define QEDE_NVRAM_CMD_READ 0
888 #define QEDE_NVRAM_CMD_WRITE 1
889 #define QEDE_NVRAM_CMD_PUT_FILE_DATA 2
890 #define QEDE_NVRAM_CMD_SET_SECURE_MODE 3
891 #define QEDE_NVRAM_CMD_DEL_FILE 4
892 #define QEDE_NVRAM_CMD_PUT_FILE_BEGIN 5
893 #define QEDE_NVRAM_CMD_GET_NVRAM_RESP 6
894
895 typedef struct {
896 uint32_t cmd;
897 uint32_t unused1;
898 uint64_t off;
899 uint32_t size;
900 uint32_t rv;
901 char uabc[2048];
902 uint64_t address;
903 void *ptr;
904 } qede_ioctl_data_t;
905
906 typedef struct {
907 uint32_t cmd;
908 uint32_t unused1;
909 uint64_t off;
910 uint32_t size;
911 uint32_t buf_size;
912 char uabc[2048];
913 uint64_t cmd2;
914 #define START_NVM_WRITE 1
915 #define ACCUMULATE_NVM_BUF 2
916 #define STOP_NVM_WRITE 3
917 #define READ_BUF 4
918 void *ptr;
919 }qede_nvram_data_t;
920
921 typedef struct {
922 char drv_name[MAX_QEDE_NAME_LEN];
923 char drv_version[QEDE_STR_SIZE];
924 char mfw_version[QEDE_STR_SIZE];
925 char stormfw_version[QEDE_STR_SIZE];
926 uint32_t eeprom_dump_len; /* in bytes */
927 uint32_t reg_dump_len; /* in bytes */
928 char bus_info[QEDE_STR_SIZE];
929 } qede_driver_info_t;
930
931 typedef struct {
932 uint32_t supported; /* Features this interface supports */
933 uint32_t advertising; /* Features this interface advertises */
934 uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */
935 uint32_t duplex; /* Duplex, half or full */
936 uint32_t port; /* Which connector port */
937 uint32_t phy_address; /* port number*/
938 uint32_t autoneg; /* Enable or disable autonegotiation */
939 } qede_func_info_t;
940
941
942 typedef struct {
943 bool link_up;
944 u32 supported_caps; /* In SUPPORTED defs */
945 u32 advertised_caps; /* In ADVERTISED defs */
946 u32 lp_caps; /* In ADVERTISED defs */
947 u32 speed; /* In Mb/s */
948 u8 duplex; /* In DUPLEX defs */
949 u8 port; /* In PORT defs */
950 bool autoneg;
951 } qede_link_output_t;
952
953 #define PORT_FIBRE (1)
954 #define SUPPORTED_FIBRE (1 << 15)
955 #define SUPPORTED_Autoneg (1 << 16)
956 #define SUPPORTED_Pause (1 << 17)
957 #define SUPPORTED_Asym_Pause (1 << 18)
958 #define SUPPORTED_1000baseT_Half (1 << 19)
959 #define SUPPORTED_1000baseT_Full (1 << 20)
960 #define SUPPORTED_10000baseKR_Full (1 << 21)
961 #define SUPPORTED_20000baseKR2_Full (1 << 22)
962 #define SUPPORTED_40000baseKR4_Full (1 << 23)
963 #define SUPPORTED_40000baseCR4_Full (1 << 24)
964 #define SUPPORTED_40000baseSR4_Full (1 << 25)
965 #define SUPPORTED_40000baseLR4_Full (1 << 26)
966
967
968
969 typedef struct {
970 uint32_t cmd;
971 #define QEDE_PCICFG_READ 0x01
972 #define QEDE_PCICFG_WRITE 0x02
973 uint32_t reg;
974 uint32_t val;
975 uint32_t width;
976 } qede_pcicfg_rdw_t;
977 /*
978 * (Internal) return values from ioctl subroutines
979 *
980 */
981 enum ioc_reply {
982 IOC_INVAL = -1, /* bad, NAK with EINVAL */
983 IOC_DONE, /* OK, reply sent */
984 IOC_ACK, /* OK, just send ACK */
985 IOC_REPLY, /* OK, just send reply */
986 IOC_RESTART_ACK, /* OK, restart & ACK */
987 IOC_RESTART_REPLY /* OK, restart & reply */
988 };
989
990 /*
991 * Loop Back Modes
992 */
993 enum {
994 QEDE_LOOP_NONE,
995 QEDE_LOOP_INTERNAL,
996 QEDE_LOOP_EXTERNAL,
997 };
998
999 /* Loopback test return values */
1000 enum {
1001 QEDE_LB_TEST_OK,
1002 QEDE_LB_SEND_WAIT_QUEUE_ERR,
1003 QEDE_LB_NORCV_ERR,
1004 QEDE_LB_NOMEM_ERR,
1005 QEDE_LB_TX_QUEUE_ERR,
1006 QEDE_LB_SHORT_DATA_ERR,
1007 QEDE_LB_SEQUENCE_ERR,
1008 QEDE_LB_DATA_ERR,
1009 QEDE_LB_ERRCNT,
1010 QEDE_LB_NOT_SUPPORTED,
1011 QEDE_LB_TEST_CHECK_CABLE,
1012 QEDE_LB_TEST_IN_PROGRESS
1013 };
1014
1015 extern qede_link_props_t qede_def_link_props;
1016 /* Functions exported by qede_cfg.c */
1017 void qede_cfg_reset(qede_t *qede);
1018 void qede_cfg_init(qede_t *qede);
1019
1020 /* Functions exported by qede_gld.c */
1021 boolean_t qede_gld_init(qede_t *qede);
1022 int qede_multicast(qede_t * qede, boolean_t flag, const uint8_t *ptr_mcaddr);
1023 int qede_set_filter_rx_mode(qede_t *qede, enum qede_filter_rx_mode_type type);
1024 int qede_set_rx_mac_mcast(qede_t *qede, enum ecore_filter_opcode opcode,
1025 uint8_t *mac, int mc_cnt);
1026 int qede_ucst_find(qede_t *qede, const uint8_t *mac_addr);
1027 int qede_clear_filters(qede_t *qede);
1028 /* Functions exported by qede_main.c */
1029 int
1030 qede_stop(qede_t *);
1031 int
1032 qede_start(qede_t *);
1033
1034 #define QEDE_DOORBELL_WR qede_bar2_write32_tx_doorbell
1035 void
1036 qede_bar2_write32_tx_doorbell(qede_tx_ring_t *tx_ring, u32 val);
1037 void
1038 qede_enable_hw_intr(qede_fastpath_t *);
1039 void
1040 qede_disable_hw_intr(qede_fastpath_t *);
1041
1042 /* Functions exported by qede_dbg.c */
1043 extern void
1044 qede_stacktrace(qede_t *);
1045 extern void
1046 qede_print_vport_params(qede_t *,
1047 struct ecore_sp_vport_update_params *);
1048 void
1049 qede_dump_single_mblk(qede_t *qede, mblk_t *mp);
1050 void
1051 qede_dump_mblk_chain_bnext_ptr(qede_t *qede, mblk_t *mp);
1052 void
1053 qede_dump_mblk_chain_bcont_ptr(qede_t *qede, mblk_t *mp);
1054 void
1055 qede_dump_bytes(char *, int);
1056 void qede_dump_reg_cqe(struct eth_fast_path_rx_reg_cqe *cqe);
1057 void qede_dump_start_lro_cqe(struct eth_fast_path_rx_tpa_start_cqe *);
1058 void qede_dump_cont_lro_cqe(struct eth_fast_path_rx_tpa_cont_cqe *);
1059 void qede_dump_end_lro_cqe(struct eth_fast_path_rx_tpa_end_cqe *);
1060 void qede_dump_mblk_chain_bcont_ptr(qede_t *, mblk_t *);
1061
1062 /* Functions exported by qede_fp.c */
1063 mblk_t *qede_fp_poll(void *arg, int poll_bytes, int poll_pkts);
1064 int qede_fp_stat(mac_ring_driver_t rh, uint_t stat, u64 *val);
1065 mblk_t *
1066 qede_process_fastpath(qede_fastpath_t *fp,
1067 int nbytes, int npkts, int *work_done);
1068 void
1069 qede_desc_dma_mem_sync(ddi_dma_handle_t *dma_handle,
1070 uint_t start, uint_t count, uint_t range,
1071 uint_t unit_size, uint_t direction);
1072
1073 /* Functions exported by qede_osal.c */
1074 u32 qede_osal_cleanup(qede_t *qede);
1075 int
1076 qede_osal_find_dma_handle_for_block(qede_t *qede, void *addr,
1077 ddi_dma_handle_t *dma_handle);
1078
1079 /* Functions exported by qede_main.c */
1080 int
1081 qede_get_mag_elem(qede_rx_ring_t *, qede_rx_buffer_t *);
1082 void
1083 qede_update_rx_q_producer(qede_rx_ring_t *rx_ring);
1084 void qede_get_link_info(struct ecore_hwfn *hwfn,struct qede_link_cfg *lnkcfg);
1085 int
1086 qede_put_to_passive_list(qede_rx_ring_t *rx_ring, qede_rx_buffer_t *rx_buffer);
1087 qede_rx_buffer_t *
1088 qede_get_from_active_list(qede_rx_ring_t *, uint32_t *);
1089 void
1090 qede_replenish_rx_buffers(qede_rx_ring_t *);
1091 void
1092 qede_recycle_copied_rx_buffer(qede_rx_buffer_t *rx_buffer);
1093 boolean_t qede_kstat_init(qede_t *qede);
1094 void qede_kstat_fini(qede_t *qede);
1095 /*void qede_get_current_link(qede_t *qede, struct qede_link_cfg *lnkcfg);*/
1096 #endif /* _QEDE_H */